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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Pistachio SoC pinctrl driver
0004  *
0005  * Copyright (C) 2014 Imagination Technologies Ltd.
0006  * Copyright (C) 2014 Google, Inc.
0007  */
0008 
0009 #include <linux/gpio/driver.h>
0010 #include <linux/interrupt.h>
0011 #include <linux/io.h>
0012 #include <linux/irq.h>
0013 #include <linux/of.h>
0014 #include <linux/of_irq.h>
0015 #include <linux/pinctrl/pinconf.h>
0016 #include <linux/pinctrl/pinconf-generic.h>
0017 #include <linux/pinctrl/pinctrl.h>
0018 #include <linux/pinctrl/pinmux.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/slab.h>
0021 #include <linux/spinlock.h>
0022 
0023 #include "pinctrl-utils.h"
0024 
0025 #define PADS_SCHMITT_EN0        0x000
0026 #define PADS_SCHMITT_EN_REG(pin)    (PADS_SCHMITT_EN0 + 0x4 * ((pin) / 32))
0027 #define PADS_SCHMITT_EN_BIT(pin)    BIT((pin) % 32)
0028 
0029 #define PADS_PU_PD0         0x040
0030 #define PADS_PU_PD_REG(pin)     (PADS_PU_PD0 + 0x4 * ((pin) / 16))
0031 #define PADS_PU_PD_SHIFT(pin)       (2 * ((pin) % 16))
0032 #define PADS_PU_PD_MASK         0x3
0033 #define PADS_PU_PD_HIGHZ        0x0
0034 #define PADS_PU_PD_UP           0x1
0035 #define PADS_PU_PD_DOWN         0x2
0036 #define PADS_PU_PD_BUS          0x3
0037 
0038 #define PADS_FUNCTION_SELECT0       0x0c0
0039 #define PADS_FUNCTION_SELECT1       0x0c4
0040 #define PADS_FUNCTION_SELECT2       0x0c8
0041 #define PADS_SCENARIO_SELECT        0x0f8
0042 
0043 #define PADS_SLEW_RATE0         0x100
0044 #define PADS_SLEW_RATE_REG(pin)     (PADS_SLEW_RATE0 + 0x4 * ((pin) / 32))
0045 #define PADS_SLEW_RATE_BIT(pin)     BIT((pin) % 32)
0046 
0047 #define PADS_DRIVE_STRENGTH0        0x120
0048 #define PADS_DRIVE_STRENGTH_REG(pin)                    \
0049     (PADS_DRIVE_STRENGTH0 + 0x4 * ((pin) / 16))
0050 #define PADS_DRIVE_STRENGTH_SHIFT(pin)  (2 * ((pin) % 16))
0051 #define PADS_DRIVE_STRENGTH_MASK    0x3
0052 #define PADS_DRIVE_STRENGTH_2MA     0x0
0053 #define PADS_DRIVE_STRENGTH_4MA     0x1
0054 #define PADS_DRIVE_STRENGTH_8MA     0x2
0055 #define PADS_DRIVE_STRENGTH_12MA    0x3
0056 
0057 #define GPIO_BANK_BASE(bank)        (0x200 + 0x24 * (bank))
0058 
0059 #define GPIO_BIT_EN         0x00
0060 #define GPIO_OUTPUT_EN          0x04
0061 #define GPIO_OUTPUT         0x08
0062 #define GPIO_INPUT          0x0c
0063 #define GPIO_INPUT_POLARITY     0x10
0064 #define GPIO_INTERRUPT_TYPE     0x14
0065 #define GPIO_INTERRUPT_TYPE_LEVEL   0x0
0066 #define GPIO_INTERRUPT_TYPE_EDGE    0x1
0067 #define GPIO_INTERRUPT_EDGE     0x18
0068 #define GPIO_INTERRUPT_EDGE_SINGLE  0x0
0069 #define GPIO_INTERRUPT_EDGE_DUAL    0x1
0070 #define GPIO_INTERRUPT_EN       0x1c
0071 #define GPIO_INTERRUPT_STATUS       0x20
0072 
0073 struct pistachio_function {
0074     const char *name;
0075     const char * const *groups;
0076     unsigned int ngroups;
0077     const int *scenarios;
0078     unsigned int nscenarios;
0079     unsigned int scenario_reg;
0080     unsigned int scenario_shift;
0081     unsigned int scenario_mask;
0082 };
0083 
0084 struct pistachio_pin_group {
0085     const char *name;
0086     unsigned int pin;
0087     int mux_option[3];
0088     int mux_reg;
0089     int mux_shift;
0090     int mux_mask;
0091 };
0092 
0093 struct pistachio_gpio_bank {
0094     struct pistachio_pinctrl *pctl;
0095     void __iomem *base;
0096     unsigned int pin_base;
0097     unsigned int npins;
0098     struct gpio_chip gpio_chip;
0099     struct irq_chip irq_chip;
0100 };
0101 
0102 struct pistachio_pinctrl {
0103     struct device *dev;
0104     void __iomem *base;
0105     struct pinctrl_dev *pctldev;
0106     const struct pinctrl_pin_desc *pins;
0107     unsigned int npins;
0108     const struct pistachio_function *functions;
0109     unsigned int nfunctions;
0110     const struct pistachio_pin_group *groups;
0111     unsigned int ngroups;
0112     struct pistachio_gpio_bank *gpio_banks;
0113     unsigned int nbanks;
0114 };
0115 
0116 #define PISTACHIO_PIN_MFIO(p)       (p)
0117 #define PISTACHIO_PIN_TCK       90
0118 #define PISTACHIO_PIN_TRSTN     91
0119 #define PISTACHIO_PIN_TDI       92
0120 #define PISTACHIO_PIN_TMS       93
0121 #define PISTACHIO_PIN_TDO       94
0122 #define PISTACHIO_PIN_JTAG_COMPLY   95
0123 #define PISTACHIO_PIN_SAFE_MODE     96
0124 #define PISTACHIO_PIN_POR_DISABLE   97
0125 #define PISTACHIO_PIN_RESETN        98
0126 
0127 #define MFIO_PIN_DESC(p)    PINCTRL_PIN(PISTACHIO_PIN_MFIO(p), "mfio" #p)
0128 
0129 static const struct pinctrl_pin_desc pistachio_pins[] = {
0130     MFIO_PIN_DESC(0),
0131     MFIO_PIN_DESC(1),
0132     MFIO_PIN_DESC(2),
0133     MFIO_PIN_DESC(3),
0134     MFIO_PIN_DESC(4),
0135     MFIO_PIN_DESC(5),
0136     MFIO_PIN_DESC(6),
0137     MFIO_PIN_DESC(7),
0138     MFIO_PIN_DESC(8),
0139     MFIO_PIN_DESC(9),
0140     MFIO_PIN_DESC(10),
0141     MFIO_PIN_DESC(11),
0142     MFIO_PIN_DESC(12),
0143     MFIO_PIN_DESC(13),
0144     MFIO_PIN_DESC(14),
0145     MFIO_PIN_DESC(15),
0146     MFIO_PIN_DESC(16),
0147     MFIO_PIN_DESC(17),
0148     MFIO_PIN_DESC(18),
0149     MFIO_PIN_DESC(19),
0150     MFIO_PIN_DESC(20),
0151     MFIO_PIN_DESC(21),
0152     MFIO_PIN_DESC(22),
0153     MFIO_PIN_DESC(23),
0154     MFIO_PIN_DESC(24),
0155     MFIO_PIN_DESC(25),
0156     MFIO_PIN_DESC(26),
0157     MFIO_PIN_DESC(27),
0158     MFIO_PIN_DESC(28),
0159     MFIO_PIN_DESC(29),
0160     MFIO_PIN_DESC(30),
0161     MFIO_PIN_DESC(31),
0162     MFIO_PIN_DESC(32),
0163     MFIO_PIN_DESC(33),
0164     MFIO_PIN_DESC(34),
0165     MFIO_PIN_DESC(35),
0166     MFIO_PIN_DESC(36),
0167     MFIO_PIN_DESC(37),
0168     MFIO_PIN_DESC(38),
0169     MFIO_PIN_DESC(39),
0170     MFIO_PIN_DESC(40),
0171     MFIO_PIN_DESC(41),
0172     MFIO_PIN_DESC(42),
0173     MFIO_PIN_DESC(43),
0174     MFIO_PIN_DESC(44),
0175     MFIO_PIN_DESC(45),
0176     MFIO_PIN_DESC(46),
0177     MFIO_PIN_DESC(47),
0178     MFIO_PIN_DESC(48),
0179     MFIO_PIN_DESC(49),
0180     MFIO_PIN_DESC(50),
0181     MFIO_PIN_DESC(51),
0182     MFIO_PIN_DESC(52),
0183     MFIO_PIN_DESC(53),
0184     MFIO_PIN_DESC(54),
0185     MFIO_PIN_DESC(55),
0186     MFIO_PIN_DESC(56),
0187     MFIO_PIN_DESC(57),
0188     MFIO_PIN_DESC(58),
0189     MFIO_PIN_DESC(59),
0190     MFIO_PIN_DESC(60),
0191     MFIO_PIN_DESC(61),
0192     MFIO_PIN_DESC(62),
0193     MFIO_PIN_DESC(63),
0194     MFIO_PIN_DESC(64),
0195     MFIO_PIN_DESC(65),
0196     MFIO_PIN_DESC(66),
0197     MFIO_PIN_DESC(67),
0198     MFIO_PIN_DESC(68),
0199     MFIO_PIN_DESC(69),
0200     MFIO_PIN_DESC(70),
0201     MFIO_PIN_DESC(71),
0202     MFIO_PIN_DESC(72),
0203     MFIO_PIN_DESC(73),
0204     MFIO_PIN_DESC(74),
0205     MFIO_PIN_DESC(75),
0206     MFIO_PIN_DESC(76),
0207     MFIO_PIN_DESC(77),
0208     MFIO_PIN_DESC(78),
0209     MFIO_PIN_DESC(79),
0210     MFIO_PIN_DESC(80),
0211     MFIO_PIN_DESC(81),
0212     MFIO_PIN_DESC(82),
0213     MFIO_PIN_DESC(83),
0214     MFIO_PIN_DESC(84),
0215     MFIO_PIN_DESC(85),
0216     MFIO_PIN_DESC(86),
0217     MFIO_PIN_DESC(87),
0218     MFIO_PIN_DESC(88),
0219     MFIO_PIN_DESC(89),
0220     PINCTRL_PIN(PISTACHIO_PIN_TCK, "tck"),
0221     PINCTRL_PIN(PISTACHIO_PIN_TRSTN, "trstn"),
0222     PINCTRL_PIN(PISTACHIO_PIN_TDI, "tdi"),
0223     PINCTRL_PIN(PISTACHIO_PIN_TMS, "tms"),
0224     PINCTRL_PIN(PISTACHIO_PIN_TDO, "tdo"),
0225     PINCTRL_PIN(PISTACHIO_PIN_JTAG_COMPLY, "jtag_comply"),
0226     PINCTRL_PIN(PISTACHIO_PIN_SAFE_MODE, "safe_mode"),
0227     PINCTRL_PIN(PISTACHIO_PIN_POR_DISABLE, "por_disable"),
0228     PINCTRL_PIN(PISTACHIO_PIN_RESETN, "resetn"),
0229 };
0230 
0231 static const char * const pistachio_spim0_groups[] = {
0232     "mfio1", "mfio2", "mfio8", "mfio9", "mfio10", "mfio28", "mfio29",
0233     "mfio30", "mfio55", "mfio56", "mfio57",
0234 };
0235 
0236 static const char * const pistachio_spim1_groups[] = {
0237     "mfio0", "mfio1", "mfio2", "mfio3", "mfio4", "mfio5", "mfio6",
0238     "mfio7", "mfio31", "mfio55", "mfio56", "mfio57", "mfio58",
0239 };
0240 
0241 static const char * const pistachio_spis_groups[] = {
0242     "mfio11", "mfio12", "mfio13", "mfio14",
0243 };
0244 
0245 static const char *const pistachio_sdhost_groups[] = {
0246     "mfio15", "mfio16", "mfio17", "mfio18", "mfio19", "mfio20",
0247     "mfio21", "mfio22", "mfio23", "mfio24", "mfio25", "mfio26",
0248     "mfio27",
0249 };
0250 
0251 static const char * const pistachio_i2c0_groups[] = {
0252     "mfio28", "mfio29",
0253 };
0254 
0255 static const char * const pistachio_i2c1_groups[] = {
0256     "mfio30", "mfio31",
0257 };
0258 
0259 static const char * const pistachio_i2c2_groups[] = {
0260     "mfio32", "mfio33",
0261 };
0262 
0263 static const char * const pistachio_i2c3_groups[] = {
0264     "mfio34", "mfio35",
0265 };
0266 
0267 static const char * const pistachio_audio_clk_in_groups[] = {
0268     "mfio36",
0269 };
0270 
0271 static const char * const pistachio_i2s_out_groups[] = {
0272     "mfio36", "mfio37", "mfio38", "mfio39", "mfio40", "mfio41",
0273     "mfio42", "mfio43", "mfio44",
0274 };
0275 
0276 static const char * const pistachio_debug_raw_cca_ind_groups[] = {
0277     "mfio37",
0278 };
0279 
0280 static const char * const pistachio_debug_ed_sec20_cca_ind_groups[] = {
0281     "mfio38",
0282 };
0283 
0284 static const char * const pistachio_debug_ed_sec40_cca_ind_groups[] = {
0285     "mfio39",
0286 };
0287 
0288 static const char * const pistachio_debug_agc_done_0_groups[] = {
0289     "mfio40",
0290 };
0291 
0292 static const char * const pistachio_debug_agc_done_1_groups[] = {
0293     "mfio41",
0294 };
0295 
0296 static const char * const pistachio_debug_ed_cca_ind_groups[] = {
0297     "mfio42",
0298 };
0299 
0300 static const char * const pistachio_debug_s2l_done_groups[] = {
0301     "mfio43",
0302 };
0303 
0304 static const char * const pistachio_i2s_dac_clk_groups[] = {
0305     "mfio45",
0306 };
0307 
0308 static const char * const pistachio_audio_sync_groups[] = {
0309     "mfio45",
0310 };
0311 
0312 static const char * const pistachio_audio_trigger_groups[] = {
0313     "mfio46",
0314 };
0315 
0316 static const char * const pistachio_i2s_in_groups[] = {
0317     "mfio47", "mfio48", "mfio49", "mfio50", "mfio51", "mfio52",
0318     "mfio53", "mfio54",
0319 };
0320 
0321 static const char * const pistachio_uart0_groups[] = {
0322     "mfio55", "mfio56", "mfio57", "mfio58",
0323 };
0324 
0325 static const char * const pistachio_uart1_groups[] = {
0326     "mfio59", "mfio60", "mfio1", "mfio2",
0327 };
0328 
0329 static const char * const pistachio_spdif_out_groups[] = {
0330     "mfio61",
0331 };
0332 
0333 static const char * const pistachio_spdif_in_groups[] = {
0334     "mfio62", "mfio54",
0335 };
0336 static const int pistachio_spdif_in_scenarios[] = {
0337     PISTACHIO_PIN_MFIO(62),
0338     PISTACHIO_PIN_MFIO(54),
0339 };
0340 
0341 static const char * const pistachio_eth_groups[] = {
0342     "mfio63", "mfio64", "mfio65", "mfio66", "mfio67", "mfio68",
0343     "mfio69", "mfio70", "mfio71",
0344 };
0345 
0346 static const char * const pistachio_ir_groups[] = {
0347     "mfio72",
0348 };
0349 
0350 static const char * const pistachio_pwmpdm_groups[] = {
0351     "mfio73", "mfio74", "mfio75", "mfio76",
0352 };
0353 
0354 static const char * const pistachio_mips_trace_clk_groups[] = {
0355     "mfio15", "mfio63", "mfio73",
0356 };
0357 
0358 static const char * const pistachio_mips_trace_dint_groups[] = {
0359     "mfio16", "mfio64", "mfio74",
0360 };
0361 static const int pistachio_mips_trace_dint_scenarios[] = {
0362     PISTACHIO_PIN_MFIO(16),
0363     PISTACHIO_PIN_MFIO(64),
0364     PISTACHIO_PIN_MFIO(74),
0365 };
0366 
0367 static const char * const pistachio_mips_trace_trigout_groups[] = {
0368     "mfio17", "mfio65", "mfio75",
0369 };
0370 
0371 static const char * const pistachio_mips_trace_trigin_groups[] = {
0372     "mfio18", "mfio66", "mfio76",
0373 };
0374 static const int pistachio_mips_trace_trigin_scenarios[] = {
0375     PISTACHIO_PIN_MFIO(18),
0376     PISTACHIO_PIN_MFIO(66),
0377     PISTACHIO_PIN_MFIO(76),
0378 };
0379 
0380 static const char * const pistachio_mips_trace_dm_groups[] = {
0381     "mfio19", "mfio67", "mfio77",
0382 };
0383 
0384 static const char * const pistachio_mips_probe_n_groups[] = {
0385     "mfio20", "mfio68", "mfio78",
0386 };
0387 static const int pistachio_mips_probe_n_scenarios[] = {
0388     PISTACHIO_PIN_MFIO(20),
0389     PISTACHIO_PIN_MFIO(68),
0390     PISTACHIO_PIN_MFIO(78),
0391 };
0392 
0393 static const char * const pistachio_mips_trace_data_groups[] = {
0394     "mfio15", "mfio16", "mfio17", "mfio18", "mfio19", "mfio20",
0395     "mfio21", "mfio22", "mfio63", "mfio64", "mfio65", "mfio66",
0396     "mfio67", "mfio68", "mfio69", "mfio70", "mfio79", "mfio80",
0397     "mfio81", "mfio82", "mfio83", "mfio84", "mfio85", "mfio86",
0398 };
0399 
0400 static const char * const pistachio_sram_debug_groups[] = {
0401     "mfio73", "mfio74",
0402 };
0403 
0404 static const char * const pistachio_rom_debug_groups[] = {
0405     "mfio75", "mfio76",
0406 };
0407 
0408 static const char * const pistachio_rpu_debug_groups[] = {
0409     "mfio77", "mfio78",
0410 };
0411 
0412 static const char * const pistachio_mips_debug_groups[] = {
0413     "mfio79", "mfio80",
0414 };
0415 
0416 static const char * const pistachio_eth_debug_groups[] = {
0417     "mfio81", "mfio82",
0418 };
0419 
0420 static const char * const pistachio_usb_debug_groups[] = {
0421     "mfio83", "mfio84",
0422 };
0423 
0424 static const char * const pistachio_sdhost_debug_groups[] = {
0425     "mfio85", "mfio86",
0426 };
0427 
0428 static const char * const pistachio_socif_debug_groups[] = {
0429     "mfio87", "mfio88",
0430 };
0431 
0432 static const char * const pistachio_mdc_debug_groups[] = {
0433     "mfio77", "mfio78",
0434 };
0435 
0436 static const char * const pistachio_ddr_debug_groups[] = {
0437     "mfio79", "mfio80",
0438 };
0439 
0440 static const char * const pistachio_dreq0_groups[] = {
0441     "mfio81",
0442 };
0443 
0444 static const char * const pistachio_dreq1_groups[] = {
0445     "mfio82",
0446 };
0447 
0448 static const char * const pistachio_dreq2_groups[] = {
0449     "mfio87",
0450 };
0451 
0452 static const char * const pistachio_dreq3_groups[] = {
0453     "mfio88",
0454 };
0455 
0456 static const char * const pistachio_dreq4_groups[] = {
0457     "mfio89",
0458 };
0459 
0460 static const char * const pistachio_dreq5_groups[] = {
0461     "mfio89",
0462 };
0463 
0464 static const char * const pistachio_mips_pll_lock_groups[] = {
0465     "mfio83",
0466 };
0467 
0468 static const char * const pistachio_audio_pll_lock_groups[] = {
0469     "mfio84",
0470 };
0471 
0472 static const char * const pistachio_rpu_v_pll_lock_groups[] = {
0473     "mfio85",
0474 };
0475 
0476 static const char * const pistachio_rpu_l_pll_lock_groups[] = {
0477     "mfio86",
0478 };
0479 
0480 static const char * const pistachio_sys_pll_lock_groups[] = {
0481     "mfio87",
0482 };
0483 
0484 static const char * const pistachio_wifi_pll_lock_groups[] = {
0485     "mfio88",
0486 };
0487 
0488 static const char * const pistachio_bt_pll_lock_groups[] = {
0489     "mfio89",
0490 };
0491 
0492 #define FUNCTION(_name)                         \
0493     {                               \
0494         .name = #_name,                     \
0495         .groups = pistachio_##_name##_groups,           \
0496         .ngroups = ARRAY_SIZE(pistachio_##_name##_groups),  \
0497     }
0498 
0499 #define FUNCTION_SCENARIO(_name, _reg, _shift, _mask)           \
0500     {                               \
0501         .name = #_name,                     \
0502         .groups = pistachio_##_name##_groups,           \
0503         .ngroups = ARRAY_SIZE(pistachio_##_name##_groups),  \
0504         .scenarios = pistachio_##_name##_scenarios,     \
0505         .nscenarios = ARRAY_SIZE(pistachio_##_name##_scenarios),\
0506         .scenario_reg = _reg,                   \
0507         .scenario_shift = _shift,               \
0508         .scenario_mask = _mask,                 \
0509     }
0510 
0511 enum pistachio_mux_option {
0512     PISTACHIO_FUNCTION_NONE = -1,
0513     PISTACHIO_FUNCTION_SPIM0,
0514     PISTACHIO_FUNCTION_SPIM1,
0515     PISTACHIO_FUNCTION_SPIS,
0516     PISTACHIO_FUNCTION_SDHOST,
0517     PISTACHIO_FUNCTION_I2C0,
0518     PISTACHIO_FUNCTION_I2C1,
0519     PISTACHIO_FUNCTION_I2C2,
0520     PISTACHIO_FUNCTION_I2C3,
0521     PISTACHIO_FUNCTION_AUDIO_CLK_IN,
0522     PISTACHIO_FUNCTION_I2S_OUT,
0523     PISTACHIO_FUNCTION_I2S_DAC_CLK,
0524     PISTACHIO_FUNCTION_AUDIO_SYNC,
0525     PISTACHIO_FUNCTION_AUDIO_TRIGGER,
0526     PISTACHIO_FUNCTION_I2S_IN,
0527     PISTACHIO_FUNCTION_UART0,
0528     PISTACHIO_FUNCTION_UART1,
0529     PISTACHIO_FUNCTION_SPDIF_OUT,
0530     PISTACHIO_FUNCTION_SPDIF_IN,
0531     PISTACHIO_FUNCTION_ETH,
0532     PISTACHIO_FUNCTION_IR,
0533     PISTACHIO_FUNCTION_PWMPDM,
0534     PISTACHIO_FUNCTION_MIPS_TRACE_CLK,
0535     PISTACHIO_FUNCTION_MIPS_TRACE_DINT,
0536     PISTACHIO_FUNCTION_MIPS_TRACE_TRIGOUT,
0537     PISTACHIO_FUNCTION_MIPS_TRACE_TRIGIN,
0538     PISTACHIO_FUNCTION_MIPS_TRACE_DM,
0539     PISTACHIO_FUNCTION_MIPS_TRACE_PROBE_N,
0540     PISTACHIO_FUNCTION_MIPS_TRACE_DATA,
0541     PISTACHIO_FUNCTION_SRAM_DEBUG,
0542     PISTACHIO_FUNCTION_ROM_DEBUG,
0543     PISTACHIO_FUNCTION_RPU_DEBUG,
0544     PISTACHIO_FUNCTION_MIPS_DEBUG,
0545     PISTACHIO_FUNCTION_ETH_DEBUG,
0546     PISTACHIO_FUNCTION_USB_DEBUG,
0547     PISTACHIO_FUNCTION_SDHOST_DEBUG,
0548     PISTACHIO_FUNCTION_SOCIF_DEBUG,
0549     PISTACHIO_FUNCTION_MDC_DEBUG,
0550     PISTACHIO_FUNCTION_DDR_DEBUG,
0551     PISTACHIO_FUNCTION_DREQ0,
0552     PISTACHIO_FUNCTION_DREQ1,
0553     PISTACHIO_FUNCTION_DREQ2,
0554     PISTACHIO_FUNCTION_DREQ3,
0555     PISTACHIO_FUNCTION_DREQ4,
0556     PISTACHIO_FUNCTION_DREQ5,
0557     PISTACHIO_FUNCTION_MIPS_PLL_LOCK,
0558     PISTACHIO_FUNCTION_AUDIO_PLL_LOCK,
0559     PISTACHIO_FUNCTION_RPU_V_PLL_LOCK,
0560     PISTACHIO_FUNCTION_RPU_L_PLL_LOCK,
0561     PISTACHIO_FUNCTION_SYS_PLL_LOCK,
0562     PISTACHIO_FUNCTION_WIFI_PLL_LOCK,
0563     PISTACHIO_FUNCTION_BT_PLL_LOCK,
0564     PISTACHIO_FUNCTION_DEBUG_RAW_CCA_IND,
0565     PISTACHIO_FUNCTION_DEBUG_ED_SEC20_CCA_IND,
0566     PISTACHIO_FUNCTION_DEBUG_ED_SEC40_CCA_IND,
0567     PISTACHIO_FUNCTION_DEBUG_AGC_DONE_0,
0568     PISTACHIO_FUNCTION_DEBUG_AGC_DONE_1,
0569     PISTACHIO_FUNCTION_DEBUG_ED_CCA_IND,
0570     PISTACHIO_FUNCTION_DEBUG_S2L_DONE,
0571 };
0572 
0573 static const struct pistachio_function pistachio_functions[] = {
0574     FUNCTION(spim0),
0575     FUNCTION(spim1),
0576     FUNCTION(spis),
0577     FUNCTION(sdhost),
0578     FUNCTION(i2c0),
0579     FUNCTION(i2c1),
0580     FUNCTION(i2c2),
0581     FUNCTION(i2c3),
0582     FUNCTION(audio_clk_in),
0583     FUNCTION(i2s_out),
0584     FUNCTION(i2s_dac_clk),
0585     FUNCTION(audio_sync),
0586     FUNCTION(audio_trigger),
0587     FUNCTION(i2s_in),
0588     FUNCTION(uart0),
0589     FUNCTION(uart1),
0590     FUNCTION(spdif_out),
0591     FUNCTION_SCENARIO(spdif_in, PADS_SCENARIO_SELECT, 0, 0x1),
0592     FUNCTION(eth),
0593     FUNCTION(ir),
0594     FUNCTION(pwmpdm),
0595     FUNCTION(mips_trace_clk),
0596     FUNCTION_SCENARIO(mips_trace_dint, PADS_SCENARIO_SELECT, 1, 0x3),
0597     FUNCTION(mips_trace_trigout),
0598     FUNCTION_SCENARIO(mips_trace_trigin, PADS_SCENARIO_SELECT, 3, 0x3),
0599     FUNCTION(mips_trace_dm),
0600     FUNCTION_SCENARIO(mips_probe_n, PADS_SCENARIO_SELECT, 5, 0x3),
0601     FUNCTION(mips_trace_data),
0602     FUNCTION(sram_debug),
0603     FUNCTION(rom_debug),
0604     FUNCTION(rpu_debug),
0605     FUNCTION(mips_debug),
0606     FUNCTION(eth_debug),
0607     FUNCTION(usb_debug),
0608     FUNCTION(sdhost_debug),
0609     FUNCTION(socif_debug),
0610     FUNCTION(mdc_debug),
0611     FUNCTION(ddr_debug),
0612     FUNCTION(dreq0),
0613     FUNCTION(dreq1),
0614     FUNCTION(dreq2),
0615     FUNCTION(dreq3),
0616     FUNCTION(dreq4),
0617     FUNCTION(dreq5),
0618     FUNCTION(mips_pll_lock),
0619     FUNCTION(audio_pll_lock),
0620     FUNCTION(rpu_v_pll_lock),
0621     FUNCTION(rpu_l_pll_lock),
0622     FUNCTION(sys_pll_lock),
0623     FUNCTION(wifi_pll_lock),
0624     FUNCTION(bt_pll_lock),
0625     FUNCTION(debug_raw_cca_ind),
0626     FUNCTION(debug_ed_sec20_cca_ind),
0627     FUNCTION(debug_ed_sec40_cca_ind),
0628     FUNCTION(debug_agc_done_0),
0629     FUNCTION(debug_agc_done_1),
0630     FUNCTION(debug_ed_cca_ind),
0631     FUNCTION(debug_s2l_done),
0632 };
0633 
0634 #define PIN_GROUP(_pin, _name)                  \
0635     {                           \
0636         .name = #_name,                 \
0637         .pin = PISTACHIO_PIN_##_pin,            \
0638         .mux_option = {                 \
0639             PISTACHIO_FUNCTION_NONE,        \
0640             PISTACHIO_FUNCTION_NONE,        \
0641             PISTACHIO_FUNCTION_NONE,        \
0642         },                      \
0643         .mux_reg = -1,                  \
0644         .mux_shift = -1,                \
0645         .mux_mask = -1,                 \
0646     }
0647 
0648 #define MFIO_PIN_GROUP(_pin, _func)             \
0649     {                           \
0650         .name = "mfio" #_pin,               \
0651         .pin = PISTACHIO_PIN_MFIO(_pin),        \
0652         .mux_option = {                 \
0653             PISTACHIO_FUNCTION_##_func,     \
0654             PISTACHIO_FUNCTION_NONE,        \
0655             PISTACHIO_FUNCTION_NONE,        \
0656         },                      \
0657         .mux_reg = -1,                  \
0658         .mux_shift = -1,                \
0659         .mux_mask = -1,                 \
0660     }
0661 
0662 #define MFIO_MUX_PIN_GROUP(_pin, _f0, _f1, _f2, _reg, _shift, _mask)    \
0663     {                               \
0664         .name = "mfio" #_pin,                   \
0665         .pin = PISTACHIO_PIN_MFIO(_pin),            \
0666         .mux_option = {                     \
0667             PISTACHIO_FUNCTION_##_f0,           \
0668             PISTACHIO_FUNCTION_##_f1,           \
0669             PISTACHIO_FUNCTION_##_f2,           \
0670         },                          \
0671         .mux_reg = _reg,                    \
0672         .mux_shift = _shift,                    \
0673         .mux_mask = _mask,                  \
0674     }
0675 
0676 static const struct pistachio_pin_group pistachio_groups[] = {
0677     MFIO_PIN_GROUP(0, SPIM1),
0678     MFIO_MUX_PIN_GROUP(1, SPIM1, SPIM0, UART1,
0679                PADS_FUNCTION_SELECT0, 0, 0x3),
0680     MFIO_MUX_PIN_GROUP(2, SPIM1, SPIM0, UART1,
0681                PADS_FUNCTION_SELECT0, 2, 0x3),
0682     MFIO_PIN_GROUP(3, SPIM1),
0683     MFIO_PIN_GROUP(4, SPIM1),
0684     MFIO_PIN_GROUP(5, SPIM1),
0685     MFIO_PIN_GROUP(6, SPIM1),
0686     MFIO_PIN_GROUP(7, SPIM1),
0687     MFIO_PIN_GROUP(8, SPIM0),
0688     MFIO_PIN_GROUP(9, SPIM0),
0689     MFIO_PIN_GROUP(10, SPIM0),
0690     MFIO_PIN_GROUP(11, SPIS),
0691     MFIO_PIN_GROUP(12, SPIS),
0692     MFIO_PIN_GROUP(13, SPIS),
0693     MFIO_PIN_GROUP(14, SPIS),
0694     MFIO_MUX_PIN_GROUP(15, SDHOST, MIPS_TRACE_CLK, MIPS_TRACE_DATA,
0695                PADS_FUNCTION_SELECT0, 4, 0x3),
0696     MFIO_MUX_PIN_GROUP(16, SDHOST, MIPS_TRACE_DINT, MIPS_TRACE_DATA,
0697                PADS_FUNCTION_SELECT0, 6, 0x3),
0698     MFIO_MUX_PIN_GROUP(17, SDHOST, MIPS_TRACE_TRIGOUT, MIPS_TRACE_DATA,
0699                PADS_FUNCTION_SELECT0, 8, 0x3),
0700     MFIO_MUX_PIN_GROUP(18, SDHOST, MIPS_TRACE_TRIGIN, MIPS_TRACE_DATA,
0701                PADS_FUNCTION_SELECT0, 10, 0x3),
0702     MFIO_MUX_PIN_GROUP(19, SDHOST, MIPS_TRACE_DM, MIPS_TRACE_DATA,
0703                PADS_FUNCTION_SELECT0, 12, 0x3),
0704     MFIO_MUX_PIN_GROUP(20, SDHOST, MIPS_TRACE_PROBE_N, MIPS_TRACE_DATA,
0705                PADS_FUNCTION_SELECT0, 14, 0x3),
0706     MFIO_MUX_PIN_GROUP(21, SDHOST, NONE, MIPS_TRACE_DATA,
0707                PADS_FUNCTION_SELECT0, 16, 0x3),
0708     MFIO_MUX_PIN_GROUP(22, SDHOST, NONE, MIPS_TRACE_DATA,
0709                PADS_FUNCTION_SELECT0, 18, 0x3),
0710     MFIO_PIN_GROUP(23, SDHOST),
0711     MFIO_PIN_GROUP(24, SDHOST),
0712     MFIO_PIN_GROUP(25, SDHOST),
0713     MFIO_PIN_GROUP(26, SDHOST),
0714     MFIO_PIN_GROUP(27, SDHOST),
0715     MFIO_MUX_PIN_GROUP(28, I2C0, SPIM0, NONE,
0716                PADS_FUNCTION_SELECT0, 20, 0x1),
0717     MFIO_MUX_PIN_GROUP(29, I2C0, SPIM0, NONE,
0718                PADS_FUNCTION_SELECT0, 21, 0x1),
0719     MFIO_MUX_PIN_GROUP(30, I2C1, SPIM0, NONE,
0720                PADS_FUNCTION_SELECT0, 22, 0x1),
0721     MFIO_MUX_PIN_GROUP(31, I2C1, SPIM1, NONE,
0722                PADS_FUNCTION_SELECT0, 23, 0x1),
0723     MFIO_PIN_GROUP(32, I2C2),
0724     MFIO_PIN_GROUP(33, I2C2),
0725     MFIO_PIN_GROUP(34, I2C3),
0726     MFIO_PIN_GROUP(35, I2C3),
0727     MFIO_MUX_PIN_GROUP(36, I2S_OUT, AUDIO_CLK_IN, NONE,
0728                PADS_FUNCTION_SELECT0, 24, 0x1),
0729     MFIO_MUX_PIN_GROUP(37, I2S_OUT, DEBUG_RAW_CCA_IND, NONE,
0730                PADS_FUNCTION_SELECT0, 25, 0x1),
0731     MFIO_MUX_PIN_GROUP(38, I2S_OUT, DEBUG_ED_SEC20_CCA_IND, NONE,
0732                PADS_FUNCTION_SELECT0, 26, 0x1),
0733     MFIO_MUX_PIN_GROUP(39, I2S_OUT, DEBUG_ED_SEC40_CCA_IND, NONE,
0734                PADS_FUNCTION_SELECT0, 27, 0x1),
0735     MFIO_MUX_PIN_GROUP(40, I2S_OUT, DEBUG_AGC_DONE_0, NONE,
0736                PADS_FUNCTION_SELECT0, 28, 0x1),
0737     MFIO_MUX_PIN_GROUP(41, I2S_OUT, DEBUG_AGC_DONE_1, NONE,
0738                PADS_FUNCTION_SELECT0, 29, 0x1),
0739     MFIO_MUX_PIN_GROUP(42, I2S_OUT, DEBUG_ED_CCA_IND, NONE,
0740                PADS_FUNCTION_SELECT0, 30, 0x1),
0741     MFIO_MUX_PIN_GROUP(43, I2S_OUT, DEBUG_S2L_DONE, NONE,
0742                PADS_FUNCTION_SELECT0, 31, 0x1),
0743     MFIO_PIN_GROUP(44, I2S_OUT),
0744     MFIO_MUX_PIN_GROUP(45, I2S_DAC_CLK, AUDIO_SYNC, NONE,
0745                PADS_FUNCTION_SELECT1, 0, 0x1),
0746     MFIO_PIN_GROUP(46, AUDIO_TRIGGER),
0747     MFIO_PIN_GROUP(47, I2S_IN),
0748     MFIO_PIN_GROUP(48, I2S_IN),
0749     MFIO_PIN_GROUP(49, I2S_IN),
0750     MFIO_PIN_GROUP(50, I2S_IN),
0751     MFIO_PIN_GROUP(51, I2S_IN),
0752     MFIO_PIN_GROUP(52, I2S_IN),
0753     MFIO_PIN_GROUP(53, I2S_IN),
0754     MFIO_MUX_PIN_GROUP(54, I2S_IN, NONE, SPDIF_IN,
0755                PADS_FUNCTION_SELECT1, 1, 0x3),
0756     MFIO_MUX_PIN_GROUP(55, UART0, SPIM0, SPIM1,
0757                PADS_FUNCTION_SELECT1, 3, 0x3),
0758     MFIO_MUX_PIN_GROUP(56, UART0, SPIM0, SPIM1,
0759                PADS_FUNCTION_SELECT1, 5, 0x3),
0760     MFIO_MUX_PIN_GROUP(57, UART0, SPIM0, SPIM1,
0761                PADS_FUNCTION_SELECT1, 7, 0x3),
0762     MFIO_MUX_PIN_GROUP(58, UART0, SPIM1, NONE,
0763                PADS_FUNCTION_SELECT1, 9, 0x1),
0764     MFIO_PIN_GROUP(59, UART1),
0765     MFIO_PIN_GROUP(60, UART1),
0766     MFIO_PIN_GROUP(61, SPDIF_OUT),
0767     MFIO_PIN_GROUP(62, SPDIF_IN),
0768     MFIO_MUX_PIN_GROUP(63, ETH, MIPS_TRACE_CLK, MIPS_TRACE_DATA,
0769                PADS_FUNCTION_SELECT1, 10, 0x3),
0770     MFIO_MUX_PIN_GROUP(64, ETH, MIPS_TRACE_DINT, MIPS_TRACE_DATA,
0771                PADS_FUNCTION_SELECT1, 12, 0x3),
0772     MFIO_MUX_PIN_GROUP(65, ETH, MIPS_TRACE_TRIGOUT, MIPS_TRACE_DATA,
0773                PADS_FUNCTION_SELECT1, 14, 0x3),
0774     MFIO_MUX_PIN_GROUP(66, ETH, MIPS_TRACE_TRIGIN, MIPS_TRACE_DATA,
0775                PADS_FUNCTION_SELECT1, 16, 0x3),
0776     MFIO_MUX_PIN_GROUP(67, ETH, MIPS_TRACE_DM, MIPS_TRACE_DATA,
0777                PADS_FUNCTION_SELECT1, 18, 0x3),
0778     MFIO_MUX_PIN_GROUP(68, ETH, MIPS_TRACE_PROBE_N, MIPS_TRACE_DATA,
0779                PADS_FUNCTION_SELECT1, 20, 0x3),
0780     MFIO_MUX_PIN_GROUP(69, ETH, NONE, MIPS_TRACE_DATA,
0781                PADS_FUNCTION_SELECT1, 22, 0x3),
0782     MFIO_MUX_PIN_GROUP(70, ETH, NONE, MIPS_TRACE_DATA,
0783                PADS_FUNCTION_SELECT1, 24, 0x3),
0784     MFIO_PIN_GROUP(71, ETH),
0785     MFIO_PIN_GROUP(72, IR),
0786     MFIO_MUX_PIN_GROUP(73, PWMPDM, MIPS_TRACE_CLK, SRAM_DEBUG,
0787                PADS_FUNCTION_SELECT1, 26, 0x3),
0788     MFIO_MUX_PIN_GROUP(74, PWMPDM, MIPS_TRACE_DINT, SRAM_DEBUG,
0789                PADS_FUNCTION_SELECT1, 28, 0x3),
0790     MFIO_MUX_PIN_GROUP(75, PWMPDM, MIPS_TRACE_TRIGOUT, ROM_DEBUG,
0791                PADS_FUNCTION_SELECT1, 30, 0x3),
0792     MFIO_MUX_PIN_GROUP(76, PWMPDM, MIPS_TRACE_TRIGIN, ROM_DEBUG,
0793                PADS_FUNCTION_SELECT2, 0, 0x3),
0794     MFIO_MUX_PIN_GROUP(77, MDC_DEBUG, MIPS_TRACE_DM, RPU_DEBUG,
0795                PADS_FUNCTION_SELECT2, 2, 0x3),
0796     MFIO_MUX_PIN_GROUP(78, MDC_DEBUG, MIPS_TRACE_PROBE_N, RPU_DEBUG,
0797                PADS_FUNCTION_SELECT2, 4, 0x3),
0798     MFIO_MUX_PIN_GROUP(79, DDR_DEBUG, MIPS_TRACE_DATA, MIPS_DEBUG,
0799                PADS_FUNCTION_SELECT2, 6, 0x3),
0800     MFIO_MUX_PIN_GROUP(80, DDR_DEBUG, MIPS_TRACE_DATA, MIPS_DEBUG,
0801                PADS_FUNCTION_SELECT2, 8, 0x3),
0802     MFIO_MUX_PIN_GROUP(81, DREQ0, MIPS_TRACE_DATA, ETH_DEBUG,
0803                PADS_FUNCTION_SELECT2, 10, 0x3),
0804     MFIO_MUX_PIN_GROUP(82, DREQ1, MIPS_TRACE_DATA, ETH_DEBUG,
0805                PADS_FUNCTION_SELECT2, 12, 0x3),
0806     MFIO_MUX_PIN_GROUP(83, MIPS_PLL_LOCK, MIPS_TRACE_DATA, USB_DEBUG,
0807                PADS_FUNCTION_SELECT2, 14, 0x3),
0808     MFIO_MUX_PIN_GROUP(84, AUDIO_PLL_LOCK, MIPS_TRACE_DATA, USB_DEBUG,
0809                PADS_FUNCTION_SELECT2, 16, 0x3),
0810     MFIO_MUX_PIN_GROUP(85, RPU_V_PLL_LOCK, MIPS_TRACE_DATA, SDHOST_DEBUG,
0811                PADS_FUNCTION_SELECT2, 18, 0x3),
0812     MFIO_MUX_PIN_GROUP(86, RPU_L_PLL_LOCK, MIPS_TRACE_DATA, SDHOST_DEBUG,
0813                PADS_FUNCTION_SELECT2, 20, 0x3),
0814     MFIO_MUX_PIN_GROUP(87, SYS_PLL_LOCK, DREQ2, SOCIF_DEBUG,
0815                PADS_FUNCTION_SELECT2, 22, 0x3),
0816     MFIO_MUX_PIN_GROUP(88, WIFI_PLL_LOCK, DREQ3, SOCIF_DEBUG,
0817                PADS_FUNCTION_SELECT2, 24, 0x3),
0818     MFIO_MUX_PIN_GROUP(89, BT_PLL_LOCK, DREQ4, DREQ5,
0819                PADS_FUNCTION_SELECT2, 26, 0x3),
0820     PIN_GROUP(TCK, "tck"),
0821     PIN_GROUP(TRSTN, "trstn"),
0822     PIN_GROUP(TDI, "tdi"),
0823     PIN_GROUP(TMS, "tms"),
0824     PIN_GROUP(TDO, "tdo"),
0825     PIN_GROUP(JTAG_COMPLY, "jtag_comply"),
0826     PIN_GROUP(SAFE_MODE, "safe_mode"),
0827     PIN_GROUP(POR_DISABLE, "por_disable"),
0828     PIN_GROUP(RESETN, "resetn"),
0829 };
0830 
0831 static inline u32 pctl_readl(struct pistachio_pinctrl *pctl, u32 reg)
0832 {
0833     return readl(pctl->base + reg);
0834 }
0835 
0836 static inline void pctl_writel(struct pistachio_pinctrl *pctl, u32 val, u32 reg)
0837 {
0838     writel(val, pctl->base + reg);
0839 }
0840 
0841 static inline struct pistachio_gpio_bank *irqd_to_bank(struct irq_data *d)
0842 {
0843     return gpiochip_get_data(irq_data_get_irq_chip_data(d));
0844 }
0845 
0846 static inline u32 gpio_readl(struct pistachio_gpio_bank *bank, u32 reg)
0847 {
0848     return readl(bank->base + reg);
0849 }
0850 
0851 static inline void gpio_writel(struct pistachio_gpio_bank *bank, u32 val,
0852                    u32 reg)
0853 {
0854     writel(val, bank->base + reg);
0855 }
0856 
0857 static inline void gpio_mask_writel(struct pistachio_gpio_bank *bank,
0858                     u32 reg, unsigned int bit, u32 val)
0859 {
0860     /*
0861      * For most of the GPIO registers, bit 16 + X must be set in order to
0862      * write bit X.
0863      */
0864     gpio_writel(bank, (0x10000 | val) << bit, reg);
0865 }
0866 
0867 static inline void gpio_enable(struct pistachio_gpio_bank *bank,
0868                    unsigned offset)
0869 {
0870     gpio_mask_writel(bank, GPIO_BIT_EN, offset, 1);
0871 }
0872 
0873 static inline void gpio_disable(struct pistachio_gpio_bank *bank,
0874                 unsigned offset)
0875 {
0876     gpio_mask_writel(bank, GPIO_BIT_EN, offset, 0);
0877 }
0878 
0879 static int pistachio_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
0880 {
0881     struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0882 
0883     return pctl->ngroups;
0884 }
0885 
0886 static const char *pistachio_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
0887                             unsigned group)
0888 {
0889     struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0890 
0891     return pctl->groups[group].name;
0892 }
0893 
0894 static int pistachio_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
0895                         unsigned group,
0896                         const unsigned **pins,
0897                         unsigned *num_pins)
0898 {
0899     struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0900 
0901     *pins = &pctl->groups[group].pin;
0902     *num_pins = 1;
0903 
0904     return 0;
0905 }
0906 
0907 static const struct pinctrl_ops pistachio_pinctrl_ops = {
0908     .get_groups_count = pistachio_pinctrl_get_groups_count,
0909     .get_group_name = pistachio_pinctrl_get_group_name,
0910     .get_group_pins = pistachio_pinctrl_get_group_pins,
0911     .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
0912     .dt_free_map = pinctrl_utils_free_map,
0913 };
0914 
0915 static int pistachio_pinmux_get_functions_count(struct pinctrl_dev *pctldev)
0916 {
0917     struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0918 
0919     return pctl->nfunctions;
0920 }
0921 
0922 static const char *
0923 pistachio_pinmux_get_function_name(struct pinctrl_dev *pctldev, unsigned func)
0924 {
0925     struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0926 
0927     return pctl->functions[func].name;
0928 }
0929 
0930 static int pistachio_pinmux_get_function_groups(struct pinctrl_dev *pctldev,
0931                         unsigned func,
0932                         const char * const **groups,
0933                         unsigned * const num_groups)
0934 {
0935     struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0936 
0937     *groups = pctl->functions[func].groups;
0938     *num_groups = pctl->functions[func].ngroups;
0939 
0940     return 0;
0941 }
0942 
0943 static int pistachio_pinmux_enable(struct pinctrl_dev *pctldev,
0944                    unsigned func, unsigned group)
0945 {
0946     struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0947     const struct pistachio_pin_group *pg = &pctl->groups[group];
0948     const struct pistachio_function *pf = &pctl->functions[func];
0949     struct pinctrl_gpio_range *range;
0950     unsigned int i;
0951     u32 val;
0952 
0953     if (pg->mux_reg > 0) {
0954         for (i = 0; i < ARRAY_SIZE(pg->mux_option); i++) {
0955             if (pg->mux_option[i] == func)
0956                 break;
0957         }
0958         if (i == ARRAY_SIZE(pg->mux_option)) {
0959             dev_err(pctl->dev, "Cannot mux pin %u to function %u\n",
0960                 group, func);
0961             return -EINVAL;
0962         }
0963 
0964         val = pctl_readl(pctl, pg->mux_reg);
0965         val &= ~(pg->mux_mask << pg->mux_shift);
0966         val |= i << pg->mux_shift;
0967         pctl_writel(pctl, val, pg->mux_reg);
0968 
0969         if (pf->scenarios) {
0970             for (i = 0; i < pf->nscenarios; i++) {
0971                 if (pf->scenarios[i] == group)
0972                     break;
0973             }
0974             if (WARN_ON(i == pf->nscenarios))
0975                 return -EINVAL;
0976 
0977             val = pctl_readl(pctl, pf->scenario_reg);
0978             val &= ~(pf->scenario_mask << pf->scenario_shift);
0979             val |= i << pf->scenario_shift;
0980             pctl_writel(pctl, val, pf->scenario_reg);
0981         }
0982     }
0983 
0984     range = pinctrl_find_gpio_range_from_pin(pctl->pctldev, pg->pin);
0985     if (range)
0986         gpio_disable(gpiochip_get_data(range->gc), pg->pin - range->pin_base);
0987 
0988     return 0;
0989 }
0990 
0991 static const struct pinmux_ops pistachio_pinmux_ops = {
0992     .get_functions_count = pistachio_pinmux_get_functions_count,
0993     .get_function_name = pistachio_pinmux_get_function_name,
0994     .get_function_groups = pistachio_pinmux_get_function_groups,
0995     .set_mux = pistachio_pinmux_enable,
0996 };
0997 
0998 static int pistachio_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
0999                  unsigned long *config)
1000 {
1001     struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1002     enum pin_config_param param = pinconf_to_config_param(*config);
1003     u32 val, arg;
1004 
1005     switch (param) {
1006     case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1007         val = pctl_readl(pctl, PADS_SCHMITT_EN_REG(pin));
1008         arg = !!(val & PADS_SCHMITT_EN_BIT(pin));
1009         break;
1010     case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
1011         val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
1012             PADS_PU_PD_SHIFT(pin);
1013         arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_HIGHZ;
1014         break;
1015     case PIN_CONFIG_BIAS_PULL_UP:
1016         val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
1017             PADS_PU_PD_SHIFT(pin);
1018         arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_UP;
1019         break;
1020     case PIN_CONFIG_BIAS_PULL_DOWN:
1021         val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
1022             PADS_PU_PD_SHIFT(pin);
1023         arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_DOWN;
1024         break;
1025     case PIN_CONFIG_BIAS_BUS_HOLD:
1026         val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
1027             PADS_PU_PD_SHIFT(pin);
1028         arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_BUS;
1029         break;
1030     case PIN_CONFIG_SLEW_RATE:
1031         val = pctl_readl(pctl, PADS_SLEW_RATE_REG(pin));
1032         arg = !!(val & PADS_SLEW_RATE_BIT(pin));
1033         break;
1034     case PIN_CONFIG_DRIVE_STRENGTH:
1035         val = pctl_readl(pctl, PADS_DRIVE_STRENGTH_REG(pin)) >>
1036             PADS_DRIVE_STRENGTH_SHIFT(pin);
1037         switch (val & PADS_DRIVE_STRENGTH_MASK) {
1038         case PADS_DRIVE_STRENGTH_2MA:
1039             arg = 2;
1040             break;
1041         case PADS_DRIVE_STRENGTH_4MA:
1042             arg = 4;
1043             break;
1044         case PADS_DRIVE_STRENGTH_8MA:
1045             arg = 8;
1046             break;
1047         case PADS_DRIVE_STRENGTH_12MA:
1048         default:
1049             arg = 12;
1050             break;
1051         }
1052         break;
1053     default:
1054         dev_dbg(pctl->dev, "Property %u not supported\n", param);
1055         return -ENOTSUPP;
1056     }
1057 
1058     *config = pinconf_to_config_packed(param, arg);
1059 
1060     return 0;
1061 }
1062 
1063 static int pistachio_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
1064                  unsigned long *configs, unsigned num_configs)
1065 {
1066     struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1067     enum pin_config_param param;
1068     u32 drv, val, arg;
1069     unsigned int i;
1070 
1071     for (i = 0; i < num_configs; i++) {
1072         param = pinconf_to_config_param(configs[i]);
1073         arg = pinconf_to_config_argument(configs[i]);
1074 
1075         switch (param) {
1076         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1077             val = pctl_readl(pctl, PADS_SCHMITT_EN_REG(pin));
1078             if (arg)
1079                 val |= PADS_SCHMITT_EN_BIT(pin);
1080             else
1081                 val &= ~PADS_SCHMITT_EN_BIT(pin);
1082             pctl_writel(pctl, val, PADS_SCHMITT_EN_REG(pin));
1083             break;
1084         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
1085             val = pctl_readl(pctl, PADS_PU_PD_REG(pin));
1086             val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));
1087             val |= PADS_PU_PD_HIGHZ << PADS_PU_PD_SHIFT(pin);
1088             pctl_writel(pctl, val, PADS_PU_PD_REG(pin));
1089             break;
1090         case PIN_CONFIG_BIAS_PULL_UP:
1091             val = pctl_readl(pctl, PADS_PU_PD_REG(pin));
1092             val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));
1093             val |= PADS_PU_PD_UP << PADS_PU_PD_SHIFT(pin);
1094             pctl_writel(pctl, val, PADS_PU_PD_REG(pin));
1095             break;
1096         case PIN_CONFIG_BIAS_PULL_DOWN:
1097             val = pctl_readl(pctl, PADS_PU_PD_REG(pin));
1098             val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));
1099             val |= PADS_PU_PD_DOWN << PADS_PU_PD_SHIFT(pin);
1100             pctl_writel(pctl, val, PADS_PU_PD_REG(pin));
1101             break;
1102         case PIN_CONFIG_BIAS_BUS_HOLD:
1103             val = pctl_readl(pctl, PADS_PU_PD_REG(pin));
1104             val &= ~(PADS_PU_PD_MASK << PADS_PU_PD_SHIFT(pin));
1105             val |= PADS_PU_PD_BUS << PADS_PU_PD_SHIFT(pin);
1106             pctl_writel(pctl, val, PADS_PU_PD_REG(pin));
1107             break;
1108         case PIN_CONFIG_SLEW_RATE:
1109             val = pctl_readl(pctl, PADS_SLEW_RATE_REG(pin));
1110             if (arg)
1111                 val |= PADS_SLEW_RATE_BIT(pin);
1112             else
1113                 val &= ~PADS_SLEW_RATE_BIT(pin);
1114             pctl_writel(pctl, val, PADS_SLEW_RATE_REG(pin));
1115             break;
1116         case PIN_CONFIG_DRIVE_STRENGTH:
1117             val = pctl_readl(pctl, PADS_DRIVE_STRENGTH_REG(pin));
1118             val &= ~(PADS_DRIVE_STRENGTH_MASK <<
1119                  PADS_DRIVE_STRENGTH_SHIFT(pin));
1120             switch (arg) {
1121             case 2:
1122                 drv = PADS_DRIVE_STRENGTH_2MA;
1123                 break;
1124             case 4:
1125                 drv = PADS_DRIVE_STRENGTH_4MA;
1126                 break;
1127             case 8:
1128                 drv = PADS_DRIVE_STRENGTH_8MA;
1129                 break;
1130             case 12:
1131                 drv = PADS_DRIVE_STRENGTH_12MA;
1132                 break;
1133             default:
1134                 dev_err(pctl->dev,
1135                     "Drive strength %umA not supported\n",
1136                     arg);
1137                 return -EINVAL;
1138             }
1139             val |= drv << PADS_DRIVE_STRENGTH_SHIFT(pin);
1140             pctl_writel(pctl, val, PADS_DRIVE_STRENGTH_REG(pin));
1141             break;
1142         default:
1143             dev_err(pctl->dev, "Property %u not supported\n",
1144                 param);
1145             return -ENOTSUPP;
1146         }
1147     }
1148 
1149     return 0;
1150 }
1151 
1152 static const struct pinconf_ops pistachio_pinconf_ops = {
1153     .pin_config_get = pistachio_pinconf_get,
1154     .pin_config_set = pistachio_pinconf_set,
1155     .is_generic = true,
1156 };
1157 
1158 static struct pinctrl_desc pistachio_pinctrl_desc = {
1159     .name = "pistachio-pinctrl",
1160     .pctlops = &pistachio_pinctrl_ops,
1161     .pmxops = &pistachio_pinmux_ops,
1162     .confops = &pistachio_pinconf_ops,
1163 };
1164 
1165 static int pistachio_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1166 {
1167     struct pistachio_gpio_bank *bank = gpiochip_get_data(chip);
1168 
1169     if (gpio_readl(bank, GPIO_OUTPUT_EN) & BIT(offset))
1170         return GPIO_LINE_DIRECTION_OUT;
1171 
1172     return GPIO_LINE_DIRECTION_IN;
1173 }
1174 
1175 static int pistachio_gpio_get(struct gpio_chip *chip, unsigned offset)
1176 {
1177     struct pistachio_gpio_bank *bank = gpiochip_get_data(chip);
1178     u32 reg;
1179 
1180     if (gpio_readl(bank, GPIO_OUTPUT_EN) & BIT(offset))
1181         reg = GPIO_OUTPUT;
1182     else
1183         reg = GPIO_INPUT;
1184 
1185     return !!(gpio_readl(bank, reg) & BIT(offset));
1186 }
1187 
1188 static void pistachio_gpio_set(struct gpio_chip *chip, unsigned offset,
1189                    int value)
1190 {
1191     struct pistachio_gpio_bank *bank = gpiochip_get_data(chip);
1192 
1193     gpio_mask_writel(bank, GPIO_OUTPUT, offset, !!value);
1194 }
1195 
1196 static int pistachio_gpio_direction_input(struct gpio_chip *chip,
1197                       unsigned offset)
1198 {
1199     struct pistachio_gpio_bank *bank = gpiochip_get_data(chip);
1200 
1201     gpio_mask_writel(bank, GPIO_OUTPUT_EN, offset, 0);
1202     gpio_enable(bank, offset);
1203 
1204     return 0;
1205 }
1206 
1207 static int pistachio_gpio_direction_output(struct gpio_chip *chip,
1208                        unsigned offset, int value)
1209 {
1210     struct pistachio_gpio_bank *bank = gpiochip_get_data(chip);
1211 
1212     pistachio_gpio_set(chip, offset, value);
1213     gpio_mask_writel(bank, GPIO_OUTPUT_EN, offset, 1);
1214     gpio_enable(bank, offset);
1215 
1216     return 0;
1217 }
1218 
1219 static void pistachio_gpio_irq_ack(struct irq_data *data)
1220 {
1221     struct pistachio_gpio_bank *bank = irqd_to_bank(data);
1222 
1223     gpio_mask_writel(bank, GPIO_INTERRUPT_STATUS, data->hwirq, 0);
1224 }
1225 
1226 static void pistachio_gpio_irq_mask(struct irq_data *data)
1227 {
1228     struct pistachio_gpio_bank *bank = irqd_to_bank(data);
1229 
1230     gpio_mask_writel(bank, GPIO_INTERRUPT_EN, data->hwirq, 0);
1231 }
1232 
1233 static void pistachio_gpio_irq_unmask(struct irq_data *data)
1234 {
1235     struct pistachio_gpio_bank *bank = irqd_to_bank(data);
1236 
1237     gpio_mask_writel(bank, GPIO_INTERRUPT_EN, data->hwirq, 1);
1238 }
1239 
1240 static unsigned int pistachio_gpio_irq_startup(struct irq_data *data)
1241 {
1242     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
1243 
1244     pistachio_gpio_direction_input(chip, data->hwirq);
1245     pistachio_gpio_irq_unmask(data);
1246 
1247     return 0;
1248 }
1249 
1250 static int pistachio_gpio_irq_set_type(struct irq_data *data, unsigned int type)
1251 {
1252     struct pistachio_gpio_bank *bank = irqd_to_bank(data);
1253 
1254     switch (type & IRQ_TYPE_SENSE_MASK) {
1255     case IRQ_TYPE_EDGE_RISING:
1256         gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 1);
1257         gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,
1258                  GPIO_INTERRUPT_TYPE_EDGE);
1259         gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, data->hwirq,
1260                  GPIO_INTERRUPT_EDGE_SINGLE);
1261         break;
1262     case IRQ_TYPE_EDGE_FALLING:
1263         gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 0);
1264         gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,
1265                  GPIO_INTERRUPT_TYPE_EDGE);
1266         gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, data->hwirq,
1267                  GPIO_INTERRUPT_EDGE_SINGLE);
1268         break;
1269     case IRQ_TYPE_EDGE_BOTH:
1270         gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,
1271                  GPIO_INTERRUPT_TYPE_EDGE);
1272         gpio_mask_writel(bank, GPIO_INTERRUPT_EDGE, data->hwirq,
1273                  GPIO_INTERRUPT_EDGE_DUAL);
1274         break;
1275     case IRQ_TYPE_LEVEL_HIGH:
1276         gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 1);
1277         gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,
1278                  GPIO_INTERRUPT_TYPE_LEVEL);
1279         break;
1280     case IRQ_TYPE_LEVEL_LOW:
1281         gpio_mask_writel(bank, GPIO_INPUT_POLARITY, data->hwirq, 0);
1282         gpio_mask_writel(bank, GPIO_INTERRUPT_TYPE, data->hwirq,
1283                  GPIO_INTERRUPT_TYPE_LEVEL);
1284         break;
1285     default:
1286         return -EINVAL;
1287     }
1288 
1289     if (type & IRQ_TYPE_LEVEL_MASK)
1290         irq_set_handler_locked(data, handle_level_irq);
1291     else
1292         irq_set_handler_locked(data, handle_edge_irq);
1293 
1294     return 0;
1295 }
1296 
1297 static void pistachio_gpio_irq_handler(struct irq_desc *desc)
1298 {
1299     struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1300     struct pistachio_gpio_bank *bank = gpiochip_get_data(gc);
1301     struct irq_chip *chip = irq_desc_get_chip(desc);
1302     unsigned long pending;
1303     unsigned int pin;
1304 
1305     chained_irq_enter(chip, desc);
1306     pending = gpio_readl(bank, GPIO_INTERRUPT_STATUS) &
1307         gpio_readl(bank, GPIO_INTERRUPT_EN);
1308     for_each_set_bit(pin, &pending, 16)
1309         generic_handle_domain_irq(gc->irq.domain, pin);
1310     chained_irq_exit(chip, desc);
1311 }
1312 
1313 #define GPIO_BANK(_bank, _pin_base, _npins)             \
1314     {                               \
1315         .pin_base = _pin_base,                  \
1316         .npins = _npins,                    \
1317         .gpio_chip = {                      \
1318             .label = "GPIO" #_bank,             \
1319             .request = gpiochip_generic_request,        \
1320             .free = gpiochip_generic_free,          \
1321             .get_direction = pistachio_gpio_get_direction,  \
1322             .direction_input = pistachio_gpio_direction_input, \
1323             .direction_output = pistachio_gpio_direction_output, \
1324             .get = pistachio_gpio_get,          \
1325             .set = pistachio_gpio_set,          \
1326             .base = _pin_base,              \
1327             .ngpio = _npins,                \
1328         },                          \
1329         .irq_chip = {                       \
1330             .name = "GPIO" #_bank,              \
1331             .irq_startup = pistachio_gpio_irq_startup,  \
1332             .irq_ack = pistachio_gpio_irq_ack,      \
1333             .irq_mask = pistachio_gpio_irq_mask,        \
1334             .irq_unmask = pistachio_gpio_irq_unmask,    \
1335             .irq_set_type = pistachio_gpio_irq_set_type,    \
1336         },                          \
1337     }
1338 
1339 static struct pistachio_gpio_bank pistachio_gpio_banks[] = {
1340     GPIO_BANK(0, PISTACHIO_PIN_MFIO(0), 16),
1341     GPIO_BANK(1, PISTACHIO_PIN_MFIO(16), 16),
1342     GPIO_BANK(2, PISTACHIO_PIN_MFIO(32), 16),
1343     GPIO_BANK(3, PISTACHIO_PIN_MFIO(48), 16),
1344     GPIO_BANK(4, PISTACHIO_PIN_MFIO(64), 16),
1345     GPIO_BANK(5, PISTACHIO_PIN_MFIO(80), 10),
1346 };
1347 
1348 static int pistachio_gpio_register(struct pistachio_pinctrl *pctl)
1349 {
1350     struct device_node *node = pctl->dev->of_node;
1351     struct pistachio_gpio_bank *bank;
1352     unsigned int i;
1353     int irq, ret = 0;
1354 
1355     for (i = 0; i < pctl->nbanks; i++) {
1356         char child_name[sizeof("gpioXX")];
1357         struct device_node *child;
1358         struct gpio_irq_chip *girq;
1359 
1360         snprintf(child_name, sizeof(child_name), "gpio%d", i);
1361         child = of_get_child_by_name(node, child_name);
1362         if (!child) {
1363             dev_err(pctl->dev, "No node for bank %u\n", i);
1364             ret = -ENODEV;
1365             goto err;
1366         }
1367 
1368         if (!of_find_property(child, "gpio-controller", NULL)) {
1369             dev_err(pctl->dev,
1370                 "No gpio-controller property for bank %u\n", i);
1371             of_node_put(child);
1372             ret = -ENODEV;
1373             goto err;
1374         }
1375 
1376         irq = irq_of_parse_and_map(child, 0);
1377         if (!irq) {
1378             dev_err(pctl->dev, "No IRQ for bank %u\n", i);
1379             of_node_put(child);
1380             ret = -EINVAL;
1381             goto err;
1382         }
1383 
1384         bank = &pctl->gpio_banks[i];
1385         bank->pctl = pctl;
1386         bank->base = pctl->base + GPIO_BANK_BASE(i);
1387 
1388         bank->gpio_chip.parent = pctl->dev;
1389         bank->gpio_chip.of_node = child;
1390 
1391         girq = &bank->gpio_chip.irq;
1392         girq->chip = &bank->irq_chip;
1393         girq->parent_handler = pistachio_gpio_irq_handler;
1394         girq->num_parents = 1;
1395         girq->parents = devm_kcalloc(pctl->dev, 1,
1396                          sizeof(*girq->parents),
1397                          GFP_KERNEL);
1398         if (!girq->parents) {
1399             ret = -ENOMEM;
1400             goto err;
1401         }
1402         girq->parents[0] = irq;
1403         girq->default_type = IRQ_TYPE_NONE;
1404         girq->handler = handle_level_irq;
1405 
1406         ret = gpiochip_add_data(&bank->gpio_chip, bank);
1407         if (ret < 0) {
1408             dev_err(pctl->dev, "Failed to add GPIO chip %u: %d\n",
1409                 i, ret);
1410             goto err;
1411         }
1412 
1413         ret = gpiochip_add_pin_range(&bank->gpio_chip,
1414                          dev_name(pctl->dev), 0,
1415                          bank->pin_base, bank->npins);
1416         if (ret < 0) {
1417             dev_err(pctl->dev, "Failed to add GPIO range %u: %d\n",
1418                 i, ret);
1419             gpiochip_remove(&bank->gpio_chip);
1420             goto err;
1421         }
1422     }
1423 
1424     return 0;
1425 err:
1426     for (; i > 0; i--) {
1427         bank = &pctl->gpio_banks[i - 1];
1428         gpiochip_remove(&bank->gpio_chip);
1429     }
1430     return ret;
1431 }
1432 
1433 static const struct of_device_id pistachio_pinctrl_of_match[] = {
1434     { .compatible = "img,pistachio-system-pinctrl", },
1435     { },
1436 };
1437 
1438 static int pistachio_pinctrl_probe(struct platform_device *pdev)
1439 {
1440     struct pistachio_pinctrl *pctl;
1441 
1442     pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1443     if (!pctl)
1444         return -ENOMEM;
1445     pctl->dev = &pdev->dev;
1446     dev_set_drvdata(&pdev->dev, pctl);
1447 
1448     pctl->base = devm_platform_ioremap_resource(pdev, 0);
1449     if (IS_ERR(pctl->base))
1450         return PTR_ERR(pctl->base);
1451 
1452     pctl->pins = pistachio_pins;
1453     pctl->npins = ARRAY_SIZE(pistachio_pins);
1454     pctl->functions = pistachio_functions;
1455     pctl->nfunctions = ARRAY_SIZE(pistachio_functions);
1456     pctl->groups = pistachio_groups;
1457     pctl->ngroups = ARRAY_SIZE(pistachio_groups);
1458     pctl->gpio_banks = pistachio_gpio_banks;
1459     pctl->nbanks = ARRAY_SIZE(pistachio_gpio_banks);
1460 
1461     pistachio_pinctrl_desc.pins = pctl->pins;
1462     pistachio_pinctrl_desc.npins = pctl->npins;
1463 
1464     pctl->pctldev = devm_pinctrl_register(&pdev->dev, &pistachio_pinctrl_desc,
1465                           pctl);
1466     if (IS_ERR(pctl->pctldev)) {
1467         dev_err(&pdev->dev, "Failed to register pinctrl device\n");
1468         return PTR_ERR(pctl->pctldev);
1469     }
1470 
1471     return pistachio_gpio_register(pctl);
1472 }
1473 
1474 static struct platform_driver pistachio_pinctrl_driver = {
1475     .driver = {
1476         .name = "pistachio-pinctrl",
1477         .of_match_table = pistachio_pinctrl_of_match,
1478         .suppress_bind_attrs = true,
1479     },
1480     .probe = pistachio_pinctrl_probe,
1481 };
1482 
1483 static int __init pistachio_pinctrl_register(void)
1484 {
1485     return platform_driver_register(&pistachio_pinctrl_driver);
1486 }
1487 arch_initcall(pistachio_pinctrl_register);
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