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0010 #include <linux/delay.h>
0011 #include <linux/module.h>
0012 #include <linux/mfd/palmas.h>
0013 #include <linux/of.h>
0014 #include <linux/of_device.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/pinctrl/machine.h>
0017 #include <linux/pinctrl/pinctrl.h>
0018 #include <linux/pinctrl/pinconf-generic.h>
0019 #include <linux/pinctrl/pinconf.h>
0020 #include <linux/pinctrl/pinmux.h>
0021 #include <linux/pm.h>
0022 #include <linux/slab.h>
0023
0024 #include "core.h"
0025 #include "pinconf.h"
0026 #include "pinctrl-utils.h"
0027
0028 #define PALMAS_PIN_GPIO0_ID 0
0029 #define PALMAS_PIN_GPIO1_VBUS_LED1_PWM1 1
0030 #define PALMAS_PIN_GPIO2_REGEN_LED2_PWM2 2
0031 #define PALMAS_PIN_GPIO3_CHRG_DET 3
0032 #define PALMAS_PIN_GPIO4_SYSEN1 4
0033 #define PALMAS_PIN_GPIO5_CLK32KGAUDIO_USB_PSEL 5
0034 #define PALMAS_PIN_GPIO6_SYSEN2 6
0035 #define PALMAS_PIN_GPIO7_MSECURE_PWRHOLD 7
0036 #define PALMAS_PIN_GPIO8_SIM1RSTI 8
0037 #define PALMAS_PIN_GPIO9_LOW_VBAT 9
0038 #define PALMAS_PIN_GPIO10_WIRELESS_CHRG1 10
0039 #define PALMAS_PIN_GPIO11_RCM 11
0040 #define PALMAS_PIN_GPIO12_SIM2RSTO 12
0041 #define PALMAS_PIN_GPIO13 13
0042 #define PALMAS_PIN_GPIO14 14
0043 #define PALMAS_PIN_GPIO15_SIM2RSTI 15
0044 #define PALMAS_PIN_VAC 16
0045 #define PALMAS_PIN_POWERGOOD_USB_PSEL 17
0046 #define PALMAS_PIN_NRESWARM 18
0047 #define PALMAS_PIN_PWRDOWN 19
0048 #define PALMAS_PIN_GPADC_START 20
0049 #define PALMAS_PIN_RESET_IN 21
0050 #define PALMAS_PIN_NSLEEP 22
0051 #define PALMAS_PIN_ENABLE1 23
0052 #define PALMAS_PIN_ENABLE2 24
0053 #define PALMAS_PIN_INT 25
0054 #define PALMAS_PIN_NUM (PALMAS_PIN_INT + 1)
0055
0056 struct palmas_pin_function {
0057 const char *name;
0058 const char * const *groups;
0059 unsigned ngroups;
0060 };
0061
0062 struct palmas_pctrl_chip_info {
0063 struct device *dev;
0064 struct pinctrl_dev *pctl;
0065 struct palmas *palmas;
0066 int pins_current_opt[PALMAS_PIN_NUM];
0067 const struct palmas_pin_function *functions;
0068 unsigned num_functions;
0069 const struct palmas_pingroup *pin_groups;
0070 int num_pin_groups;
0071 const struct pinctrl_pin_desc *pins;
0072 unsigned num_pins;
0073 };
0074
0075 static const struct pinctrl_pin_desc palmas_pins_desc[] = {
0076 PINCTRL_PIN(PALMAS_PIN_GPIO0_ID, "gpio0"),
0077 PINCTRL_PIN(PALMAS_PIN_GPIO1_VBUS_LED1_PWM1, "gpio1"),
0078 PINCTRL_PIN(PALMAS_PIN_GPIO2_REGEN_LED2_PWM2, "gpio2"),
0079 PINCTRL_PIN(PALMAS_PIN_GPIO3_CHRG_DET, "gpio3"),
0080 PINCTRL_PIN(PALMAS_PIN_GPIO4_SYSEN1, "gpio4"),
0081 PINCTRL_PIN(PALMAS_PIN_GPIO5_CLK32KGAUDIO_USB_PSEL, "gpio5"),
0082 PINCTRL_PIN(PALMAS_PIN_GPIO6_SYSEN2, "gpio6"),
0083 PINCTRL_PIN(PALMAS_PIN_GPIO7_MSECURE_PWRHOLD, "gpio7"),
0084 PINCTRL_PIN(PALMAS_PIN_GPIO8_SIM1RSTI, "gpio8"),
0085 PINCTRL_PIN(PALMAS_PIN_GPIO9_LOW_VBAT, "gpio9"),
0086 PINCTRL_PIN(PALMAS_PIN_GPIO10_WIRELESS_CHRG1, "gpio10"),
0087 PINCTRL_PIN(PALMAS_PIN_GPIO11_RCM, "gpio11"),
0088 PINCTRL_PIN(PALMAS_PIN_GPIO12_SIM2RSTO, "gpio12"),
0089 PINCTRL_PIN(PALMAS_PIN_GPIO13, "gpio13"),
0090 PINCTRL_PIN(PALMAS_PIN_GPIO14, "gpio14"),
0091 PINCTRL_PIN(PALMAS_PIN_GPIO15_SIM2RSTI, "gpio15"),
0092 PINCTRL_PIN(PALMAS_PIN_VAC, "vac"),
0093 PINCTRL_PIN(PALMAS_PIN_POWERGOOD_USB_PSEL, "powergood"),
0094 PINCTRL_PIN(PALMAS_PIN_NRESWARM, "nreswarm"),
0095 PINCTRL_PIN(PALMAS_PIN_PWRDOWN, "pwrdown"),
0096 PINCTRL_PIN(PALMAS_PIN_GPADC_START, "gpadc_start"),
0097 PINCTRL_PIN(PALMAS_PIN_RESET_IN, "reset_in"),
0098 PINCTRL_PIN(PALMAS_PIN_NSLEEP, "nsleep"),
0099 PINCTRL_PIN(PALMAS_PIN_ENABLE1, "enable1"),
0100 PINCTRL_PIN(PALMAS_PIN_ENABLE2, "enable2"),
0101 PINCTRL_PIN(PALMAS_PIN_INT, "int"),
0102 };
0103
0104 static const char * const opt0_groups[] = {
0105 "gpio0",
0106 "gpio1",
0107 "gpio2",
0108 "gpio3",
0109 "gpio4",
0110 "gpio5",
0111 "gpio6",
0112 "gpio7",
0113 "gpio8",
0114 "gpio9",
0115 "gpio10",
0116 "gpio11",
0117 "gpio12",
0118 "gpio13",
0119 "gpio14",
0120 "gpio15",
0121 "vac",
0122 "powergood",
0123 "nreswarm",
0124 "pwrdown",
0125 "gpadc_start",
0126 "reset_in",
0127 "nsleep",
0128 "enable1",
0129 "enable2",
0130 "int",
0131 };
0132
0133 static const char * const opt1_groups[] = {
0134 "gpio0",
0135 "gpio1",
0136 "gpio2",
0137 "gpio3",
0138 "gpio4",
0139 "gpio5",
0140 "gpio6",
0141 "gpio7",
0142 "gpio8",
0143 "gpio9",
0144 "gpio10",
0145 "gpio11",
0146 "gpio12",
0147 "gpio15",
0148 "vac",
0149 "powergood",
0150 };
0151
0152 static const char * const opt2_groups[] = {
0153 "gpio1",
0154 "gpio2",
0155 "gpio5",
0156 "gpio7",
0157 };
0158
0159 static const char * const opt3_groups[] = {
0160 "gpio1",
0161 "gpio2",
0162 };
0163
0164 static const char * const gpio_groups[] = {
0165 "gpio0",
0166 "gpio1",
0167 "gpio2",
0168 "gpio3",
0169 "gpio4",
0170 "gpio5",
0171 "gpio6",
0172 "gpio7",
0173 "gpio8",
0174 "gpio9",
0175 "gpio10",
0176 "gpio11",
0177 "gpio12",
0178 "gpio13",
0179 "gpio14",
0180 "gpio15",
0181 };
0182
0183 static const char * const led_groups[] = {
0184 "gpio1",
0185 "gpio2",
0186 };
0187
0188 static const char * const pwm_groups[] = {
0189 "gpio1",
0190 "gpio2",
0191 };
0192
0193 static const char * const regen_groups[] = {
0194 "gpio2",
0195 };
0196
0197 static const char * const sysen_groups[] = {
0198 "gpio4",
0199 "gpio6",
0200 };
0201
0202 static const char * const clk32kgaudio_groups[] = {
0203 "gpio5",
0204 };
0205
0206 static const char * const id_groups[] = {
0207 "gpio0",
0208 };
0209
0210 static const char * const vbus_det_groups[] = {
0211 "gpio1",
0212 };
0213
0214 static const char * const chrg_det_groups[] = {
0215 "gpio3",
0216 };
0217
0218 static const char * const vac_groups[] = {
0219 "vac",
0220 };
0221
0222 static const char * const vacok_groups[] = {
0223 "vac",
0224 };
0225
0226 static const char * const powergood_groups[] = {
0227 "powergood",
0228 };
0229
0230 static const char * const usb_psel_groups[] = {
0231 "gpio5",
0232 "powergood",
0233 };
0234
0235 static const char * const msecure_groups[] = {
0236 "gpio7",
0237 };
0238
0239 static const char * const pwrhold_groups[] = {
0240 "gpio7",
0241 };
0242
0243 static const char * const int_groups[] = {
0244 "int",
0245 };
0246
0247 static const char * const nreswarm_groups[] = {
0248 "nreswarm",
0249 };
0250
0251 static const char * const simrsto_groups[] = {
0252 "gpio12",
0253 };
0254
0255 static const char * const simrsti_groups[] = {
0256 "gpio8",
0257 "gpio15",
0258 };
0259
0260 static const char * const low_vbat_groups[] = {
0261 "gpio9",
0262 };
0263
0264 static const char * const wireless_chrg1_groups[] = {
0265 "gpio10",
0266 };
0267
0268 static const char * const rcm_groups[] = {
0269 "gpio11",
0270 };
0271
0272 static const char * const pwrdown_groups[] = {
0273 "pwrdown",
0274 };
0275
0276 static const char * const gpadc_start_groups[] = {
0277 "gpadc_start",
0278 };
0279
0280 static const char * const reset_in_groups[] = {
0281 "reset_in",
0282 };
0283
0284 static const char * const nsleep_groups[] = {
0285 "nsleep",
0286 };
0287
0288 static const char * const enable_groups[] = {
0289 "enable1",
0290 "enable2",
0291 };
0292
0293 #define FUNCTION_GROUPS \
0294 FUNCTION_GROUP(opt0, OPTION0), \
0295 FUNCTION_GROUP(opt1, OPTION1), \
0296 FUNCTION_GROUP(opt2, OPTION2), \
0297 FUNCTION_GROUP(opt3, OPTION3), \
0298 FUNCTION_GROUP(gpio, GPIO), \
0299 FUNCTION_GROUP(led, LED), \
0300 FUNCTION_GROUP(pwm, PWM), \
0301 FUNCTION_GROUP(regen, REGEN), \
0302 FUNCTION_GROUP(sysen, SYSEN), \
0303 FUNCTION_GROUP(clk32kgaudio, CLK32KGAUDIO), \
0304 FUNCTION_GROUP(id, ID), \
0305 FUNCTION_GROUP(vbus_det, VBUS_DET), \
0306 FUNCTION_GROUP(chrg_det, CHRG_DET), \
0307 FUNCTION_GROUP(vac, VAC), \
0308 FUNCTION_GROUP(vacok, VACOK), \
0309 FUNCTION_GROUP(powergood, POWERGOOD), \
0310 FUNCTION_GROUP(usb_psel, USB_PSEL), \
0311 FUNCTION_GROUP(msecure, MSECURE), \
0312 FUNCTION_GROUP(pwrhold, PWRHOLD), \
0313 FUNCTION_GROUP(int, INT), \
0314 FUNCTION_GROUP(nreswarm, NRESWARM), \
0315 FUNCTION_GROUP(simrsto, SIMRSTO), \
0316 FUNCTION_GROUP(simrsti, SIMRSTI), \
0317 FUNCTION_GROUP(low_vbat, LOW_VBAT), \
0318 FUNCTION_GROUP(wireless_chrg1, WIRELESS_CHRG1), \
0319 FUNCTION_GROUP(rcm, RCM), \
0320 FUNCTION_GROUP(pwrdown, PWRDOWN), \
0321 FUNCTION_GROUP(gpadc_start, GPADC_START), \
0322 FUNCTION_GROUP(reset_in, RESET_IN), \
0323 FUNCTION_GROUP(nsleep, NSLEEP), \
0324 FUNCTION_GROUP(enable, ENABLE)
0325
0326 static const struct palmas_pin_function palmas_pin_function[] = {
0327 #undef FUNCTION_GROUP
0328 #define FUNCTION_GROUP(fname, mux) \
0329 { \
0330 .name = #fname, \
0331 .groups = fname##_groups, \
0332 .ngroups = ARRAY_SIZE(fname##_groups), \
0333 }
0334
0335 FUNCTION_GROUPS,
0336 };
0337
0338 enum palmas_pinmux {
0339 #undef FUNCTION_GROUP
0340 #define FUNCTION_GROUP(fname, mux) PALMAS_PINMUX_##mux
0341 FUNCTION_GROUPS,
0342 PALMAS_PINMUX_NA = 0xFFFF,
0343 };
0344
0345 struct palmas_pins_pullup_dn_info {
0346 int pullup_dn_reg_base;
0347 int pullup_dn_reg_add;
0348 int pullup_dn_mask;
0349 int normal_val;
0350 int pull_up_val;
0351 int pull_dn_val;
0352 };
0353
0354 struct palmas_pins_od_info {
0355 int od_reg_base;
0356 int od_reg_add;
0357 int od_mask;
0358 int od_enable;
0359 int od_disable;
0360 };
0361
0362 struct palmas_pin_info {
0363 enum palmas_pinmux mux_opt;
0364 const struct palmas_pins_pullup_dn_info *pud_info;
0365 const struct palmas_pins_od_info *od_info;
0366 };
0367
0368 struct palmas_pingroup {
0369 const char *name;
0370 const unsigned pins[1];
0371 unsigned npins;
0372 unsigned mux_reg_base;
0373 unsigned mux_reg_add;
0374 unsigned mux_reg_mask;
0375 unsigned mux_bit_shift;
0376 const struct palmas_pin_info *opt[4];
0377 };
0378
0379 #define PULL_UP_DN(_name, _rbase, _add, _mask, _nv, _uv, _dv) \
0380 static const struct palmas_pins_pullup_dn_info pud_##_name##_info = { \
0381 .pullup_dn_reg_base = PALMAS_##_rbase##_BASE, \
0382 .pullup_dn_reg_add = _add, \
0383 .pullup_dn_mask = _mask, \
0384 .normal_val = _nv, \
0385 .pull_up_val = _uv, \
0386 .pull_dn_val = _dv, \
0387 }
0388
0389 PULL_UP_DN(nreswarm, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL1, 0x2, 0x0, 0x2, -1);
0390 PULL_UP_DN(pwrdown, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL1, 0x4, 0x0, -1, 0x4);
0391 PULL_UP_DN(gpadc_start, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL1, 0x30, 0x0, 0x20, 0x10);
0392 PULL_UP_DN(reset_in, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL1, 0x40, 0x0, -1, 0x40);
0393 PULL_UP_DN(nsleep, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL2, 0x3, 0x0, 0x2, 0x1);
0394 PULL_UP_DN(enable1, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL2, 0xC, 0x0, 0x8, 0x4);
0395 PULL_UP_DN(enable2, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL2, 0x30, 0x0, 0x20, 0x10);
0396 PULL_UP_DN(vacok, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL3, 0x40, 0x0, -1, 0x40);
0397 PULL_UP_DN(chrg_det, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL3, 0x10, 0x0, -1, 0x10);
0398 PULL_UP_DN(pwrhold, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL3, 0x4, 0x0, -1, 0x4);
0399 PULL_UP_DN(msecure, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL3, 0x1, 0x0, -1, 0x1);
0400 PULL_UP_DN(id, USB_OTG, PALMAS_USB_ID_CTRL_SET, 0x40, 0x0, 0x40, -1);
0401 PULL_UP_DN(gpio0, GPIO, PALMAS_PU_PD_GPIO_CTRL1, 0x04, 0, -1, 1);
0402 PULL_UP_DN(gpio1, GPIO, PALMAS_PU_PD_GPIO_CTRL1, 0x0C, 0, 0x8, 0x4);
0403 PULL_UP_DN(gpio2, GPIO, PALMAS_PU_PD_GPIO_CTRL1, 0x30, 0x0, 0x20, 0x10);
0404 PULL_UP_DN(gpio3, GPIO, PALMAS_PU_PD_GPIO_CTRL1, 0x40, 0x0, -1, 0x40);
0405 PULL_UP_DN(gpio4, GPIO, PALMAS_PU_PD_GPIO_CTRL2, 0x03, 0x0, 0x2, 0x1);
0406 PULL_UP_DN(gpio5, GPIO, PALMAS_PU_PD_GPIO_CTRL2, 0x0c, 0x0, 0x8, 0x4);
0407 PULL_UP_DN(gpio6, GPIO, PALMAS_PU_PD_GPIO_CTRL2, 0x30, 0x0, 0x20, 0x10);
0408 PULL_UP_DN(gpio7, GPIO, PALMAS_PU_PD_GPIO_CTRL2, 0x40, 0x0, -1, 0x40);
0409 PULL_UP_DN(gpio9, GPIO, PALMAS_PU_PD_GPIO_CTRL3, 0x0C, 0x0, 0x8, 0x4);
0410 PULL_UP_DN(gpio10, GPIO, PALMAS_PU_PD_GPIO_CTRL3, 0x30, 0x0, 0x20, 0x10);
0411 PULL_UP_DN(gpio11, GPIO, PALMAS_PU_PD_GPIO_CTRL3, 0xC0, 0x0, 0x80, 0x40);
0412 PULL_UP_DN(gpio13, GPIO, PALMAS_PU_PD_GPIO_CTRL4, 0x04, 0x0, -1, 0x04);
0413 PULL_UP_DN(gpio14, GPIO, PALMAS_PU_PD_GPIO_CTRL4, 0x30, 0x0, 0x20, 0x10);
0414
0415 #define OD_INFO(_name, _rbase, _add, _mask, _ev, _dv) \
0416 static const struct palmas_pins_od_info od_##_name##_info = { \
0417 .od_reg_base = PALMAS_##_rbase##_BASE, \
0418 .od_reg_add = _add, \
0419 .od_mask = _mask, \
0420 .od_enable = _ev, \
0421 .od_disable = _dv, \
0422 }
0423
0424 OD_INFO(gpio1, GPIO, PALMAS_OD_OUTPUT_GPIO_CTRL, 0x1, 0x1, 0x0);
0425 OD_INFO(gpio2, GPIO, PALMAS_OD_OUTPUT_GPIO_CTRL, 0x2, 0x2, 0x0);
0426 OD_INFO(gpio5, GPIO, PALMAS_OD_OUTPUT_GPIO_CTRL, 0x20, 0x20, 0x0);
0427 OD_INFO(gpio10, GPIO, PALMAS_OD_OUTPUT_GPIO_CTRL2, 0x04, 0x04, 0x0);
0428 OD_INFO(gpio13, GPIO, PALMAS_OD_OUTPUT_GPIO_CTRL2, 0x20, 0x20, 0x0);
0429 OD_INFO(int, PU_PD_OD, PALMAS_OD_OUTPUT_CTRL, 0x8, 0x8, 0x0);
0430 OD_INFO(pwm1, PU_PD_OD, PALMAS_OD_OUTPUT_CTRL, 0x20, 0x20, 0x0);
0431 OD_INFO(pwm2, PU_PD_OD, PALMAS_OD_OUTPUT_CTRL, 0x80, 0x80, 0x0);
0432 OD_INFO(vbus_det, PU_PD_OD, PALMAS_OD_OUTPUT_CTRL, 0x40, 0x40, 0x0);
0433
0434 #define PIN_INFO(_name, _id, _pud_info, _od_info) \
0435 static const struct palmas_pin_info pin_##_name##_info = { \
0436 .mux_opt = PALMAS_PINMUX_##_id, \
0437 .pud_info = _pud_info, \
0438 .od_info = _od_info \
0439 }
0440
0441 PIN_INFO(gpio0, GPIO, &pud_gpio0_info, NULL);
0442 PIN_INFO(gpio1, GPIO, &pud_gpio1_info, &od_gpio1_info);
0443 PIN_INFO(gpio2, GPIO, &pud_gpio2_info, &od_gpio2_info);
0444 PIN_INFO(gpio3, GPIO, &pud_gpio3_info, NULL);
0445 PIN_INFO(gpio4, GPIO, &pud_gpio4_info, NULL);
0446 PIN_INFO(gpio5, GPIO, &pud_gpio5_info, &od_gpio5_info);
0447 PIN_INFO(gpio6, GPIO, &pud_gpio6_info, NULL);
0448 PIN_INFO(gpio7, GPIO, &pud_gpio7_info, NULL);
0449 PIN_INFO(gpio8, GPIO, NULL, NULL);
0450 PIN_INFO(gpio9, GPIO, &pud_gpio9_info, NULL);
0451 PIN_INFO(gpio10, GPIO, &pud_gpio10_info, &od_gpio10_info);
0452 PIN_INFO(gpio11, GPIO, &pud_gpio11_info, NULL);
0453 PIN_INFO(gpio12, GPIO, NULL, NULL);
0454 PIN_INFO(gpio13, GPIO, &pud_gpio13_info, &od_gpio13_info);
0455 PIN_INFO(gpio14, GPIO, &pud_gpio14_info, NULL);
0456 PIN_INFO(gpio15, GPIO, NULL, NULL);
0457 PIN_INFO(id, ID, &pud_id_info, NULL);
0458 PIN_INFO(led1, LED, NULL, NULL);
0459 PIN_INFO(led2, LED, NULL, NULL);
0460 PIN_INFO(regen, REGEN, NULL, NULL);
0461 PIN_INFO(sysen1, SYSEN, NULL, NULL);
0462 PIN_INFO(sysen2, SYSEN, NULL, NULL);
0463 PIN_INFO(int, INT, NULL, &od_int_info);
0464 PIN_INFO(pwm1, PWM, NULL, &od_pwm1_info);
0465 PIN_INFO(pwm2, PWM, NULL, &od_pwm2_info);
0466 PIN_INFO(vacok, VACOK, &pud_vacok_info, NULL);
0467 PIN_INFO(chrg_det, CHRG_DET, &pud_chrg_det_info, NULL);
0468 PIN_INFO(pwrhold, PWRHOLD, &pud_pwrhold_info, NULL);
0469 PIN_INFO(msecure, MSECURE, &pud_msecure_info, NULL);
0470 PIN_INFO(nreswarm, NA, &pud_nreswarm_info, NULL);
0471 PIN_INFO(pwrdown, NA, &pud_pwrdown_info, NULL);
0472 PIN_INFO(gpadc_start, NA, &pud_gpadc_start_info, NULL);
0473 PIN_INFO(reset_in, NA, &pud_reset_in_info, NULL);
0474 PIN_INFO(nsleep, NA, &pud_nsleep_info, NULL);
0475 PIN_INFO(enable1, NA, &pud_enable1_info, NULL);
0476 PIN_INFO(enable2, NA, &pud_enable2_info, NULL);
0477 PIN_INFO(clk32kgaudio, CLK32KGAUDIO, NULL, NULL);
0478 PIN_INFO(usb_psel, USB_PSEL, NULL, NULL);
0479 PIN_INFO(vac, VAC, NULL, NULL);
0480 PIN_INFO(powergood, POWERGOOD, NULL, NULL);
0481 PIN_INFO(vbus_det, VBUS_DET, NULL, &od_vbus_det_info);
0482 PIN_INFO(sim1rsti, SIMRSTI, NULL, NULL);
0483 PIN_INFO(low_vbat, LOW_VBAT, NULL, NULL);
0484 PIN_INFO(rcm, RCM, NULL, NULL);
0485 PIN_INFO(sim2rsto, SIMRSTO, NULL, NULL);
0486 PIN_INFO(sim2rsti, SIMRSTI, NULL, NULL);
0487 PIN_INFO(wireless_chrg1, WIRELESS_CHRG1, NULL, NULL);
0488
0489 #define PALMAS_PRIMARY_SECONDARY_NONE 0
0490 #define PALMAS_NONE_BASE 0
0491 #define PALMAS_PRIMARY_SECONDARY_INPUT3 PALMAS_PU_PD_INPUT_CTRL3
0492
0493 #define PALMAS_PINGROUP(pg_name, pin_id, base, reg, _mask, _bshift, o0, o1, o2, o3) \
0494 { \
0495 .name = #pg_name, \
0496 .pins = {PALMAS_PIN_##pin_id}, \
0497 .npins = 1, \
0498 .mux_reg_base = PALMAS_##base##_BASE, \
0499 .mux_reg_add = PALMAS_PRIMARY_SECONDARY_##reg, \
0500 .mux_reg_mask = _mask, \
0501 .mux_bit_shift = _bshift, \
0502 .opt = { \
0503 o0, \
0504 o1, \
0505 o2, \
0506 o3, \
0507 }, \
0508 }
0509
0510 static const struct palmas_pingroup tps65913_pingroups[] = {
0511 PALMAS_PINGROUP(gpio0, GPIO0_ID, PU_PD_OD, PAD1, 0x4, 0x2, &pin_gpio0_info, &pin_id_info, NULL, NULL),
0512 PALMAS_PINGROUP(gpio1, GPIO1_VBUS_LED1_PWM1, PU_PD_OD, PAD1, 0x18, 0x3, &pin_gpio1_info, &pin_vbus_det_info, &pin_led1_info, &pin_pwm1_info),
0513 PALMAS_PINGROUP(gpio2, GPIO2_REGEN_LED2_PWM2, PU_PD_OD, PAD1, 0x60, 0x5, &pin_gpio2_info, &pin_regen_info, &pin_led2_info, &pin_pwm2_info),
0514 PALMAS_PINGROUP(gpio3, GPIO3_CHRG_DET, PU_PD_OD, PAD1, 0x80, 0x7, &pin_gpio3_info, &pin_chrg_det_info, NULL, NULL),
0515 PALMAS_PINGROUP(gpio4, GPIO4_SYSEN1, PU_PD_OD, PAD1, 0x01, 0x0, &pin_gpio4_info, &pin_sysen1_info, NULL, NULL),
0516 PALMAS_PINGROUP(gpio5, GPIO5_CLK32KGAUDIO_USB_PSEL, PU_PD_OD, PAD2, 0x6, 0x1, &pin_gpio5_info, &pin_clk32kgaudio_info, &pin_usb_psel_info, NULL),
0517 PALMAS_PINGROUP(gpio6, GPIO6_SYSEN2, PU_PD_OD, PAD2, 0x08, 0x3, &pin_gpio6_info, &pin_sysen2_info, NULL, NULL),
0518 PALMAS_PINGROUP(gpio7, GPIO7_MSECURE_PWRHOLD, PU_PD_OD, PAD2, 0x30, 0x4, &pin_gpio7_info, &pin_msecure_info, &pin_pwrhold_info, NULL),
0519 PALMAS_PINGROUP(vac, VAC, PU_PD_OD, PAD1, 0x02, 0x1, &pin_vac_info, &pin_vacok_info, NULL, NULL),
0520 PALMAS_PINGROUP(powergood, POWERGOOD_USB_PSEL, PU_PD_OD, PAD1, 0x01, 0x0, &pin_powergood_info, &pin_usb_psel_info, NULL, NULL),
0521 PALMAS_PINGROUP(nreswarm, NRESWARM, NONE, NONE, 0x0, 0x0, &pin_nreswarm_info, NULL, NULL, NULL),
0522 PALMAS_PINGROUP(pwrdown, PWRDOWN, NONE, NONE, 0x0, 0x0, &pin_pwrdown_info, NULL, NULL, NULL),
0523 PALMAS_PINGROUP(gpadc_start, GPADC_START, NONE, NONE, 0x0, 0x0, &pin_gpadc_start_info, NULL, NULL, NULL),
0524 PALMAS_PINGROUP(reset_in, RESET_IN, NONE, NONE, 0x0, 0x0, &pin_reset_in_info, NULL, NULL, NULL),
0525 PALMAS_PINGROUP(nsleep, NSLEEP, NONE, NONE, 0x0, 0x0, &pin_nsleep_info, NULL, NULL, NULL),
0526 PALMAS_PINGROUP(enable1, ENABLE1, NONE, NONE, 0x0, 0x0, &pin_enable1_info, NULL, NULL, NULL),
0527 PALMAS_PINGROUP(enable2, ENABLE2, NONE, NONE, 0x0, 0x0, &pin_enable2_info, NULL, NULL, NULL),
0528 PALMAS_PINGROUP(int, INT, NONE, NONE, 0x0, 0x0, &pin_int_info, NULL, NULL, NULL),
0529 };
0530
0531 static const struct palmas_pingroup tps80036_pingroups[] = {
0532 PALMAS_PINGROUP(gpio0, GPIO0_ID, PU_PD_OD, PAD1, 0x4, 0x2, &pin_gpio0_info, &pin_id_info, NULL, NULL),
0533 PALMAS_PINGROUP(gpio1, GPIO1_VBUS_LED1_PWM1, PU_PD_OD, PAD1, 0x18, 0x3, &pin_gpio1_info, &pin_vbus_det_info, &pin_led1_info, &pin_pwm1_info),
0534 PALMAS_PINGROUP(gpio2, GPIO2_REGEN_LED2_PWM2, PU_PD_OD, PAD1, 0x60, 0x5, &pin_gpio2_info, &pin_regen_info, &pin_led2_info, &pin_pwm2_info),
0535 PALMAS_PINGROUP(gpio3, GPIO3_CHRG_DET, PU_PD_OD, PAD1, 0x80, 0x7, &pin_gpio3_info, &pin_chrg_det_info, NULL, NULL),
0536 PALMAS_PINGROUP(gpio4, GPIO4_SYSEN1, PU_PD_OD, PAD1, 0x01, 0x0, &pin_gpio4_info, &pin_sysen1_info, NULL, NULL),
0537 PALMAS_PINGROUP(gpio5, GPIO5_CLK32KGAUDIO_USB_PSEL, PU_PD_OD, PAD2, 0x6, 0x1, &pin_gpio5_info, &pin_clk32kgaudio_info, &pin_usb_psel_info, NULL),
0538 PALMAS_PINGROUP(gpio6, GPIO6_SYSEN2, PU_PD_OD, PAD2, 0x08, 0x3, &pin_gpio6_info, &pin_sysen2_info, NULL, NULL),
0539 PALMAS_PINGROUP(gpio7, GPIO7_MSECURE_PWRHOLD, PU_PD_OD, PAD2, 0x30, 0x4, &pin_gpio7_info, &pin_msecure_info, &pin_pwrhold_info, NULL),
0540 PALMAS_PINGROUP(gpio8, GPIO8_SIM1RSTI, PU_PD_OD, PAD4, 0x01, 0x0, &pin_gpio8_info, &pin_sim1rsti_info, NULL, NULL),
0541 PALMAS_PINGROUP(gpio9, GPIO9_LOW_VBAT, PU_PD_OD, PAD4, 0x02, 0x1, &pin_gpio9_info, &pin_low_vbat_info, NULL, NULL),
0542 PALMAS_PINGROUP(gpio10, GPIO10_WIRELESS_CHRG1, PU_PD_OD, PAD4, 0x04, 0x2, &pin_gpio10_info, &pin_wireless_chrg1_info, NULL, NULL),
0543 PALMAS_PINGROUP(gpio11, GPIO11_RCM, PU_PD_OD, PAD4, 0x08, 0x3, &pin_gpio11_info, &pin_rcm_info, NULL, NULL),
0544 PALMAS_PINGROUP(gpio12, GPIO12_SIM2RSTO, PU_PD_OD, PAD4, 0x10, 0x4, &pin_gpio12_info, &pin_sim2rsto_info, NULL, NULL),
0545 PALMAS_PINGROUP(gpio13, GPIO13, NONE, NONE, 0x00, 0x0, &pin_gpio13_info, NULL, NULL, NULL),
0546 PALMAS_PINGROUP(gpio14, GPIO14, NONE, NONE, 0x00, 0x0, &pin_gpio14_info, NULL, NULL, NULL),
0547 PALMAS_PINGROUP(gpio15, GPIO15_SIM2RSTI, PU_PD_OD, PAD4, 0x80, 0x7, &pin_gpio15_info, &pin_sim2rsti_info, NULL, NULL),
0548 PALMAS_PINGROUP(vac, VAC, PU_PD_OD, PAD1, 0x02, 0x1, &pin_vac_info, &pin_vacok_info, NULL, NULL),
0549 PALMAS_PINGROUP(powergood, POWERGOOD_USB_PSEL, PU_PD_OD, PAD1, 0x01, 0x0, &pin_powergood_info, &pin_usb_psel_info, NULL, NULL),
0550 PALMAS_PINGROUP(nreswarm, NRESWARM, NONE, NONE, 0x0, 0x0, &pin_nreswarm_info, NULL, NULL, NULL),
0551 PALMAS_PINGROUP(pwrdown, PWRDOWN, NONE, NONE, 0x0, 0x0, &pin_pwrdown_info, NULL, NULL, NULL),
0552 PALMAS_PINGROUP(gpadc_start, GPADC_START, NONE, NONE, 0x0, 0x0, &pin_gpadc_start_info, NULL, NULL, NULL),
0553 PALMAS_PINGROUP(reset_in, RESET_IN, NONE, NONE, 0x0, 0x0, &pin_reset_in_info, NULL, NULL, NULL),
0554 PALMAS_PINGROUP(nsleep, NSLEEP, NONE, NONE, 0x0, 0x0, &pin_nsleep_info, NULL, NULL, NULL),
0555 PALMAS_PINGROUP(enable1, ENABLE1, NONE, NONE, 0x0, 0x0, &pin_enable1_info, NULL, NULL, NULL),
0556 PALMAS_PINGROUP(enable2, ENABLE2, NONE, NONE, 0x0, 0x0, &pin_enable2_info, NULL, NULL, NULL),
0557 PALMAS_PINGROUP(int, INT, NONE, NONE, 0x0, 0x0, &pin_int_info, NULL, NULL, NULL),
0558 };
0559
0560 static int palmas_pinctrl_get_pin_mux(struct palmas_pctrl_chip_info *pci)
0561 {
0562 const struct palmas_pingroup *g;
0563 unsigned int val;
0564 int ret;
0565 int i;
0566
0567 for (i = 0; i < pci->num_pin_groups; ++i) {
0568 g = &pci->pin_groups[i];
0569 if (g->mux_reg_base == PALMAS_NONE_BASE) {
0570 pci->pins_current_opt[i] = 0;
0571 continue;
0572 }
0573 ret = palmas_read(pci->palmas, g->mux_reg_base,
0574 g->mux_reg_add, &val);
0575 if (ret < 0) {
0576 dev_err(pci->dev, "mux_reg 0x%02x read failed: %d\n",
0577 g->mux_reg_add, ret);
0578 return ret;
0579 }
0580 val &= g->mux_reg_mask;
0581 pci->pins_current_opt[i] = val >> g->mux_bit_shift;
0582 }
0583 return 0;
0584 }
0585
0586 static int palmas_pinctrl_set_dvfs1(struct palmas_pctrl_chip_info *pci,
0587 bool enable)
0588 {
0589 int ret;
0590 int val;
0591
0592 val = enable ? PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 : 0;
0593 ret = palmas_update_bits(pci->palmas, PALMAS_PU_PD_OD_BASE,
0594 PALMAS_PRIMARY_SECONDARY_PAD3,
0595 PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1, val);
0596 if (ret < 0)
0597 dev_err(pci->dev, "SECONDARY_PAD3 update failed %d\n", ret);
0598 return ret;
0599 }
0600
0601 static int palmas_pinctrl_set_dvfs2(struct palmas_pctrl_chip_info *pci,
0602 bool enable)
0603 {
0604 int ret;
0605 int val;
0606
0607 val = enable ? PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 : 0;
0608 ret = palmas_update_bits(pci->palmas, PALMAS_PU_PD_OD_BASE,
0609 PALMAS_PRIMARY_SECONDARY_PAD3,
0610 PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2, val);
0611 if (ret < 0)
0612 dev_err(pci->dev, "SECONDARY_PAD3 update failed %d\n", ret);
0613 return ret;
0614 }
0615
0616 static int palmas_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
0617 {
0618 struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
0619
0620 return pci->num_pin_groups;
0621 }
0622
0623 static const char *palmas_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
0624 unsigned group)
0625 {
0626 struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
0627
0628 return pci->pin_groups[group].name;
0629 }
0630
0631 static int palmas_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
0632 unsigned group, const unsigned **pins, unsigned *num_pins)
0633 {
0634 struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
0635
0636 *pins = pci->pin_groups[group].pins;
0637 *num_pins = pci->pin_groups[group].npins;
0638 return 0;
0639 }
0640
0641 static const struct pinctrl_ops palmas_pinctrl_ops = {
0642 .get_groups_count = palmas_pinctrl_get_groups_count,
0643 .get_group_name = palmas_pinctrl_get_group_name,
0644 .get_group_pins = palmas_pinctrl_get_group_pins,
0645 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
0646 .dt_free_map = pinctrl_utils_free_map,
0647 };
0648
0649 static int palmas_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
0650 {
0651 struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
0652
0653 return pci->num_functions;
0654 }
0655
0656 static const char *palmas_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
0657 unsigned function)
0658 {
0659 struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
0660
0661 return pci->functions[function].name;
0662 }
0663
0664 static int palmas_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
0665 unsigned function, const char * const **groups,
0666 unsigned * const num_groups)
0667 {
0668 struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
0669
0670 *groups = pci->functions[function].groups;
0671 *num_groups = pci->functions[function].ngroups;
0672 return 0;
0673 }
0674
0675 static int palmas_pinctrl_set_mux(struct pinctrl_dev *pctldev,
0676 unsigned function,
0677 unsigned group)
0678 {
0679 struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
0680 const struct palmas_pingroup *g;
0681 int i;
0682 int ret;
0683
0684 g = &pci->pin_groups[group];
0685
0686
0687 if (function <= PALMAS_PINMUX_OPTION3) {
0688 if (!g->opt[function]) {
0689 dev_err(pci->dev, "Pin %s does not support option %d\n",
0690 g->name, function);
0691 return -EINVAL;
0692 }
0693 i = function;
0694 } else {
0695 for (i = 0; i < ARRAY_SIZE(g->opt); i++) {
0696 if (!g->opt[i])
0697 continue;
0698 if (g->opt[i]->mux_opt == function)
0699 break;
0700 }
0701 if (WARN_ON(i == ARRAY_SIZE(g->opt))) {
0702 dev_err(pci->dev, "Pin %s does not support option %d\n",
0703 g->name, function);
0704 return -EINVAL;
0705 }
0706 }
0707
0708 if (g->mux_reg_base == PALMAS_NONE_BASE) {
0709 if (WARN_ON(i != 0))
0710 return -EINVAL;
0711 return 0;
0712 }
0713
0714 dev_dbg(pci->dev, "%s(): Base0x%02x:0x%02x:0x%02x:0x%02x\n",
0715 __func__, g->mux_reg_base, g->mux_reg_add,
0716 g->mux_reg_mask, i << g->mux_bit_shift);
0717
0718 ret = palmas_update_bits(pci->palmas, g->mux_reg_base, g->mux_reg_add,
0719 g->mux_reg_mask, i << g->mux_bit_shift);
0720 if (ret < 0) {
0721 dev_err(pci->dev, "Reg 0x%02x update failed: %d\n",
0722 g->mux_reg_add, ret);
0723 return ret;
0724 }
0725 pci->pins_current_opt[group] = i;
0726 return 0;
0727 }
0728
0729 static const struct pinmux_ops palmas_pinmux_ops = {
0730 .get_functions_count = palmas_pinctrl_get_funcs_count,
0731 .get_function_name = palmas_pinctrl_get_func_name,
0732 .get_function_groups = palmas_pinctrl_get_func_groups,
0733 .set_mux = palmas_pinctrl_set_mux,
0734 };
0735
0736 static int palmas_pinconf_get(struct pinctrl_dev *pctldev,
0737 unsigned pin, unsigned long *config)
0738 {
0739 struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
0740 enum pin_config_param param = pinconf_to_config_param(*config);
0741 const struct palmas_pingroup *g;
0742 const struct palmas_pin_info *opt;
0743 unsigned int val;
0744 int ret;
0745 int base, add;
0746 int rval;
0747 int arg;
0748 int group_nr;
0749
0750 for (group_nr = 0; group_nr < pci->num_pin_groups; ++group_nr) {
0751 if (pci->pin_groups[group_nr].pins[0] == pin)
0752 break;
0753 }
0754
0755 if (group_nr == pci->num_pin_groups) {
0756 dev_err(pci->dev,
0757 "Pinconf is not supported for pin-id %d\n", pin);
0758 return -ENOTSUPP;
0759 }
0760
0761 g = &pci->pin_groups[group_nr];
0762 opt = g->opt[pci->pins_current_opt[group_nr]];
0763 if (!opt) {
0764 dev_err(pci->dev,
0765 "Pinconf is not supported for pin %s\n", g->name);
0766 return -ENOTSUPP;
0767 }
0768
0769 switch (param) {
0770 case PIN_CONFIG_BIAS_DISABLE:
0771 case PIN_CONFIG_BIAS_PULL_UP:
0772 case PIN_CONFIG_BIAS_PULL_DOWN:
0773 if (!opt->pud_info) {
0774 dev_err(pci->dev,
0775 "PULL control not supported for pin %s\n",
0776 g->name);
0777 return -ENOTSUPP;
0778 }
0779 base = opt->pud_info->pullup_dn_reg_base;
0780 add = opt->pud_info->pullup_dn_reg_add;
0781 ret = palmas_read(pci->palmas, base, add, &val);
0782 if (ret < 0) {
0783 dev_err(pci->dev, "Reg 0x%02x read failed: %d\n",
0784 add, ret);
0785 return ret;
0786 }
0787
0788 rval = val & opt->pud_info->pullup_dn_mask;
0789 arg = 0;
0790 if ((opt->pud_info->normal_val >= 0) &&
0791 (opt->pud_info->normal_val == rval) &&
0792 (param == PIN_CONFIG_BIAS_DISABLE))
0793 arg = 1;
0794 else if ((opt->pud_info->pull_up_val >= 0) &&
0795 (opt->pud_info->pull_up_val == rval) &&
0796 (param == PIN_CONFIG_BIAS_PULL_UP))
0797 arg = 1;
0798 else if ((opt->pud_info->pull_dn_val >= 0) &&
0799 (opt->pud_info->pull_dn_val == rval) &&
0800 (param == PIN_CONFIG_BIAS_PULL_DOWN))
0801 arg = 1;
0802 break;
0803
0804 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
0805 if (!opt->od_info) {
0806 dev_err(pci->dev,
0807 "OD control not supported for pin %s\n",
0808 g->name);
0809 return -ENOTSUPP;
0810 }
0811 base = opt->od_info->od_reg_base;
0812 add = opt->od_info->od_reg_add;
0813 ret = palmas_read(pci->palmas, base, add, &val);
0814 if (ret < 0) {
0815 dev_err(pci->dev, "Reg 0x%02x read failed: %d\n",
0816 add, ret);
0817 return ret;
0818 }
0819 rval = val & opt->od_info->od_mask;
0820 arg = -1;
0821 if ((opt->od_info->od_disable >= 0) &&
0822 (opt->od_info->od_disable == rval))
0823 arg = 0;
0824 else if ((opt->od_info->od_enable >= 0) &&
0825 (opt->od_info->od_enable == rval))
0826 arg = 1;
0827 if (arg < 0) {
0828 dev_err(pci->dev,
0829 "OD control not supported for pin %s\n",
0830 g->name);
0831 return -ENOTSUPP;
0832 }
0833 break;
0834
0835 default:
0836 dev_err(pci->dev, "Properties not supported\n");
0837 return -ENOTSUPP;
0838 }
0839
0840 *config = pinconf_to_config_packed(param, (u16)arg);
0841 return 0;
0842 }
0843
0844 static int palmas_pinconf_set(struct pinctrl_dev *pctldev,
0845 unsigned pin, unsigned long *configs,
0846 unsigned num_configs)
0847 {
0848 struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
0849 enum pin_config_param param;
0850 u32 param_val;
0851 const struct palmas_pingroup *g;
0852 const struct palmas_pin_info *opt;
0853 int ret;
0854 int base, add, mask;
0855 int rval;
0856 int group_nr;
0857 int i;
0858
0859 for (group_nr = 0; group_nr < pci->num_pin_groups; ++group_nr) {
0860 if (pci->pin_groups[group_nr].pins[0] == pin)
0861 break;
0862 }
0863
0864 if (group_nr == pci->num_pin_groups) {
0865 dev_err(pci->dev,
0866 "Pinconf is not supported for pin-id %d\n", pin);
0867 return -ENOTSUPP;
0868 }
0869
0870 g = &pci->pin_groups[group_nr];
0871 opt = g->opt[pci->pins_current_opt[group_nr]];
0872 if (!opt) {
0873 dev_err(pci->dev,
0874 "Pinconf is not supported for pin %s\n", g->name);
0875 return -ENOTSUPP;
0876 }
0877
0878 for (i = 0; i < num_configs; i++) {
0879 param = pinconf_to_config_param(configs[i]);
0880 param_val = pinconf_to_config_argument(configs[i]);
0881
0882 switch (param) {
0883 case PIN_CONFIG_BIAS_DISABLE:
0884 case PIN_CONFIG_BIAS_PULL_UP:
0885 case PIN_CONFIG_BIAS_PULL_DOWN:
0886 if (!opt->pud_info) {
0887 dev_err(pci->dev,
0888 "PULL control not supported for pin %s\n",
0889 g->name);
0890 return -ENOTSUPP;
0891 }
0892 base = opt->pud_info->pullup_dn_reg_base;
0893 add = opt->pud_info->pullup_dn_reg_add;
0894 mask = opt->pud_info->pullup_dn_mask;
0895
0896 if (param == PIN_CONFIG_BIAS_DISABLE)
0897 rval = opt->pud_info->normal_val;
0898 else if (param == PIN_CONFIG_BIAS_PULL_UP)
0899 rval = opt->pud_info->pull_up_val;
0900 else
0901 rval = opt->pud_info->pull_dn_val;
0902
0903 if (rval < 0) {
0904 dev_err(pci->dev,
0905 "PULL control not supported for pin %s\n",
0906 g->name);
0907 return -ENOTSUPP;
0908 }
0909 break;
0910
0911 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
0912 if (!opt->od_info) {
0913 dev_err(pci->dev,
0914 "OD control not supported for pin %s\n",
0915 g->name);
0916 return -ENOTSUPP;
0917 }
0918 base = opt->od_info->od_reg_base;
0919 add = opt->od_info->od_reg_add;
0920 mask = opt->od_info->od_mask;
0921 if (param_val == 0)
0922 rval = opt->od_info->od_disable;
0923 else
0924 rval = opt->od_info->od_enable;
0925 if (rval < 0) {
0926 dev_err(pci->dev,
0927 "OD control not supported for pin %s\n",
0928 g->name);
0929 return -ENOTSUPP;
0930 }
0931 break;
0932 default:
0933 dev_err(pci->dev, "Properties not supported\n");
0934 return -ENOTSUPP;
0935 }
0936
0937 dev_dbg(pci->dev, "%s(): Add0x%02x:0x%02x:0x%02x:0x%02x\n",
0938 __func__, base, add, mask, rval);
0939 ret = palmas_update_bits(pci->palmas, base, add, mask, rval);
0940 if (ret < 0) {
0941 dev_err(pci->dev, "Reg 0x%02x update failed: %d\n",
0942 add, ret);
0943 return ret;
0944 }
0945 }
0946
0947 return 0;
0948 }
0949
0950 static const struct pinconf_ops palmas_pinconf_ops = {
0951 .pin_config_get = palmas_pinconf_get,
0952 .pin_config_set = palmas_pinconf_set,
0953 };
0954
0955 static struct pinctrl_desc palmas_pinctrl_desc = {
0956 .pctlops = &palmas_pinctrl_ops,
0957 .pmxops = &palmas_pinmux_ops,
0958 .confops = &palmas_pinconf_ops,
0959 .owner = THIS_MODULE,
0960 };
0961
0962 struct palmas_pinctrl_data {
0963 const struct palmas_pingroup *pin_groups;
0964 int num_pin_groups;
0965 };
0966
0967 static struct palmas_pinctrl_data tps65913_pinctrl_data = {
0968 .pin_groups = tps65913_pingroups,
0969 .num_pin_groups = ARRAY_SIZE(tps65913_pingroups),
0970 };
0971
0972 static struct palmas_pinctrl_data tps80036_pinctrl_data = {
0973 .pin_groups = tps80036_pingroups,
0974 .num_pin_groups = ARRAY_SIZE(tps80036_pingroups),
0975 };
0976
0977 static const struct of_device_id palmas_pinctrl_of_match[] = {
0978 { .compatible = "ti,palmas-pinctrl", .data = &tps65913_pinctrl_data},
0979 { .compatible = "ti,tps65913-pinctrl", .data = &tps65913_pinctrl_data},
0980 { .compatible = "ti,tps80036-pinctrl", .data = &tps80036_pinctrl_data},
0981 { },
0982 };
0983 MODULE_DEVICE_TABLE(of, palmas_pinctrl_of_match);
0984
0985 static int palmas_pinctrl_probe(struct platform_device *pdev)
0986 {
0987 struct palmas_pctrl_chip_info *pci;
0988 const struct palmas_pinctrl_data *pinctrl_data = &tps65913_pinctrl_data;
0989 int ret;
0990 bool enable_dvfs1 = false;
0991 bool enable_dvfs2 = false;
0992
0993 if (pdev->dev.of_node) {
0994 pinctrl_data = of_device_get_match_data(&pdev->dev);
0995 enable_dvfs1 = of_property_read_bool(pdev->dev.of_node,
0996 "ti,palmas-enable-dvfs1");
0997 enable_dvfs2 = of_property_read_bool(pdev->dev.of_node,
0998 "ti,palmas-enable-dvfs2");
0999 }
1000
1001 pci = devm_kzalloc(&pdev->dev, sizeof(*pci), GFP_KERNEL);
1002 if (!pci)
1003 return -ENOMEM;
1004
1005 pci->dev = &pdev->dev;
1006 pci->palmas = dev_get_drvdata(pdev->dev.parent);
1007
1008 pci->pins = palmas_pins_desc;
1009 pci->num_pins = ARRAY_SIZE(palmas_pins_desc);
1010 pci->functions = palmas_pin_function;
1011 pci->num_functions = ARRAY_SIZE(palmas_pin_function);
1012 pci->pin_groups = pinctrl_data->pin_groups;
1013 pci->num_pin_groups = pinctrl_data->num_pin_groups;
1014
1015 platform_set_drvdata(pdev, pci);
1016
1017 palmas_pinctrl_set_dvfs1(pci, enable_dvfs1);
1018 palmas_pinctrl_set_dvfs2(pci, enable_dvfs2);
1019 ret = palmas_pinctrl_get_pin_mux(pci);
1020 if (ret < 0) {
1021 dev_err(&pdev->dev,
1022 "Reading pinctrol option register failed: %d\n", ret);
1023 return ret;
1024 }
1025
1026 palmas_pinctrl_desc.name = dev_name(&pdev->dev);
1027 palmas_pinctrl_desc.pins = palmas_pins_desc;
1028 palmas_pinctrl_desc.npins = ARRAY_SIZE(palmas_pins_desc);
1029 pci->pctl = devm_pinctrl_register(&pdev->dev, &palmas_pinctrl_desc,
1030 pci);
1031 if (IS_ERR(pci->pctl)) {
1032 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
1033 return PTR_ERR(pci->pctl);
1034 }
1035 return 0;
1036 }
1037
1038 static struct platform_driver palmas_pinctrl_driver = {
1039 .driver = {
1040 .name = "palmas-pinctrl",
1041 .of_match_table = palmas_pinctrl_of_match,
1042 },
1043 .probe = palmas_pinctrl_probe,
1044 };
1045
1046 module_platform_driver(palmas_pinctrl_driver);
1047
1048 MODULE_DESCRIPTION("Palmas pin control driver");
1049 MODULE_AUTHOR("Laxman Dewangan<ldewangan@nvidia.com>");
1050 MODULE_ALIAS("platform:palmas-pinctrl");
1051 MODULE_LICENSE("GPL v2");
