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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Oxford Semiconductor OXNAS SoC Family pinctrl driver
0004  *
0005  * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
0006  *
0007  * Based on pinctrl-pic32.c
0008  * Joshua Henderson, <joshua.henderson@microchip.com>
0009  * Copyright (C) 2015 Microchip Technology Inc.  All rights reserved.
0010  */
0011 #include <linux/gpio/driver.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/io.h>
0014 #include <linux/irq.h>
0015 #include <linux/of.h>
0016 #include <linux/of_device.h>
0017 #include <linux/pinctrl/pinconf.h>
0018 #include <linux/pinctrl/pinconf-generic.h>
0019 #include <linux/pinctrl/pinctrl.h>
0020 #include <linux/pinctrl/pinmux.h>
0021 #include <linux/platform_device.h>
0022 #include <linux/slab.h>
0023 #include <linux/regmap.h>
0024 #include <linux/mfd/syscon.h>
0025 
0026 #include "pinctrl-utils.h"
0027 
0028 #define PINS_PER_BANK       32
0029 
0030 #define GPIO_BANK_START(bank)       ((bank) * PINS_PER_BANK)
0031 
0032 /* OX810 Regmap Offsets */
0033 #define PINMUX_810_PRIMARY_SEL0     0x0c
0034 #define PINMUX_810_SECONDARY_SEL0   0x14
0035 #define PINMUX_810_TERTIARY_SEL0    0x8c
0036 #define PINMUX_810_PRIMARY_SEL1     0x10
0037 #define PINMUX_810_SECONDARY_SEL1   0x18
0038 #define PINMUX_810_TERTIARY_SEL1    0x90
0039 #define PINMUX_810_PULLUP_CTRL0     0xac
0040 #define PINMUX_810_PULLUP_CTRL1     0xb0
0041 
0042 /* OX820 Regmap Offsets */
0043 #define PINMUX_820_BANK_OFFSET      0x100000
0044 #define PINMUX_820_SECONDARY_SEL    0x14
0045 #define PINMUX_820_TERTIARY_SEL     0x8c
0046 #define PINMUX_820_QUATERNARY_SEL   0x94
0047 #define PINMUX_820_DEBUG_SEL        0x9c
0048 #define PINMUX_820_ALTERNATIVE_SEL  0xa4
0049 #define PINMUX_820_PULLUP_CTRL      0xac
0050 
0051 /* GPIO Registers */
0052 #define INPUT_VALUE 0x00
0053 #define OUTPUT_EN   0x04
0054 #define IRQ_PENDING 0x0c
0055 #define OUTPUT_SET  0x14
0056 #define OUTPUT_CLEAR    0x18
0057 #define OUTPUT_EN_SET   0x1c
0058 #define OUTPUT_EN_CLEAR 0x20
0059 #define RE_IRQ_ENABLE   0x28
0060 #define FE_IRQ_ENABLE   0x2c
0061 
0062 struct oxnas_function {
0063     const char *name;
0064     const char * const *groups;
0065     unsigned int ngroups;
0066 };
0067 
0068 struct oxnas_pin_group {
0069     const char *name;
0070     unsigned int pin;
0071     unsigned int bank;
0072     struct oxnas_desc_function *functions;
0073 };
0074 
0075 struct oxnas_desc_function {
0076     const char *name;
0077     unsigned int fct;
0078 };
0079 
0080 struct oxnas_gpio_bank {
0081     void __iomem *reg_base;
0082     struct gpio_chip gpio_chip;
0083     struct irq_chip irq_chip;
0084     unsigned int id;
0085 };
0086 
0087 struct oxnas_pinctrl {
0088     struct regmap *regmap;
0089     struct device *dev;
0090     struct pinctrl_dev *pctldev;
0091     const struct oxnas_function *functions;
0092     unsigned int nfunctions;
0093     const struct oxnas_pin_group *groups;
0094     unsigned int ngroups;
0095     struct oxnas_gpio_bank *gpio_banks;
0096     unsigned int nbanks;
0097 };
0098 
0099 struct oxnas_pinctrl_data {
0100     struct pinctrl_desc *desc;
0101     struct oxnas_pinctrl *pctl;
0102 };
0103 
0104 static const struct pinctrl_pin_desc oxnas_ox810se_pins[] = {
0105     PINCTRL_PIN(0, "gpio0"),
0106     PINCTRL_PIN(1, "gpio1"),
0107     PINCTRL_PIN(2, "gpio2"),
0108     PINCTRL_PIN(3, "gpio3"),
0109     PINCTRL_PIN(4, "gpio4"),
0110     PINCTRL_PIN(5, "gpio5"),
0111     PINCTRL_PIN(6, "gpio6"),
0112     PINCTRL_PIN(7, "gpio7"),
0113     PINCTRL_PIN(8, "gpio8"),
0114     PINCTRL_PIN(9, "gpio9"),
0115     PINCTRL_PIN(10, "gpio10"),
0116     PINCTRL_PIN(11, "gpio11"),
0117     PINCTRL_PIN(12, "gpio12"),
0118     PINCTRL_PIN(13, "gpio13"),
0119     PINCTRL_PIN(14, "gpio14"),
0120     PINCTRL_PIN(15, "gpio15"),
0121     PINCTRL_PIN(16, "gpio16"),
0122     PINCTRL_PIN(17, "gpio17"),
0123     PINCTRL_PIN(18, "gpio18"),
0124     PINCTRL_PIN(19, "gpio19"),
0125     PINCTRL_PIN(20, "gpio20"),
0126     PINCTRL_PIN(21, "gpio21"),
0127     PINCTRL_PIN(22, "gpio22"),
0128     PINCTRL_PIN(23, "gpio23"),
0129     PINCTRL_PIN(24, "gpio24"),
0130     PINCTRL_PIN(25, "gpio25"),
0131     PINCTRL_PIN(26, "gpio26"),
0132     PINCTRL_PIN(27, "gpio27"),
0133     PINCTRL_PIN(28, "gpio28"),
0134     PINCTRL_PIN(29, "gpio29"),
0135     PINCTRL_PIN(30, "gpio30"),
0136     PINCTRL_PIN(31, "gpio31"),
0137     PINCTRL_PIN(32, "gpio32"),
0138     PINCTRL_PIN(33, "gpio33"),
0139     PINCTRL_PIN(34, "gpio34"),
0140 };
0141 
0142 static const struct pinctrl_pin_desc oxnas_ox820_pins[] = {
0143     PINCTRL_PIN(0, "gpio0"),
0144     PINCTRL_PIN(1, "gpio1"),
0145     PINCTRL_PIN(2, "gpio2"),
0146     PINCTRL_PIN(3, "gpio3"),
0147     PINCTRL_PIN(4, "gpio4"),
0148     PINCTRL_PIN(5, "gpio5"),
0149     PINCTRL_PIN(6, "gpio6"),
0150     PINCTRL_PIN(7, "gpio7"),
0151     PINCTRL_PIN(8, "gpio8"),
0152     PINCTRL_PIN(9, "gpio9"),
0153     PINCTRL_PIN(10, "gpio10"),
0154     PINCTRL_PIN(11, "gpio11"),
0155     PINCTRL_PIN(12, "gpio12"),
0156     PINCTRL_PIN(13, "gpio13"),
0157     PINCTRL_PIN(14, "gpio14"),
0158     PINCTRL_PIN(15, "gpio15"),
0159     PINCTRL_PIN(16, "gpio16"),
0160     PINCTRL_PIN(17, "gpio17"),
0161     PINCTRL_PIN(18, "gpio18"),
0162     PINCTRL_PIN(19, "gpio19"),
0163     PINCTRL_PIN(20, "gpio20"),
0164     PINCTRL_PIN(21, "gpio21"),
0165     PINCTRL_PIN(22, "gpio22"),
0166     PINCTRL_PIN(23, "gpio23"),
0167     PINCTRL_PIN(24, "gpio24"),
0168     PINCTRL_PIN(25, "gpio25"),
0169     PINCTRL_PIN(26, "gpio26"),
0170     PINCTRL_PIN(27, "gpio27"),
0171     PINCTRL_PIN(28, "gpio28"),
0172     PINCTRL_PIN(29, "gpio29"),
0173     PINCTRL_PIN(30, "gpio30"),
0174     PINCTRL_PIN(31, "gpio31"),
0175     PINCTRL_PIN(32, "gpio32"),
0176     PINCTRL_PIN(33, "gpio33"),
0177     PINCTRL_PIN(34, "gpio34"),
0178     PINCTRL_PIN(35, "gpio35"),
0179     PINCTRL_PIN(36, "gpio36"),
0180     PINCTRL_PIN(37, "gpio37"),
0181     PINCTRL_PIN(38, "gpio38"),
0182     PINCTRL_PIN(39, "gpio39"),
0183     PINCTRL_PIN(40, "gpio40"),
0184     PINCTRL_PIN(41, "gpio41"),
0185     PINCTRL_PIN(42, "gpio42"),
0186     PINCTRL_PIN(43, "gpio43"),
0187     PINCTRL_PIN(44, "gpio44"),
0188     PINCTRL_PIN(45, "gpio45"),
0189     PINCTRL_PIN(46, "gpio46"),
0190     PINCTRL_PIN(47, "gpio47"),
0191     PINCTRL_PIN(48, "gpio48"),
0192     PINCTRL_PIN(49, "gpio49"),
0193 };
0194 
0195 static const char * const oxnas_ox810se_fct0_group[] = {
0196     "gpio0",  "gpio1",  "gpio2",  "gpio3",
0197     "gpio4",  "gpio5",  "gpio6",  "gpio7",
0198     "gpio8",  "gpio9",  "gpio10", "gpio11",
0199     "gpio12", "gpio13", "gpio14", "gpio15",
0200     "gpio16", "gpio17", "gpio18", "gpio19",
0201     "gpio20", "gpio21", "gpio22", "gpio23",
0202     "gpio24", "gpio25", "gpio26", "gpio27",
0203     "gpio28", "gpio29", "gpio30", "gpio31",
0204     "gpio32", "gpio33", "gpio34"
0205 };
0206 
0207 static const char * const oxnas_ox810se_fct3_group[] = {
0208     "gpio0",  "gpio1",  "gpio2",  "gpio3",
0209     "gpio4",  "gpio5",  "gpio6",  "gpio7",
0210     "gpio8",  "gpio9",
0211     "gpio20",
0212     "gpio22", "gpio23", "gpio24", "gpio25",
0213     "gpio26", "gpio27", "gpio28", "gpio29",
0214     "gpio30", "gpio31", "gpio32", "gpio33",
0215     "gpio34"
0216 };
0217 
0218 static const char * const oxnas_ox820_fct0_group[] = {
0219     "gpio0",  "gpio1",  "gpio2",  "gpio3",
0220     "gpio4",  "gpio5",  "gpio6",  "gpio7",
0221     "gpio8",  "gpio9",  "gpio10", "gpio11",
0222     "gpio12", "gpio13", "gpio14", "gpio15",
0223     "gpio16", "gpio17", "gpio18", "gpio19",
0224     "gpio20", "gpio21", "gpio22", "gpio23",
0225     "gpio24", "gpio25", "gpio26", "gpio27",
0226     "gpio28", "gpio29", "gpio30", "gpio31",
0227     "gpio32", "gpio33", "gpio34", "gpio35",
0228     "gpio36", "gpio37", "gpio38", "gpio39",
0229     "gpio40", "gpio41", "gpio42", "gpio43",
0230     "gpio44", "gpio45", "gpio46", "gpio47",
0231     "gpio48", "gpio49"
0232 };
0233 
0234 static const char * const oxnas_ox820_fct1_group[] = {
0235     "gpio3", "gpio4",
0236     "gpio12", "gpio13", "gpio14", "gpio15",
0237     "gpio16", "gpio17", "gpio18", "gpio19",
0238     "gpio20", "gpio21", "gpio22", "gpio23",
0239     "gpio24"
0240 };
0241 
0242 static const char * const oxnas_ox820_fct4_group[] = {
0243     "gpio5", "gpio6", "gpio7", "gpio8",
0244     "gpio24", "gpio25", "gpio26", "gpio27",
0245     "gpio40", "gpio41", "gpio42", "gpio43"
0246 };
0247 
0248 static const char * const oxnas_ox820_fct5_group[] = {
0249     "gpio28", "gpio29", "gpio30", "gpio31"
0250 };
0251 
0252 #define FUNCTION(_name, _gr)                    \
0253     {                           \
0254         .name = #_name,                 \
0255         .groups = oxnas_##_gr##_group,          \
0256         .ngroups = ARRAY_SIZE(oxnas_##_gr##_group), \
0257     }
0258 
0259 static const struct oxnas_function oxnas_ox810se_functions[] = {
0260     FUNCTION(gpio, ox810se_fct0),
0261     FUNCTION(fct3, ox810se_fct3),
0262 };
0263 
0264 static const struct oxnas_function oxnas_ox820_functions[] = {
0265     FUNCTION(gpio, ox820_fct0),
0266     FUNCTION(fct1, ox820_fct1),
0267     FUNCTION(fct4, ox820_fct4),
0268     FUNCTION(fct5, ox820_fct5),
0269 };
0270 
0271 #define OXNAS_PINCTRL_GROUP(_pin, _name, ...)               \
0272     {                               \
0273         .name = #_name,                     \
0274         .pin = _pin,                        \
0275         .bank = _pin / PINS_PER_BANK,               \
0276         .functions = (struct oxnas_desc_function[]){        \
0277             __VA_ARGS__, { } },             \
0278     }
0279 
0280 #define OXNAS_PINCTRL_FUNCTION(_name, _fct)     \
0281     {                       \
0282         .name = #_name,             \
0283         .fct = _fct,                \
0284     }
0285 
0286 static const struct oxnas_pin_group oxnas_ox810se_groups[] = {
0287     OXNAS_PINCTRL_GROUP(0, gpio0,
0288             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0289             OXNAS_PINCTRL_FUNCTION(fct3, 3)),
0290     OXNAS_PINCTRL_GROUP(1, gpio1,
0291             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0292             OXNAS_PINCTRL_FUNCTION(fct3, 3)),
0293     OXNAS_PINCTRL_GROUP(2, gpio2,
0294             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0295             OXNAS_PINCTRL_FUNCTION(fct3, 3)),
0296     OXNAS_PINCTRL_GROUP(3, gpio3,
0297             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0298             OXNAS_PINCTRL_FUNCTION(fct3, 3)),
0299     OXNAS_PINCTRL_GROUP(4, gpio4,
0300             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0301             OXNAS_PINCTRL_FUNCTION(fct3, 3)),
0302     OXNAS_PINCTRL_GROUP(5, gpio5,
0303             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0304             OXNAS_PINCTRL_FUNCTION(fct3, 3)),
0305     OXNAS_PINCTRL_GROUP(6, gpio6,
0306             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0307             OXNAS_PINCTRL_FUNCTION(fct3, 3)),
0308     OXNAS_PINCTRL_GROUP(7, gpio7,
0309             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0310             OXNAS_PINCTRL_FUNCTION(fct3, 3)),
0311     OXNAS_PINCTRL_GROUP(8, gpio8,
0312             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0313             OXNAS_PINCTRL_FUNCTION(fct3, 3)),
0314     OXNAS_PINCTRL_GROUP(9, gpio9,
0315             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0316             OXNAS_PINCTRL_FUNCTION(fct3, 3)),
0317     OXNAS_PINCTRL_GROUP(10, gpio10,
0318             OXNAS_PINCTRL_FUNCTION(gpio, 0)),
0319     OXNAS_PINCTRL_GROUP(11, gpio11,
0320             OXNAS_PINCTRL_FUNCTION(gpio, 0)),
0321     OXNAS_PINCTRL_GROUP(12, gpio12,
0322             OXNAS_PINCTRL_FUNCTION(gpio, 0)),
0323     OXNAS_PINCTRL_GROUP(13, gpio13,
0324             OXNAS_PINCTRL_FUNCTION(gpio, 0)),
0325     OXNAS_PINCTRL_GROUP(14, gpio14,
0326             OXNAS_PINCTRL_FUNCTION(gpio, 0)),
0327     OXNAS_PINCTRL_GROUP(15, gpio15,
0328             OXNAS_PINCTRL_FUNCTION(gpio, 0)),
0329     OXNAS_PINCTRL_GROUP(16, gpio16,
0330             OXNAS_PINCTRL_FUNCTION(gpio, 0)),
0331     OXNAS_PINCTRL_GROUP(17, gpio17,
0332             OXNAS_PINCTRL_FUNCTION(gpio, 0)),
0333     OXNAS_PINCTRL_GROUP(18, gpio18,
0334             OXNAS_PINCTRL_FUNCTION(gpio, 0)),
0335     OXNAS_PINCTRL_GROUP(19, gpio19,
0336             OXNAS_PINCTRL_FUNCTION(gpio, 0)),
0337     OXNAS_PINCTRL_GROUP(20, gpio20,
0338             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0339             OXNAS_PINCTRL_FUNCTION(fct3, 3)),
0340     OXNAS_PINCTRL_GROUP(21, gpio21,
0341             OXNAS_PINCTRL_FUNCTION(gpio, 0)),
0342     OXNAS_PINCTRL_GROUP(22, gpio22,
0343             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0344             OXNAS_PINCTRL_FUNCTION(fct3, 3)),
0345     OXNAS_PINCTRL_GROUP(23, gpio23,
0346             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0347             OXNAS_PINCTRL_FUNCTION(fct3, 3)),
0348     OXNAS_PINCTRL_GROUP(24, gpio24,
0349             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0350             OXNAS_PINCTRL_FUNCTION(fct3, 3)),
0351     OXNAS_PINCTRL_GROUP(25, gpio25,
0352             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0353             OXNAS_PINCTRL_FUNCTION(fct3, 3)),
0354     OXNAS_PINCTRL_GROUP(26, gpio26,
0355             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0356             OXNAS_PINCTRL_FUNCTION(fct3, 3)),
0357     OXNAS_PINCTRL_GROUP(27, gpio27,
0358             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0359             OXNAS_PINCTRL_FUNCTION(fct3, 3)),
0360     OXNAS_PINCTRL_GROUP(28, gpio28,
0361             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0362             OXNAS_PINCTRL_FUNCTION(fct3, 3)),
0363     OXNAS_PINCTRL_GROUP(29, gpio29,
0364             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0365             OXNAS_PINCTRL_FUNCTION(fct3, 3)),
0366     OXNAS_PINCTRL_GROUP(30, gpio30,
0367             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0368             OXNAS_PINCTRL_FUNCTION(fct3, 3)),
0369     OXNAS_PINCTRL_GROUP(31, gpio31,
0370             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0371             OXNAS_PINCTRL_FUNCTION(fct3, 3)),
0372     OXNAS_PINCTRL_GROUP(32, gpio32,
0373             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0374             OXNAS_PINCTRL_FUNCTION(fct3, 3)),
0375     OXNAS_PINCTRL_GROUP(33, gpio33,
0376             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0377             OXNAS_PINCTRL_FUNCTION(fct3, 3)),
0378     OXNAS_PINCTRL_GROUP(34, gpio34,
0379             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0380             OXNAS_PINCTRL_FUNCTION(fct3, 3)),
0381 };
0382 
0383 static const struct oxnas_pin_group oxnas_ox820_groups[] = {
0384     OXNAS_PINCTRL_GROUP(0, gpio0,
0385             OXNAS_PINCTRL_FUNCTION(gpio, 0)),
0386     OXNAS_PINCTRL_GROUP(1, gpio1,
0387             OXNAS_PINCTRL_FUNCTION(gpio, 0)),
0388     OXNAS_PINCTRL_GROUP(2, gpio2,
0389             OXNAS_PINCTRL_FUNCTION(gpio, 0)),
0390     OXNAS_PINCTRL_GROUP(3, gpio3,
0391             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0392             OXNAS_PINCTRL_FUNCTION(fct1, 1)),
0393     OXNAS_PINCTRL_GROUP(4, gpio4,
0394             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0395             OXNAS_PINCTRL_FUNCTION(fct1, 1)),
0396     OXNAS_PINCTRL_GROUP(5, gpio5,
0397             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0398             OXNAS_PINCTRL_FUNCTION(fct4, 4)),
0399     OXNAS_PINCTRL_GROUP(6, gpio6,
0400             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0401             OXNAS_PINCTRL_FUNCTION(fct4, 4)),
0402     OXNAS_PINCTRL_GROUP(7, gpio7,
0403             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0404             OXNAS_PINCTRL_FUNCTION(fct4, 4)),
0405     OXNAS_PINCTRL_GROUP(8, gpio8,
0406             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0407             OXNAS_PINCTRL_FUNCTION(fct4, 4)),
0408     OXNAS_PINCTRL_GROUP(9, gpio9,
0409             OXNAS_PINCTRL_FUNCTION(gpio, 0)),
0410     OXNAS_PINCTRL_GROUP(10, gpio10,
0411             OXNAS_PINCTRL_FUNCTION(gpio, 0)),
0412     OXNAS_PINCTRL_GROUP(11, gpio11,
0413             OXNAS_PINCTRL_FUNCTION(gpio, 0)),
0414     OXNAS_PINCTRL_GROUP(12, gpio12,
0415             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0416             OXNAS_PINCTRL_FUNCTION(fct1, 1)),
0417     OXNAS_PINCTRL_GROUP(13, gpio13,
0418             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0419             OXNAS_PINCTRL_FUNCTION(fct1, 1)),
0420     OXNAS_PINCTRL_GROUP(14, gpio14,
0421             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0422             OXNAS_PINCTRL_FUNCTION(fct1, 1)),
0423     OXNAS_PINCTRL_GROUP(15, gpio15,
0424             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0425             OXNAS_PINCTRL_FUNCTION(fct1, 1)),
0426     OXNAS_PINCTRL_GROUP(16, gpio16,
0427             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0428             OXNAS_PINCTRL_FUNCTION(fct1, 1)),
0429     OXNAS_PINCTRL_GROUP(17, gpio17,
0430             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0431             OXNAS_PINCTRL_FUNCTION(fct1, 1)),
0432     OXNAS_PINCTRL_GROUP(18, gpio18,
0433             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0434             OXNAS_PINCTRL_FUNCTION(fct1, 1)),
0435     OXNAS_PINCTRL_GROUP(19, gpio19,
0436             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0437             OXNAS_PINCTRL_FUNCTION(fct1, 1)),
0438     OXNAS_PINCTRL_GROUP(20, gpio20,
0439             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0440             OXNAS_PINCTRL_FUNCTION(fct1, 1)),
0441     OXNAS_PINCTRL_GROUP(21, gpio21,
0442             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0443             OXNAS_PINCTRL_FUNCTION(fct1, 1)),
0444     OXNAS_PINCTRL_GROUP(22, gpio22,
0445             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0446             OXNAS_PINCTRL_FUNCTION(fct1, 1)),
0447     OXNAS_PINCTRL_GROUP(23, gpio23,
0448             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0449             OXNAS_PINCTRL_FUNCTION(fct1, 1)),
0450     OXNAS_PINCTRL_GROUP(24, gpio24,
0451             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0452             OXNAS_PINCTRL_FUNCTION(fct1, 1),
0453             OXNAS_PINCTRL_FUNCTION(fct4, 5)),
0454     OXNAS_PINCTRL_GROUP(25, gpio25,
0455             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0456             OXNAS_PINCTRL_FUNCTION(fct4, 4)),
0457     OXNAS_PINCTRL_GROUP(26, gpio26,
0458             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0459             OXNAS_PINCTRL_FUNCTION(fct4, 4)),
0460     OXNAS_PINCTRL_GROUP(27, gpio27,
0461             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0462             OXNAS_PINCTRL_FUNCTION(fct4, 4)),
0463     OXNAS_PINCTRL_GROUP(28, gpio28,
0464             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0465             OXNAS_PINCTRL_FUNCTION(fct5, 5)),
0466     OXNAS_PINCTRL_GROUP(29, gpio29,
0467             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0468             OXNAS_PINCTRL_FUNCTION(fct5, 5)),
0469     OXNAS_PINCTRL_GROUP(30, gpio30,
0470             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0471             OXNAS_PINCTRL_FUNCTION(fct5, 5)),
0472     OXNAS_PINCTRL_GROUP(31, gpio31,
0473             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0474             OXNAS_PINCTRL_FUNCTION(fct5, 5)),
0475     OXNAS_PINCTRL_GROUP(32, gpio32,
0476             OXNAS_PINCTRL_FUNCTION(gpio, 0)),
0477     OXNAS_PINCTRL_GROUP(33, gpio33,
0478             OXNAS_PINCTRL_FUNCTION(gpio, 0)),
0479     OXNAS_PINCTRL_GROUP(34, gpio34,
0480             OXNAS_PINCTRL_FUNCTION(gpio, 0)),
0481     OXNAS_PINCTRL_GROUP(35, gpio35,
0482             OXNAS_PINCTRL_FUNCTION(gpio, 0)),
0483     OXNAS_PINCTRL_GROUP(36, gpio36,
0484             OXNAS_PINCTRL_FUNCTION(gpio, 0)),
0485     OXNAS_PINCTRL_GROUP(37, gpio37,
0486             OXNAS_PINCTRL_FUNCTION(gpio, 0)),
0487     OXNAS_PINCTRL_GROUP(38, gpio38,
0488             OXNAS_PINCTRL_FUNCTION(gpio, 0)),
0489     OXNAS_PINCTRL_GROUP(39, gpio39,
0490             OXNAS_PINCTRL_FUNCTION(gpio, 0)),
0491     OXNAS_PINCTRL_GROUP(40, gpio40,
0492             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0493             OXNAS_PINCTRL_FUNCTION(fct4, 4)),
0494     OXNAS_PINCTRL_GROUP(41, gpio41,
0495             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0496             OXNAS_PINCTRL_FUNCTION(fct4, 4)),
0497     OXNAS_PINCTRL_GROUP(42, gpio42,
0498             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0499             OXNAS_PINCTRL_FUNCTION(fct4, 4)),
0500     OXNAS_PINCTRL_GROUP(43, gpio43,
0501             OXNAS_PINCTRL_FUNCTION(gpio, 0),
0502             OXNAS_PINCTRL_FUNCTION(fct4, 4)),
0503     OXNAS_PINCTRL_GROUP(44, gpio44,
0504             OXNAS_PINCTRL_FUNCTION(gpio, 0)),
0505     OXNAS_PINCTRL_GROUP(45, gpio45,
0506             OXNAS_PINCTRL_FUNCTION(gpio, 0)),
0507     OXNAS_PINCTRL_GROUP(46, gpio46,
0508             OXNAS_PINCTRL_FUNCTION(gpio, 0)),
0509     OXNAS_PINCTRL_GROUP(47, gpio47,
0510             OXNAS_PINCTRL_FUNCTION(gpio, 0)),
0511     OXNAS_PINCTRL_GROUP(48, gpio48,
0512             OXNAS_PINCTRL_FUNCTION(gpio, 0)),
0513     OXNAS_PINCTRL_GROUP(49, gpio49,
0514             OXNAS_PINCTRL_FUNCTION(gpio, 0)),
0515 };
0516 
0517 static inline struct oxnas_gpio_bank *pctl_to_bank(struct oxnas_pinctrl *pctl,
0518                            unsigned int pin)
0519 {
0520     return &pctl->gpio_banks[pin / PINS_PER_BANK];
0521 }
0522 
0523 static int oxnas_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
0524 {
0525     struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0526 
0527     return pctl->ngroups;
0528 }
0529 
0530 static const char *oxnas_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
0531                         unsigned int group)
0532 {
0533     struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0534 
0535     return pctl->groups[group].name;
0536 }
0537 
0538 static int oxnas_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
0539                     unsigned int group,
0540                     const unsigned int **pins,
0541                     unsigned int *num_pins)
0542 {
0543     struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0544 
0545     *pins = &pctl->groups[group].pin;
0546     *num_pins = 1;
0547 
0548     return 0;
0549 }
0550 
0551 static const struct pinctrl_ops oxnas_pinctrl_ops = {
0552     .get_groups_count = oxnas_pinctrl_get_groups_count,
0553     .get_group_name = oxnas_pinctrl_get_group_name,
0554     .get_group_pins = oxnas_pinctrl_get_group_pins,
0555     .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
0556     .dt_free_map = pinctrl_utils_free_map,
0557 };
0558 
0559 static int oxnas_pinmux_get_functions_count(struct pinctrl_dev *pctldev)
0560 {
0561     struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0562 
0563     return pctl->nfunctions;
0564 }
0565 
0566 static const char *
0567 oxnas_pinmux_get_function_name(struct pinctrl_dev *pctldev, unsigned int func)
0568 {
0569     struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0570 
0571     return pctl->functions[func].name;
0572 }
0573 
0574 static int oxnas_pinmux_get_function_groups(struct pinctrl_dev *pctldev,
0575                         unsigned int func,
0576                         const char * const **groups,
0577                         unsigned int * const num_groups)
0578 {
0579     struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0580 
0581     *groups = pctl->functions[func].groups;
0582     *num_groups = pctl->functions[func].ngroups;
0583 
0584     return 0;
0585 }
0586 
0587 static int oxnas_ox810se_pinmux_enable(struct pinctrl_dev *pctldev,
0588                        unsigned int func, unsigned int group)
0589 {
0590     struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0591     const struct oxnas_pin_group *pg = &pctl->groups[group];
0592     const struct oxnas_function *pf = &pctl->functions[func];
0593     const char *fname = pf->name;
0594     struct oxnas_desc_function *functions = pg->functions;
0595     u32 mask = BIT(pg->pin);
0596 
0597     while (functions->name) {
0598         if (!strcmp(functions->name, fname)) {
0599             dev_dbg(pctl->dev,
0600                 "setting function %s bank %d pin %d fct %d mask %x\n",
0601                 fname, pg->bank, pg->pin,
0602                 functions->fct, mask);
0603 
0604             regmap_write_bits(pctl->regmap,
0605                       (pg->bank ?
0606                         PINMUX_810_PRIMARY_SEL1 :
0607                         PINMUX_810_PRIMARY_SEL0),
0608                       mask,
0609                       (functions->fct == 1 ?
0610                         mask : 0));
0611             regmap_write_bits(pctl->regmap,
0612                       (pg->bank ?
0613                         PINMUX_810_SECONDARY_SEL1 :
0614                         PINMUX_810_SECONDARY_SEL0),
0615                       mask,
0616                       (functions->fct == 2 ?
0617                         mask : 0));
0618             regmap_write_bits(pctl->regmap,
0619                       (pg->bank ?
0620                         PINMUX_810_TERTIARY_SEL1 :
0621                         PINMUX_810_TERTIARY_SEL0),
0622                       mask,
0623                       (functions->fct == 3 ?
0624                         mask : 0));
0625 
0626             return 0;
0627         }
0628 
0629         functions++;
0630     }
0631 
0632     dev_err(pctl->dev, "cannot mux pin %u to function %u\n", group, func);
0633 
0634     return -EINVAL;
0635 }
0636 
0637 static int oxnas_ox820_pinmux_enable(struct pinctrl_dev *pctldev,
0638                      unsigned int func, unsigned int group)
0639 {
0640     struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0641     const struct oxnas_pin_group *pg = &pctl->groups[group];
0642     const struct oxnas_function *pf = &pctl->functions[func];
0643     const char *fname = pf->name;
0644     struct oxnas_desc_function *functions = pg->functions;
0645     unsigned int offset = (pg->bank ? PINMUX_820_BANK_OFFSET : 0);
0646     u32 mask = BIT(pg->pin);
0647 
0648     while (functions->name) {
0649         if (!strcmp(functions->name, fname)) {
0650             dev_dbg(pctl->dev,
0651                 "setting function %s bank %d pin %d fct %d mask %x\n",
0652                 fname, pg->bank, pg->pin,
0653                 functions->fct, mask);
0654 
0655             regmap_write_bits(pctl->regmap,
0656                       offset + PINMUX_820_SECONDARY_SEL,
0657                       mask,
0658                       (functions->fct == 1 ?
0659                         mask : 0));
0660             regmap_write_bits(pctl->regmap,
0661                       offset + PINMUX_820_TERTIARY_SEL,
0662                       mask,
0663                       (functions->fct == 2 ?
0664                         mask : 0));
0665             regmap_write_bits(pctl->regmap,
0666                       offset + PINMUX_820_QUATERNARY_SEL,
0667                       mask,
0668                       (functions->fct == 3 ?
0669                         mask : 0));
0670             regmap_write_bits(pctl->regmap,
0671                       offset + PINMUX_820_DEBUG_SEL,
0672                       mask,
0673                       (functions->fct == 4 ?
0674                         mask : 0));
0675             regmap_write_bits(pctl->regmap,
0676                       offset + PINMUX_820_ALTERNATIVE_SEL,
0677                       mask,
0678                       (functions->fct == 5 ?
0679                         mask : 0));
0680 
0681             return 0;
0682         }
0683 
0684         functions++;
0685     }
0686 
0687     dev_err(pctl->dev, "cannot mux pin %u to function %u\n", group, func);
0688 
0689     return -EINVAL;
0690 }
0691 
0692 static int oxnas_ox810se_gpio_request_enable(struct pinctrl_dev *pctldev,
0693                          struct pinctrl_gpio_range *range,
0694                          unsigned int offset)
0695 {
0696     struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0697     struct oxnas_gpio_bank *bank = gpiochip_get_data(range->gc);
0698     u32 mask = BIT(offset - bank->gpio_chip.base);
0699 
0700     dev_dbg(pctl->dev, "requesting gpio %d in bank %d (id %d) with mask 0x%x\n",
0701         offset, bank->gpio_chip.base, bank->id, mask);
0702 
0703     regmap_write_bits(pctl->regmap,
0704               (bank->id ?
0705                 PINMUX_810_PRIMARY_SEL1 :
0706                 PINMUX_810_PRIMARY_SEL0),
0707               mask, 0);
0708     regmap_write_bits(pctl->regmap,
0709               (bank->id ?
0710                 PINMUX_810_SECONDARY_SEL1 :
0711                 PINMUX_810_SECONDARY_SEL0),
0712               mask, 0);
0713     regmap_write_bits(pctl->regmap,
0714               (bank->id ?
0715                 PINMUX_810_TERTIARY_SEL1 :
0716                 PINMUX_810_TERTIARY_SEL0),
0717               mask, 0);
0718 
0719     return 0;
0720 }
0721 
0722 static int oxnas_ox820_gpio_request_enable(struct pinctrl_dev *pctldev,
0723                        struct pinctrl_gpio_range *range,
0724                        unsigned int offset)
0725 {
0726     struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0727     struct oxnas_gpio_bank *bank = gpiochip_get_data(range->gc);
0728     unsigned int bank_offset = (bank->id ? PINMUX_820_BANK_OFFSET : 0);
0729     u32 mask = BIT(offset - bank->gpio_chip.base);
0730 
0731     dev_dbg(pctl->dev, "requesting gpio %d in bank %d (id %d) with mask 0x%x\n",
0732         offset, bank->gpio_chip.base, bank->id, mask);
0733 
0734     regmap_write_bits(pctl->regmap,
0735               bank_offset + PINMUX_820_SECONDARY_SEL,
0736               mask, 0);
0737     regmap_write_bits(pctl->regmap,
0738               bank_offset + PINMUX_820_TERTIARY_SEL,
0739               mask, 0);
0740     regmap_write_bits(pctl->regmap,
0741               bank_offset + PINMUX_820_QUATERNARY_SEL,
0742               mask, 0);
0743     regmap_write_bits(pctl->regmap,
0744               bank_offset + PINMUX_820_DEBUG_SEL,
0745               mask, 0);
0746     regmap_write_bits(pctl->regmap,
0747               bank_offset + PINMUX_820_ALTERNATIVE_SEL,
0748               mask, 0);
0749 
0750     return 0;
0751 }
0752 
0753 static int oxnas_gpio_get_direction(struct gpio_chip *chip,
0754                       unsigned int offset)
0755 {
0756     struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
0757     u32 mask = BIT(offset);
0758 
0759     if (readl_relaxed(bank->reg_base + OUTPUT_EN) & mask)
0760         return GPIO_LINE_DIRECTION_OUT;
0761 
0762     return GPIO_LINE_DIRECTION_IN;
0763 }
0764 
0765 static int oxnas_gpio_direction_input(struct gpio_chip *chip,
0766                       unsigned int offset)
0767 {
0768     struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
0769     u32 mask = BIT(offset);
0770 
0771     writel_relaxed(mask, bank->reg_base + OUTPUT_EN_CLEAR);
0772 
0773     return 0;
0774 }
0775 
0776 static int oxnas_gpio_get(struct gpio_chip *chip, unsigned int offset)
0777 {
0778     struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
0779     u32 mask = BIT(offset);
0780 
0781     return (readl_relaxed(bank->reg_base + INPUT_VALUE) & mask) != 0;
0782 }
0783 
0784 static void oxnas_gpio_set(struct gpio_chip *chip, unsigned int offset,
0785                    int value)
0786 {
0787     struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
0788     u32 mask = BIT(offset);
0789 
0790     if (value)
0791         writel_relaxed(mask, bank->reg_base + OUTPUT_SET);
0792     else
0793         writel_relaxed(mask, bank->reg_base + OUTPUT_CLEAR);
0794 }
0795 
0796 static int oxnas_gpio_direction_output(struct gpio_chip *chip,
0797                        unsigned int offset, int value)
0798 {
0799     struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
0800     u32 mask = BIT(offset);
0801 
0802     oxnas_gpio_set(chip, offset, value);
0803     writel_relaxed(mask, bank->reg_base + OUTPUT_EN_SET);
0804 
0805     return 0;
0806 }
0807 
0808 static int oxnas_gpio_set_direction(struct pinctrl_dev *pctldev,
0809                     struct pinctrl_gpio_range *range,
0810                     unsigned int offset, bool input)
0811 {
0812     struct gpio_chip *chip = range->gc;
0813 
0814     if (input)
0815         oxnas_gpio_direction_input(chip, offset);
0816     else
0817         oxnas_gpio_direction_output(chip, offset, 0);
0818 
0819     return 0;
0820 }
0821 
0822 static const struct pinmux_ops oxnas_ox810se_pinmux_ops = {
0823     .get_functions_count = oxnas_pinmux_get_functions_count,
0824     .get_function_name = oxnas_pinmux_get_function_name,
0825     .get_function_groups = oxnas_pinmux_get_function_groups,
0826     .set_mux = oxnas_ox810se_pinmux_enable,
0827     .gpio_request_enable = oxnas_ox810se_gpio_request_enable,
0828     .gpio_set_direction = oxnas_gpio_set_direction,
0829 };
0830 
0831 static const struct pinmux_ops oxnas_ox820_pinmux_ops = {
0832     .get_functions_count = oxnas_pinmux_get_functions_count,
0833     .get_function_name = oxnas_pinmux_get_function_name,
0834     .get_function_groups = oxnas_pinmux_get_function_groups,
0835     .set_mux = oxnas_ox820_pinmux_enable,
0836     .gpio_request_enable = oxnas_ox820_gpio_request_enable,
0837     .gpio_set_direction = oxnas_gpio_set_direction,
0838 };
0839 
0840 static int oxnas_ox810se_pinconf_get(struct pinctrl_dev *pctldev,
0841                      unsigned int pin, unsigned long *config)
0842 {
0843     struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0844     struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);
0845     unsigned int param = pinconf_to_config_param(*config);
0846     u32 mask = BIT(pin - bank->gpio_chip.base);
0847     int ret;
0848     u32 arg;
0849 
0850     switch (param) {
0851     case PIN_CONFIG_BIAS_PULL_UP:
0852         ret = regmap_read(pctl->regmap,
0853                   (bank->id ?
0854                     PINMUX_810_PULLUP_CTRL1 :
0855                     PINMUX_810_PULLUP_CTRL0),
0856                   &arg);
0857         if (ret)
0858             return ret;
0859 
0860         arg = !!(arg & mask);
0861         break;
0862     default:
0863         return -ENOTSUPP;
0864     }
0865 
0866     *config = pinconf_to_config_packed(param, arg);
0867 
0868     return 0;
0869 }
0870 
0871 static int oxnas_ox820_pinconf_get(struct pinctrl_dev *pctldev,
0872                    unsigned int pin, unsigned long *config)
0873 {
0874     struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0875     struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);
0876     unsigned int param = pinconf_to_config_param(*config);
0877     unsigned int bank_offset = (bank->id ? PINMUX_820_BANK_OFFSET : 0);
0878     u32 mask = BIT(pin - bank->gpio_chip.base);
0879     int ret;
0880     u32 arg;
0881 
0882     switch (param) {
0883     case PIN_CONFIG_BIAS_PULL_UP:
0884         ret = regmap_read(pctl->regmap,
0885                   bank_offset + PINMUX_820_PULLUP_CTRL,
0886                   &arg);
0887         if (ret)
0888             return ret;
0889 
0890         arg = !!(arg & mask);
0891         break;
0892     default:
0893         return -ENOTSUPP;
0894     }
0895 
0896     *config = pinconf_to_config_packed(param, arg);
0897 
0898     return 0;
0899 }
0900 
0901 static int oxnas_ox810se_pinconf_set(struct pinctrl_dev *pctldev,
0902                      unsigned int pin, unsigned long *configs,
0903                      unsigned int num_configs)
0904 {
0905     struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0906     struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);
0907     unsigned int param;
0908     unsigned int i;
0909     u32 offset = pin - bank->gpio_chip.base;
0910     u32 mask = BIT(offset);
0911 
0912     dev_dbg(pctl->dev, "setting pin %d bank %d mask 0x%x\n",
0913         pin, bank->gpio_chip.base, mask);
0914 
0915     for (i = 0; i < num_configs; i++) {
0916         param = pinconf_to_config_param(configs[i]);
0917 
0918         switch (param) {
0919         case PIN_CONFIG_BIAS_PULL_UP:
0920             dev_dbg(pctl->dev, "   pullup\n");
0921             regmap_write_bits(pctl->regmap,
0922                       (bank->id ?
0923                         PINMUX_810_PULLUP_CTRL1 :
0924                         PINMUX_810_PULLUP_CTRL0),
0925                       mask, mask);
0926             break;
0927         default:
0928             dev_err(pctl->dev, "Property %u not supported\n",
0929                 param);
0930             return -ENOTSUPP;
0931         }
0932     }
0933 
0934     return 0;
0935 }
0936 
0937 static int oxnas_ox820_pinconf_set(struct pinctrl_dev *pctldev,
0938                    unsigned int pin, unsigned long *configs,
0939                    unsigned int num_configs)
0940 {
0941     struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0942     struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);
0943     unsigned int bank_offset = (bank->id ? PINMUX_820_BANK_OFFSET : 0);
0944     unsigned int param;
0945     unsigned int i;
0946     u32 offset = pin - bank->gpio_chip.base;
0947     u32 mask = BIT(offset);
0948 
0949     dev_dbg(pctl->dev, "setting pin %d bank %d mask 0x%x\n",
0950         pin, bank->gpio_chip.base, mask);
0951 
0952     for (i = 0; i < num_configs; i++) {
0953         param = pinconf_to_config_param(configs[i]);
0954 
0955         switch (param) {
0956         case PIN_CONFIG_BIAS_PULL_UP:
0957             dev_dbg(pctl->dev, "   pullup\n");
0958             regmap_write_bits(pctl->regmap,
0959                       bank_offset + PINMUX_820_PULLUP_CTRL,
0960                       mask, mask);
0961             break;
0962         default:
0963             dev_err(pctl->dev, "Property %u not supported\n",
0964                 param);
0965             return -ENOTSUPP;
0966         }
0967     }
0968 
0969     return 0;
0970 }
0971 
0972 static const struct pinconf_ops oxnas_ox810se_pinconf_ops = {
0973     .pin_config_get = oxnas_ox810se_pinconf_get,
0974     .pin_config_set = oxnas_ox810se_pinconf_set,
0975     .is_generic = true,
0976 };
0977 
0978 static const struct pinconf_ops oxnas_ox820_pinconf_ops = {
0979     .pin_config_get = oxnas_ox820_pinconf_get,
0980     .pin_config_set = oxnas_ox820_pinconf_set,
0981     .is_generic = true,
0982 };
0983 
0984 static void oxnas_gpio_irq_ack(struct irq_data *data)
0985 {
0986     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
0987     struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
0988     u32 mask = BIT(data->hwirq);
0989 
0990     writel(mask, bank->reg_base + IRQ_PENDING);
0991 }
0992 
0993 static void oxnas_gpio_irq_mask(struct irq_data *data)
0994 {
0995     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
0996     struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
0997     unsigned int type = irqd_get_trigger_type(data);
0998     u32 mask = BIT(data->hwirq);
0999 
1000     if (type & IRQ_TYPE_EDGE_RISING)
1001         writel(readl(bank->reg_base + RE_IRQ_ENABLE) & ~mask,
1002                bank->reg_base + RE_IRQ_ENABLE);
1003 
1004     if (type & IRQ_TYPE_EDGE_FALLING)
1005         writel(readl(bank->reg_base + FE_IRQ_ENABLE) & ~mask,
1006                bank->reg_base + FE_IRQ_ENABLE);
1007 }
1008 
1009 static void oxnas_gpio_irq_unmask(struct irq_data *data)
1010 {
1011     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
1012     struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
1013     unsigned int type = irqd_get_trigger_type(data);
1014     u32 mask = BIT(data->hwirq);
1015 
1016     if (type & IRQ_TYPE_EDGE_RISING)
1017         writel(readl(bank->reg_base + RE_IRQ_ENABLE) | mask,
1018                bank->reg_base + RE_IRQ_ENABLE);
1019 
1020     if (type & IRQ_TYPE_EDGE_FALLING)
1021         writel(readl(bank->reg_base + FE_IRQ_ENABLE) | mask,
1022                bank->reg_base + FE_IRQ_ENABLE);
1023 }
1024 
1025 static unsigned int oxnas_gpio_irq_startup(struct irq_data *data)
1026 {
1027     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
1028 
1029     oxnas_gpio_direction_input(chip, data->hwirq);
1030     oxnas_gpio_irq_unmask(data);
1031 
1032     return 0;
1033 }
1034 
1035 static int oxnas_gpio_irq_set_type(struct irq_data *data, unsigned int type)
1036 {
1037     if ((type & (IRQ_TYPE_EDGE_RISING|IRQ_TYPE_EDGE_FALLING)) == 0)
1038         return -EINVAL;
1039 
1040     irq_set_handler_locked(data, handle_edge_irq);
1041 
1042     return 0;
1043 }
1044 
1045 static void oxnas_gpio_irq_handler(struct irq_desc *desc)
1046 {
1047     struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1048     struct oxnas_gpio_bank *bank = gpiochip_get_data(gc);
1049     struct irq_chip *chip = irq_desc_get_chip(desc);
1050     unsigned long stat;
1051     unsigned int pin;
1052 
1053     chained_irq_enter(chip, desc);
1054 
1055     stat = readl(bank->reg_base + IRQ_PENDING);
1056 
1057     for_each_set_bit(pin, &stat, BITS_PER_LONG)
1058         generic_handle_domain_irq(gc->irq.domain, pin);
1059 
1060     chained_irq_exit(chip, desc);
1061 }
1062 
1063 #define GPIO_BANK(_bank)                        \
1064     {                               \
1065         .gpio_chip = {                      \
1066             .label = "GPIO" #_bank,             \
1067             .request = gpiochip_generic_request,        \
1068             .free = gpiochip_generic_free,          \
1069             .get_direction = oxnas_gpio_get_direction,  \
1070             .direction_input = oxnas_gpio_direction_input,  \
1071             .direction_output = oxnas_gpio_direction_output, \
1072             .get = oxnas_gpio_get,              \
1073             .set = oxnas_gpio_set,              \
1074             .ngpio = PINS_PER_BANK,             \
1075             .base = GPIO_BANK_START(_bank),         \
1076             .owner = THIS_MODULE,               \
1077             .can_sleep = 0,                 \
1078         },                          \
1079         .irq_chip = {                       \
1080             .name = "GPIO" #_bank,              \
1081             .irq_startup = oxnas_gpio_irq_startup,  \
1082             .irq_ack = oxnas_gpio_irq_ack,      \
1083             .irq_mask = oxnas_gpio_irq_mask,        \
1084             .irq_unmask = oxnas_gpio_irq_unmask,        \
1085             .irq_set_type = oxnas_gpio_irq_set_type,    \
1086         },                          \
1087     }
1088 
1089 static struct oxnas_gpio_bank oxnas_gpio_banks[] = {
1090     GPIO_BANK(0),
1091     GPIO_BANK(1),
1092 };
1093 
1094 static struct oxnas_pinctrl ox810se_pinctrl = {
1095     .functions = oxnas_ox810se_functions,
1096     .nfunctions = ARRAY_SIZE(oxnas_ox810se_functions),
1097     .groups = oxnas_ox810se_groups,
1098     .ngroups = ARRAY_SIZE(oxnas_ox810se_groups),
1099     .gpio_banks = oxnas_gpio_banks,
1100     .nbanks = ARRAY_SIZE(oxnas_gpio_banks),
1101 };
1102 
1103 static struct pinctrl_desc oxnas_ox810se_pinctrl_desc = {
1104     .name = "oxnas-pinctrl",
1105     .pins = oxnas_ox810se_pins,
1106     .npins = ARRAY_SIZE(oxnas_ox810se_pins),
1107     .pctlops = &oxnas_pinctrl_ops,
1108     .pmxops = &oxnas_ox810se_pinmux_ops,
1109     .confops = &oxnas_ox810se_pinconf_ops,
1110     .owner = THIS_MODULE,
1111 };
1112 
1113 static struct oxnas_pinctrl ox820_pinctrl = {
1114     .functions = oxnas_ox820_functions,
1115     .nfunctions = ARRAY_SIZE(oxnas_ox820_functions),
1116     .groups = oxnas_ox820_groups,
1117     .ngroups = ARRAY_SIZE(oxnas_ox820_groups),
1118     .gpio_banks = oxnas_gpio_banks,
1119     .nbanks = ARRAY_SIZE(oxnas_gpio_banks),
1120 };
1121 
1122 static struct pinctrl_desc oxnas_ox820_pinctrl_desc = {
1123     .name = "oxnas-pinctrl",
1124     .pins = oxnas_ox820_pins,
1125     .npins = ARRAY_SIZE(oxnas_ox820_pins),
1126     .pctlops = &oxnas_pinctrl_ops,
1127     .pmxops = &oxnas_ox820_pinmux_ops,
1128     .confops = &oxnas_ox820_pinconf_ops,
1129     .owner = THIS_MODULE,
1130 };
1131 
1132 static struct oxnas_pinctrl_data oxnas_ox810se_pinctrl_data = {
1133     .desc = &oxnas_ox810se_pinctrl_desc,
1134     .pctl = &ox810se_pinctrl,
1135 };
1136 
1137 static struct oxnas_pinctrl_data oxnas_ox820_pinctrl_data = {
1138     .desc = &oxnas_ox820_pinctrl_desc,
1139     .pctl = &ox820_pinctrl,
1140 };
1141 
1142 static const struct of_device_id oxnas_pinctrl_of_match[] = {
1143     { .compatible = "oxsemi,ox810se-pinctrl",
1144       .data = &oxnas_ox810se_pinctrl_data
1145     },
1146     { .compatible = "oxsemi,ox820-pinctrl",
1147       .data = &oxnas_ox820_pinctrl_data,
1148     },
1149     { },
1150 };
1151 
1152 static int oxnas_pinctrl_probe(struct platform_device *pdev)
1153 {
1154     const struct of_device_id *id;
1155     const struct oxnas_pinctrl_data *data;
1156     struct oxnas_pinctrl *pctl;
1157 
1158     id = of_match_node(oxnas_pinctrl_of_match, pdev->dev.of_node);
1159     if (!id)
1160         return -ENODEV;
1161 
1162     data = id->data;
1163     if (!data || !data->pctl || !data->desc)
1164         return -EINVAL;
1165 
1166     pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1167     if (!pctl)
1168         return -ENOMEM;
1169     pctl->dev = &pdev->dev;
1170     dev_set_drvdata(&pdev->dev, pctl);
1171 
1172     pctl->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1173                                "oxsemi,sys-ctrl");
1174     if (IS_ERR(pctl->regmap)) {
1175         dev_err(&pdev->dev, "failed to get sys ctrl regmap\n");
1176         return -ENODEV;
1177     }
1178 
1179     pctl->functions = data->pctl->functions;
1180     pctl->nfunctions = data->pctl->nfunctions;
1181     pctl->groups = data->pctl->groups;
1182     pctl->ngroups = data->pctl->ngroups;
1183     pctl->gpio_banks = data->pctl->gpio_banks;
1184     pctl->nbanks = data->pctl->nbanks;
1185 
1186     pctl->pctldev = pinctrl_register(data->desc, &pdev->dev, pctl);
1187     if (IS_ERR(pctl->pctldev)) {
1188         dev_err(&pdev->dev, "Failed to register pinctrl device\n");
1189         return PTR_ERR(pctl->pctldev);
1190     }
1191 
1192     return 0;
1193 }
1194 
1195 static int oxnas_gpio_probe(struct platform_device *pdev)
1196 {
1197     struct device_node *np = pdev->dev.of_node;
1198     struct of_phandle_args pinspec;
1199     struct oxnas_gpio_bank *bank;
1200     unsigned int id, ngpios;
1201     int irq, ret;
1202     struct gpio_irq_chip *girq;
1203 
1204     if (of_parse_phandle_with_fixed_args(np, "gpio-ranges",
1205                          3, 0, &pinspec)) {
1206         dev_err(&pdev->dev, "gpio-ranges property not found\n");
1207         return -EINVAL;
1208     }
1209 
1210     id = pinspec.args[1] / PINS_PER_BANK;
1211     ngpios = pinspec.args[2];
1212 
1213     if (id >= ARRAY_SIZE(oxnas_gpio_banks)) {
1214         dev_err(&pdev->dev, "invalid gpio-ranges base arg\n");
1215         return -EINVAL;
1216     }
1217 
1218     if (ngpios > PINS_PER_BANK) {
1219         dev_err(&pdev->dev, "invalid gpio-ranges count arg\n");
1220         return -EINVAL;
1221     }
1222 
1223     bank = &oxnas_gpio_banks[id];
1224 
1225     bank->reg_base = devm_platform_ioremap_resource(pdev, 0);
1226     if (IS_ERR(bank->reg_base))
1227         return PTR_ERR(bank->reg_base);
1228 
1229     irq = platform_get_irq(pdev, 0);
1230     if (irq < 0)
1231         return irq;
1232 
1233     bank->id = id;
1234     bank->gpio_chip.parent = &pdev->dev;
1235     bank->gpio_chip.ngpio = ngpios;
1236     girq = &bank->gpio_chip.irq;
1237     girq->chip = &bank->irq_chip;
1238     girq->parent_handler = oxnas_gpio_irq_handler;
1239     girq->num_parents = 1;
1240     girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents),
1241                      GFP_KERNEL);
1242     if (!girq->parents)
1243         return -ENOMEM;
1244     girq->parents[0] = irq;
1245     girq->default_type = IRQ_TYPE_NONE;
1246     girq->handler = handle_level_irq;
1247 
1248     ret = gpiochip_add_data(&bank->gpio_chip, bank);
1249     if (ret < 0) {
1250         dev_err(&pdev->dev, "Failed to add GPIO chip %u: %d\n",
1251             id, ret);
1252         return ret;
1253     }
1254 
1255     return 0;
1256 }
1257 
1258 static struct platform_driver oxnas_pinctrl_driver = {
1259     .driver = {
1260         .name = "oxnas-pinctrl",
1261         .of_match_table = oxnas_pinctrl_of_match,
1262         .suppress_bind_attrs = true,
1263     },
1264     .probe = oxnas_pinctrl_probe,
1265 };
1266 
1267 static const struct of_device_id oxnas_gpio_of_match[] = {
1268     { .compatible = "oxsemi,ox810se-gpio", },
1269     { .compatible = "oxsemi,ox820-gpio", },
1270     { },
1271 };
1272 
1273 static struct platform_driver oxnas_gpio_driver = {
1274     .driver = {
1275         .name = "oxnas-gpio",
1276         .of_match_table = oxnas_gpio_of_match,
1277         .suppress_bind_attrs = true,
1278     },
1279     .probe = oxnas_gpio_probe,
1280 };
1281 
1282 static int __init oxnas_gpio_register(void)
1283 {
1284     return platform_driver_register(&oxnas_gpio_driver);
1285 }
1286 arch_initcall(oxnas_gpio_register);
1287 
1288 static int __init oxnas_pinctrl_register(void)
1289 {
1290     return platform_driver_register(&oxnas_pinctrl_driver);
1291 }
1292 arch_initcall(oxnas_pinctrl_register);
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