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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Microsemi/Microchip SoCs serial gpio driver
0004  *
0005  * Author: Lars Povlsen <lars.povlsen@microchip.com>
0006  *
0007  * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
0008  */
0009 
0010 #include <linux/bitfield.h>
0011 #include <linux/bits.h>
0012 #include <linux/clk.h>
0013 #include <linux/gpio/driver.h>
0014 #include <linux/io.h>
0015 #include <linux/mod_devicetable.h>
0016 #include <linux/module.h>
0017 #include <linux/pinctrl/pinmux.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/property.h>
0020 #include <linux/regmap.h>
0021 #include <linux/reset.h>
0022 #include <linux/spinlock.h>
0023 
0024 #include "core.h"
0025 #include "pinconf.h"
0026 
0027 #define SGPIO_BITS_PER_WORD 32
0028 #define SGPIO_MAX_BITS      4
0029 #define SGPIO_SRC_BITS      3 /* 3 bit wide field per pin */
0030 
0031 enum {
0032     REG_INPUT_DATA,
0033     REG_PORT_CONFIG,
0034     REG_PORT_ENABLE,
0035     REG_SIO_CONFIG,
0036     REG_SIO_CLOCK,
0037     REG_INT_POLARITY,
0038     REG_INT_TRIGGER,
0039     REG_INT_ACK,
0040     REG_INT_ENABLE,
0041     REG_INT_IDENT,
0042     MAXREG
0043 };
0044 
0045 enum {
0046     SGPIO_ARCH_LUTON,
0047     SGPIO_ARCH_OCELOT,
0048     SGPIO_ARCH_SPARX5,
0049 };
0050 
0051 enum {
0052     SGPIO_FLAGS_HAS_IRQ = BIT(0),
0053 };
0054 
0055 struct sgpio_properties {
0056     int arch;
0057     int flags;
0058     u8 regoff[MAXREG];
0059 };
0060 
0061 #define SGPIO_LUTON_AUTO_REPEAT  BIT(5)
0062 #define SGPIO_LUTON_PORT_WIDTH   GENMASK(3, 2)
0063 #define SGPIO_LUTON_CLK_FREQ     GENMASK(11, 0)
0064 #define SGPIO_LUTON_BIT_SOURCE   GENMASK(11, 0)
0065 
0066 #define SGPIO_OCELOT_AUTO_REPEAT BIT(10)
0067 #define SGPIO_OCELOT_SINGLE_SHOT BIT(11)
0068 #define SGPIO_OCELOT_PORT_WIDTH  GENMASK(8, 7)
0069 #define SGPIO_OCELOT_CLK_FREQ    GENMASK(19, 8)
0070 #define SGPIO_OCELOT_BIT_SOURCE  GENMASK(23, 12)
0071 
0072 #define SGPIO_SPARX5_AUTO_REPEAT BIT(6)
0073 #define SGPIO_SPARX5_SINGLE_SHOT BIT(7)
0074 #define SGPIO_SPARX5_PORT_WIDTH  GENMASK(4, 3)
0075 #define SGPIO_SPARX5_CLK_FREQ    GENMASK(19, 8)
0076 #define SGPIO_SPARX5_BIT_SOURCE  GENMASK(23, 12)
0077 
0078 #define SGPIO_MASTER_INTR_ENA    BIT(0)
0079 
0080 #define SGPIO_INT_TRG_LEVEL 0
0081 #define SGPIO_INT_TRG_EDGE  1
0082 #define SGPIO_INT_TRG_EDGE_FALL 2
0083 #define SGPIO_INT_TRG_EDGE_RISE 3
0084 
0085 #define SGPIO_TRG_LEVEL_HIGH    0
0086 #define SGPIO_TRG_LEVEL_LOW 1
0087 
0088 static const struct sgpio_properties properties_luton = {
0089     .arch   = SGPIO_ARCH_LUTON,
0090     .regoff = { 0x00, 0x09, 0x29, 0x2a, 0x2b },
0091 };
0092 
0093 static const struct sgpio_properties properties_ocelot = {
0094     .arch   = SGPIO_ARCH_OCELOT,
0095     .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05 },
0096 };
0097 
0098 static const struct sgpio_properties properties_sparx5 = {
0099     .arch   = SGPIO_ARCH_SPARX5,
0100     .flags  = SGPIO_FLAGS_HAS_IRQ,
0101     .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05, 0x2a, 0x32, 0x3a, 0x3e, 0x42 },
0102 };
0103 
0104 static const char * const functions[] = { "gpio" };
0105 
0106 struct sgpio_bank {
0107     struct sgpio_priv *priv;
0108     bool is_input;
0109     struct gpio_chip gpio;
0110     struct pinctrl_desc pctl_desc;
0111 };
0112 
0113 struct sgpio_priv {
0114     struct device *dev;
0115     struct sgpio_bank in;
0116     struct sgpio_bank out;
0117     u32 bitcount;
0118     u32 ports;
0119     u32 clock;
0120     struct regmap *regs;
0121     const struct sgpio_properties *properties;
0122     spinlock_t lock;
0123     /* protects the config register and single shot mode */
0124     struct mutex poll_lock;
0125 };
0126 
0127 struct sgpio_port_addr {
0128     u8 port;
0129     u8 bit;
0130 };
0131 
0132 static inline void sgpio_pin_to_addr(struct sgpio_priv *priv, int pin,
0133                      struct sgpio_port_addr *addr)
0134 {
0135     addr->port = pin / priv->bitcount;
0136     addr->bit = pin % priv->bitcount;
0137 }
0138 
0139 static inline int sgpio_addr_to_pin(struct sgpio_priv *priv, int port, int bit)
0140 {
0141     return bit + port * priv->bitcount;
0142 }
0143 
0144 static inline u32 sgpio_get_addr(struct sgpio_priv *priv, u32 rno, u32 off)
0145 {
0146     return (priv->properties->regoff[rno] + off) *
0147         regmap_get_reg_stride(priv->regs);
0148 }
0149 
0150 static u32 sgpio_readl(struct sgpio_priv *priv, u32 rno, u32 off)
0151 {
0152     u32 addr = sgpio_get_addr(priv, rno, off);
0153     u32 val = 0;
0154     int ret;
0155 
0156     ret = regmap_read(priv->regs, addr, &val);
0157     WARN_ONCE(ret, "error reading sgpio reg %d\n", ret);
0158 
0159     return val;
0160 }
0161 
0162 static void sgpio_writel(struct sgpio_priv *priv,
0163                 u32 val, u32 rno, u32 off)
0164 {
0165     u32 addr = sgpio_get_addr(priv, rno, off);
0166     int ret;
0167 
0168     ret = regmap_write(priv->regs, addr, val);
0169     WARN_ONCE(ret, "error writing sgpio reg %d\n", ret);
0170 }
0171 
0172 static inline void sgpio_clrsetbits(struct sgpio_priv *priv,
0173                     u32 rno, u32 off, u32 clear, u32 set)
0174 {
0175     u32 addr = sgpio_get_addr(priv, rno, off);
0176     int ret;
0177 
0178     ret = regmap_update_bits(priv->regs, addr, clear | set, set);
0179     WARN_ONCE(ret, "error updating sgpio reg %d\n", ret);
0180 }
0181 
0182 static inline void sgpio_configure_bitstream(struct sgpio_priv *priv)
0183 {
0184     int width = priv->bitcount - 1;
0185     u32 clr, set;
0186 
0187     switch (priv->properties->arch) {
0188     case SGPIO_ARCH_LUTON:
0189         clr = SGPIO_LUTON_PORT_WIDTH;
0190         set = SGPIO_LUTON_AUTO_REPEAT |
0191             FIELD_PREP(SGPIO_LUTON_PORT_WIDTH, width);
0192         break;
0193     case SGPIO_ARCH_OCELOT:
0194         clr = SGPIO_OCELOT_PORT_WIDTH;
0195         set = SGPIO_OCELOT_AUTO_REPEAT |
0196             FIELD_PREP(SGPIO_OCELOT_PORT_WIDTH, width);
0197         break;
0198     case SGPIO_ARCH_SPARX5:
0199         clr = SGPIO_SPARX5_PORT_WIDTH;
0200         set = SGPIO_SPARX5_AUTO_REPEAT |
0201             FIELD_PREP(SGPIO_SPARX5_PORT_WIDTH, width);
0202         break;
0203     default:
0204         return;
0205     }
0206     sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, clr, set);
0207 }
0208 
0209 static inline void sgpio_configure_clock(struct sgpio_priv *priv, u32 clkfrq)
0210 {
0211     u32 clr, set;
0212 
0213     switch (priv->properties->arch) {
0214     case SGPIO_ARCH_LUTON:
0215         clr = SGPIO_LUTON_CLK_FREQ;
0216         set = FIELD_PREP(SGPIO_LUTON_CLK_FREQ, clkfrq);
0217         break;
0218     case SGPIO_ARCH_OCELOT:
0219         clr = SGPIO_OCELOT_CLK_FREQ;
0220         set = FIELD_PREP(SGPIO_OCELOT_CLK_FREQ, clkfrq);
0221         break;
0222     case SGPIO_ARCH_SPARX5:
0223         clr = SGPIO_SPARX5_CLK_FREQ;
0224         set = FIELD_PREP(SGPIO_SPARX5_CLK_FREQ, clkfrq);
0225         break;
0226     default:
0227         return;
0228     }
0229     sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0, clr, set);
0230 }
0231 
0232 static int sgpio_single_shot(struct sgpio_priv *priv)
0233 {
0234     u32 addr = sgpio_get_addr(priv, REG_SIO_CONFIG, 0);
0235     int ret, ret2;
0236     u32 ctrl;
0237     unsigned int single_shot;
0238     unsigned int auto_repeat;
0239 
0240     switch (priv->properties->arch) {
0241     case SGPIO_ARCH_LUTON:
0242         /* not supported for now */
0243         return 0;
0244     case SGPIO_ARCH_OCELOT:
0245         single_shot = SGPIO_OCELOT_SINGLE_SHOT;
0246         auto_repeat = SGPIO_OCELOT_AUTO_REPEAT;
0247         break;
0248     case SGPIO_ARCH_SPARX5:
0249         single_shot = SGPIO_SPARX5_SINGLE_SHOT;
0250         auto_repeat = SGPIO_SPARX5_AUTO_REPEAT;
0251         break;
0252     default:
0253         return -EINVAL;
0254     }
0255 
0256     /*
0257      * Trigger immediate burst. This only works when auto repeat is turned
0258      * off. Otherwise, the single shot bit will never be cleared by the
0259      * hardware. Measurements showed that an update might take as long as
0260      * the burst gap. On a LAN9668 this is about 50ms for the largest
0261      * setting.
0262      * After the manual burst, reenable the auto repeat mode again.
0263      */
0264     mutex_lock(&priv->poll_lock);
0265     ret = regmap_update_bits(priv->regs, addr, single_shot | auto_repeat,
0266                  single_shot);
0267     if (ret)
0268         goto out;
0269 
0270     ret = regmap_read_poll_timeout(priv->regs, addr, ctrl,
0271                        !(ctrl & single_shot), 100, 60000);
0272 
0273     /* reenable auto repeat mode even if there was an error */
0274     ret2 = regmap_update_bits(priv->regs, addr, auto_repeat, auto_repeat);
0275 out:
0276     mutex_unlock(&priv->poll_lock);
0277 
0278     return ret ?: ret2;
0279 }
0280 
0281 static int sgpio_output_set(struct sgpio_priv *priv,
0282                 struct sgpio_port_addr *addr,
0283                 int value)
0284 {
0285     unsigned int bit = SGPIO_SRC_BITS * addr->bit;
0286     u32 reg = sgpio_get_addr(priv, REG_PORT_CONFIG, addr->port);
0287     bool changed;
0288     u32 clr, set;
0289     int ret;
0290 
0291     switch (priv->properties->arch) {
0292     case SGPIO_ARCH_LUTON:
0293         clr = FIELD_PREP(SGPIO_LUTON_BIT_SOURCE, BIT(bit));
0294         set = FIELD_PREP(SGPIO_LUTON_BIT_SOURCE, value << bit);
0295         break;
0296     case SGPIO_ARCH_OCELOT:
0297         clr = FIELD_PREP(SGPIO_OCELOT_BIT_SOURCE, BIT(bit));
0298         set = FIELD_PREP(SGPIO_OCELOT_BIT_SOURCE, value << bit);
0299         break;
0300     case SGPIO_ARCH_SPARX5:
0301         clr = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, BIT(bit));
0302         set = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, value << bit);
0303         break;
0304     default:
0305         return -EINVAL;
0306     }
0307 
0308     ret = regmap_update_bits_check(priv->regs, reg, clr | set, set,
0309                        &changed);
0310     if (ret)
0311         return ret;
0312 
0313     if (changed) {
0314         ret = sgpio_single_shot(priv);
0315         if (ret)
0316             return ret;
0317     }
0318 
0319     return 0;
0320 }
0321 
0322 static int sgpio_output_get(struct sgpio_priv *priv,
0323                 struct sgpio_port_addr *addr)
0324 {
0325     u32 val, portval = sgpio_readl(priv, REG_PORT_CONFIG, addr->port);
0326     unsigned int bit = SGPIO_SRC_BITS * addr->bit;
0327 
0328     switch (priv->properties->arch) {
0329     case SGPIO_ARCH_LUTON:
0330         val = FIELD_GET(SGPIO_LUTON_BIT_SOURCE, portval);
0331         break;
0332     case SGPIO_ARCH_OCELOT:
0333         val = FIELD_GET(SGPIO_OCELOT_BIT_SOURCE, portval);
0334         break;
0335     case SGPIO_ARCH_SPARX5:
0336         val = FIELD_GET(SGPIO_SPARX5_BIT_SOURCE, portval);
0337         break;
0338     default:
0339         val = 0;
0340         break;
0341     }
0342     return !!(val & BIT(bit));
0343 }
0344 
0345 static int sgpio_input_get(struct sgpio_priv *priv,
0346                struct sgpio_port_addr *addr)
0347 {
0348     return !!(sgpio_readl(priv, REG_INPUT_DATA, addr->bit) & BIT(addr->port));
0349 }
0350 
0351 static int sgpio_pinconf_get(struct pinctrl_dev *pctldev,
0352                  unsigned int pin, unsigned long *config)
0353 {
0354     struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
0355     u32 param = pinconf_to_config_param(*config);
0356     struct sgpio_priv *priv = bank->priv;
0357     struct sgpio_port_addr addr;
0358     int val;
0359 
0360     sgpio_pin_to_addr(priv, pin, &addr);
0361 
0362     switch (param) {
0363     case PIN_CONFIG_INPUT_ENABLE:
0364         val = bank->is_input;
0365         break;
0366 
0367     case PIN_CONFIG_OUTPUT_ENABLE:
0368         val = !bank->is_input;
0369         break;
0370 
0371     case PIN_CONFIG_OUTPUT:
0372         if (bank->is_input)
0373             return -EINVAL;
0374         val = sgpio_output_get(priv, &addr);
0375         break;
0376 
0377     default:
0378         return -ENOTSUPP;
0379     }
0380 
0381     *config = pinconf_to_config_packed(param, val);
0382 
0383     return 0;
0384 }
0385 
0386 static int sgpio_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
0387                  unsigned long *configs, unsigned int num_configs)
0388 {
0389     struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
0390     struct sgpio_priv *priv = bank->priv;
0391     struct sgpio_port_addr addr;
0392     int cfg, err = 0;
0393     u32 param, arg;
0394 
0395     sgpio_pin_to_addr(priv, pin, &addr);
0396 
0397     for (cfg = 0; cfg < num_configs; cfg++) {
0398         param = pinconf_to_config_param(configs[cfg]);
0399         arg = pinconf_to_config_argument(configs[cfg]);
0400 
0401         switch (param) {
0402         case PIN_CONFIG_OUTPUT:
0403             if (bank->is_input)
0404                 return -EINVAL;
0405             err = sgpio_output_set(priv, &addr, arg);
0406             break;
0407 
0408         default:
0409             err = -ENOTSUPP;
0410         }
0411     }
0412 
0413     return err;
0414 }
0415 
0416 static const struct pinconf_ops sgpio_confops = {
0417     .is_generic = true,
0418     .pin_config_get = sgpio_pinconf_get,
0419     .pin_config_set = sgpio_pinconf_set,
0420     .pin_config_config_dbg_show = pinconf_generic_dump_config,
0421 };
0422 
0423 static int sgpio_get_functions_count(struct pinctrl_dev *pctldev)
0424 {
0425     return 1;
0426 }
0427 
0428 static const char *sgpio_get_function_name(struct pinctrl_dev *pctldev,
0429                        unsigned int function)
0430 {
0431     return functions[0];
0432 }
0433 
0434 static int sgpio_get_function_groups(struct pinctrl_dev *pctldev,
0435                      unsigned int function,
0436                      const char *const **groups,
0437                      unsigned *const num_groups)
0438 {
0439     *groups  = functions;
0440     *num_groups = ARRAY_SIZE(functions);
0441 
0442     return 0;
0443 }
0444 
0445 static int sgpio_pinmux_set_mux(struct pinctrl_dev *pctldev,
0446                 unsigned int selector, unsigned int group)
0447 {
0448     return 0;
0449 }
0450 
0451 static int sgpio_gpio_set_direction(struct pinctrl_dev *pctldev,
0452                     struct pinctrl_gpio_range *range,
0453                     unsigned int pin, bool input)
0454 {
0455     struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
0456 
0457     return (input == bank->is_input) ? 0 : -EINVAL;
0458 }
0459 
0460 static int sgpio_gpio_request_enable(struct pinctrl_dev *pctldev,
0461                      struct pinctrl_gpio_range *range,
0462                      unsigned int offset)
0463 {
0464     struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
0465     struct sgpio_priv *priv = bank->priv;
0466     struct sgpio_port_addr addr;
0467 
0468     sgpio_pin_to_addr(priv, offset, &addr);
0469 
0470     if ((priv->ports & BIT(addr.port)) == 0) {
0471         dev_warn(priv->dev, "Request port %d.%d: Port is not enabled\n",
0472              addr.port, addr.bit);
0473         return -EINVAL;
0474     }
0475 
0476     return 0;
0477 }
0478 
0479 static const struct pinmux_ops sgpio_pmx_ops = {
0480     .get_functions_count = sgpio_get_functions_count,
0481     .get_function_name = sgpio_get_function_name,
0482     .get_function_groups = sgpio_get_function_groups,
0483     .set_mux = sgpio_pinmux_set_mux,
0484     .gpio_set_direction = sgpio_gpio_set_direction,
0485     .gpio_request_enable = sgpio_gpio_request_enable,
0486 };
0487 
0488 static int sgpio_pctl_get_groups_count(struct pinctrl_dev *pctldev)
0489 {
0490     struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
0491 
0492     return bank->pctl_desc.npins;
0493 }
0494 
0495 static const char *sgpio_pctl_get_group_name(struct pinctrl_dev *pctldev,
0496                          unsigned int group)
0497 {
0498     struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
0499 
0500     return bank->pctl_desc.pins[group].name;
0501 }
0502 
0503 static int sgpio_pctl_get_group_pins(struct pinctrl_dev *pctldev,
0504                      unsigned int group,
0505                      const unsigned int **pins,
0506                      unsigned int *num_pins)
0507 {
0508     struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
0509 
0510     *pins = &bank->pctl_desc.pins[group].number;
0511     *num_pins = 1;
0512 
0513     return 0;
0514 }
0515 
0516 static const struct pinctrl_ops sgpio_pctl_ops = {
0517     .get_groups_count = sgpio_pctl_get_groups_count,
0518     .get_group_name = sgpio_pctl_get_group_name,
0519     .get_group_pins = sgpio_pctl_get_group_pins,
0520     .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
0521     .dt_free_map = pinconf_generic_dt_free_map,
0522 };
0523 
0524 static int microchip_sgpio_direction_input(struct gpio_chip *gc, unsigned int gpio)
0525 {
0526     struct sgpio_bank *bank = gpiochip_get_data(gc);
0527 
0528     /* Fixed-position function */
0529     return bank->is_input ? 0 : -EINVAL;
0530 }
0531 
0532 static int microchip_sgpio_direction_output(struct gpio_chip *gc,
0533                        unsigned int gpio, int value)
0534 {
0535     struct sgpio_bank *bank = gpiochip_get_data(gc);
0536     struct sgpio_priv *priv = bank->priv;
0537     struct sgpio_port_addr addr;
0538 
0539     /* Fixed-position function */
0540     if (bank->is_input)
0541         return -EINVAL;
0542 
0543     sgpio_pin_to_addr(priv, gpio, &addr);
0544 
0545     return sgpio_output_set(priv, &addr, value);
0546 }
0547 
0548 static int microchip_sgpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
0549 {
0550     struct sgpio_bank *bank = gpiochip_get_data(gc);
0551 
0552     return bank->is_input ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT;
0553 }
0554 
0555 static void microchip_sgpio_set_value(struct gpio_chip *gc,
0556                 unsigned int gpio, int value)
0557 {
0558     microchip_sgpio_direction_output(gc, gpio, value);
0559 }
0560 
0561 static int microchip_sgpio_get_value(struct gpio_chip *gc, unsigned int gpio)
0562 {
0563     struct sgpio_bank *bank = gpiochip_get_data(gc);
0564     struct sgpio_priv *priv = bank->priv;
0565     struct sgpio_port_addr addr;
0566 
0567     sgpio_pin_to_addr(priv, gpio, &addr);
0568 
0569     return bank->is_input ? sgpio_input_get(priv, &addr) : sgpio_output_get(priv, &addr);
0570 }
0571 
0572 static int microchip_sgpio_of_xlate(struct gpio_chip *gc,
0573                    const struct of_phandle_args *gpiospec,
0574                    u32 *flags)
0575 {
0576     struct sgpio_bank *bank = gpiochip_get_data(gc);
0577     struct sgpio_priv *priv = bank->priv;
0578     int pin;
0579 
0580     /*
0581      * Note that the SGIO pin is defined by *2* numbers, a port
0582      * number between 0 and 31, and a bit index, 0 to 3.
0583      */
0584     if (gpiospec->args[0] > SGPIO_BITS_PER_WORD ||
0585         gpiospec->args[1] > priv->bitcount)
0586         return -EINVAL;
0587 
0588     pin = sgpio_addr_to_pin(priv, gpiospec->args[0], gpiospec->args[1]);
0589 
0590     if (pin > gc->ngpio)
0591         return -EINVAL;
0592 
0593     if (flags)
0594         *flags = gpiospec->args[2];
0595 
0596     return pin;
0597 }
0598 
0599 static int microchip_sgpio_get_ports(struct sgpio_priv *priv)
0600 {
0601     const char *range_property_name = "microchip,sgpio-port-ranges";
0602     struct device *dev = priv->dev;
0603     u32 range_params[64];
0604     int i, nranges, ret;
0605 
0606     /* Calculate port mask */
0607     nranges = device_property_count_u32(dev, range_property_name);
0608     if (nranges < 2 || nranges % 2 || nranges > ARRAY_SIZE(range_params)) {
0609         dev_err(dev, "%s port range: '%s' property\n",
0610             nranges == -EINVAL ? "Missing" : "Invalid",
0611             range_property_name);
0612         return -EINVAL;
0613     }
0614 
0615     ret = device_property_read_u32_array(dev, range_property_name,
0616                          range_params, nranges);
0617     if (ret) {
0618         dev_err(dev, "failed to parse '%s' property: %d\n",
0619             range_property_name, ret);
0620         return ret;
0621     }
0622     for (i = 0; i < nranges; i += 2) {
0623         int start, end;
0624 
0625         start = range_params[i];
0626         end = range_params[i + 1];
0627         if (start > end || end >= SGPIO_BITS_PER_WORD) {
0628             dev_err(dev, "Ill-formed port-range [%d:%d]\n",
0629                 start, end);
0630         }
0631         priv->ports |= GENMASK(end, start);
0632     }
0633 
0634     return 0;
0635 }
0636 
0637 static void microchip_sgpio_irq_settype(struct irq_data *data,
0638                     int type,
0639                     int polarity)
0640 {
0641     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
0642     struct sgpio_bank *bank = gpiochip_get_data(chip);
0643     unsigned int gpio = irqd_to_hwirq(data);
0644     struct sgpio_port_addr addr;
0645     unsigned long flags;
0646     u32 ena;
0647 
0648     sgpio_pin_to_addr(bank->priv, gpio, &addr);
0649 
0650     spin_lock_irqsave(&bank->priv->lock, flags);
0651 
0652     /* Disable interrupt while changing type */
0653     ena = sgpio_readl(bank->priv, REG_INT_ENABLE, addr.bit);
0654     sgpio_writel(bank->priv, ena & ~BIT(addr.port), REG_INT_ENABLE, addr.bit);
0655 
0656     /* Type value spread over 2 registers sets: low, high bit */
0657     sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, addr.bit,
0658              BIT(addr.port), (!!(type & 0x1)) << addr.port);
0659     sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, SGPIO_MAX_BITS + addr.bit,
0660              BIT(addr.port), (!!(type & 0x2)) << addr.port);
0661 
0662     if (type == SGPIO_INT_TRG_LEVEL)
0663         sgpio_clrsetbits(bank->priv, REG_INT_POLARITY, addr.bit,
0664                  BIT(addr.port), polarity << addr.port);
0665 
0666     /* Possibly re-enable interrupts */
0667     sgpio_writel(bank->priv, ena, REG_INT_ENABLE, addr.bit);
0668 
0669     spin_unlock_irqrestore(&bank->priv->lock, flags);
0670 }
0671 
0672 static void microchip_sgpio_irq_setreg(struct irq_data *data,
0673                        int reg,
0674                        bool clear)
0675 {
0676     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
0677     struct sgpio_bank *bank = gpiochip_get_data(chip);
0678     unsigned int gpio = irqd_to_hwirq(data);
0679     struct sgpio_port_addr addr;
0680 
0681     sgpio_pin_to_addr(bank->priv, gpio, &addr);
0682 
0683     if (clear)
0684         sgpio_clrsetbits(bank->priv, reg, addr.bit, BIT(addr.port), 0);
0685     else
0686         sgpio_clrsetbits(bank->priv, reg, addr.bit, 0, BIT(addr.port));
0687 }
0688 
0689 static void microchip_sgpio_irq_mask(struct irq_data *data)
0690 {
0691     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
0692 
0693     microchip_sgpio_irq_setreg(data, REG_INT_ENABLE, true);
0694     gpiochip_disable_irq(chip, data->hwirq);
0695 }
0696 
0697 static void microchip_sgpio_irq_unmask(struct irq_data *data)
0698 {
0699     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
0700 
0701     gpiochip_enable_irq(chip, data->hwirq);
0702     microchip_sgpio_irq_setreg(data, REG_INT_ENABLE, false);
0703 }
0704 
0705 static void microchip_sgpio_irq_ack(struct irq_data *data)
0706 {
0707     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
0708     struct sgpio_bank *bank = gpiochip_get_data(chip);
0709     unsigned int gpio = irqd_to_hwirq(data);
0710     struct sgpio_port_addr addr;
0711 
0712     sgpio_pin_to_addr(bank->priv, gpio, &addr);
0713 
0714     sgpio_writel(bank->priv, BIT(addr.port), REG_INT_ACK, addr.bit);
0715 }
0716 
0717 static int microchip_sgpio_irq_set_type(struct irq_data *data, unsigned int type)
0718 {
0719     type &= IRQ_TYPE_SENSE_MASK;
0720 
0721     switch (type) {
0722     case IRQ_TYPE_EDGE_BOTH:
0723         irq_set_handler_locked(data, handle_edge_irq);
0724         microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE, 0);
0725         break;
0726     case IRQ_TYPE_EDGE_RISING:
0727         irq_set_handler_locked(data, handle_edge_irq);
0728         microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE_RISE, 0);
0729         break;
0730     case IRQ_TYPE_EDGE_FALLING:
0731         irq_set_handler_locked(data, handle_edge_irq);
0732         microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE_FALL, 0);
0733         break;
0734     case IRQ_TYPE_LEVEL_HIGH:
0735         irq_set_handler_locked(data, handle_level_irq);
0736         microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_LEVEL, SGPIO_TRG_LEVEL_HIGH);
0737         break;
0738     case IRQ_TYPE_LEVEL_LOW:
0739         irq_set_handler_locked(data, handle_level_irq);
0740         microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_LEVEL, SGPIO_TRG_LEVEL_LOW);
0741         break;
0742     default:
0743         return -EINVAL;
0744     }
0745 
0746     return 0;
0747 }
0748 
0749 static const struct irq_chip microchip_sgpio_irqchip = {
0750     .name       = "gpio",
0751     .irq_mask   = microchip_sgpio_irq_mask,
0752     .irq_ack    = microchip_sgpio_irq_ack,
0753     .irq_unmask = microchip_sgpio_irq_unmask,
0754     .irq_set_type   = microchip_sgpio_irq_set_type,
0755     .flags      = IRQCHIP_IMMUTABLE,
0756     GPIOCHIP_IRQ_RESOURCE_HELPERS,
0757 };
0758 
0759 static void sgpio_irq_handler(struct irq_desc *desc)
0760 {
0761     struct irq_chip *parent_chip = irq_desc_get_chip(desc);
0762     struct gpio_chip *chip = irq_desc_get_handler_data(desc);
0763     struct sgpio_bank *bank = gpiochip_get_data(chip);
0764     struct sgpio_priv *priv = bank->priv;
0765     int bit, port, gpio;
0766     long val;
0767 
0768     for (bit = 0; bit < priv->bitcount; bit++) {
0769         val = sgpio_readl(priv, REG_INT_IDENT, bit);
0770         if (!val)
0771             continue;
0772 
0773         chained_irq_enter(parent_chip, desc);
0774 
0775         for_each_set_bit(port, &val, SGPIO_BITS_PER_WORD) {
0776             gpio = sgpio_addr_to_pin(priv, port, bit);
0777             generic_handle_domain_irq(chip->irq.domain, gpio);
0778         }
0779 
0780         chained_irq_exit(parent_chip, desc);
0781     }
0782 }
0783 
0784 static int microchip_sgpio_register_bank(struct device *dev,
0785                      struct sgpio_priv *priv,
0786                      struct fwnode_handle *fwnode,
0787                      int bankno)
0788 {
0789     struct pinctrl_pin_desc *pins;
0790     struct pinctrl_desc *pctl_desc;
0791     struct pinctrl_dev *pctldev;
0792     struct sgpio_bank *bank;
0793     struct gpio_chip *gc;
0794     u32 ngpios;
0795     int i, ret;
0796 
0797     /* Get overall bank struct */
0798     bank = (bankno == 0) ? &priv->in : &priv->out;
0799     bank->priv = priv;
0800 
0801     if (fwnode_property_read_u32(fwnode, "ngpios", &ngpios)) {
0802         dev_info(dev, "failed to get number of gpios for bank%d\n",
0803              bankno);
0804         ngpios = 64;
0805     }
0806 
0807     priv->bitcount = ngpios / SGPIO_BITS_PER_WORD;
0808     if (priv->bitcount > SGPIO_MAX_BITS) {
0809         dev_err(dev, "Bit width exceeds maximum (%d)\n",
0810             SGPIO_MAX_BITS);
0811         return -EINVAL;
0812     }
0813 
0814     pctl_desc = &bank->pctl_desc;
0815     pctl_desc->name = devm_kasprintf(dev, GFP_KERNEL, "%s-%sput",
0816                      dev_name(dev),
0817                      bank->is_input ? "in" : "out");
0818     pctl_desc->pctlops = &sgpio_pctl_ops;
0819     pctl_desc->pmxops = &sgpio_pmx_ops;
0820     pctl_desc->confops = &sgpio_confops;
0821     pctl_desc->owner = THIS_MODULE;
0822 
0823     pins = devm_kzalloc(dev, sizeof(*pins)*ngpios, GFP_KERNEL);
0824     if (!pins)
0825         return -ENOMEM;
0826 
0827     pctl_desc->npins = ngpios;
0828     pctl_desc->pins = pins;
0829 
0830     for (i = 0; i < ngpios; i++) {
0831         struct sgpio_port_addr addr;
0832 
0833         sgpio_pin_to_addr(priv, i, &addr);
0834 
0835         pins[i].number = i;
0836         pins[i].name = devm_kasprintf(dev, GFP_KERNEL,
0837                           "SGPIO_%c_p%db%d",
0838                           bank->is_input ? 'I' : 'O',
0839                           addr.port, addr.bit);
0840         if (!pins[i].name)
0841             return -ENOMEM;
0842     }
0843 
0844     pctldev = devm_pinctrl_register(dev, pctl_desc, bank);
0845     if (IS_ERR(pctldev))
0846         return dev_err_probe(dev, PTR_ERR(pctldev), "Failed to register pinctrl\n");
0847 
0848     gc          = &bank->gpio;
0849     gc->label       = pctl_desc->name;
0850     gc->parent      = dev;
0851     gc->fwnode      = fwnode;
0852     gc->owner       = THIS_MODULE;
0853     gc->get_direction   = microchip_sgpio_get_direction;
0854     gc->direction_input = microchip_sgpio_direction_input;
0855     gc->direction_output    = microchip_sgpio_direction_output;
0856     gc->get         = microchip_sgpio_get_value;
0857     gc->set         = microchip_sgpio_set_value;
0858     gc->request     = gpiochip_generic_request;
0859     gc->free        = gpiochip_generic_free;
0860     gc->of_xlate        = microchip_sgpio_of_xlate;
0861     gc->of_gpio_n_cells     = 3;
0862     gc->base        = -1;
0863     gc->ngpio       = ngpios;
0864     gc->can_sleep       = !bank->is_input;
0865 
0866     if (bank->is_input && priv->properties->flags & SGPIO_FLAGS_HAS_IRQ) {
0867         int irq = fwnode_irq_get(fwnode, 0);
0868 
0869         if (irq) {
0870             struct gpio_irq_chip *girq = &gc->irq;
0871 
0872             gpio_irq_chip_set_chip(girq, &microchip_sgpio_irqchip);
0873             girq->parent_handler = sgpio_irq_handler;
0874             girq->num_parents = 1;
0875             girq->parents = devm_kcalloc(dev, 1,
0876                              sizeof(*girq->parents),
0877                              GFP_KERNEL);
0878             if (!girq->parents)
0879                 return -ENOMEM;
0880             girq->parents[0] = irq;
0881             girq->default_type = IRQ_TYPE_NONE;
0882             girq->handler = handle_bad_irq;
0883 
0884             /* Disable all individual pins */
0885             for (i = 0; i < SGPIO_MAX_BITS; i++)
0886                 sgpio_writel(priv, 0, REG_INT_ENABLE, i);
0887             /* Master enable */
0888             sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, 0, SGPIO_MASTER_INTR_ENA);
0889         }
0890     }
0891 
0892     ret = devm_gpiochip_add_data(dev, gc, bank);
0893     if (ret)
0894         dev_err(dev, "Failed to register: ret %d\n", ret);
0895 
0896     return ret;
0897 }
0898 
0899 static int microchip_sgpio_probe(struct platform_device *pdev)
0900 {
0901     int div_clock = 0, ret, port, i, nbanks;
0902     struct device *dev = &pdev->dev;
0903     struct fwnode_handle *fwnode;
0904     struct reset_control *reset;
0905     struct sgpio_priv *priv;
0906     struct clk *clk;
0907     u32 __iomem *regs;
0908     u32 val;
0909     struct regmap_config regmap_config = {
0910         .reg_bits = 32,
0911         .val_bits = 32,
0912         .reg_stride = 4,
0913     };
0914 
0915     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0916     if (!priv)
0917         return -ENOMEM;
0918 
0919     priv->dev = dev;
0920     spin_lock_init(&priv->lock);
0921     mutex_init(&priv->poll_lock);
0922 
0923     reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch");
0924     if (IS_ERR(reset))
0925         return dev_err_probe(dev, PTR_ERR(reset), "Failed to get reset\n");
0926     reset_control_reset(reset);
0927 
0928     clk = devm_clk_get(dev, NULL);
0929     if (IS_ERR(clk))
0930         return dev_err_probe(dev, PTR_ERR(clk), "Failed to get clock\n");
0931 
0932     div_clock = clk_get_rate(clk);
0933     if (device_property_read_u32(dev, "bus-frequency", &priv->clock))
0934         priv->clock = 12500000;
0935     if (priv->clock == 0 || priv->clock > (div_clock / 2)) {
0936         dev_err(dev, "Invalid frequency %d\n", priv->clock);
0937         return -EINVAL;
0938     }
0939 
0940     regs = devm_platform_ioremap_resource(pdev, 0);
0941     if (IS_ERR(regs))
0942         return PTR_ERR(regs);
0943 
0944     priv->regs = devm_regmap_init_mmio(dev, regs, &regmap_config);
0945     if (IS_ERR(priv->regs))
0946         return PTR_ERR(priv->regs);
0947 
0948     priv->properties = device_get_match_data(dev);
0949     priv->in.is_input = true;
0950 
0951     /* Get rest of device properties */
0952     ret = microchip_sgpio_get_ports(priv);
0953     if (ret)
0954         return ret;
0955 
0956     nbanks = device_get_child_node_count(dev);
0957     if (nbanks != 2) {
0958         dev_err(dev, "Must have 2 banks (have %d)\n", nbanks);
0959         return -EINVAL;
0960     }
0961 
0962     i = 0;
0963     device_for_each_child_node(dev, fwnode) {
0964         ret = microchip_sgpio_register_bank(dev, priv, fwnode, i++);
0965         if (ret) {
0966             fwnode_handle_put(fwnode);
0967             return ret;
0968         }
0969     }
0970 
0971     if (priv->in.gpio.ngpio != priv->out.gpio.ngpio) {
0972         dev_err(dev, "Banks must have same GPIO count\n");
0973         return -ERANGE;
0974     }
0975 
0976     sgpio_configure_bitstream(priv);
0977 
0978     val = max(2U, div_clock / priv->clock);
0979     sgpio_configure_clock(priv, val);
0980 
0981     for (port = 0; port < SGPIO_BITS_PER_WORD; port++)
0982         sgpio_writel(priv, 0, REG_PORT_CONFIG, port);
0983     sgpio_writel(priv, priv->ports, REG_PORT_ENABLE, 0);
0984 
0985     return 0;
0986 }
0987 
0988 static const struct of_device_id microchip_sgpio_gpio_of_match[] = {
0989     {
0990         .compatible = "microchip,sparx5-sgpio",
0991         .data = &properties_sparx5,
0992     }, {
0993         .compatible = "mscc,luton-sgpio",
0994         .data = &properties_luton,
0995     }, {
0996         .compatible = "mscc,ocelot-sgpio",
0997         .data = &properties_ocelot,
0998     }, {
0999         /* sentinel */
1000     }
1001 };
1002 
1003 static struct platform_driver microchip_sgpio_pinctrl_driver = {
1004     .driver = {
1005         .name = "pinctrl-microchip-sgpio",
1006         .of_match_table = microchip_sgpio_gpio_of_match,
1007         .suppress_bind_attrs = true,
1008     },
1009     .probe = microchip_sgpio_probe,
1010 };
1011 builtin_platform_driver(microchip_sgpio_pinctrl_driver);
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