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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /* MCP23S08 SPI/I2C GPIO driver */
0003 
0004 #include <linux/bitops.h>
0005 #include <linux/kernel.h>
0006 #include <linux/device.h>
0007 #include <linux/mutex.h>
0008 #include <linux/mod_devicetable.h>
0009 #include <linux/module.h>
0010 #include <linux/export.h>
0011 #include <linux/gpio/driver.h>
0012 #include <linux/gpio/consumer.h>
0013 #include <linux/slab.h>
0014 #include <asm/byteorder.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/regmap.h>
0017 #include <linux/pinctrl/pinctrl.h>
0018 #include <linux/pinctrl/pinconf.h>
0019 #include <linux/pinctrl/pinconf-generic.h>
0020 
0021 #include "pinctrl-mcp23s08.h"
0022 
0023 /* Registers are all 8 bits wide.
0024  *
0025  * The mcp23s17 has twice as many bits, and can be configured to work
0026  * with either 16 bit registers or with two adjacent 8 bit banks.
0027  */
0028 #define MCP_IODIR   0x00        /* init/reset:  all ones */
0029 #define MCP_IPOL    0x01
0030 #define MCP_GPINTEN 0x02
0031 #define MCP_DEFVAL  0x03
0032 #define MCP_INTCON  0x04
0033 #define MCP_IOCON   0x05
0034 #   define IOCON_MIRROR (1 << 6)
0035 #   define IOCON_SEQOP  (1 << 5)
0036 #   define IOCON_HAEN   (1 << 3)
0037 #   define IOCON_ODR    (1 << 2)
0038 #   define IOCON_INTPOL (1 << 1)
0039 #   define IOCON_INTCC  (1)
0040 #define MCP_GPPU    0x06
0041 #define MCP_INTF    0x07
0042 #define MCP_INTCAP  0x08
0043 #define MCP_GPIO    0x09
0044 #define MCP_OLAT    0x0a
0045 
0046 static const struct reg_default mcp23x08_defaults[] = {
0047     {.reg = MCP_IODIR,      .def = 0xff},
0048     {.reg = MCP_IPOL,       .def = 0x00},
0049     {.reg = MCP_GPINTEN,        .def = 0x00},
0050     {.reg = MCP_DEFVAL,     .def = 0x00},
0051     {.reg = MCP_INTCON,     .def = 0x00},
0052     {.reg = MCP_IOCON,      .def = 0x00},
0053     {.reg = MCP_GPPU,       .def = 0x00},
0054     {.reg = MCP_OLAT,       .def = 0x00},
0055 };
0056 
0057 static const struct regmap_range mcp23x08_volatile_range = {
0058     .range_min = MCP_INTF,
0059     .range_max = MCP_GPIO,
0060 };
0061 
0062 static const struct regmap_access_table mcp23x08_volatile_table = {
0063     .yes_ranges = &mcp23x08_volatile_range,
0064     .n_yes_ranges = 1,
0065 };
0066 
0067 static const struct regmap_range mcp23x08_precious_range = {
0068     .range_min = MCP_GPIO,
0069     .range_max = MCP_GPIO,
0070 };
0071 
0072 static const struct regmap_access_table mcp23x08_precious_table = {
0073     .yes_ranges = &mcp23x08_precious_range,
0074     .n_yes_ranges = 1,
0075 };
0076 
0077 const struct regmap_config mcp23x08_regmap = {
0078     .reg_bits = 8,
0079     .val_bits = 8,
0080 
0081     .reg_stride = 1,
0082     .volatile_table = &mcp23x08_volatile_table,
0083     .precious_table = &mcp23x08_precious_table,
0084     .reg_defaults = mcp23x08_defaults,
0085     .num_reg_defaults = ARRAY_SIZE(mcp23x08_defaults),
0086     .cache_type = REGCACHE_FLAT,
0087     .max_register = MCP_OLAT,
0088 };
0089 EXPORT_SYMBOL_GPL(mcp23x08_regmap);
0090 
0091 static const struct reg_default mcp23x17_defaults[] = {
0092     {.reg = MCP_IODIR << 1,     .def = 0xffff},
0093     {.reg = MCP_IPOL << 1,      .def = 0x0000},
0094     {.reg = MCP_GPINTEN << 1,   .def = 0x0000},
0095     {.reg = MCP_DEFVAL << 1,    .def = 0x0000},
0096     {.reg = MCP_INTCON << 1,    .def = 0x0000},
0097     {.reg = MCP_IOCON << 1,     .def = 0x0000},
0098     {.reg = MCP_GPPU << 1,      .def = 0x0000},
0099     {.reg = MCP_OLAT << 1,      .def = 0x0000},
0100 };
0101 
0102 static const struct regmap_range mcp23x17_volatile_range = {
0103     .range_min = MCP_INTF << 1,
0104     .range_max = MCP_GPIO << 1,
0105 };
0106 
0107 static const struct regmap_access_table mcp23x17_volatile_table = {
0108     .yes_ranges = &mcp23x17_volatile_range,
0109     .n_yes_ranges = 1,
0110 };
0111 
0112 static const struct regmap_range mcp23x17_precious_range = {
0113     .range_min = MCP_INTCAP << 1,
0114     .range_max = MCP_GPIO << 1,
0115 };
0116 
0117 static const struct regmap_access_table mcp23x17_precious_table = {
0118     .yes_ranges = &mcp23x17_precious_range,
0119     .n_yes_ranges = 1,
0120 };
0121 
0122 const struct regmap_config mcp23x17_regmap = {
0123     .reg_bits = 8,
0124     .val_bits = 16,
0125 
0126     .reg_stride = 2,
0127     .max_register = MCP_OLAT << 1,
0128     .volatile_table = &mcp23x17_volatile_table,
0129     .precious_table = &mcp23x17_precious_table,
0130     .reg_defaults = mcp23x17_defaults,
0131     .num_reg_defaults = ARRAY_SIZE(mcp23x17_defaults),
0132     .cache_type = REGCACHE_FLAT,
0133     .val_format_endian = REGMAP_ENDIAN_LITTLE,
0134 };
0135 EXPORT_SYMBOL_GPL(mcp23x17_regmap);
0136 
0137 static int mcp_read(struct mcp23s08 *mcp, unsigned int reg, unsigned int *val)
0138 {
0139     return regmap_read(mcp->regmap, reg << mcp->reg_shift, val);
0140 }
0141 
0142 static int mcp_write(struct mcp23s08 *mcp, unsigned int reg, unsigned int val)
0143 {
0144     return regmap_write(mcp->regmap, reg << mcp->reg_shift, val);
0145 }
0146 
0147 static int mcp_set_mask(struct mcp23s08 *mcp, unsigned int reg,
0148                unsigned int mask, bool enabled)
0149 {
0150     u16 val  = enabled ? 0xffff : 0x0000;
0151     return regmap_update_bits(mcp->regmap, reg << mcp->reg_shift,
0152                   mask, val);
0153 }
0154 
0155 static int mcp_set_bit(struct mcp23s08 *mcp, unsigned int reg,
0156                unsigned int pin, bool enabled)
0157 {
0158     u16 mask = BIT(pin);
0159     return mcp_set_mask(mcp, reg, mask, enabled);
0160 }
0161 
0162 static const struct pinctrl_pin_desc mcp23x08_pins[] = {
0163     PINCTRL_PIN(0, "gpio0"),
0164     PINCTRL_PIN(1, "gpio1"),
0165     PINCTRL_PIN(2, "gpio2"),
0166     PINCTRL_PIN(3, "gpio3"),
0167     PINCTRL_PIN(4, "gpio4"),
0168     PINCTRL_PIN(5, "gpio5"),
0169     PINCTRL_PIN(6, "gpio6"),
0170     PINCTRL_PIN(7, "gpio7"),
0171 };
0172 
0173 static const struct pinctrl_pin_desc mcp23x17_pins[] = {
0174     PINCTRL_PIN(0, "gpio0"),
0175     PINCTRL_PIN(1, "gpio1"),
0176     PINCTRL_PIN(2, "gpio2"),
0177     PINCTRL_PIN(3, "gpio3"),
0178     PINCTRL_PIN(4, "gpio4"),
0179     PINCTRL_PIN(5, "gpio5"),
0180     PINCTRL_PIN(6, "gpio6"),
0181     PINCTRL_PIN(7, "gpio7"),
0182     PINCTRL_PIN(8, "gpio8"),
0183     PINCTRL_PIN(9, "gpio9"),
0184     PINCTRL_PIN(10, "gpio10"),
0185     PINCTRL_PIN(11, "gpio11"),
0186     PINCTRL_PIN(12, "gpio12"),
0187     PINCTRL_PIN(13, "gpio13"),
0188     PINCTRL_PIN(14, "gpio14"),
0189     PINCTRL_PIN(15, "gpio15"),
0190 };
0191 
0192 static int mcp_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
0193 {
0194     return 0;
0195 }
0196 
0197 static const char *mcp_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
0198                         unsigned int group)
0199 {
0200     return NULL;
0201 }
0202 
0203 static int mcp_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
0204                     unsigned int group,
0205                     const unsigned int **pins,
0206                     unsigned int *num_pins)
0207 {
0208     return -ENOTSUPP;
0209 }
0210 
0211 static const struct pinctrl_ops mcp_pinctrl_ops = {
0212     .get_groups_count = mcp_pinctrl_get_groups_count,
0213     .get_group_name = mcp_pinctrl_get_group_name,
0214     .get_group_pins = mcp_pinctrl_get_group_pins,
0215 #ifdef CONFIG_OF
0216     .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
0217     .dt_free_map = pinconf_generic_dt_free_map,
0218 #endif
0219 };
0220 
0221 static int mcp_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
0222                   unsigned long *config)
0223 {
0224     struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev);
0225     enum pin_config_param param = pinconf_to_config_param(*config);
0226     unsigned int data, status;
0227     int ret;
0228 
0229     switch (param) {
0230     case PIN_CONFIG_BIAS_PULL_UP:
0231         ret = mcp_read(mcp, MCP_GPPU, &data);
0232         if (ret < 0)
0233             return ret;
0234         status = (data & BIT(pin)) ? 1 : 0;
0235         break;
0236     default:
0237         return -ENOTSUPP;
0238     }
0239 
0240     *config = 0;
0241 
0242     return status ? 0 : -EINVAL;
0243 }
0244 
0245 static int mcp_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
0246                   unsigned long *configs, unsigned int num_configs)
0247 {
0248     struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev);
0249     enum pin_config_param param;
0250     u32 arg;
0251     int ret = 0;
0252     int i;
0253 
0254     for (i = 0; i < num_configs; i++) {
0255         param = pinconf_to_config_param(configs[i]);
0256         arg = pinconf_to_config_argument(configs[i]);
0257 
0258         switch (param) {
0259         case PIN_CONFIG_BIAS_PULL_UP:
0260             ret = mcp_set_bit(mcp, MCP_GPPU, pin, arg);
0261             break;
0262         default:
0263             dev_dbg(mcp->dev, "Invalid config param %04x\n", param);
0264             return -ENOTSUPP;
0265         }
0266     }
0267 
0268     return ret;
0269 }
0270 
0271 static const struct pinconf_ops mcp_pinconf_ops = {
0272     .pin_config_get = mcp_pinconf_get,
0273     .pin_config_set = mcp_pinconf_set,
0274     .is_generic = true,
0275 };
0276 
0277 /*----------------------------------------------------------------------*/
0278 
0279 static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset)
0280 {
0281     struct mcp23s08 *mcp = gpiochip_get_data(chip);
0282     int status;
0283 
0284     mutex_lock(&mcp->lock);
0285     status = mcp_set_bit(mcp, MCP_IODIR, offset, true);
0286     mutex_unlock(&mcp->lock);
0287 
0288     return status;
0289 }
0290 
0291 static int mcp23s08_get(struct gpio_chip *chip, unsigned offset)
0292 {
0293     struct mcp23s08 *mcp = gpiochip_get_data(chip);
0294     int status, ret;
0295 
0296     mutex_lock(&mcp->lock);
0297 
0298     /* REVISIT reading this clears any IRQ ... */
0299     ret = mcp_read(mcp, MCP_GPIO, &status);
0300     if (ret < 0)
0301         status = 0;
0302     else {
0303         mcp->cached_gpio = status;
0304         status = !!(status & (1 << offset));
0305     }
0306 
0307     mutex_unlock(&mcp->lock);
0308     return status;
0309 }
0310 
0311 static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, bool value)
0312 {
0313     return mcp_set_mask(mcp, MCP_OLAT, mask, value);
0314 }
0315 
0316 static void mcp23s08_set(struct gpio_chip *chip, unsigned offset, int value)
0317 {
0318     struct mcp23s08 *mcp = gpiochip_get_data(chip);
0319     unsigned mask = BIT(offset);
0320 
0321     mutex_lock(&mcp->lock);
0322     __mcp23s08_set(mcp, mask, !!value);
0323     mutex_unlock(&mcp->lock);
0324 }
0325 
0326 static int
0327 mcp23s08_direction_output(struct gpio_chip *chip, unsigned offset, int value)
0328 {
0329     struct mcp23s08 *mcp = gpiochip_get_data(chip);
0330     unsigned mask = BIT(offset);
0331     int status;
0332 
0333     mutex_lock(&mcp->lock);
0334     status = __mcp23s08_set(mcp, mask, value);
0335     if (status == 0) {
0336         status = mcp_set_mask(mcp, MCP_IODIR, mask, false);
0337     }
0338     mutex_unlock(&mcp->lock);
0339     return status;
0340 }
0341 
0342 /*----------------------------------------------------------------------*/
0343 static irqreturn_t mcp23s08_irq(int irq, void *data)
0344 {
0345     struct mcp23s08 *mcp = data;
0346     int intcap, intcon, intf, i, gpio, gpio_orig, intcap_mask, defval;
0347     unsigned int child_irq;
0348     bool intf_set, intcap_changed, gpio_bit_changed,
0349         defval_changed, gpio_set;
0350 
0351     mutex_lock(&mcp->lock);
0352     if (mcp_read(mcp, MCP_INTF, &intf))
0353         goto unlock;
0354 
0355     if (intf == 0) {
0356         /* There is no interrupt pending */
0357         goto unlock;
0358     }
0359 
0360     if (mcp_read(mcp, MCP_INTCAP, &intcap))
0361         goto unlock;
0362 
0363     if (mcp_read(mcp, MCP_INTCON, &intcon))
0364         goto unlock;
0365 
0366     if (mcp_read(mcp, MCP_DEFVAL, &defval))
0367         goto unlock;
0368 
0369     /* This clears the interrupt(configurable on S18) */
0370     if (mcp_read(mcp, MCP_GPIO, &gpio))
0371         goto unlock;
0372 
0373     gpio_orig = mcp->cached_gpio;
0374     mcp->cached_gpio = gpio;
0375     mutex_unlock(&mcp->lock);
0376 
0377     dev_dbg(mcp->chip.parent,
0378         "intcap 0x%04X intf 0x%04X gpio_orig 0x%04X gpio 0x%04X\n",
0379         intcap, intf, gpio_orig, gpio);
0380 
0381     for (i = 0; i < mcp->chip.ngpio; i++) {
0382         /* We must check all of the inputs on the chip,
0383          * otherwise we may not notice a change on >=2 pins.
0384          *
0385          * On at least the mcp23s17, INTCAP is only updated
0386          * one byte at a time(INTCAPA and INTCAPB are
0387          * not written to at the same time - only on a per-bank
0388          * basis).
0389          *
0390          * INTF only contains the single bit that caused the
0391          * interrupt per-bank.  On the mcp23s17, there is
0392          * INTFA and INTFB.  If two pins are changed on the A
0393          * side at the same time, INTF will only have one bit
0394          * set.  If one pin on the A side and one pin on the B
0395          * side are changed at the same time, INTF will have
0396          * two bits set.  Thus, INTF can't be the only check
0397          * to see if the input has changed.
0398          */
0399 
0400         intf_set = intf & BIT(i);
0401         if (i < 8 && intf_set)
0402             intcap_mask = 0x00FF;
0403         else if (i >= 8 && intf_set)
0404             intcap_mask = 0xFF00;
0405         else
0406             intcap_mask = 0x00;
0407 
0408         intcap_changed = (intcap_mask &
0409             (intcap & BIT(i))) !=
0410             (intcap_mask & (BIT(i) & gpio_orig));
0411         gpio_set = BIT(i) & gpio;
0412         gpio_bit_changed = (BIT(i) & gpio_orig) !=
0413             (BIT(i) & gpio);
0414         defval_changed = (BIT(i) & intcon) &&
0415             ((BIT(i) & gpio) !=
0416             (BIT(i) & defval));
0417 
0418         if (((gpio_bit_changed || intcap_changed) &&
0419             (BIT(i) & mcp->irq_rise) && gpio_set) ||
0420             ((gpio_bit_changed || intcap_changed) &&
0421             (BIT(i) & mcp->irq_fall) && !gpio_set) ||
0422             defval_changed) {
0423             child_irq = irq_find_mapping(mcp->chip.irq.domain, i);
0424             handle_nested_irq(child_irq);
0425         }
0426     }
0427 
0428     return IRQ_HANDLED;
0429 
0430 unlock:
0431     mutex_unlock(&mcp->lock);
0432     return IRQ_HANDLED;
0433 }
0434 
0435 static void mcp23s08_irq_mask(struct irq_data *data)
0436 {
0437     struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
0438     struct mcp23s08 *mcp = gpiochip_get_data(gc);
0439     unsigned int pos = data->hwirq;
0440 
0441     mcp_set_bit(mcp, MCP_GPINTEN, pos, false);
0442 }
0443 
0444 static void mcp23s08_irq_unmask(struct irq_data *data)
0445 {
0446     struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
0447     struct mcp23s08 *mcp = gpiochip_get_data(gc);
0448     unsigned int pos = data->hwirq;
0449 
0450     mcp_set_bit(mcp, MCP_GPINTEN, pos, true);
0451 }
0452 
0453 static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type)
0454 {
0455     struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
0456     struct mcp23s08 *mcp = gpiochip_get_data(gc);
0457     unsigned int pos = data->hwirq;
0458 
0459     if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
0460         mcp_set_bit(mcp, MCP_INTCON, pos, false);
0461         mcp->irq_rise |= BIT(pos);
0462         mcp->irq_fall |= BIT(pos);
0463     } else if (type & IRQ_TYPE_EDGE_RISING) {
0464         mcp_set_bit(mcp, MCP_INTCON, pos, false);
0465         mcp->irq_rise |= BIT(pos);
0466         mcp->irq_fall &= ~BIT(pos);
0467     } else if (type & IRQ_TYPE_EDGE_FALLING) {
0468         mcp_set_bit(mcp, MCP_INTCON, pos, false);
0469         mcp->irq_rise &= ~BIT(pos);
0470         mcp->irq_fall |= BIT(pos);
0471     } else if (type & IRQ_TYPE_LEVEL_HIGH) {
0472         mcp_set_bit(mcp, MCP_INTCON, pos, true);
0473         mcp_set_bit(mcp, MCP_DEFVAL, pos, false);
0474     } else if (type & IRQ_TYPE_LEVEL_LOW) {
0475         mcp_set_bit(mcp, MCP_INTCON, pos, true);
0476         mcp_set_bit(mcp, MCP_DEFVAL, pos, true);
0477     } else
0478         return -EINVAL;
0479 
0480     return 0;
0481 }
0482 
0483 static void mcp23s08_irq_bus_lock(struct irq_data *data)
0484 {
0485     struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
0486     struct mcp23s08 *mcp = gpiochip_get_data(gc);
0487 
0488     mutex_lock(&mcp->lock);
0489     regcache_cache_only(mcp->regmap, true);
0490 }
0491 
0492 static void mcp23s08_irq_bus_unlock(struct irq_data *data)
0493 {
0494     struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
0495     struct mcp23s08 *mcp = gpiochip_get_data(gc);
0496 
0497     regcache_cache_only(mcp->regmap, false);
0498     regcache_sync(mcp->regmap);
0499 
0500     mutex_unlock(&mcp->lock);
0501 }
0502 
0503 static int mcp23s08_irq_setup(struct mcp23s08 *mcp)
0504 {
0505     struct gpio_chip *chip = &mcp->chip;
0506     int err;
0507     unsigned long irqflags = IRQF_ONESHOT | IRQF_SHARED;
0508 
0509     if (mcp->irq_active_high)
0510         irqflags |= IRQF_TRIGGER_HIGH;
0511     else
0512         irqflags |= IRQF_TRIGGER_LOW;
0513 
0514     err = devm_request_threaded_irq(chip->parent, mcp->irq, NULL,
0515                     mcp23s08_irq,
0516                     irqflags, dev_name(chip->parent), mcp);
0517     if (err != 0) {
0518         dev_err(chip->parent, "unable to request IRQ#%d: %d\n",
0519             mcp->irq, err);
0520         return err;
0521     }
0522 
0523     return 0;
0524 }
0525 
0526 /*----------------------------------------------------------------------*/
0527 
0528 int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
0529                unsigned int addr, unsigned int type, unsigned int base)
0530 {
0531     int status, ret;
0532     bool mirror = false;
0533     bool open_drain = false;
0534 
0535     mutex_init(&mcp->lock);
0536 
0537     mcp->dev = dev;
0538     mcp->addr = addr;
0539 
0540     mcp->irq_active_high = false;
0541     mcp->irq_chip.name = dev_name(dev);
0542     mcp->irq_chip.irq_mask = mcp23s08_irq_mask;
0543     mcp->irq_chip.irq_unmask = mcp23s08_irq_unmask;
0544     mcp->irq_chip.irq_set_type = mcp23s08_irq_set_type;
0545     mcp->irq_chip.irq_bus_lock = mcp23s08_irq_bus_lock;
0546     mcp->irq_chip.irq_bus_sync_unlock = mcp23s08_irq_bus_unlock;
0547 
0548     mcp->chip.direction_input = mcp23s08_direction_input;
0549     mcp->chip.get = mcp23s08_get;
0550     mcp->chip.direction_output = mcp23s08_direction_output;
0551     mcp->chip.set = mcp23s08_set;
0552 #ifdef CONFIG_OF_GPIO
0553     mcp->chip.of_gpio_n_cells = 2;
0554 #endif
0555 
0556     mcp->chip.base = base;
0557     mcp->chip.can_sleep = true;
0558     mcp->chip.parent = dev;
0559     mcp->chip.owner = THIS_MODULE;
0560 
0561     mcp->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
0562 
0563     /* verify MCP_IOCON.SEQOP = 0, so sequential reads work,
0564      * and MCP_IOCON.HAEN = 1, so we work with all chips.
0565      */
0566 
0567     ret = mcp_read(mcp, MCP_IOCON, &status);
0568     if (ret < 0)
0569         return dev_err_probe(dev, ret, "can't identify chip %d\n", addr);
0570 
0571     mcp->irq_controller =
0572         device_property_read_bool(dev, "interrupt-controller");
0573     if (mcp->irq && mcp->irq_controller) {
0574         mcp->irq_active_high =
0575             device_property_read_bool(dev,
0576                           "microchip,irq-active-high");
0577 
0578         mirror = device_property_read_bool(dev, "microchip,irq-mirror");
0579         open_drain = device_property_read_bool(dev, "drive-open-drain");
0580     }
0581 
0582     if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN) || mirror ||
0583          mcp->irq_active_high || open_drain) {
0584         /* mcp23s17 has IOCON twice, make sure they are in sync */
0585         status &= ~(IOCON_SEQOP | (IOCON_SEQOP << 8));
0586         status |= IOCON_HAEN | (IOCON_HAEN << 8);
0587         if (mcp->irq_active_high)
0588             status |= IOCON_INTPOL | (IOCON_INTPOL << 8);
0589         else
0590             status &= ~(IOCON_INTPOL | (IOCON_INTPOL << 8));
0591 
0592         if (mirror)
0593             status |= IOCON_MIRROR | (IOCON_MIRROR << 8);
0594 
0595         if (open_drain)
0596             status |= IOCON_ODR | (IOCON_ODR << 8);
0597 
0598         if (type == MCP_TYPE_S18 || type == MCP_TYPE_018)
0599             status |= IOCON_INTCC | (IOCON_INTCC << 8);
0600 
0601         ret = mcp_write(mcp, MCP_IOCON, status);
0602         if (ret < 0)
0603             return dev_err_probe(dev, ret, "can't write IOCON %d\n", addr);
0604     }
0605 
0606     if (mcp->irq && mcp->irq_controller) {
0607         struct gpio_irq_chip *girq = &mcp->chip.irq;
0608 
0609         girq->chip = &mcp->irq_chip;
0610         /* This will let us handle the parent IRQ in the driver */
0611         girq->parent_handler = NULL;
0612         girq->num_parents = 0;
0613         girq->parents = NULL;
0614         girq->default_type = IRQ_TYPE_NONE;
0615         girq->handler = handle_simple_irq;
0616         girq->threaded = true;
0617     }
0618 
0619     ret = devm_gpiochip_add_data(dev, &mcp->chip, mcp);
0620     if (ret < 0)
0621         return dev_err_probe(dev, ret, "can't add GPIO chip\n");
0622 
0623     mcp->pinctrl_desc.pctlops = &mcp_pinctrl_ops;
0624     mcp->pinctrl_desc.confops = &mcp_pinconf_ops;
0625     mcp->pinctrl_desc.npins = mcp->chip.ngpio;
0626     if (mcp->pinctrl_desc.npins == 8)
0627         mcp->pinctrl_desc.pins = mcp23x08_pins;
0628     else if (mcp->pinctrl_desc.npins == 16)
0629         mcp->pinctrl_desc.pins = mcp23x17_pins;
0630     mcp->pinctrl_desc.owner = THIS_MODULE;
0631 
0632     mcp->pctldev = devm_pinctrl_register(dev, &mcp->pinctrl_desc, mcp);
0633     if (IS_ERR(mcp->pctldev))
0634         return dev_err_probe(dev, PTR_ERR(mcp->pctldev), "can't register controller\n");
0635 
0636     if (mcp->irq) {
0637         ret = mcp23s08_irq_setup(mcp);
0638         if (ret)
0639             return dev_err_probe(dev, ret, "can't setup IRQ\n");
0640     }
0641 
0642     return 0;
0643 }
0644 EXPORT_SYMBOL_GPL(mcp23s08_probe_one);
0645 
0646 MODULE_LICENSE("GPL");
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