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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * MAX77620 pin control driver.
0004  *
0005  * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
0006  *
0007  * Author:
0008  *  Chaitanya Bandi <bandik@nvidia.com>
0009  *  Laxman Dewangan <ldewangan@nvidia.com>
0010  */
0011 
0012 #include <linux/mfd/max77620.h>
0013 #include <linux/mod_devicetable.h>
0014 #include <linux/module.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/property.h>
0017 #include <linux/regmap.h>
0018 
0019 #include <linux/pinctrl/pinctrl.h>
0020 #include <linux/pinctrl/pinconf-generic.h>
0021 #include <linux/pinctrl/pinconf.h>
0022 #include <linux/pinctrl/pinmux.h>
0023 
0024 #include "core.h"
0025 #include "pinconf.h"
0026 #include "pinctrl-utils.h"
0027 
0028 #define MAX77620_PIN_NUM 8
0029 
0030 enum max77620_pin_ppdrv {
0031     MAX77620_PIN_UNCONFIG_DRV,
0032     MAX77620_PIN_OD_DRV,
0033     MAX77620_PIN_PP_DRV,
0034 };
0035 
0036 #define MAX77620_ACTIVE_FPS_SOURCE      (PIN_CONFIG_END + 1)
0037 #define MAX77620_ACTIVE_FPS_POWER_ON_SLOTS  (PIN_CONFIG_END + 2)
0038 #define MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS    (PIN_CONFIG_END + 3)
0039 #define MAX77620_SUSPEND_FPS_SOURCE     (PIN_CONFIG_END + 4)
0040 #define MAX77620_SUSPEND_FPS_POWER_ON_SLOTS (PIN_CONFIG_END + 5)
0041 #define MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS   (PIN_CONFIG_END + 6)
0042 
0043 struct max77620_pin_function {
0044     const char *name;
0045     const char * const *groups;
0046     unsigned int ngroups;
0047     int mux_option;
0048 };
0049 
0050 static const struct pinconf_generic_params max77620_cfg_params[] = {
0051     {
0052         .property = "maxim,active-fps-source",
0053         .param = MAX77620_ACTIVE_FPS_SOURCE,
0054     }, {
0055         .property = "maxim,active-fps-power-up-slot",
0056         .param = MAX77620_ACTIVE_FPS_POWER_ON_SLOTS,
0057     }, {
0058         .property = "maxim,active-fps-power-down-slot",
0059         .param = MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS,
0060     }, {
0061         .property = "maxim,suspend-fps-source",
0062         .param = MAX77620_SUSPEND_FPS_SOURCE,
0063     }, {
0064         .property = "maxim,suspend-fps-power-up-slot",
0065         .param = MAX77620_SUSPEND_FPS_POWER_ON_SLOTS,
0066     }, {
0067         .property = "maxim,suspend-fps-power-down-slot",
0068         .param = MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS,
0069     },
0070 };
0071 
0072 enum max77620_alternate_pinmux_option {
0073     MAX77620_PINMUX_GPIO                = 0,
0074     MAX77620_PINMUX_LOW_POWER_MODE_CONTROL_IN   = 1,
0075     MAX77620_PINMUX_FLEXIBLE_POWER_SEQUENCER_OUT    = 2,
0076     MAX77620_PINMUX_32K_OUT1            = 3,
0077     MAX77620_PINMUX_SD0_DYNAMIC_VOLTAGE_SCALING_IN  = 4,
0078     MAX77620_PINMUX_SD1_DYNAMIC_VOLTAGE_SCALING_IN  = 5,
0079     MAX77620_PINMUX_REFERENCE_OUT           = 6,
0080 };
0081 
0082 struct max77620_pingroup {
0083     const char *name;
0084     const unsigned int pins[1];
0085     unsigned int npins;
0086     enum max77620_alternate_pinmux_option alt_option;
0087 };
0088 
0089 struct max77620_pin_info {
0090     enum max77620_pin_ppdrv drv_type;
0091     int pull_config;
0092 };
0093 
0094 struct max77620_fps_config {
0095     int active_fps_src;
0096     int active_power_up_slots;
0097     int active_power_down_slots;
0098     int suspend_fps_src;
0099     int suspend_power_up_slots;
0100     int suspend_power_down_slots;
0101 };
0102 
0103 struct max77620_pctrl_info {
0104     struct device *dev;
0105     struct pinctrl_dev *pctl;
0106     struct regmap *rmap;
0107     int pins_current_opt[MAX77620_GPIO_NR];
0108     const struct max77620_pin_function *functions;
0109     unsigned int num_functions;
0110     const struct max77620_pingroup *pin_groups;
0111     int num_pin_groups;
0112     const struct pinctrl_pin_desc *pins;
0113     unsigned int num_pins;
0114     struct max77620_pin_info pin_info[MAX77620_PIN_NUM];
0115     struct max77620_fps_config fps_config[MAX77620_PIN_NUM];
0116 };
0117 
0118 static const struct pinctrl_pin_desc max77620_pins_desc[] = {
0119     PINCTRL_PIN(MAX77620_GPIO0, "gpio0"),
0120     PINCTRL_PIN(MAX77620_GPIO1, "gpio1"),
0121     PINCTRL_PIN(MAX77620_GPIO2, "gpio2"),
0122     PINCTRL_PIN(MAX77620_GPIO3, "gpio3"),
0123     PINCTRL_PIN(MAX77620_GPIO4, "gpio4"),
0124     PINCTRL_PIN(MAX77620_GPIO5, "gpio5"),
0125     PINCTRL_PIN(MAX77620_GPIO6, "gpio6"),
0126     PINCTRL_PIN(MAX77620_GPIO7, "gpio7"),
0127 };
0128 
0129 static const char * const gpio_groups[] = {
0130     "gpio0",
0131     "gpio1",
0132     "gpio2",
0133     "gpio3",
0134     "gpio4",
0135     "gpio5",
0136     "gpio6",
0137     "gpio7",
0138 };
0139 
0140 #define FUNCTION_GROUP(fname, mux)          \
0141     {                       \
0142         .name = fname,              \
0143         .groups = gpio_groups,          \
0144         .ngroups = ARRAY_SIZE(gpio_groups), \
0145         .mux_option = MAX77620_PINMUX_##mux,    \
0146     }
0147 
0148 static const struct max77620_pin_function max77620_pin_function[] = {
0149     FUNCTION_GROUP("gpio", GPIO),
0150     FUNCTION_GROUP("lpm-control-in", LOW_POWER_MODE_CONTROL_IN),
0151     FUNCTION_GROUP("fps-out", FLEXIBLE_POWER_SEQUENCER_OUT),
0152     FUNCTION_GROUP("32k-out1", 32K_OUT1),
0153     FUNCTION_GROUP("sd0-dvs-in", SD0_DYNAMIC_VOLTAGE_SCALING_IN),
0154     FUNCTION_GROUP("sd1-dvs-in", SD1_DYNAMIC_VOLTAGE_SCALING_IN),
0155     FUNCTION_GROUP("reference-out", REFERENCE_OUT),
0156 };
0157 
0158 #define MAX77620_PINGROUP(pg_name, pin_id, option) \
0159     {                               \
0160         .name = #pg_name,                   \
0161         .pins = {MAX77620_##pin_id},                \
0162         .npins = 1,                     \
0163         .alt_option = MAX77620_PINMUX_##option,         \
0164     }
0165 
0166 static const struct max77620_pingroup max77620_pingroups[] = {
0167     MAX77620_PINGROUP(gpio0, GPIO0, LOW_POWER_MODE_CONTROL_IN),
0168     MAX77620_PINGROUP(gpio1, GPIO1, FLEXIBLE_POWER_SEQUENCER_OUT),
0169     MAX77620_PINGROUP(gpio2, GPIO2, FLEXIBLE_POWER_SEQUENCER_OUT),
0170     MAX77620_PINGROUP(gpio3, GPIO3, FLEXIBLE_POWER_SEQUENCER_OUT),
0171     MAX77620_PINGROUP(gpio4, GPIO4, 32K_OUT1),
0172     MAX77620_PINGROUP(gpio5, GPIO5, SD0_DYNAMIC_VOLTAGE_SCALING_IN),
0173     MAX77620_PINGROUP(gpio6, GPIO6, SD1_DYNAMIC_VOLTAGE_SCALING_IN),
0174     MAX77620_PINGROUP(gpio7, GPIO7, REFERENCE_OUT),
0175 };
0176 
0177 static int max77620_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
0178 {
0179     struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
0180 
0181     return mpci->num_pin_groups;
0182 }
0183 
0184 static const char *max77620_pinctrl_get_group_name(
0185         struct pinctrl_dev *pctldev, unsigned int group)
0186 {
0187     struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
0188 
0189     return mpci->pin_groups[group].name;
0190 }
0191 
0192 static int max77620_pinctrl_get_group_pins(
0193         struct pinctrl_dev *pctldev, unsigned int group,
0194         const unsigned int **pins, unsigned int *num_pins)
0195 {
0196     struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
0197 
0198     *pins = mpci->pin_groups[group].pins;
0199     *num_pins = mpci->pin_groups[group].npins;
0200 
0201     return 0;
0202 }
0203 
0204 static const struct pinctrl_ops max77620_pinctrl_ops = {
0205     .get_groups_count = max77620_pinctrl_get_groups_count,
0206     .get_group_name = max77620_pinctrl_get_group_name,
0207     .get_group_pins = max77620_pinctrl_get_group_pins,
0208     .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
0209     .dt_free_map = pinctrl_utils_free_map,
0210 };
0211 
0212 static int max77620_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
0213 {
0214     struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
0215 
0216     return mpci->num_functions;
0217 }
0218 
0219 static const char *max77620_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
0220                           unsigned int function)
0221 {
0222     struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
0223 
0224     return mpci->functions[function].name;
0225 }
0226 
0227 static int max77620_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
0228                         unsigned int function,
0229                         const char * const **groups,
0230                         unsigned int * const num_groups)
0231 {
0232     struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
0233 
0234     *groups = mpci->functions[function].groups;
0235     *num_groups = mpci->functions[function].ngroups;
0236 
0237     return 0;
0238 }
0239 
0240 static int max77620_pinctrl_enable(struct pinctrl_dev *pctldev,
0241                    unsigned int function, unsigned int group)
0242 {
0243     struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
0244     u8 val;
0245     int ret;
0246 
0247     if (function == MAX77620_PINMUX_GPIO) {
0248         val = 0;
0249     } else if (function == mpci->pin_groups[group].alt_option) {
0250         val = 1 << group;
0251     } else {
0252         dev_err(mpci->dev, "GPIO %u doesn't have function %u\n",
0253             group, function);
0254         return -EINVAL;
0255     }
0256     ret = regmap_update_bits(mpci->rmap, MAX77620_REG_AME_GPIO,
0257                  BIT(group), val);
0258     if (ret < 0)
0259         dev_err(mpci->dev, "REG AME GPIO update failed: %d\n", ret);
0260 
0261     return ret;
0262 }
0263 
0264 static const struct pinmux_ops max77620_pinmux_ops = {
0265     .get_functions_count    = max77620_pinctrl_get_funcs_count,
0266     .get_function_name  = max77620_pinctrl_get_func_name,
0267     .get_function_groups    = max77620_pinctrl_get_func_groups,
0268     .set_mux        = max77620_pinctrl_enable,
0269 };
0270 
0271 static int max77620_pinconf_get(struct pinctrl_dev *pctldev,
0272                 unsigned int pin, unsigned long *config)
0273 {
0274     struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
0275     struct device *dev = mpci->dev;
0276     enum pin_config_param param = pinconf_to_config_param(*config);
0277     unsigned int val;
0278     int arg = 0;
0279     int ret;
0280 
0281     switch (param) {
0282     case PIN_CONFIG_DRIVE_OPEN_DRAIN:
0283         if (mpci->pin_info[pin].drv_type == MAX77620_PIN_OD_DRV)
0284             arg = 1;
0285         break;
0286 
0287     case PIN_CONFIG_DRIVE_PUSH_PULL:
0288         if (mpci->pin_info[pin].drv_type == MAX77620_PIN_PP_DRV)
0289             arg = 1;
0290         break;
0291 
0292     case PIN_CONFIG_BIAS_PULL_UP:
0293         ret = regmap_read(mpci->rmap, MAX77620_REG_PUE_GPIO, &val);
0294         if (ret < 0) {
0295             dev_err(dev, "Reg PUE_GPIO read failed: %d\n", ret);
0296             return ret;
0297         }
0298         if (val & BIT(pin))
0299             arg = 1;
0300         break;
0301 
0302     case PIN_CONFIG_BIAS_PULL_DOWN:
0303         ret = regmap_read(mpci->rmap, MAX77620_REG_PDE_GPIO, &val);
0304         if (ret < 0) {
0305             dev_err(dev, "Reg PDE_GPIO read failed: %d\n", ret);
0306             return ret;
0307         }
0308         if (val & BIT(pin))
0309             arg = 1;
0310         break;
0311 
0312     default:
0313         dev_err(dev, "Properties not supported\n");
0314         return -ENOTSUPP;
0315     }
0316 
0317     *config = pinconf_to_config_packed(param, (u16)arg);
0318 
0319     return 0;
0320 }
0321 
0322 static int max77620_get_default_fps(struct max77620_pctrl_info *mpci,
0323                     int addr, int *fps)
0324 {
0325     unsigned int val;
0326     int ret;
0327 
0328     ret = regmap_read(mpci->rmap, addr, &val);
0329     if (ret < 0) {
0330         dev_err(mpci->dev, "Reg PUE_GPIO read failed: %d\n", ret);
0331         return ret;
0332     }
0333     *fps = (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT;
0334 
0335     return 0;
0336 }
0337 
0338 static int max77620_set_fps_param(struct max77620_pctrl_info *mpci,
0339                   int pin, int param)
0340 {
0341     struct max77620_fps_config *fps_config = &mpci->fps_config[pin];
0342     int addr, ret;
0343     int param_val;
0344     int mask, shift;
0345 
0346     if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
0347         return 0;
0348 
0349     addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
0350     switch (param) {
0351     case MAX77620_ACTIVE_FPS_SOURCE:
0352     case MAX77620_SUSPEND_FPS_SOURCE:
0353         mask = MAX77620_FPS_SRC_MASK;
0354         shift = MAX77620_FPS_SRC_SHIFT;
0355         param_val = fps_config->active_fps_src;
0356         if (param == MAX77620_SUSPEND_FPS_SOURCE)
0357             param_val = fps_config->suspend_fps_src;
0358         break;
0359 
0360     case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS:
0361     case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS:
0362         mask = MAX77620_FPS_PU_PERIOD_MASK;
0363         shift = MAX77620_FPS_PU_PERIOD_SHIFT;
0364         param_val = fps_config->active_power_up_slots;
0365         if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS)
0366             param_val = fps_config->suspend_power_up_slots;
0367         break;
0368 
0369     case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS:
0370     case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS:
0371         mask = MAX77620_FPS_PD_PERIOD_MASK;
0372         shift = MAX77620_FPS_PD_PERIOD_SHIFT;
0373         param_val = fps_config->active_power_down_slots;
0374         if (param == MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS)
0375             param_val = fps_config->suspend_power_down_slots;
0376         break;
0377 
0378     default:
0379         dev_err(mpci->dev, "Invalid parameter %d for pin %d\n",
0380             param, pin);
0381         return -EINVAL;
0382     }
0383 
0384     if (param_val < 0)
0385         return 0;
0386 
0387     ret = regmap_update_bits(mpci->rmap, addr, mask, param_val << shift);
0388     if (ret < 0)
0389         dev_err(mpci->dev, "Reg 0x%02x update failed %d\n", addr, ret);
0390 
0391     return ret;
0392 }
0393 
0394 static int max77620_pinconf_set(struct pinctrl_dev *pctldev,
0395                 unsigned int pin, unsigned long *configs,
0396                 unsigned int num_configs)
0397 {
0398     struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
0399     struct device *dev = mpci->dev;
0400     struct max77620_fps_config *fps_config;
0401     int param;
0402     u32 param_val;
0403     unsigned int val;
0404     unsigned int pu_val;
0405     unsigned int pd_val;
0406     int addr, ret;
0407     int i;
0408 
0409     for (i = 0; i < num_configs; i++) {
0410         param = pinconf_to_config_param(configs[i]);
0411         param_val = pinconf_to_config_argument(configs[i]);
0412 
0413         switch (param) {
0414         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
0415             val = param_val ? 0 : 1;
0416             ret = regmap_update_bits(mpci->rmap,
0417                          MAX77620_REG_GPIO0 + pin,
0418                          MAX77620_CNFG_GPIO_DRV_MASK,
0419                          val);
0420             if (ret)
0421                 goto report_update_failure;
0422 
0423             mpci->pin_info[pin].drv_type = val ?
0424                 MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV;
0425             break;
0426 
0427         case PIN_CONFIG_DRIVE_PUSH_PULL:
0428             val = param_val ? 1 : 0;
0429             ret = regmap_update_bits(mpci->rmap,
0430                          MAX77620_REG_GPIO0 + pin,
0431                          MAX77620_CNFG_GPIO_DRV_MASK,
0432                          val);
0433             if (ret)
0434                 goto report_update_failure;
0435 
0436             mpci->pin_info[pin].drv_type = val ?
0437                 MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV;
0438             break;
0439 
0440         case MAX77620_ACTIVE_FPS_SOURCE:
0441         case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS:
0442         case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS:
0443             if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
0444                 return -EINVAL;
0445 
0446             fps_config = &mpci->fps_config[pin];
0447 
0448             if ((param == MAX77620_ACTIVE_FPS_SOURCE) &&
0449                 (param_val == MAX77620_FPS_SRC_DEF)) {
0450                 addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
0451                 ret = max77620_get_default_fps(
0452                         mpci, addr,
0453                         &fps_config->active_fps_src);
0454                 if (ret < 0)
0455                     return ret;
0456                 break;
0457             }
0458 
0459             if (param == MAX77620_ACTIVE_FPS_SOURCE)
0460                 fps_config->active_fps_src = param_val;
0461             else if (param == MAX77620_ACTIVE_FPS_POWER_ON_SLOTS)
0462                 fps_config->active_power_up_slots = param_val;
0463             else
0464                 fps_config->active_power_down_slots = param_val;
0465 
0466             ret = max77620_set_fps_param(mpci, pin, param);
0467             if (ret < 0)
0468                 return ret;
0469             break;
0470 
0471         case MAX77620_SUSPEND_FPS_SOURCE:
0472         case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS:
0473         case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS:
0474             if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
0475                 return -EINVAL;
0476 
0477             fps_config = &mpci->fps_config[pin];
0478 
0479             if ((param == MAX77620_SUSPEND_FPS_SOURCE) &&
0480                 (param_val == MAX77620_FPS_SRC_DEF)) {
0481                 addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
0482                 ret = max77620_get_default_fps(
0483                         mpci, addr,
0484                         &fps_config->suspend_fps_src);
0485                 if (ret < 0)
0486                     return ret;
0487                 break;
0488             }
0489 
0490             if (param == MAX77620_SUSPEND_FPS_SOURCE)
0491                 fps_config->suspend_fps_src = param_val;
0492             else if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS)
0493                 fps_config->suspend_power_up_slots = param_val;
0494             else
0495                 fps_config->suspend_power_down_slots =
0496                                 param_val;
0497             break;
0498 
0499         case PIN_CONFIG_BIAS_PULL_UP:
0500         case PIN_CONFIG_BIAS_PULL_DOWN:
0501             pu_val = (param == PIN_CONFIG_BIAS_PULL_UP) ?
0502                             BIT(pin) : 0;
0503             pd_val = (param == PIN_CONFIG_BIAS_PULL_DOWN) ?
0504                             BIT(pin) : 0;
0505 
0506             ret = regmap_update_bits(mpci->rmap,
0507                          MAX77620_REG_PUE_GPIO,
0508                          BIT(pin), pu_val);
0509             if (ret < 0) {
0510                 dev_err(dev, "PUE_GPIO update failed: %d\n",
0511                     ret);
0512                 return ret;
0513             }
0514 
0515             ret = regmap_update_bits(mpci->rmap,
0516                          MAX77620_REG_PDE_GPIO,
0517                          BIT(pin), pd_val);
0518             if (ret < 0) {
0519                 dev_err(dev, "PDE_GPIO update failed: %d\n",
0520                     ret);
0521                 return ret;
0522             }
0523             break;
0524 
0525         default:
0526             dev_err(dev, "Properties not supported\n");
0527             return -ENOTSUPP;
0528         }
0529     }
0530 
0531     return 0;
0532 
0533 report_update_failure:
0534     dev_err(dev, "Reg 0x%02x update failed %d\n",
0535         MAX77620_REG_GPIO0 + pin, ret);
0536     return ret;
0537 }
0538 
0539 static const struct pinconf_ops max77620_pinconf_ops = {
0540     .pin_config_get = max77620_pinconf_get,
0541     .pin_config_set = max77620_pinconf_set,
0542 };
0543 
0544 static struct pinctrl_desc max77620_pinctrl_desc = {
0545     .pctlops = &max77620_pinctrl_ops,
0546     .pmxops = &max77620_pinmux_ops,
0547     .confops = &max77620_pinconf_ops,
0548 };
0549 
0550 static int max77620_pinctrl_probe(struct platform_device *pdev)
0551 {
0552     struct max77620_chip *max77620 = dev_get_drvdata(pdev->dev.parent);
0553     struct max77620_pctrl_info *mpci;
0554     int i;
0555 
0556     device_set_node(&pdev->dev, dev_fwnode(pdev->dev.parent));
0557 
0558     mpci = devm_kzalloc(&pdev->dev, sizeof(*mpci), GFP_KERNEL);
0559     if (!mpci)
0560         return -ENOMEM;
0561 
0562     mpci->dev = &pdev->dev;
0563     mpci->rmap = max77620->rmap;
0564 
0565     mpci->pins = max77620_pins_desc;
0566     mpci->num_pins = ARRAY_SIZE(max77620_pins_desc);
0567     mpci->functions = max77620_pin_function;
0568     mpci->num_functions = ARRAY_SIZE(max77620_pin_function);
0569     mpci->pin_groups = max77620_pingroups;
0570     mpci->num_pin_groups = ARRAY_SIZE(max77620_pingroups);
0571     platform_set_drvdata(pdev, mpci);
0572 
0573     max77620_pinctrl_desc.name = dev_name(&pdev->dev);
0574     max77620_pinctrl_desc.pins = max77620_pins_desc;
0575     max77620_pinctrl_desc.npins = ARRAY_SIZE(max77620_pins_desc);
0576     max77620_pinctrl_desc.num_custom_params =
0577                 ARRAY_SIZE(max77620_cfg_params);
0578     max77620_pinctrl_desc.custom_params = max77620_cfg_params;
0579 
0580     for (i = 0; i < MAX77620_PIN_NUM; ++i) {
0581         mpci->fps_config[i].active_fps_src = -1;
0582         mpci->fps_config[i].active_power_up_slots = -1;
0583         mpci->fps_config[i].active_power_down_slots = -1;
0584         mpci->fps_config[i].suspend_fps_src = -1;
0585         mpci->fps_config[i].suspend_power_up_slots = -1;
0586         mpci->fps_config[i].suspend_power_down_slots = -1;
0587     }
0588 
0589     mpci->pctl = devm_pinctrl_register(&pdev->dev, &max77620_pinctrl_desc,
0590                        mpci);
0591     if (IS_ERR(mpci->pctl)) {
0592         dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
0593         return PTR_ERR(mpci->pctl);
0594     }
0595 
0596     return 0;
0597 }
0598 
0599 #ifdef CONFIG_PM_SLEEP
0600 static int max77620_suspend_fps_param[] = {
0601     MAX77620_SUSPEND_FPS_SOURCE,
0602     MAX77620_SUSPEND_FPS_POWER_ON_SLOTS,
0603     MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS,
0604 };
0605 
0606 static int max77620_active_fps_param[] = {
0607     MAX77620_ACTIVE_FPS_SOURCE,
0608     MAX77620_ACTIVE_FPS_POWER_ON_SLOTS,
0609     MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS,
0610 };
0611 
0612 static int max77620_pinctrl_suspend(struct device *dev)
0613 {
0614     struct max77620_pctrl_info *mpci = dev_get_drvdata(dev);
0615     int pin, p;
0616 
0617     for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) {
0618         if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
0619             continue;
0620         for (p = 0; p < 3; ++p)
0621             max77620_set_fps_param(
0622                 mpci, pin, max77620_suspend_fps_param[p]);
0623     }
0624 
0625     return 0;
0626 };
0627 
0628 static int max77620_pinctrl_resume(struct device *dev)
0629 {
0630     struct max77620_pctrl_info *mpci = dev_get_drvdata(dev);
0631     int pin, p;
0632 
0633     for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) {
0634         if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
0635             continue;
0636         for (p = 0; p < 3; ++p)
0637             max77620_set_fps_param(
0638                 mpci, pin, max77620_active_fps_param[p]);
0639     }
0640 
0641     return 0;
0642 }
0643 #endif
0644 
0645 static const struct dev_pm_ops max77620_pinctrl_pm_ops = {
0646     SET_SYSTEM_SLEEP_PM_OPS(
0647         max77620_pinctrl_suspend, max77620_pinctrl_resume)
0648 };
0649 
0650 static const struct platform_device_id max77620_pinctrl_devtype[] = {
0651     { .name = "max77620-pinctrl", },
0652     { .name = "max20024-pinctrl", },
0653     {},
0654 };
0655 MODULE_DEVICE_TABLE(platform, max77620_pinctrl_devtype);
0656 
0657 static struct platform_driver max77620_pinctrl_driver = {
0658     .driver = {
0659         .name = "max77620-pinctrl",
0660         .pm = &max77620_pinctrl_pm_ops,
0661     },
0662     .probe = max77620_pinctrl_probe,
0663     .id_table = max77620_pinctrl_devtype,
0664 };
0665 
0666 module_platform_driver(max77620_pinctrl_driver);
0667 
0668 MODULE_DESCRIPTION("MAX77620/MAX20024 pin control driver");
0669 MODULE_AUTHOR("Chaitanya Bandi<bandik@nvidia.com>");
0670 MODULE_AUTHOR("Laxman Dewangan<ldewangan@nvidia.com>");
0671 MODULE_LICENSE("GPL v2");
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