drivers/pinctrl/pinctrl-lantiq.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  linux/drivers/pinctrl/pinctrl-lantiq.h
0004  *  based on linux/drivers/pinctrl/pinctrl-pxa3xx.h
0005  *
0006  *  Copyright (C) 2012 John Crispin <john@phrozen.org>
0007  */
0008
0009 #ifndef __PINCTRL_LANTIQ_H
0010 #define __PINCTRL_LANTIQ_H
0011
0012 #include <linux/clkdev.h>
0013 #include <linux/pinctrl/pinctrl.h>
0014 #include <linux/pinctrl/pinconf.h>
0015 #include <linux/pinctrl/pinmux.h>
0016 #include <linux/pinctrl/consumer.h>
0017 #include <linux/pinctrl/machine.h>
0018
0019 #include "core.h"
0020
0021 #define ARRAY_AND_SIZE(x)   (x), ARRAY_SIZE(x)
0022
0023 #define LTQ_MAX_MUX     4
0024 #define MFPR_FUNC_MASK      0x3
0025
0026 #define LTQ_PINCONF_PACK(param, arg)        ((param) << 16 | (arg))
0027 #define LTQ_PINCONF_UNPACK_PARAM(conf)      ((conf) >> 16)
0028 #define LTQ_PINCONF_UNPACK_ARG(conf)        ((conf) & 0xffff)
0029
0030 enum ltq_pinconf_param {
0031     LTQ_PINCONF_PARAM_PULL,
0032     LTQ_PINCONF_PARAM_OPEN_DRAIN,
0033     LTQ_PINCONF_PARAM_DRIVE_CURRENT,
0034     LTQ_PINCONF_PARAM_SLEW_RATE,
0035     LTQ_PINCONF_PARAM_OUTPUT,
0036 };
0037
0038 struct ltq_cfg_param {
0039     const char *property;
0040     enum ltq_pinconf_param param;
0041 };
0042
0043 struct ltq_mfp_pin {
0044     const char *name;
0045     const unsigned int pin;
0046     const unsigned short func[LTQ_MAX_MUX];
0047 };
0048
0049 struct ltq_pin_group {
0050     const char *name;
0051     const unsigned mux;
0052     const unsigned *pins;
0053     const unsigned npins;
0054 };
0055
0056 struct ltq_pmx_func {
0057     const char *name;
0058     const char * const *groups;
0059     const unsigned num_groups;
0060 };
0061
0062 struct ltq_pinmux_info {
0063     struct device *dev;
0064     struct pinctrl_dev *pctrl;
0065
0066     /* we need to manage up to 5 pad controllers */
0067     void __iomem *membase[5];
0068
0069     /* the descriptor for the subsystem */
0070     struct pinctrl_desc *desc;
0071
0072     /* we expose our pads to the subsystem */
0073     struct pinctrl_pin_desc *pads;
0074
0075     /* the number of pads. this varies between socs */
0076     unsigned int num_pads;
0077
0078     /* these are our multifunction pins */
0079     const struct ltq_mfp_pin *mfp;
0080     unsigned int num_mfp;
0081
0082     /* a number of multifunction pins can be grouped together */
0083     const struct ltq_pin_group *grps;
0084     unsigned int num_grps;
0085
0086     /* a mapping between function string and id */
0087     const struct ltq_pmx_func *funcs;
0088     unsigned int num_funcs;
0089
0090     /* the pinconf options that we are able to read from the DT */
0091     const struct ltq_cfg_param *params;
0092     unsigned int num_params;
0093
0094     /* the pad controller can have a irq mapping  */
0095     const unsigned *exin;
0096     unsigned int num_exin;
0097
0098     /* we need 5 clocks max */
0099     struct clk *clk[5];
0100
0101     /* soc specific callback used to apply muxing */
0102     int (*apply_mux)(struct pinctrl_dev *pctrldev, int pin, int mux);
0103 };
0104
0105 enum ltq_pin {
0106     GPIO0 = 0,
0107     GPIO1,
0108     GPIO2,
0109     GPIO3,
0110     GPIO4,
0111     GPIO5,
0112     GPIO6,
0113     GPIO7,
0114     GPIO8,
0115     GPIO9,
0116     GPIO10, /* 10 */
0117     GPIO11,
0118     GPIO12,
0119     GPIO13,
0120     GPIO14,
0121     GPIO15,
0122     GPIO16,
0123     GPIO17,
0124     GPIO18,
0125     GPIO19,
0126     GPIO20, /* 20 */
0127     GPIO21,
0128     GPIO22,
0129     GPIO23,
0130     GPIO24,
0131     GPIO25,
0132     GPIO26,
0133     GPIO27,
0134     GPIO28,
0135     GPIO29,
0136     GPIO30, /* 30 */
0137     GPIO31,
0138     GPIO32,
0139     GPIO33,
0140     GPIO34,
0141     GPIO35,
0142     GPIO36,
0143     GPIO37,
0144     GPIO38,
0145     GPIO39,
0146     GPIO40, /* 40 */
0147     GPIO41,
0148     GPIO42,
0149     GPIO43,
0150     GPIO44,
0151     GPIO45,
0152     GPIO46,
0153     GPIO47,
0154     GPIO48,
0155     GPIO49,
0156     GPIO50, /* 50 */
0157     GPIO51,
0158     GPIO52,
0159     GPIO53,
0160     GPIO54,
0161     GPIO55,
0162     GPIO56,
0163     GPIO57,
0164     GPIO58,
0165     GPIO59,
0166     GPIO60, /* 60 */
0167     GPIO61,
0168     GPIO62,
0169     GPIO63,
0170
0171     GPIO64,
0172     GPIO65,
0173     GPIO66,
0174     GPIO67,
0175     GPIO68,
0176     GPIO69,
0177     GPIO70,
0178     GPIO71,
0179     GPIO72,
0180     GPIO73,
0181     GPIO74,
0182     GPIO75,
0183     GPIO76,
0184     GPIO77,
0185     GPIO78,
0186     GPIO79,
0187     GPIO80,
0188     GPIO81,
0189     GPIO82,
0190     GPIO83,
0191     GPIO84,
0192     GPIO85,
0193     GPIO86,
0194     GPIO87,
0195     GPIO88,
0196 };
0197
0198 extern int ltq_pinctrl_register(struct platform_device *pdev,
0199                    struct ltq_pinmux_info *info);
0200 extern int ltq_pinctrl_unregister(struct platform_device *pdev);
0201 #endif  /* __PINCTRL_LANTIQ_H */