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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Copyright (C) 2020 Intel Corporation */
0003 
0004 #include <linux/bitfield.h>
0005 #include <linux/bitops.h>
0006 #include <linux/gpio/driver.h>
0007 #include <linux/interrupt.h>
0008 #include <linux/io.h>
0009 #include <linux/module.h>
0010 
0011 #include <linux/pinctrl/pinconf.h>
0012 #include <linux/pinctrl/pinconf-generic.h>
0013 #include <linux/pinctrl/pinctrl.h>
0014 #include <linux/pinctrl/pinmux.h>
0015 
0016 #include <linux/platform_device.h>
0017 
0018 #include "core.h"
0019 #include "pinmux.h"
0020 
0021 /* GPIO data registers' offsets */
0022 #define KEEMBAY_GPIO_DATA_OUT       0x000
0023 #define KEEMBAY_GPIO_DATA_IN        0x020
0024 #define KEEMBAY_GPIO_DATA_IN_RAW    0x040
0025 #define KEEMBAY_GPIO_DATA_HIGH      0x060
0026 #define KEEMBAY_GPIO_DATA_LOW       0x080
0027 
0028 /* GPIO Interrupt and mode registers' offsets */
0029 #define KEEMBAY_GPIO_INT_CFG        0x000
0030 #define KEEMBAY_GPIO_MODE       0x070
0031 
0032 /* GPIO mode register bit fields */
0033 #define KEEMBAY_GPIO_MODE_PULLUP_MASK   GENMASK(13, 12)
0034 #define KEEMBAY_GPIO_MODE_DRIVE_MASK    GENMASK(8, 7)
0035 #define KEEMBAY_GPIO_MODE_INV_MASK  GENMASK(5, 4)
0036 #define KEEMBAY_GPIO_MODE_SELECT_MASK   GENMASK(2, 0)
0037 #define KEEMBAY_GPIO_MODE_DIR_OVR   BIT(15)
0038 #define KEEMBAY_GPIO_MODE_REN       BIT(11)
0039 #define KEEMBAY_GPIO_MODE_SCHMITT_EN    BIT(10)
0040 #define KEEMBAY_GPIO_MODE_SLEW_RATE BIT(9)
0041 #define KEEMBAY_GPIO_IRQ_ENABLE     BIT(7)
0042 #define KEEMBAY_GPIO_MODE_DIR       BIT(3)
0043 #define KEEMBAY_GPIO_MODE_DEFAULT   0x7
0044 #define KEEMBAY_GPIO_MODE_INV_VAL   0x3
0045 
0046 #define KEEMBAY_GPIO_DISABLE        0
0047 #define KEEMBAY_GPIO_PULL_UP        1
0048 #define KEEMBAY_GPIO_PULL_DOWN      2
0049 #define KEEMBAY_GPIO_BUS_HOLD       3
0050 #define KEEMBAY_GPIO_NUM_IRQ        8
0051 #define KEEMBAY_GPIO_MAX_PER_IRQ    4
0052 #define KEEMBAY_GPIO_MAX_PER_REG    32
0053 #define KEEMBAY_GPIO_MIN_STRENGTH   2
0054 #define KEEMBAY_GPIO_MAX_STRENGTH   12
0055 #define KEEMBAY_GPIO_SENSE_LOW      (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)
0056 
0057 /* GPIO reg address calculation */
0058 #define KEEMBAY_GPIO_REG_OFFSET(pin)    ((pin) * 4)
0059 
0060 /**
0061  * struct keembay_mux_desc - Mux properties of each GPIO pin
0062  * @mode: Pin mode when operating in this function
0063  * @name: Pin function name
0064  */
0065 struct keembay_mux_desc {
0066     u8 mode;
0067     const char *name;
0068 };
0069 
0070 #define KEEMBAY_PIN_DESC(pin_number, pin_name, ...) {   \
0071     .number = pin_number,               \
0072     .name = pin_name,               \
0073     .drv_data = &(struct keembay_mux_desc[]) {  \
0074             __VA_ARGS__, { } },         \
0075 }                           \
0076 
0077 #define KEEMBAY_MUX(pin_mode, pin_function) {       \
0078     .mode = pin_mode,               \
0079     .name = pin_function,               \
0080 }                           \
0081 
0082 /**
0083  * struct keembay_gpio_irq - Config of each GPIO Interrupt sources
0084  * @source: Interrupt source number (0 - 7)
0085  * @line: Actual Interrupt line number
0086  * @pins: Array of GPIO pins using this Interrupt line
0087  * @trigger: Interrupt trigger type for this line
0088  * @num_share: Number of pins currently using this Interrupt line
0089  */
0090 struct keembay_gpio_irq {
0091     unsigned int source;
0092     unsigned int line;
0093     unsigned int pins[KEEMBAY_GPIO_MAX_PER_IRQ];
0094     unsigned int trigger;
0095     unsigned int num_share;
0096 };
0097 
0098 /**
0099  * struct keembay_pinctrl - Intel Keembay pinctrl structure
0100  * @pctrl: Pointer to the pin controller device
0101  * @base0: First register base address
0102  * @base1: Second register base address
0103  * @dev: Pointer to the device structure
0104  * @chip: GPIO chip used by this pin controller
0105  * @soc: Pin control configuration data based on SoC
0106  * @lock: Spinlock to protect various gpio config register access
0107  * @ngroups: Number of pin groups available
0108  * @nfuncs: Number of pin functions available
0109  * @npins: Number of GPIO pins available
0110  * @irq: Store Interrupt source
0111  * @max_gpios_level_type: Store max level trigger type
0112  * @max_gpios_edge_type: Store max edge trigger type
0113  */
0114 struct keembay_pinctrl {
0115     struct pinctrl_dev *pctrl;
0116     void __iomem *base0;
0117     void __iomem *base1;
0118     struct device *dev;
0119     struct gpio_chip chip;
0120     const struct keembay_pin_soc *soc;
0121     raw_spinlock_t lock;
0122     unsigned int ngroups;
0123     unsigned int nfuncs;
0124     unsigned int npins;
0125     struct keembay_gpio_irq irq[KEEMBAY_GPIO_NUM_IRQ];
0126     int max_gpios_level_type;
0127     int max_gpios_edge_type;
0128 };
0129 
0130 /**
0131  * struct keembay_pin_soc - Pin control config data based on SoC
0132  * @pins: Pin description structure
0133  */
0134 struct keembay_pin_soc {
0135     const struct pinctrl_pin_desc *pins;
0136 };
0137 
0138 static const struct pinctrl_pin_desc keembay_pins[] = {
0139     KEEMBAY_PIN_DESC(0, "GPIO0",
0140              KEEMBAY_MUX(0x0, "I2S0_M0"),
0141              KEEMBAY_MUX(0x1, "SD0_M1"),
0142              KEEMBAY_MUX(0x2, "SLVDS0_M2"),
0143              KEEMBAY_MUX(0x3, "I2C0_M3"),
0144              KEEMBAY_MUX(0x4, "CAM_M4"),
0145              KEEMBAY_MUX(0x5, "ETH_M5"),
0146              KEEMBAY_MUX(0x6, "LCD_M6"),
0147              KEEMBAY_MUX(0x7, "GPIO_M7")),
0148     KEEMBAY_PIN_DESC(1, "GPIO1",
0149              KEEMBAY_MUX(0x0, "I2S0_M0"),
0150              KEEMBAY_MUX(0x1, "SD0_M1"),
0151              KEEMBAY_MUX(0x2, "SLVDS0_M2"),
0152              KEEMBAY_MUX(0x3, "I2C0_M3"),
0153              KEEMBAY_MUX(0x4, "CAM_M4"),
0154              KEEMBAY_MUX(0x5, "ETH_M5"),
0155              KEEMBAY_MUX(0x6, "LCD_M6"),
0156              KEEMBAY_MUX(0x7, "GPIO_M7")),
0157     KEEMBAY_PIN_DESC(2, "GPIO2",
0158              KEEMBAY_MUX(0x0, "I2S0_M0"),
0159              KEEMBAY_MUX(0x1, "I2S0_M1"),
0160              KEEMBAY_MUX(0x2, "SLVDS0_M2"),
0161              KEEMBAY_MUX(0x3, "I2C1_M3"),
0162              KEEMBAY_MUX(0x4, "CAM_M4"),
0163              KEEMBAY_MUX(0x5, "ETH_M5"),
0164              KEEMBAY_MUX(0x6, "LCD_M6"),
0165              KEEMBAY_MUX(0x7, "GPIO_M7")),
0166     KEEMBAY_PIN_DESC(3, "GPIO3",
0167              KEEMBAY_MUX(0x0, "I2S0_M0"),
0168              KEEMBAY_MUX(0x1, "I2S0_M1"),
0169              KEEMBAY_MUX(0x2, "SLVDS0_M2"),
0170              KEEMBAY_MUX(0x3, "I2C1_M3"),
0171              KEEMBAY_MUX(0x4, "CAM_M4"),
0172              KEEMBAY_MUX(0x5, "ETH_M5"),
0173              KEEMBAY_MUX(0x6, "LCD_M6"),
0174              KEEMBAY_MUX(0x7, "GPIO_M7")),
0175     KEEMBAY_PIN_DESC(4, "GPIO4",
0176              KEEMBAY_MUX(0x0, "I2S0_M0"),
0177              KEEMBAY_MUX(0x1, "I2S0_M1"),
0178              KEEMBAY_MUX(0x2, "SLVDS0_M2"),
0179              KEEMBAY_MUX(0x3, "I2C2_M3"),
0180              KEEMBAY_MUX(0x4, "CAM_M4"),
0181              KEEMBAY_MUX(0x5, "ETH_M5"),
0182              KEEMBAY_MUX(0x6, "LCD_M6"),
0183              KEEMBAY_MUX(0x7, "GPIO_M7")),
0184     KEEMBAY_PIN_DESC(5, "GPIO5",
0185              KEEMBAY_MUX(0x0, "I2S0_M0"),
0186              KEEMBAY_MUX(0x1, "I2S0_M1"),
0187              KEEMBAY_MUX(0x2, "SLVDS0_M2"),
0188              KEEMBAY_MUX(0x3, "I2C2_M3"),
0189              KEEMBAY_MUX(0x4, "CAM_M4"),
0190              KEEMBAY_MUX(0x5, "ETH_M5"),
0191              KEEMBAY_MUX(0x6, "LCD_M6"),
0192              KEEMBAY_MUX(0x7, "GPIO_M7")),
0193     KEEMBAY_PIN_DESC(6, "GPIO6",
0194              KEEMBAY_MUX(0x0, "I2S1_M0"),
0195              KEEMBAY_MUX(0x1, "SD0_M1"),
0196              KEEMBAY_MUX(0x2, "SLVDS0_M2"),
0197              KEEMBAY_MUX(0x3, "I2C3_M3"),
0198              KEEMBAY_MUX(0x4, "CAM_M4"),
0199              KEEMBAY_MUX(0x5, "ETH_M5"),
0200              KEEMBAY_MUX(0x6, "LCD_M6"),
0201              KEEMBAY_MUX(0x7, "GPIO_M7")),
0202     KEEMBAY_PIN_DESC(7, "GPIO7",
0203              KEEMBAY_MUX(0x0, "I2S1_M0"),
0204              KEEMBAY_MUX(0x1, "SD0_M1"),
0205              KEEMBAY_MUX(0x2, "SLVDS0_M2"),
0206              KEEMBAY_MUX(0x3, "I2C3_M3"),
0207              KEEMBAY_MUX(0x4, "CAM_M4"),
0208              KEEMBAY_MUX(0x5, "ETH_M5"),
0209              KEEMBAY_MUX(0x6, "LCD_M6"),
0210              KEEMBAY_MUX(0x7, "GPIO_M7")),
0211     KEEMBAY_PIN_DESC(8, "GPIO8",
0212              KEEMBAY_MUX(0x0, "I2S1_M0"),
0213              KEEMBAY_MUX(0x1, "I2S1_M1"),
0214              KEEMBAY_MUX(0x2, "SLVDS0_M2"),
0215              KEEMBAY_MUX(0x3, "UART0_M3"),
0216              KEEMBAY_MUX(0x4, "CAM_M4"),
0217              KEEMBAY_MUX(0x5, "ETH_M5"),
0218              KEEMBAY_MUX(0x6, "LCD_M6"),
0219              KEEMBAY_MUX(0x7, "GPIO_M7")),
0220     KEEMBAY_PIN_DESC(9, "GPIO9",
0221              KEEMBAY_MUX(0x0, "I2S1_M0"),
0222              KEEMBAY_MUX(0x1, "I2S1_M1"),
0223              KEEMBAY_MUX(0x2, "PWM_M2"),
0224              KEEMBAY_MUX(0x3, "UART0_M3"),
0225              KEEMBAY_MUX(0x4, "CAM_M4"),
0226              KEEMBAY_MUX(0x5, "ETH_M5"),
0227              KEEMBAY_MUX(0x6, "LCD_M6"),
0228              KEEMBAY_MUX(0x7, "GPIO_M7")),
0229     KEEMBAY_PIN_DESC(10, "GPIO10",
0230              KEEMBAY_MUX(0x0, "I2S2_M0"),
0231              KEEMBAY_MUX(0x1, "SD0_M1"),
0232              KEEMBAY_MUX(0x2, "PWM_M2"),
0233              KEEMBAY_MUX(0x3, "UART0_M3"),
0234              KEEMBAY_MUX(0x4, "CAM_M4"),
0235              KEEMBAY_MUX(0x5, "ETH_M5"),
0236              KEEMBAY_MUX(0x6, "LCD_M6"),
0237              KEEMBAY_MUX(0x7, "GPIO_M7")),
0238     KEEMBAY_PIN_DESC(11, "GPIO11",
0239              KEEMBAY_MUX(0x0, "I2S2_M0"),
0240              KEEMBAY_MUX(0x1, "SD0_M1"),
0241              KEEMBAY_MUX(0x2, "PWM_M2"),
0242              KEEMBAY_MUX(0x3, "UART0_M3"),
0243              KEEMBAY_MUX(0x4, "CAM_M4"),
0244              KEEMBAY_MUX(0x5, "ETH_M5"),
0245              KEEMBAY_MUX(0x6, "LCD_M6"),
0246              KEEMBAY_MUX(0x7, "GPIO_M7")),
0247     KEEMBAY_PIN_DESC(12, "GPIO12",
0248              KEEMBAY_MUX(0x0, "I2S2_M0"),
0249              KEEMBAY_MUX(0x1, "I2S2_M1"),
0250              KEEMBAY_MUX(0x2, "PWM_M2"),
0251              KEEMBAY_MUX(0x3, "SPI0_M3"),
0252              KEEMBAY_MUX(0x4, "CAM_M4"),
0253              KEEMBAY_MUX(0x5, "ETH_M5"),
0254              KEEMBAY_MUX(0x6, "LCD_M6"),
0255              KEEMBAY_MUX(0x7, "GPIO_M7")),
0256     KEEMBAY_PIN_DESC(13, "GPIO13",
0257              KEEMBAY_MUX(0x0, "I2S2_M0"),
0258              KEEMBAY_MUX(0x1, "I2S2_M1"),
0259              KEEMBAY_MUX(0x2, "PWM_M2"),
0260              KEEMBAY_MUX(0x3, "SPI0_M3"),
0261              KEEMBAY_MUX(0x4, "CAM_M4"),
0262              KEEMBAY_MUX(0x5, "ETH_M5"),
0263              KEEMBAY_MUX(0x6, "LCD_M6"),
0264              KEEMBAY_MUX(0x7, "GPIO_M7")),
0265     KEEMBAY_PIN_DESC(14, "GPIO14",
0266              KEEMBAY_MUX(0x0, "UART0_M0"),
0267              KEEMBAY_MUX(0x1, "I2S3_M1"),
0268              KEEMBAY_MUX(0x2, "PWM_M2"),
0269              KEEMBAY_MUX(0x3, "SD1_M3"),
0270              KEEMBAY_MUX(0x4, "CAM_M4"),
0271              KEEMBAY_MUX(0x5, "ETH_M5"),
0272              KEEMBAY_MUX(0x6, "LCD_M6"),
0273              KEEMBAY_MUX(0x7, "GPIO_M7")),
0274     KEEMBAY_PIN_DESC(15, "GPIO15",
0275              KEEMBAY_MUX(0x0, "UART0_M0"),
0276              KEEMBAY_MUX(0x1, "I2S3_M1"),
0277              KEEMBAY_MUX(0x2, "UART0_M2"),
0278              KEEMBAY_MUX(0x3, "SD1_M3"),
0279              KEEMBAY_MUX(0x4, "CAM_M4"),
0280              KEEMBAY_MUX(0x5, "SPI1_M5"),
0281              KEEMBAY_MUX(0x6, "LCD_M6"),
0282              KEEMBAY_MUX(0x7, "GPIO_M7")),
0283     KEEMBAY_PIN_DESC(16, "GPIO16",
0284              KEEMBAY_MUX(0x0, "UART0_M0"),
0285              KEEMBAY_MUX(0x1, "I2S3_M1"),
0286              KEEMBAY_MUX(0x2, "UART0_M2"),
0287              KEEMBAY_MUX(0x3, "SD1_M3"),
0288              KEEMBAY_MUX(0x4, "CAM_M4"),
0289              KEEMBAY_MUX(0x5, "SPI1_M5"),
0290              KEEMBAY_MUX(0x6, "LCD_M6"),
0291              KEEMBAY_MUX(0x7, "GPIO_M7")),
0292     KEEMBAY_PIN_DESC(17, "GPIO17",
0293              KEEMBAY_MUX(0x0, "UART0_M0"),
0294              KEEMBAY_MUX(0x1, "I2S3_M1"),
0295              KEEMBAY_MUX(0x2, "I2S3_M2"),
0296              KEEMBAY_MUX(0x3, "SD1_M3"),
0297              KEEMBAY_MUX(0x4, "CAM_M4"),
0298              KEEMBAY_MUX(0x5, "SPI1_M5"),
0299              KEEMBAY_MUX(0x6, "LCD_M6"),
0300              KEEMBAY_MUX(0x7, "GPIO_M7")),
0301     KEEMBAY_PIN_DESC(18, "GPIO18",
0302              KEEMBAY_MUX(0x0, "UART1_M0"),
0303              KEEMBAY_MUX(0x1, "SPI0_M1"),
0304              KEEMBAY_MUX(0x2, "I2S3_M2"),
0305              KEEMBAY_MUX(0x3, "SD1_M3"),
0306              KEEMBAY_MUX(0x4, "CAM_M4"),
0307              KEEMBAY_MUX(0x5, "SPI1_M5"),
0308              KEEMBAY_MUX(0x6, "LCD_M6"),
0309              KEEMBAY_MUX(0x7, "GPIO_M7")),
0310     KEEMBAY_PIN_DESC(19, "GPIO19",
0311              KEEMBAY_MUX(0x0, "UART1_M0"),
0312              KEEMBAY_MUX(0x1, "LCD_M1"),
0313              KEEMBAY_MUX(0x2, "DEBUG_M2"),
0314              KEEMBAY_MUX(0x3, "SD1_M3"),
0315              KEEMBAY_MUX(0x4, "CAM_M4"),
0316              KEEMBAY_MUX(0x5, "SPI1_M5"),
0317              KEEMBAY_MUX(0x6, "LCD_M6"),
0318              KEEMBAY_MUX(0x7, "GPIO_M7")),
0319     KEEMBAY_PIN_DESC(20, "GPIO20",
0320              KEEMBAY_MUX(0x0, "UART1_M0"),
0321              KEEMBAY_MUX(0x1, "LCD_M1"),
0322              KEEMBAY_MUX(0x2, "DEBUG_M2"),
0323              KEEMBAY_MUX(0x3, "CPR_M3"),
0324              KEEMBAY_MUX(0x4, "CAM_M4"),
0325              KEEMBAY_MUX(0x5, "SPI1_M5"),
0326              KEEMBAY_MUX(0x6, "SLVDS0_M6"),
0327              KEEMBAY_MUX(0x7, "GPIO_M7")),
0328     KEEMBAY_PIN_DESC(21, "GPIO21",
0329              KEEMBAY_MUX(0x0, "UART1_M0"),
0330              KEEMBAY_MUX(0x1, "LCD_M1"),
0331              KEEMBAY_MUX(0x2, "DEBUG_M2"),
0332              KEEMBAY_MUX(0x3, "CPR_M3"),
0333              KEEMBAY_MUX(0x4, "CAM_M4"),
0334              KEEMBAY_MUX(0x5, "I3C0_M5"),
0335              KEEMBAY_MUX(0x6, "SLVDS0_M6"),
0336              KEEMBAY_MUX(0x7, "GPIO_M7")),
0337     KEEMBAY_PIN_DESC(22, "GPIO22",
0338              KEEMBAY_MUX(0x0, "I2C0_M0"),
0339              KEEMBAY_MUX(0x1, "UART2_M1"),
0340              KEEMBAY_MUX(0x2, "DEBUG_M2"),
0341              KEEMBAY_MUX(0x3, "CPR_M3"),
0342              KEEMBAY_MUX(0x4, "CAM_M4"),
0343              KEEMBAY_MUX(0x5, "I3C0_M5"),
0344              KEEMBAY_MUX(0x6, "SLVDS0_M6"),
0345              KEEMBAY_MUX(0x7, "GPIO_M7")),
0346     KEEMBAY_PIN_DESC(23, "GPIO23",
0347              KEEMBAY_MUX(0x0, "I2C0_M0"),
0348              KEEMBAY_MUX(0x1, "UART2_M1"),
0349              KEEMBAY_MUX(0x2, "DEBUG_M2"),
0350              KEEMBAY_MUX(0x3, "CPR_M3"),
0351              KEEMBAY_MUX(0x4, "CAM_M4"),
0352              KEEMBAY_MUX(0x5, "I3C1_M5"),
0353              KEEMBAY_MUX(0x6, "SLVDS0_M6"),
0354              KEEMBAY_MUX(0x7, "GPIO_M7")),
0355     KEEMBAY_PIN_DESC(24, "GPIO24",
0356              KEEMBAY_MUX(0x0, "I2C1_M0"),
0357              KEEMBAY_MUX(0x1, "UART2_M1"),
0358              KEEMBAY_MUX(0x2, "DEBUG_M2"),
0359              KEEMBAY_MUX(0x3, "CPR_M3"),
0360              KEEMBAY_MUX(0x4, "CAM_M4"),
0361              KEEMBAY_MUX(0x5, "I3C1_M5"),
0362              KEEMBAY_MUX(0x6, "SLVDS0_M6"),
0363              KEEMBAY_MUX(0x7, "GPIO_M7")),
0364     KEEMBAY_PIN_DESC(25, "GPIO25",
0365              KEEMBAY_MUX(0x0, "I2C1_M0"),
0366              KEEMBAY_MUX(0x1, "UART2_M1"),
0367              KEEMBAY_MUX(0x2, "SPI0_M2"),
0368              KEEMBAY_MUX(0x3, "CPR_M3"),
0369              KEEMBAY_MUX(0x4, "CAM_M4"),
0370              KEEMBAY_MUX(0x5, "I3C2_M5"),
0371              KEEMBAY_MUX(0x6, "SLVDS0_M6"),
0372              KEEMBAY_MUX(0x7, "GPIO_M7")),
0373     KEEMBAY_PIN_DESC(26, "GPIO26",
0374              KEEMBAY_MUX(0x0, "SPI0_M0"),
0375              KEEMBAY_MUX(0x1, "I2C2_M1"),
0376              KEEMBAY_MUX(0x2, "UART0_M2"),
0377              KEEMBAY_MUX(0x3, "DSU_M3"),
0378              KEEMBAY_MUX(0x4, "CAM_M4"),
0379              KEEMBAY_MUX(0x5, "I3C2_M5"),
0380              KEEMBAY_MUX(0x6, "SLVDS0_M6"),
0381              KEEMBAY_MUX(0x7, "GPIO_M7")),
0382     KEEMBAY_PIN_DESC(27, "GPIO27",
0383              KEEMBAY_MUX(0x0, "SPI0_M0"),
0384              KEEMBAY_MUX(0x1, "I2C2_M1"),
0385              KEEMBAY_MUX(0x2, "UART0_M2"),
0386              KEEMBAY_MUX(0x3, "DSU_M3"),
0387              KEEMBAY_MUX(0x4, "CAM_M4"),
0388              KEEMBAY_MUX(0x5, "I3C0_M5"),
0389              KEEMBAY_MUX(0x6, "SLVDS0_M6"),
0390              KEEMBAY_MUX(0x7, "GPIO_M7")),
0391     KEEMBAY_PIN_DESC(28, "GPIO28",
0392              KEEMBAY_MUX(0x0, "SPI0_M0"),
0393              KEEMBAY_MUX(0x1, "I2C3_M1"),
0394              KEEMBAY_MUX(0x2, "UART0_M2"),
0395              KEEMBAY_MUX(0x3, "PWM_M3"),
0396              KEEMBAY_MUX(0x4, "CAM_M4"),
0397              KEEMBAY_MUX(0x5, "I3C1_M5"),
0398              KEEMBAY_MUX(0x6, "SLVDS0_M6"),
0399              KEEMBAY_MUX(0x7, "GPIO_M7")),
0400     KEEMBAY_PIN_DESC(29, "GPIO29",
0401              KEEMBAY_MUX(0x0, "SPI0_M0"),
0402              KEEMBAY_MUX(0x1, "I2C3_M1"),
0403              KEEMBAY_MUX(0x2, "UART0_M2"),
0404              KEEMBAY_MUX(0x3, "PWM_M3"),
0405              KEEMBAY_MUX(0x4, "CAM_M4"),
0406              KEEMBAY_MUX(0x5, "I3C2_M5"),
0407              KEEMBAY_MUX(0x6, "SLVDS1_M6"),
0408              KEEMBAY_MUX(0x7, "GPIO_M7")),
0409     KEEMBAY_PIN_DESC(30, "GPIO30",
0410              KEEMBAY_MUX(0x0, "SPI0_M0"),
0411              KEEMBAY_MUX(0x1, "I2S0_M1"),
0412              KEEMBAY_MUX(0x2, "I2C4_M2"),
0413              KEEMBAY_MUX(0x3, "PWM_M3"),
0414              KEEMBAY_MUX(0x4, "CAM_M4"),
0415              KEEMBAY_MUX(0x5, "LCD_M5"),
0416              KEEMBAY_MUX(0x6, "SLVDS1_M6"),
0417              KEEMBAY_MUX(0x7, "GPIO_M7")),
0418     KEEMBAY_PIN_DESC(31, "GPIO31",
0419              KEEMBAY_MUX(0x0, "SPI0_M0"),
0420              KEEMBAY_MUX(0x1, "I2S0_M1"),
0421              KEEMBAY_MUX(0x2, "I2C4_M2"),
0422              KEEMBAY_MUX(0x3, "PWM_M3"),
0423              KEEMBAY_MUX(0x4, "CAM_M4"),
0424              KEEMBAY_MUX(0x5, "UART1_M5"),
0425              KEEMBAY_MUX(0x6, "SLVDS1_M6"),
0426              KEEMBAY_MUX(0x7, "GPIO_M7")),
0427     KEEMBAY_PIN_DESC(32, "GPIO32",
0428              KEEMBAY_MUX(0x0, "SD0_M0"),
0429              KEEMBAY_MUX(0x1, "SPI0_M1"),
0430              KEEMBAY_MUX(0x2, "UART1_M2"),
0431              KEEMBAY_MUX(0x3, "PWM_M3"),
0432              KEEMBAY_MUX(0x4, "CAM_M4"),
0433              KEEMBAY_MUX(0x5, "PCIE_M5"),
0434              KEEMBAY_MUX(0x6, "SLVDS1_M6"),
0435              KEEMBAY_MUX(0x7, "GPIO_M7")),
0436     KEEMBAY_PIN_DESC(33, "GPIO33",
0437              KEEMBAY_MUX(0x0, "SD0_M0"),
0438              KEEMBAY_MUX(0x1, "SPI0_M1"),
0439              KEEMBAY_MUX(0x2, "UART1_M2"),
0440              KEEMBAY_MUX(0x3, "PWM_M3"),
0441              KEEMBAY_MUX(0x4, "CAM_M4"),
0442              KEEMBAY_MUX(0x5, "PCIE_M5"),
0443              KEEMBAY_MUX(0x6, "SLVDS1_M6"),
0444              KEEMBAY_MUX(0x7, "GPIO_M7")),
0445     KEEMBAY_PIN_DESC(34, "GPIO34",
0446              KEEMBAY_MUX(0x0, "SD0_M0"),
0447              KEEMBAY_MUX(0x1, "SPI0_M1"),
0448              KEEMBAY_MUX(0x2, "I2C0_M2"),
0449              KEEMBAY_MUX(0x3, "UART1_M3"),
0450              KEEMBAY_MUX(0x4, "CAM_M4"),
0451              KEEMBAY_MUX(0x5, "I2S0_M5"),
0452              KEEMBAY_MUX(0x6, "SLVDS1_M6"),
0453              KEEMBAY_MUX(0x7, "GPIO_M7")),
0454     KEEMBAY_PIN_DESC(35, "GPIO35",
0455              KEEMBAY_MUX(0x0, "SD0_M0"),
0456              KEEMBAY_MUX(0x1, "PCIE_M1"),
0457              KEEMBAY_MUX(0x2, "I2C0_M2"),
0458              KEEMBAY_MUX(0x3, "UART1_M3"),
0459              KEEMBAY_MUX(0x4, "CAM_M4"),
0460              KEEMBAY_MUX(0x5, "I2S0_M5"),
0461              KEEMBAY_MUX(0x6, "SLVDS1_M6"),
0462              KEEMBAY_MUX(0x7, "GPIO_M7")),
0463     KEEMBAY_PIN_DESC(36, "GPIO36",
0464              KEEMBAY_MUX(0x0, "SD0_M0"),
0465              KEEMBAY_MUX(0x1, "SPI3_M1"),
0466              KEEMBAY_MUX(0x2, "I2C1_M2"),
0467              KEEMBAY_MUX(0x3, "DEBUG_M3"),
0468              KEEMBAY_MUX(0x4, "CAM_M4"),
0469              KEEMBAY_MUX(0x5, "I2S0_M5"),
0470              KEEMBAY_MUX(0x6, "SLVDS1_M6"),
0471              KEEMBAY_MUX(0x7, "GPIO_M7")),
0472     KEEMBAY_PIN_DESC(37, "GPIO37",
0473              KEEMBAY_MUX(0x0, "SD0_M0"),
0474              KEEMBAY_MUX(0x1, "SPI3_M1"),
0475              KEEMBAY_MUX(0x2, "I2C1_M2"),
0476              KEEMBAY_MUX(0x3, "DEBUG_M3"),
0477              KEEMBAY_MUX(0x4, "CAM_M4"),
0478              KEEMBAY_MUX(0x5, "I2S0_M5"),
0479              KEEMBAY_MUX(0x6, "SLVDS1_M6"),
0480              KEEMBAY_MUX(0x7, "GPIO_M7")),
0481     KEEMBAY_PIN_DESC(38, "GPIO38",
0482              KEEMBAY_MUX(0x0, "I3C1_M0"),
0483              KEEMBAY_MUX(0x1, "SPI3_M1"),
0484              KEEMBAY_MUX(0x2, "UART3_M2"),
0485              KEEMBAY_MUX(0x3, "DEBUG_M3"),
0486              KEEMBAY_MUX(0x4, "CAM_M4"),
0487              KEEMBAY_MUX(0x5, "LCD_M5"),
0488              KEEMBAY_MUX(0x6, "I2C2_M6"),
0489              KEEMBAY_MUX(0x7, "GPIO_M7")),
0490     KEEMBAY_PIN_DESC(39, "GPIO39",
0491              KEEMBAY_MUX(0x0, "I3C1_M0"),
0492              KEEMBAY_MUX(0x1, "SPI3_M1"),
0493              KEEMBAY_MUX(0x2, "UART3_M2"),
0494              KEEMBAY_MUX(0x3, "DEBUG_M3"),
0495              KEEMBAY_MUX(0x4, "CAM_M4"),
0496              KEEMBAY_MUX(0x5, "LCD_M5"),
0497              KEEMBAY_MUX(0x6, "I2C2_M6"),
0498              KEEMBAY_MUX(0x7, "GPIO_M7")),
0499     KEEMBAY_PIN_DESC(40, "GPIO40",
0500              KEEMBAY_MUX(0x0, "I2S2_M0"),
0501              KEEMBAY_MUX(0x1, "SPI3_M1"),
0502              KEEMBAY_MUX(0x2, "UART3_M2"),
0503              KEEMBAY_MUX(0x3, "DEBUG_M3"),
0504              KEEMBAY_MUX(0x4, "CAM_M4"),
0505              KEEMBAY_MUX(0x5, "LCD_M5"),
0506              KEEMBAY_MUX(0x6, "I2C3_M6"),
0507              KEEMBAY_MUX(0x7, "GPIO_M7")),
0508     KEEMBAY_PIN_DESC(41, "GPIO41",
0509              KEEMBAY_MUX(0x0, "ETH_M0"),
0510              KEEMBAY_MUX(0x1, "SPI3_M1"),
0511              KEEMBAY_MUX(0x2, "SPI3_M2"),
0512              KEEMBAY_MUX(0x3, "DEBUG_M3"),
0513              KEEMBAY_MUX(0x4, "CAM_M4"),
0514              KEEMBAY_MUX(0x5, "LCD_M5"),
0515              KEEMBAY_MUX(0x6, "I2C3_M6"),
0516              KEEMBAY_MUX(0x7, "GPIO_M7")),
0517     KEEMBAY_PIN_DESC(42, "GPIO42",
0518              KEEMBAY_MUX(0x0, "ETH_M0"),
0519              KEEMBAY_MUX(0x1, "SD1_M1"),
0520              KEEMBAY_MUX(0x2, "SPI3_M2"),
0521              KEEMBAY_MUX(0x3, "CPR_M3"),
0522              KEEMBAY_MUX(0x4, "CAM_M4"),
0523              KEEMBAY_MUX(0x5, "LCD_M5"),
0524              KEEMBAY_MUX(0x6, "I2C4_M6"),
0525              KEEMBAY_MUX(0x7, "GPIO_M7")),
0526     KEEMBAY_PIN_DESC(43, "GPIO43",
0527              KEEMBAY_MUX(0x0, "ETH_M0"),
0528              KEEMBAY_MUX(0x1, "SD1_M1"),
0529              KEEMBAY_MUX(0x2, "SPI3_M2"),
0530              KEEMBAY_MUX(0x3, "CPR_M3"),
0531              KEEMBAY_MUX(0x4, "I2S0_M4"),
0532              KEEMBAY_MUX(0x5, "LCD_M5"),
0533              KEEMBAY_MUX(0x6, "I2C4_M6"),
0534              KEEMBAY_MUX(0x7, "GPIO_M7")),
0535     KEEMBAY_PIN_DESC(44, "GPIO44",
0536              KEEMBAY_MUX(0x0, "ETH_M0"),
0537              KEEMBAY_MUX(0x1, "SD1_M1"),
0538              KEEMBAY_MUX(0x2, "SPI0_M2"),
0539              KEEMBAY_MUX(0x3, "CPR_M3"),
0540              KEEMBAY_MUX(0x4, "I2S0_M4"),
0541              KEEMBAY_MUX(0x5, "LCD_M5"),
0542              KEEMBAY_MUX(0x6, "CAM_M6"),
0543              KEEMBAY_MUX(0x7, "GPIO_M7")),
0544     KEEMBAY_PIN_DESC(45, "GPIO45",
0545              KEEMBAY_MUX(0x0, "ETH_M0"),
0546              KEEMBAY_MUX(0x1, "SD1_M1"),
0547              KEEMBAY_MUX(0x2, "SPI0_M2"),
0548              KEEMBAY_MUX(0x3, "CPR_M3"),
0549              KEEMBAY_MUX(0x4, "I2S0_M4"),
0550              KEEMBAY_MUX(0x5, "LCD_M5"),
0551              KEEMBAY_MUX(0x6, "CAM_M6"),
0552              KEEMBAY_MUX(0x7, "GPIO_M7")),
0553     KEEMBAY_PIN_DESC(46, "GPIO46",
0554              KEEMBAY_MUX(0x0, "ETH_M0"),
0555              KEEMBAY_MUX(0x1, "SD1_M1"),
0556              KEEMBAY_MUX(0x2, "SPI0_M2"),
0557              KEEMBAY_MUX(0x3, "TPIU_M3"),
0558              KEEMBAY_MUX(0x4, "I2S0_M4"),
0559              KEEMBAY_MUX(0x5, "LCD_M5"),
0560              KEEMBAY_MUX(0x6, "CAM_M6"),
0561              KEEMBAY_MUX(0x7, "GPIO_M7")),
0562     KEEMBAY_PIN_DESC(47, "GPIO47",
0563              KEEMBAY_MUX(0x0, "ETH_M0"),
0564              KEEMBAY_MUX(0x1, "SD1_M1"),
0565              KEEMBAY_MUX(0x2, "SPI0_M2"),
0566              KEEMBAY_MUX(0x3, "TPIU_M3"),
0567              KEEMBAY_MUX(0x4, "I2S0_M4"),
0568              KEEMBAY_MUX(0x5, "LCD_M5"),
0569              KEEMBAY_MUX(0x6, "CAM_M6"),
0570              KEEMBAY_MUX(0x7, "GPIO_M7")),
0571     KEEMBAY_PIN_DESC(48, "GPIO48",
0572              KEEMBAY_MUX(0x0, "ETH_M0"),
0573              KEEMBAY_MUX(0x1, "SPI2_M1"),
0574              KEEMBAY_MUX(0x2, "UART2_M2"),
0575              KEEMBAY_MUX(0x3, "TPIU_M3"),
0576              KEEMBAY_MUX(0x4, "I2S0_M4"),
0577              KEEMBAY_MUX(0x5, "LCD_M5"),
0578              KEEMBAY_MUX(0x6, "CAM_M6"),
0579              KEEMBAY_MUX(0x7, "GPIO_M7")),
0580     KEEMBAY_PIN_DESC(49, "GPIO49",
0581              KEEMBAY_MUX(0x0, "ETH_M0"),
0582              KEEMBAY_MUX(0x1, "SPI2_M1"),
0583              KEEMBAY_MUX(0x2, "UART2_M2"),
0584              KEEMBAY_MUX(0x3, "TPIU_M3"),
0585              KEEMBAY_MUX(0x4, "I2S1_M4"),
0586              KEEMBAY_MUX(0x5, "LCD_M5"),
0587              KEEMBAY_MUX(0x6, "CAM_M6"),
0588              KEEMBAY_MUX(0x7, "GPIO_M7")),
0589     KEEMBAY_PIN_DESC(50, "GPIO50",
0590              KEEMBAY_MUX(0x0, "ETH_M0"),
0591              KEEMBAY_MUX(0x1, "SPI2_M1"),
0592              KEEMBAY_MUX(0x2, "UART2_M2"),
0593              KEEMBAY_MUX(0x3, "TPIU_M3"),
0594              KEEMBAY_MUX(0x4, "I2S1_M4"),
0595              KEEMBAY_MUX(0x5, "LCD_M5"),
0596              KEEMBAY_MUX(0x6, "CAM_M6"),
0597              KEEMBAY_MUX(0x7, "GPIO_M7")),
0598     KEEMBAY_PIN_DESC(51, "GPIO51",
0599              KEEMBAY_MUX(0x0, "ETH_M0"),
0600              KEEMBAY_MUX(0x1, "SPI2_M1"),
0601              KEEMBAY_MUX(0x2, "UART2_M2"),
0602              KEEMBAY_MUX(0x3, "TPIU_M3"),
0603              KEEMBAY_MUX(0x4, "I2S1_M4"),
0604              KEEMBAY_MUX(0x5, "LCD_M5"),
0605              KEEMBAY_MUX(0x6, "CAM_M6"),
0606              KEEMBAY_MUX(0x7, "GPIO_M7")),
0607     KEEMBAY_PIN_DESC(52, "GPIO52",
0608              KEEMBAY_MUX(0x0, "ETH_M0"),
0609              KEEMBAY_MUX(0x1, "SPI2_M1"),
0610              KEEMBAY_MUX(0x2, "SD0_M2"),
0611              KEEMBAY_MUX(0x3, "TPIU_M3"),
0612              KEEMBAY_MUX(0x4, "I2S1_M4"),
0613              KEEMBAY_MUX(0x5, "LCD_M5"),
0614              KEEMBAY_MUX(0x6, "CAM_M6"),
0615              KEEMBAY_MUX(0x7, "GPIO_M7")),
0616     KEEMBAY_PIN_DESC(53, "GPIO53",
0617              KEEMBAY_MUX(0x0, "ETH_M0"),
0618              KEEMBAY_MUX(0x1, "SPI2_M1"),
0619              KEEMBAY_MUX(0x2, "SD0_M2"),
0620              KEEMBAY_MUX(0x3, "TPIU_M3"),
0621              KEEMBAY_MUX(0x4, "I2S2_M4"),
0622              KEEMBAY_MUX(0x5, "LCD_M5"),
0623              KEEMBAY_MUX(0x6, "CAM_M6"),
0624              KEEMBAY_MUX(0x7, "GPIO_M7")),
0625     KEEMBAY_PIN_DESC(54, "GPIO54",
0626              KEEMBAY_MUX(0x0, "ETH_M0"),
0627              KEEMBAY_MUX(0x1, "SPI2_M1"),
0628              KEEMBAY_MUX(0x2, "SD0_M2"),
0629              KEEMBAY_MUX(0x3, "TPIU_M3"),
0630              KEEMBAY_MUX(0x4, "I2S2_M4"),
0631              KEEMBAY_MUX(0x5, "LCD_M5"),
0632              KEEMBAY_MUX(0x6, "CAM_M6"),
0633              KEEMBAY_MUX(0x7, "GPIO_M7")),
0634     KEEMBAY_PIN_DESC(55, "GPIO55",
0635              KEEMBAY_MUX(0x0, "ETH_M0"),
0636              KEEMBAY_MUX(0x1, "SPI2_M1"),
0637              KEEMBAY_MUX(0x2, "SD1_M2"),
0638              KEEMBAY_MUX(0x3, "TPIU_M3"),
0639              KEEMBAY_MUX(0x4, "I2S2_M4"),
0640              KEEMBAY_MUX(0x5, "LCD_M5"),
0641              KEEMBAY_MUX(0x6, "CAM_M6"),
0642              KEEMBAY_MUX(0x7, "GPIO_M7")),
0643     KEEMBAY_PIN_DESC(56, "GPIO56",
0644              KEEMBAY_MUX(0x0, "ETH_M0"),
0645              KEEMBAY_MUX(0x1, "SPI2_M1"),
0646              KEEMBAY_MUX(0x2, "SD1_M2"),
0647              KEEMBAY_MUX(0x3, "TPIU_M3"),
0648              KEEMBAY_MUX(0x4, "I2S2_M4"),
0649              KEEMBAY_MUX(0x5, "LCD_M5"),
0650              KEEMBAY_MUX(0x6, "CAM_M6"),
0651              KEEMBAY_MUX(0x7, "GPIO_M7")),
0652     KEEMBAY_PIN_DESC(57, "GPIO57",
0653              KEEMBAY_MUX(0x0, "SPI1_M0"),
0654              KEEMBAY_MUX(0x1, "I2S1_M1"),
0655              KEEMBAY_MUX(0x2, "SD1_M2"),
0656              KEEMBAY_MUX(0x3, "TPIU_M3"),
0657              KEEMBAY_MUX(0x4, "UART0_M4"),
0658              KEEMBAY_MUX(0x5, "LCD_M5"),
0659              KEEMBAY_MUX(0x6, "CAM_M6"),
0660              KEEMBAY_MUX(0x7, "GPIO_M7")),
0661     KEEMBAY_PIN_DESC(58, "GPIO58",
0662              KEEMBAY_MUX(0x0, "SPI1_M0"),
0663              KEEMBAY_MUX(0x1, "ETH_M1"),
0664              KEEMBAY_MUX(0x2, "SD0_M2"),
0665              KEEMBAY_MUX(0x3, "TPIU_M3"),
0666              KEEMBAY_MUX(0x4, "UART0_M4"),
0667              KEEMBAY_MUX(0x5, "LCD_M5"),
0668              KEEMBAY_MUX(0x6, "CAM_M6"),
0669              KEEMBAY_MUX(0x7, "GPIO_M7")),
0670     KEEMBAY_PIN_DESC(59, "GPIO59",
0671              KEEMBAY_MUX(0x0, "SPI1_M0"),
0672              KEEMBAY_MUX(0x1, "ETH_M1"),
0673              KEEMBAY_MUX(0x2, "SD0_M2"),
0674              KEEMBAY_MUX(0x3, "TPIU_M3"),
0675              KEEMBAY_MUX(0x4, "UART0_M4"),
0676              KEEMBAY_MUX(0x5, "LCD_M5"),
0677              KEEMBAY_MUX(0x6, "CAM_M6"),
0678              KEEMBAY_MUX(0x7, "GPIO_M7")),
0679     KEEMBAY_PIN_DESC(60, "GPIO60",
0680              KEEMBAY_MUX(0x0, "SPI1_M0"),
0681              KEEMBAY_MUX(0x1, "ETH_M1"),
0682              KEEMBAY_MUX(0x2, "I3C1_M2"),
0683              KEEMBAY_MUX(0x3, "TPIU_M3"),
0684              KEEMBAY_MUX(0x4, "UART0_M4"),
0685              KEEMBAY_MUX(0x5, "LCD_M5"),
0686              KEEMBAY_MUX(0x6, "CAM_M6"),
0687              KEEMBAY_MUX(0x7, "GPIO_M7")),
0688     KEEMBAY_PIN_DESC(61, "GPIO61",
0689              KEEMBAY_MUX(0x0, "SPI1_M0"),
0690              KEEMBAY_MUX(0x1, "ETH_M1"),
0691              KEEMBAY_MUX(0x2, "SD0_M2"),
0692              KEEMBAY_MUX(0x3, "TPIU_M3"),
0693              KEEMBAY_MUX(0x4, "UART1_M4"),
0694              KEEMBAY_MUX(0x5, "LCD_M5"),
0695              KEEMBAY_MUX(0x6, "CAM_M6"),
0696              KEEMBAY_MUX(0x7, "GPIO_M7")),
0697     KEEMBAY_PIN_DESC(62, "GPIO62",
0698              KEEMBAY_MUX(0x0, "SPI1_M0"),
0699              KEEMBAY_MUX(0x1, "ETH_M1"),
0700              KEEMBAY_MUX(0x2, "SD1_M2"),
0701              KEEMBAY_MUX(0x3, "TPIU_M3"),
0702              KEEMBAY_MUX(0x4, "UART1_M4"),
0703              KEEMBAY_MUX(0x5, "LCD_M5"),
0704              KEEMBAY_MUX(0x6, "CAM_M6"),
0705              KEEMBAY_MUX(0x7, "GPIO_M7")),
0706     KEEMBAY_PIN_DESC(63, "GPIO63",
0707              KEEMBAY_MUX(0x0, "I2S1_M0"),
0708              KEEMBAY_MUX(0x1, "SPI1_M1"),
0709              KEEMBAY_MUX(0x2, "SD1_M2"),
0710              KEEMBAY_MUX(0x3, "TPIU_M3"),
0711              KEEMBAY_MUX(0x4, "UART1_M4"),
0712              KEEMBAY_MUX(0x5, "LCD_M5"),
0713              KEEMBAY_MUX(0x6, "CAM_M6"),
0714              KEEMBAY_MUX(0x7, "GPIO_M7")),
0715     KEEMBAY_PIN_DESC(64, "GPIO64",
0716              KEEMBAY_MUX(0x0, "I2S2_M0"),
0717              KEEMBAY_MUX(0x1, "SPI1_M1"),
0718              KEEMBAY_MUX(0x2, "ETH_M2"),
0719              KEEMBAY_MUX(0x3, "TPIU_M3"),
0720              KEEMBAY_MUX(0x4, "UART1_M4"),
0721              KEEMBAY_MUX(0x5, "LCD_M5"),
0722              KEEMBAY_MUX(0x6, "CAM_M6"),
0723              KEEMBAY_MUX(0x7, "GPIO_M7")),
0724     KEEMBAY_PIN_DESC(65, "GPIO65",
0725              KEEMBAY_MUX(0x0, "I3C0_M0"),
0726              KEEMBAY_MUX(0x1, "SPI1_M1"),
0727              KEEMBAY_MUX(0x2, "SD1_M2"),
0728              KEEMBAY_MUX(0x3, "TPIU_M3"),
0729              KEEMBAY_MUX(0x4, "SPI0_M4"),
0730              KEEMBAY_MUX(0x5, "LCD_M5"),
0731              KEEMBAY_MUX(0x6, "CAM_M6"),
0732              KEEMBAY_MUX(0x7, "GPIO_M7")),
0733     KEEMBAY_PIN_DESC(66, "GPIO66",
0734              KEEMBAY_MUX(0x0, "I3C0_M0"),
0735              KEEMBAY_MUX(0x1, "ETH_M1"),
0736              KEEMBAY_MUX(0x2, "I2C0_M2"),
0737              KEEMBAY_MUX(0x3, "TPIU_M3"),
0738              KEEMBAY_MUX(0x4, "SPI0_M4"),
0739              KEEMBAY_MUX(0x5, "LCD_M5"),
0740              KEEMBAY_MUX(0x6, "CAM_M6"),
0741              KEEMBAY_MUX(0x7, "GPIO_M7")),
0742     KEEMBAY_PIN_DESC(67, "GPIO67",
0743              KEEMBAY_MUX(0x0, "I3C1_M0"),
0744              KEEMBAY_MUX(0x1, "ETH_M1"),
0745              KEEMBAY_MUX(0x2, "I2C0_M2"),
0746              KEEMBAY_MUX(0x3, "TPIU_M3"),
0747              KEEMBAY_MUX(0x4, "SPI0_M4"),
0748              KEEMBAY_MUX(0x5, "LCD_M5"),
0749              KEEMBAY_MUX(0x6, "I2S3_M6"),
0750              KEEMBAY_MUX(0x7, "GPIO_M7")),
0751     KEEMBAY_PIN_DESC(68, "GPIO68",
0752              KEEMBAY_MUX(0x0, "I3C1_M0"),
0753              KEEMBAY_MUX(0x1, "ETH_M1"),
0754              KEEMBAY_MUX(0x2, "I2C1_M2"),
0755              KEEMBAY_MUX(0x3, "TPIU_M3"),
0756              KEEMBAY_MUX(0x4, "SPI0_M4"),
0757              KEEMBAY_MUX(0x5, "LCD_M5"),
0758              KEEMBAY_MUX(0x6, "I2S3_M6"),
0759              KEEMBAY_MUX(0x7, "GPIO_M7")),
0760     KEEMBAY_PIN_DESC(69, "GPIO69",
0761              KEEMBAY_MUX(0x0, "I3C2_M0"),
0762              KEEMBAY_MUX(0x1, "ETH_M1"),
0763              KEEMBAY_MUX(0x2, "I2C1_M2"),
0764              KEEMBAY_MUX(0x3, "TPIU_M3"),
0765              KEEMBAY_MUX(0x4, "SPI0_M4"),
0766              KEEMBAY_MUX(0x5, "LCD_M5"),
0767              KEEMBAY_MUX(0x6, "I2S3_M6"),
0768              KEEMBAY_MUX(0x7, "GPIO_M7")),
0769     KEEMBAY_PIN_DESC(70, "GPIO70",
0770              KEEMBAY_MUX(0x0, "I3C2_M0"),
0771              KEEMBAY_MUX(0x1, "ETH_M1"),
0772              KEEMBAY_MUX(0x2, "SPI0_M2"),
0773              KEEMBAY_MUX(0x3, "TPIU_M3"),
0774              KEEMBAY_MUX(0x4, "SD0_M4"),
0775              KEEMBAY_MUX(0x5, "LCD_M5"),
0776              KEEMBAY_MUX(0x6, "I2S3_M6"),
0777              KEEMBAY_MUX(0x7, "GPIO_M7")),
0778     KEEMBAY_PIN_DESC(71, "GPIO71",
0779              KEEMBAY_MUX(0x0, "I3C0_M0"),
0780              KEEMBAY_MUX(0x1, "ETH_M1"),
0781              KEEMBAY_MUX(0x2, "SLVDS1_M2"),
0782              KEEMBAY_MUX(0x3, "TPIU_M3"),
0783              KEEMBAY_MUX(0x4, "SD0_M4"),
0784              KEEMBAY_MUX(0x5, "LCD_M5"),
0785              KEEMBAY_MUX(0x6, "I2S3_M6"),
0786              KEEMBAY_MUX(0x7, "GPIO_M7")),
0787     KEEMBAY_PIN_DESC(72, "GPIO72",
0788              KEEMBAY_MUX(0x0, "I3C1_M0"),
0789              KEEMBAY_MUX(0x1, "ETH_M1"),
0790              KEEMBAY_MUX(0x2, "SLVDS1_M2"),
0791              KEEMBAY_MUX(0x3, "TPIU_M3"),
0792              KEEMBAY_MUX(0x4, "SD0_M4"),
0793              KEEMBAY_MUX(0x5, "LCD_M5"),
0794              KEEMBAY_MUX(0x6, "UART2_M6"),
0795              KEEMBAY_MUX(0x7, "GPIO_M7")),
0796     KEEMBAY_PIN_DESC(73, "GPIO73",
0797              KEEMBAY_MUX(0x0, "I3C2_M0"),
0798              KEEMBAY_MUX(0x1, "ETH_M1"),
0799              KEEMBAY_MUX(0x2, "SLVDS1_M2"),
0800              KEEMBAY_MUX(0x3, "TPIU_M3"),
0801              KEEMBAY_MUX(0x4, "SD0_M4"),
0802              KEEMBAY_MUX(0x5, "LCD_M5"),
0803              KEEMBAY_MUX(0x6, "UART2_M6"),
0804              KEEMBAY_MUX(0x7, "GPIO_M7")),
0805     KEEMBAY_PIN_DESC(74, "GPIO74",
0806              KEEMBAY_MUX(0x0, "I3C0_M0"),
0807              KEEMBAY_MUX(0x1, "ETH_M1"),
0808              KEEMBAY_MUX(0x2, "SLVDS1_M2"),
0809              KEEMBAY_MUX(0x3, "TPIU_M3"),
0810              KEEMBAY_MUX(0x4, "SD0_M4"),
0811              KEEMBAY_MUX(0x5, "LCD_M5"),
0812              KEEMBAY_MUX(0x6, "UART2_M6"),
0813              KEEMBAY_MUX(0x7, "GPIO_M7")),
0814     KEEMBAY_PIN_DESC(75, "GPIO75",
0815              KEEMBAY_MUX(0x0, "I3C0_M0"),
0816              KEEMBAY_MUX(0x1, "ETH_M1"),
0817              KEEMBAY_MUX(0x2, "SLVDS1_M2"),
0818              KEEMBAY_MUX(0x3, "TPIU_M3"),
0819              KEEMBAY_MUX(0x4, "SD0_M4"),
0820              KEEMBAY_MUX(0x5, "LCD_M5"),
0821              KEEMBAY_MUX(0x6, "UART2_M6"),
0822              KEEMBAY_MUX(0x7, "GPIO_M7")),
0823     KEEMBAY_PIN_DESC(76, "GPIO76",
0824              KEEMBAY_MUX(0x0, "I2C2_M0"),
0825              KEEMBAY_MUX(0x1, "I3C0_M1"),
0826              KEEMBAY_MUX(0x2, "SLVDS1_M2"),
0827              KEEMBAY_MUX(0x3, "TPIU_M3"),
0828              KEEMBAY_MUX(0x4, "ETH_M4"),
0829              KEEMBAY_MUX(0x5, "LCD_M5"),
0830              KEEMBAY_MUX(0x6, "UART3_M6"),
0831              KEEMBAY_MUX(0x7, "GPIO_M7")),
0832     KEEMBAY_PIN_DESC(77, "GPIO77",
0833              KEEMBAY_MUX(0x0, "PCIE_M0"),
0834              KEEMBAY_MUX(0x1, "I3C1_M1"),
0835              KEEMBAY_MUX(0x2, "SLVDS1_M2"),
0836              KEEMBAY_MUX(0x3, "TPIU_M3"),
0837              KEEMBAY_MUX(0x4, "I3C2_M4"),
0838              KEEMBAY_MUX(0x5, "LCD_M5"),
0839              KEEMBAY_MUX(0x6, "UART3_M6"),
0840              KEEMBAY_MUX(0x7, "GPIO_M7")),
0841     KEEMBAY_PIN_DESC(78, "GPIO78",
0842              KEEMBAY_MUX(0x0, "PCIE_M0"),
0843              KEEMBAY_MUX(0x1, "I3C2_M1"),
0844              KEEMBAY_MUX(0x2, "SLVDS1_M2"),
0845              KEEMBAY_MUX(0x3, "TPIU_M3"),
0846              KEEMBAY_MUX(0x4, "I3C2_M4"),
0847              KEEMBAY_MUX(0x5, "LCD_M5"),
0848              KEEMBAY_MUX(0x6, "UART3_M6"),
0849              KEEMBAY_MUX(0x7, "GPIO_M7")),
0850     KEEMBAY_PIN_DESC(79, "GPIO79",
0851              KEEMBAY_MUX(0x0, "PCIE_M0"),
0852              KEEMBAY_MUX(0x1, "I2C2_M1"),
0853              KEEMBAY_MUX(0x2, "SLVDS1_M2"),
0854              KEEMBAY_MUX(0x3, "TPIU_M3"),
0855              KEEMBAY_MUX(0x4, "I3C2_M4"),
0856              KEEMBAY_MUX(0x5, "LCD_M5"),
0857              KEEMBAY_MUX(0x6, "UART3_M6"),
0858              KEEMBAY_MUX(0x7, "GPIO_M7")),
0859 };
0860 
0861 static inline u32 keembay_read_reg(void __iomem *base, unsigned int pin)
0862 {
0863     return readl(base + KEEMBAY_GPIO_REG_OFFSET(pin));
0864 }
0865 
0866 static inline u32 keembay_read_gpio_reg(void __iomem *base, unsigned int pin)
0867 {
0868     return keembay_read_reg(base, pin / KEEMBAY_GPIO_MAX_PER_REG);
0869 }
0870 
0871 static inline u32 keembay_read_pin(void __iomem *base, unsigned int pin)
0872 {
0873     u32 val = keembay_read_gpio_reg(base, pin);
0874 
0875     return !!(val & BIT(pin % KEEMBAY_GPIO_MAX_PER_REG));
0876 }
0877 
0878 static inline void keembay_write_reg(u32 val, void __iomem *base, unsigned int pin)
0879 {
0880     writel(val, base + KEEMBAY_GPIO_REG_OFFSET(pin));
0881 }
0882 
0883 static inline void keembay_write_gpio_reg(u32 val, void __iomem *base, unsigned int pin)
0884 {
0885     keembay_write_reg(val, base, pin / KEEMBAY_GPIO_MAX_PER_REG);
0886 }
0887 
0888 static void keembay_gpio_invert(struct keembay_pinctrl *kpc, unsigned int pin)
0889 {
0890     unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
0891 
0892     /*
0893      * This IP doesn't support the falling edge and low level interrupt
0894      * trigger. Invert API is used to mimic the falling edge and low
0895      * level support
0896      */
0897 
0898     val |= FIELD_PREP(KEEMBAY_GPIO_MODE_INV_MASK, KEEMBAY_GPIO_MODE_INV_VAL);
0899     keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin);
0900 }
0901 
0902 static void keembay_gpio_restore_default(struct keembay_pinctrl *kpc, unsigned int pin)
0903 {
0904     unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
0905 
0906     val &= FIELD_PREP(KEEMBAY_GPIO_MODE_INV_MASK, 0);
0907     keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin);
0908 }
0909 
0910 static int keembay_request_gpio(struct pinctrl_dev *pctldev,
0911                 struct pinctrl_gpio_range *range, unsigned int pin)
0912 {
0913     struct keembay_pinctrl *kpc = pinctrl_dev_get_drvdata(pctldev);
0914     unsigned int val;
0915 
0916     if (pin >= kpc->npins)
0917         return -EINVAL;
0918 
0919     val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
0920     val = FIELD_GET(KEEMBAY_GPIO_MODE_SELECT_MASK, val);
0921 
0922     /* As per Pin Mux Map, Modes 0 to 6 are for peripherals */
0923     if (val != KEEMBAY_GPIO_MODE_DEFAULT)
0924         return -EBUSY;
0925 
0926     return 0;
0927 }
0928 
0929 static int keembay_set_mux(struct pinctrl_dev *pctldev, unsigned int fun_sel,
0930                unsigned int grp_sel)
0931 {
0932     struct keembay_pinctrl *kpc = pinctrl_dev_get_drvdata(pctldev);
0933     struct function_desc *func;
0934     struct group_desc *grp;
0935     unsigned int val;
0936     u8 pin_mode;
0937     int pin;
0938 
0939     grp = pinctrl_generic_get_group(pctldev, grp_sel);
0940     if (!grp)
0941         return -EINVAL;
0942 
0943     func = pinmux_generic_get_function(pctldev, fun_sel);
0944     if (!func)
0945         return -EINVAL;
0946 
0947     /* Change modes for pins in the selected group */
0948     pin = *grp->pins;
0949     pin_mode = *(u8 *)(func->data);
0950 
0951     val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
0952     val = u32_replace_bits(val, pin_mode, KEEMBAY_GPIO_MODE_SELECT_MASK);
0953     keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin);
0954 
0955     return 0;
0956 }
0957 
0958 static u32 keembay_pinconf_get_pull(struct keembay_pinctrl *kpc, unsigned int pin)
0959 {
0960     unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
0961 
0962     return FIELD_GET(KEEMBAY_GPIO_MODE_PULLUP_MASK, val);
0963 }
0964 
0965 static int keembay_pinconf_set_pull(struct keembay_pinctrl *kpc, unsigned int pin,
0966                     unsigned int pull)
0967 {
0968     unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
0969 
0970     val = u32_replace_bits(val, pull, KEEMBAY_GPIO_MODE_PULLUP_MASK);
0971     keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin);
0972 
0973     return 0;
0974 }
0975 
0976 static int keembay_pinconf_get_drive(struct keembay_pinctrl *kpc, unsigned int pin)
0977 {
0978     unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
0979 
0980     val = FIELD_GET(KEEMBAY_GPIO_MODE_DRIVE_MASK, val) * 4;
0981     if (val)
0982         return val;
0983 
0984     return KEEMBAY_GPIO_MIN_STRENGTH;
0985 }
0986 
0987 static int keembay_pinconf_set_drive(struct keembay_pinctrl *kpc, unsigned int pin,
0988                      unsigned int drive)
0989 {
0990     unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
0991     unsigned int strength = clamp_val(drive, KEEMBAY_GPIO_MIN_STRENGTH,
0992                  KEEMBAY_GPIO_MAX_STRENGTH) / 4;
0993 
0994     val = u32_replace_bits(val, strength, KEEMBAY_GPIO_MODE_DRIVE_MASK);
0995     keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin);
0996 
0997     return 0;
0998 }
0999 
1000 static int keembay_pinconf_get_slew_rate(struct keembay_pinctrl *kpc, unsigned int pin)
1001 {
1002     unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
1003 
1004     return !!(val & KEEMBAY_GPIO_MODE_SLEW_RATE);
1005 }
1006 
1007 static int keembay_pinconf_set_slew_rate(struct keembay_pinctrl *kpc, unsigned int pin,
1008                      unsigned int slew_rate)
1009 {
1010     unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
1011 
1012     if (slew_rate)
1013         val |= KEEMBAY_GPIO_MODE_SLEW_RATE;
1014     else
1015         val &= ~KEEMBAY_GPIO_MODE_SLEW_RATE;
1016 
1017     keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin);
1018 
1019     return 0;
1020 }
1021 
1022 static int keembay_pinconf_get_schmitt(struct keembay_pinctrl *kpc, unsigned int pin)
1023 {
1024     unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
1025 
1026     return !!(val & KEEMBAY_GPIO_MODE_SCHMITT_EN);
1027 }
1028 
1029 static int keembay_pinconf_set_schmitt(struct keembay_pinctrl *kpc, unsigned int pin,
1030                        unsigned int schmitt_en)
1031 {
1032     unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
1033 
1034     if (schmitt_en)
1035         val |= KEEMBAY_GPIO_MODE_SCHMITT_EN;
1036     else
1037         val &= ~KEEMBAY_GPIO_MODE_SCHMITT_EN;
1038 
1039     keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin);
1040 
1041     return 0;
1042 }
1043 
1044 static int keembay_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
1045                    unsigned long *cfg)
1046 {
1047     struct keembay_pinctrl *kpc = pinctrl_dev_get_drvdata(pctldev);
1048     unsigned int param = pinconf_to_config_param(*cfg);
1049     unsigned int val;
1050 
1051     if (pin >= kpc->npins)
1052         return -EINVAL;
1053 
1054     switch (param) {
1055     case PIN_CONFIG_BIAS_DISABLE:
1056         if (keembay_pinconf_get_pull(kpc, pin) != KEEMBAY_GPIO_DISABLE)
1057             return -EINVAL;
1058         break;
1059 
1060     case PIN_CONFIG_BIAS_PULL_UP:
1061         if (keembay_pinconf_get_pull(kpc, pin) != KEEMBAY_GPIO_PULL_UP)
1062             return -EINVAL;
1063         break;
1064 
1065     case PIN_CONFIG_BIAS_PULL_DOWN:
1066         if (keembay_pinconf_get_pull(kpc, pin) != KEEMBAY_GPIO_PULL_DOWN)
1067             return -EINVAL;
1068         break;
1069 
1070     case PIN_CONFIG_BIAS_BUS_HOLD:
1071         if (keembay_pinconf_get_pull(kpc, pin) != KEEMBAY_GPIO_BUS_HOLD)
1072             return -EINVAL;
1073         break;
1074 
1075     case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1076         if (!keembay_pinconf_get_schmitt(kpc, pin))
1077             return -EINVAL;
1078         break;
1079 
1080     case PIN_CONFIG_SLEW_RATE:
1081         val = keembay_pinconf_get_slew_rate(kpc, pin);
1082         *cfg = pinconf_to_config_packed(param, val);
1083         break;
1084 
1085     case PIN_CONFIG_DRIVE_STRENGTH:
1086         val = keembay_pinconf_get_drive(kpc, pin);
1087         *cfg = pinconf_to_config_packed(param, val);
1088         break;
1089 
1090     default:
1091         return -ENOTSUPP;
1092     }
1093 
1094     return 0;
1095 }
1096 
1097 static int keembay_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1098                    unsigned long *cfg, unsigned int num_configs)
1099 {
1100     struct keembay_pinctrl *kpc = pinctrl_dev_get_drvdata(pctldev);
1101     enum pin_config_param param;
1102     unsigned int arg, i;
1103     int ret = 0;
1104 
1105     if (pin >= kpc->npins)
1106         return -EINVAL;
1107 
1108     for (i = 0; i < num_configs; i++) {
1109         param = pinconf_to_config_param(cfg[i]);
1110         arg = pinconf_to_config_argument(cfg[i]);
1111 
1112         switch (param) {
1113         case PIN_CONFIG_BIAS_DISABLE:
1114             ret = keembay_pinconf_set_pull(kpc, pin, KEEMBAY_GPIO_DISABLE);
1115             break;
1116 
1117         case PIN_CONFIG_BIAS_PULL_UP:
1118             ret = keembay_pinconf_set_pull(kpc, pin, KEEMBAY_GPIO_PULL_UP);
1119             break;
1120 
1121         case PIN_CONFIG_BIAS_PULL_DOWN:
1122             ret = keembay_pinconf_set_pull(kpc, pin, KEEMBAY_GPIO_PULL_DOWN);
1123             break;
1124 
1125         case PIN_CONFIG_BIAS_BUS_HOLD:
1126             ret = keembay_pinconf_set_pull(kpc, pin, KEEMBAY_GPIO_BUS_HOLD);
1127             break;
1128 
1129         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1130             ret = keembay_pinconf_set_schmitt(kpc, pin, arg);
1131             break;
1132 
1133         case PIN_CONFIG_SLEW_RATE:
1134             ret = keembay_pinconf_set_slew_rate(kpc, pin, arg);
1135             break;
1136 
1137         case PIN_CONFIG_DRIVE_STRENGTH:
1138             ret = keembay_pinconf_set_drive(kpc, pin, arg);
1139             break;
1140 
1141         default:
1142             return -ENOTSUPP;
1143         }
1144         if (ret)
1145             return ret;
1146     }
1147     return ret;
1148 }
1149 
1150 static const struct pinctrl_ops keembay_pctlops = {
1151     .get_groups_count   = pinctrl_generic_get_group_count,
1152     .get_group_name     = pinctrl_generic_get_group_name,
1153     .get_group_pins     = pinctrl_generic_get_group_pins,
1154     .dt_node_to_map     = pinconf_generic_dt_node_to_map_all,
1155     .dt_free_map        = pinconf_generic_dt_free_map,
1156 };
1157 
1158 static const struct pinmux_ops keembay_pmxops = {
1159     .get_functions_count    = pinmux_generic_get_function_count,
1160     .get_function_name  = pinmux_generic_get_function_name,
1161     .get_function_groups    = pinmux_generic_get_function_groups,
1162     .gpio_request_enable    = keembay_request_gpio,
1163     .set_mux        = keembay_set_mux,
1164 };
1165 
1166 static const struct pinconf_ops keembay_confops = {
1167     .is_generic = true,
1168     .pin_config_get = keembay_pinconf_get,
1169     .pin_config_set = keembay_pinconf_set,
1170 };
1171 
1172 static struct pinctrl_desc keembay_pinctrl_desc = {
1173     .name       = "keembay-pinmux",
1174     .pctlops    = &keembay_pctlops,
1175     .pmxops     = &keembay_pmxops,
1176     .confops    = &keembay_confops,
1177     .owner      = THIS_MODULE,
1178 };
1179 
1180 static int keembay_gpio_get(struct gpio_chip *gc, unsigned int pin)
1181 {
1182     struct keembay_pinctrl *kpc = gpiochip_get_data(gc);
1183     unsigned int val, offset;
1184 
1185     val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
1186     offset = (val & KEEMBAY_GPIO_MODE_DIR) ? KEEMBAY_GPIO_DATA_IN : KEEMBAY_GPIO_DATA_OUT;
1187 
1188     return keembay_read_pin(kpc->base0 + offset, pin);
1189 }
1190 
1191 static void keembay_gpio_set(struct gpio_chip *gc, unsigned int pin, int val)
1192 {
1193     struct keembay_pinctrl *kpc = gpiochip_get_data(gc);
1194     unsigned int reg_val;
1195 
1196     reg_val = keembay_read_gpio_reg(kpc->base0 + KEEMBAY_GPIO_DATA_OUT, pin);
1197     if (val)
1198         keembay_write_gpio_reg(reg_val | BIT(pin % KEEMBAY_GPIO_MAX_PER_REG),
1199                        kpc->base0 + KEEMBAY_GPIO_DATA_HIGH, pin);
1200     else
1201         keembay_write_gpio_reg(~reg_val | BIT(pin % KEEMBAY_GPIO_MAX_PER_REG),
1202                        kpc->base0 + KEEMBAY_GPIO_DATA_LOW, pin);
1203 }
1204 
1205 static int keembay_gpio_get_direction(struct gpio_chip *gc, unsigned int pin)
1206 {
1207     struct keembay_pinctrl *kpc = gpiochip_get_data(gc);
1208     unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
1209 
1210     return !!(val & KEEMBAY_GPIO_MODE_DIR);
1211 }
1212 
1213 static int keembay_gpio_set_direction_in(struct gpio_chip *gc, unsigned int pin)
1214 {
1215     struct keembay_pinctrl *kpc = gpiochip_get_data(gc);
1216     unsigned int val;
1217 
1218     val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
1219     val |= KEEMBAY_GPIO_MODE_DIR;
1220     keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin);
1221 
1222     return 0;
1223 }
1224 
1225 static int keembay_gpio_set_direction_out(struct gpio_chip *gc,
1226                       unsigned int pin, int value)
1227 {
1228     struct keembay_pinctrl *kpc = gpiochip_get_data(gc);
1229     unsigned int val;
1230 
1231     val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
1232     val &= ~KEEMBAY_GPIO_MODE_DIR;
1233     keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin);
1234     keembay_gpio_set(gc, pin, value);
1235 
1236     return 0;
1237 }
1238 
1239 static void keembay_gpio_irq_handler(struct irq_desc *desc)
1240 {
1241     struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1242     unsigned int kmb_irq = irq_desc_get_irq(desc);
1243     unsigned long reg, clump = 0, bit = 0;
1244     struct irq_chip *parent_chip;
1245     struct keembay_pinctrl *kpc;
1246     unsigned int src, pin, val;
1247 
1248     /* Identify GPIO interrupt number from GIC interrupt number */
1249     for (src = 0; src < KEEMBAY_GPIO_NUM_IRQ; src++) {
1250         if (kmb_irq == gc->irq.parents[src])
1251             break;
1252     }
1253 
1254     if (src == KEEMBAY_GPIO_NUM_IRQ)
1255         return;
1256 
1257     parent_chip = irq_desc_get_chip(desc);
1258     kpc = gpiochip_get_data(gc);
1259 
1260     chained_irq_enter(parent_chip, desc);
1261     reg = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_INT_CFG, src);
1262 
1263     /*
1264      * Each Interrupt line can be shared by up to 4 GPIO pins. Enable bit
1265      * and input values were checked to identify the source of the
1266      * Interrupt. The checked enable bit positions are 7, 15, 23 and 31.
1267      */
1268     for_each_set_clump8(bit, clump, &reg, BITS_PER_TYPE(typeof(reg))) {
1269         pin = clump & ~KEEMBAY_GPIO_IRQ_ENABLE;
1270         val = keembay_read_pin(kpc->base0 + KEEMBAY_GPIO_DATA_IN, pin);
1271         kmb_irq = irq_linear_revmap(gc->irq.domain, pin);
1272 
1273         /* Checks if the interrupt is enabled */
1274         if (val && (clump & KEEMBAY_GPIO_IRQ_ENABLE))
1275             generic_handle_irq(kmb_irq);
1276     }
1277     chained_irq_exit(parent_chip, desc);
1278 }
1279 
1280 static void keembay_gpio_clear_irq(struct irq_data *data, unsigned long pos,
1281                    u32 src, irq_hw_number_t pin)
1282 {
1283     struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
1284     struct keembay_pinctrl *kpc = gpiochip_get_data(gc);
1285     unsigned long trig = irqd_get_trigger_type(data);
1286     struct keembay_gpio_irq *irq = &kpc->irq[src];
1287     unsigned long val;
1288 
1289     /* Check if the value of pos/KEEMBAY_GPIO_NUM_IRQ is in valid range. */
1290     if ((pos / KEEMBAY_GPIO_NUM_IRQ) >= KEEMBAY_GPIO_MAX_PER_IRQ)
1291         return;
1292 
1293     /* Retains val register as it handles other interrupts as well. */
1294     val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_INT_CFG, src);
1295 
1296     bitmap_set_value8(&val, 0, pos);
1297     keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_INT_CFG, src);
1298 
1299     irq->num_share--;
1300     irq->pins[pos / KEEMBAY_GPIO_NUM_IRQ] = 0;
1301 
1302     if (trig & IRQ_TYPE_LEVEL_MASK)
1303         keembay_gpio_restore_default(kpc, pin);
1304 
1305     if (irq->trigger == IRQ_TYPE_LEVEL_HIGH)
1306         kpc->max_gpios_level_type++;
1307     else if (irq->trigger == IRQ_TYPE_EDGE_RISING)
1308         kpc->max_gpios_edge_type++;
1309 }
1310 
1311 static int keembay_find_free_slot(struct keembay_pinctrl *kpc, unsigned int src)
1312 {
1313     unsigned long val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_INT_CFG, src);
1314 
1315     return bitmap_find_free_region(&val, KEEMBAY_GPIO_MAX_PER_REG, 3) / KEEMBAY_GPIO_NUM_IRQ;
1316 }
1317 
1318 static int keembay_find_free_src(struct keembay_pinctrl *kpc, unsigned int trig)
1319 {
1320     int src, type = 0;
1321 
1322     if (trig & IRQ_TYPE_LEVEL_MASK)
1323         type = IRQ_TYPE_LEVEL_HIGH;
1324     else if (trig & IRQ_TYPE_EDGE_BOTH)
1325         type = IRQ_TYPE_EDGE_RISING;
1326 
1327     for (src = 0; src < KEEMBAY_GPIO_NUM_IRQ; src++) {
1328         if (kpc->irq[src].trigger != type)
1329             continue;
1330 
1331         if (!keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_INT_CFG, src) ||
1332             kpc->irq[src].num_share < KEEMBAY_GPIO_MAX_PER_IRQ)
1333             return src;
1334     }
1335 
1336     return -EBUSY;
1337 }
1338 
1339 static void keembay_gpio_set_irq(struct keembay_pinctrl *kpc, int src,
1340                  int slot, irq_hw_number_t pin)
1341 {
1342     unsigned long val = pin | KEEMBAY_GPIO_IRQ_ENABLE;
1343     struct keembay_gpio_irq *irq = &kpc->irq[src];
1344     unsigned long flags, reg;
1345 
1346     raw_spin_lock_irqsave(&kpc->lock, flags);
1347     reg = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_INT_CFG, src);
1348     bitmap_set_value8(&reg, val, slot * 8);
1349     keembay_write_reg(reg, kpc->base1 + KEEMBAY_GPIO_INT_CFG, src);
1350     raw_spin_unlock_irqrestore(&kpc->lock, flags);
1351 
1352     if (irq->trigger == IRQ_TYPE_LEVEL_HIGH)
1353         kpc->max_gpios_level_type--;
1354     else if (irq->trigger == IRQ_TYPE_EDGE_RISING)
1355         kpc->max_gpios_edge_type--;
1356 
1357     irq->source = src;
1358     irq->pins[slot] = pin;
1359     irq->num_share++;
1360 }
1361 
1362 static void keembay_gpio_irq_enable(struct irq_data *data)
1363 {
1364     struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
1365     struct keembay_pinctrl *kpc = gpiochip_get_data(gc);
1366     unsigned int trig = irqd_get_trigger_type(data);
1367     irq_hw_number_t pin = irqd_to_hwirq(data);
1368     int src, slot;
1369 
1370     /* Check which Interrupt source and slot is available */
1371     src = keembay_find_free_src(kpc, trig);
1372     slot = keembay_find_free_slot(kpc, src);
1373 
1374     if (src < 0 || slot < 0)
1375         return;
1376 
1377     if (trig & KEEMBAY_GPIO_SENSE_LOW)
1378         keembay_gpio_invert(kpc, pin);
1379 
1380     keembay_gpio_set_irq(kpc, src, slot, pin);
1381 }
1382 
1383 static void keembay_gpio_irq_ack(struct irq_data *data)
1384 {
1385     /*
1386      * The keembay_gpio_irq_ack function is needed to handle_edge_irq.
1387      * IRQ ack is not possible from the SOC perspective. The IP by itself
1388      * is used for handling interrupts which do not come in short-time and
1389      * not used as protocol or communication interrupts. All the interrupts
1390      * are threaded IRQ interrupts. But this function is expected to be
1391      * present as the gpio IP is registered with irq framework. Otherwise
1392      * handle_edge_irq() fails.
1393      */
1394 }
1395 
1396 static void keembay_gpio_irq_disable(struct irq_data *data)
1397 {
1398     struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
1399     struct keembay_pinctrl *kpc = gpiochip_get_data(gc);
1400     irq_hw_number_t pin = irqd_to_hwirq(data);
1401     unsigned long reg, clump = 0, pos = 0;
1402     unsigned int src;
1403 
1404     for (src = 0; src < KEEMBAY_GPIO_NUM_IRQ; src++) {
1405         reg = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_INT_CFG, src);
1406         for_each_set_clump8(pos, clump, &reg, BITS_PER_TYPE(typeof(reg))) {
1407             if ((clump & ~KEEMBAY_GPIO_IRQ_ENABLE) == pin) {
1408                 keembay_gpio_clear_irq(data, pos, src, pin);
1409                 return;
1410             }
1411         }
1412     }
1413 }
1414 
1415 static int keembay_gpio_irq_set_type(struct irq_data *data, unsigned int type)
1416 {
1417     struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
1418     struct keembay_pinctrl *kpc = gpiochip_get_data(gc);
1419 
1420     /* Change EDGE_BOTH as EDGE_RISING in order to claim the IRQ for power button */
1421     if (!kpc->max_gpios_edge_type && (type & IRQ_TYPE_EDGE_BOTH))
1422         type = IRQ_TYPE_EDGE_RISING;
1423 
1424     if (!kpc->max_gpios_level_type && (type & IRQ_TYPE_LEVEL_MASK))
1425         type = IRQ_TYPE_NONE;
1426 
1427     if (type & IRQ_TYPE_EDGE_BOTH)
1428         irq_set_handler_locked(data, handle_edge_irq);
1429     else if (type & IRQ_TYPE_LEVEL_MASK)
1430         irq_set_handler_locked(data, handle_level_irq);
1431     else
1432         return -EINVAL;
1433 
1434     return 0;
1435 }
1436 
1437 static int keembay_gpio_add_pin_ranges(struct gpio_chip *chip)
1438 {
1439     struct keembay_pinctrl *kpc = gpiochip_get_data(chip);
1440     int ret;
1441 
1442     ret = gpiochip_add_pin_range(chip, dev_name(kpc->dev), 0, 0, chip->ngpio);
1443     if (ret)
1444         dev_err_probe(kpc->dev, ret, "failed to add GPIO pin range\n");
1445     return ret;
1446 }
1447 
1448 static struct irq_chip keembay_gpio_irqchip = {
1449     .name = "keembay-gpio",
1450     .irq_enable = keembay_gpio_irq_enable,
1451     .irq_disable = keembay_gpio_irq_disable,
1452     .irq_set_type = keembay_gpio_irq_set_type,
1453     .irq_ack = keembay_gpio_irq_ack,
1454 };
1455 
1456 static int keembay_gpiochip_probe(struct keembay_pinctrl *kpc,
1457                   struct platform_device *pdev)
1458 {
1459     unsigned int i, level_line = 0, edge_line = 0;
1460     struct gpio_chip *gc = &kpc->chip;
1461     struct gpio_irq_chip *girq;
1462 
1463     /* Setup GPIO IRQ chip */
1464     girq            = &kpc->chip.irq;
1465     girq->chip      = &keembay_gpio_irqchip;
1466     girq->parent_handler    = keembay_gpio_irq_handler;
1467     girq->num_parents   = KEEMBAY_GPIO_NUM_IRQ;
1468     girq->parents       = devm_kcalloc(kpc->dev, girq->num_parents,
1469                            sizeof(*girq->parents), GFP_KERNEL);
1470 
1471     if (!girq->parents)
1472         return -ENOMEM;
1473 
1474     /* Setup GPIO chip */
1475     gc->label       = dev_name(kpc->dev);
1476     gc->parent      = kpc->dev;
1477     gc->request     = gpiochip_generic_request;
1478     gc->free        = gpiochip_generic_free;
1479     gc->get_direction   = keembay_gpio_get_direction;
1480     gc->direction_input = keembay_gpio_set_direction_in;
1481     gc->direction_output    = keembay_gpio_set_direction_out;
1482     gc->get         = keembay_gpio_get;
1483     gc->set         = keembay_gpio_set;
1484     gc->set_config      = gpiochip_generic_config;
1485     gc->base        = -1;
1486     gc->ngpio       = kpc->npins;
1487     gc->add_pin_ranges  = keembay_gpio_add_pin_ranges;
1488 
1489     for (i = 0; i < KEEMBAY_GPIO_NUM_IRQ; i++) {
1490         struct keembay_gpio_irq *kmb_irq = &kpc->irq[i];
1491         int irq;
1492 
1493         irq = platform_get_irq_optional(pdev, i);
1494         if (irq <= 0)
1495             continue;
1496 
1497         girq->parents[i]    = irq;
1498         kmb_irq->line   = girq->parents[i];
1499         kmb_irq->source = i;
1500         kmb_irq->trigger    = irq_get_trigger_type(girq->parents[i]);
1501         kmb_irq->num_share  = 0;
1502 
1503         if (kmb_irq->trigger == IRQ_TYPE_LEVEL_HIGH)
1504             level_line++;
1505         else
1506             edge_line++;
1507     }
1508 
1509     kpc->max_gpios_level_type = level_line * KEEMBAY_GPIO_MAX_PER_IRQ;
1510     kpc->max_gpios_edge_type = edge_line * KEEMBAY_GPIO_MAX_PER_IRQ;
1511 
1512     girq->default_type = IRQ_TYPE_NONE;
1513     girq->handler = handle_bad_irq;
1514 
1515     return devm_gpiochip_add_data(kpc->dev, gc, kpc);
1516 }
1517 
1518 static int keembay_build_groups(struct keembay_pinctrl *kpc)
1519 {
1520     struct group_desc *grp;
1521     unsigned int i;
1522 
1523     kpc->ngroups = kpc->npins;
1524     grp = devm_kcalloc(kpc->dev, kpc->ngroups, sizeof(*grp), GFP_KERNEL);
1525     if (!grp)
1526         return -ENOMEM;
1527 
1528     /* Each pin is categorised as one group */
1529     for (i = 0; i < kpc->ngroups; i++) {
1530         const struct pinctrl_pin_desc *pdesc = keembay_pins + i;
1531         struct group_desc *kmb_grp = grp + i;
1532 
1533         kmb_grp->name = pdesc->name;
1534         kmb_grp->pins = (int *)&pdesc->number;
1535         pinctrl_generic_add_group(kpc->pctrl, kmb_grp->name,
1536                       kmb_grp->pins, 1, NULL);
1537     }
1538 
1539     return 0;
1540 }
1541 
1542 static int keembay_pinctrl_reg(struct keembay_pinctrl *kpc,  struct device *dev)
1543 {
1544     int ret;
1545 
1546     keembay_pinctrl_desc.pins = keembay_pins;
1547     ret = of_property_read_u32(dev->of_node, "ngpios", &kpc->npins);
1548     if (ret < 0)
1549         return ret;
1550     keembay_pinctrl_desc.npins = kpc->npins;
1551 
1552     kpc->pctrl = devm_pinctrl_register(kpc->dev, &keembay_pinctrl_desc, kpc);
1553 
1554     return PTR_ERR_OR_ZERO(kpc->pctrl);
1555 }
1556 
1557 static int keembay_add_functions(struct keembay_pinctrl *kpc,
1558                  struct function_desc *functions)
1559 {
1560     unsigned int i;
1561 
1562     /* Assign the groups for each function */
1563     for (i = 0; i < kpc->nfuncs; i++) {
1564         struct function_desc *func = &functions[i];
1565         const char **group_names;
1566         unsigned int grp_idx = 0;
1567         int j;
1568 
1569         group_names = devm_kcalloc(kpc->dev, func->num_group_names,
1570                        sizeof(*group_names), GFP_KERNEL);
1571         if (!group_names)
1572             return -ENOMEM;
1573 
1574         for (j = 0; j < kpc->npins; j++) {
1575             const struct pinctrl_pin_desc *pdesc = &keembay_pins[j];
1576             struct keembay_mux_desc *mux;
1577 
1578             for (mux = pdesc->drv_data; mux->name; mux++) {
1579                 if (!strcmp(mux->name, func->name))
1580                     group_names[grp_idx++] = pdesc->name;
1581             }
1582         }
1583 
1584         func->group_names = group_names;
1585     }
1586 
1587     /* Add all functions */
1588     for (i = 0; i < kpc->nfuncs; i++) {
1589         pinmux_generic_add_function(kpc->pctrl,
1590                         functions[i].name,
1591                         functions[i].group_names,
1592                         functions[i].num_group_names,
1593                         functions[i].data);
1594     }
1595 
1596     return 0;
1597 }
1598 
1599 static int keembay_build_functions(struct keembay_pinctrl *kpc)
1600 {
1601     struct function_desc *keembay_funcs, *new_funcs;
1602     int i;
1603 
1604     /*
1605      * Allocate maximum possible number of functions. Assume every pin
1606      * being part of 8 (hw maximum) globally unique muxes.
1607      */
1608     kpc->nfuncs = 0;
1609     keembay_funcs = kcalloc(kpc->npins * 8, sizeof(*keembay_funcs), GFP_KERNEL);
1610     if (!keembay_funcs)
1611         return -ENOMEM;
1612 
1613     /* Setup 1 function for each unique mux */
1614     for (i = 0; i < kpc->npins; i++) {
1615         const struct pinctrl_pin_desc *pdesc = keembay_pins + i;
1616         struct keembay_mux_desc *mux;
1617 
1618         for (mux = pdesc->drv_data; mux->name; mux++) {
1619             struct function_desc *fdesc;
1620 
1621             /* Check if we already have function for this mux */
1622             for (fdesc = keembay_funcs; fdesc->name; fdesc++) {
1623                 if (!strcmp(mux->name, fdesc->name)) {
1624                     fdesc->num_group_names++;
1625                     break;
1626                 }
1627             }
1628 
1629             /* Setup new function for this mux we didn't see before */
1630             if (!fdesc->name) {
1631                 fdesc->name = mux->name;
1632                 fdesc->num_group_names = 1;
1633                 fdesc->data = &mux->mode;
1634                 kpc->nfuncs++;
1635             }
1636         }
1637     }
1638 
1639     /* Reallocate memory based on actual number of functions */
1640     new_funcs = krealloc(keembay_funcs, kpc->nfuncs * sizeof(*new_funcs), GFP_KERNEL);
1641     if (!new_funcs) {
1642         kfree(keembay_funcs);
1643         return -ENOMEM;
1644     }
1645 
1646     return keembay_add_functions(kpc, new_funcs);
1647 }
1648 
1649 static const struct keembay_pin_soc keembay_data = {
1650     .pins    = keembay_pins,
1651 };
1652 
1653 static const struct of_device_id keembay_pinctrl_match[] = {
1654     { .compatible = "intel,keembay-pinctrl", .data = &keembay_data },
1655     { }
1656 };
1657 MODULE_DEVICE_TABLE(of, keembay_pinctrl_match);
1658 
1659 static int keembay_pinctrl_probe(struct platform_device *pdev)
1660 {
1661     struct device *dev = &pdev->dev;
1662     struct keembay_pinctrl *kpc;
1663     int ret;
1664 
1665     kpc = devm_kzalloc(dev, sizeof(*kpc), GFP_KERNEL);
1666     if (!kpc)
1667         return -ENOMEM;
1668 
1669     kpc->dev = dev;
1670     kpc->soc = device_get_match_data(dev);
1671 
1672     kpc->base0 = devm_platform_ioremap_resource(pdev, 0);
1673     if (IS_ERR(kpc->base0))
1674         return PTR_ERR(kpc->base0);
1675 
1676     kpc->base1 = devm_platform_ioremap_resource(pdev, 1);
1677     if (IS_ERR(kpc->base1))
1678         return PTR_ERR(kpc->base1);
1679 
1680     raw_spin_lock_init(&kpc->lock);
1681 
1682     ret = keembay_pinctrl_reg(kpc, dev);
1683     if (ret)
1684         return ret;
1685 
1686     ret = keembay_build_groups(kpc);
1687     if (ret)
1688         return ret;
1689 
1690     ret = keembay_build_functions(kpc);
1691     if (ret)
1692         return ret;
1693 
1694     ret = keembay_gpiochip_probe(kpc, pdev);
1695     if (ret)
1696         return ret;
1697 
1698     platform_set_drvdata(pdev, kpc);
1699 
1700     return 0;
1701 }
1702 
1703 static struct platform_driver keembay_pinctrl_driver = {
1704     .probe = keembay_pinctrl_probe,
1705     .driver = {
1706         .name = "keembay-pinctrl",
1707         .of_match_table = keembay_pinctrl_match,
1708     },
1709 };
1710 module_platform_driver(keembay_pinctrl_driver);
1711 
1712 MODULE_AUTHOR("Muhammad Husaini Zulkifli <muhammad.husaini.zulkifli@intel.com>");
1713 MODULE_AUTHOR("Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>");
1714 MODULE_AUTHOR("Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>");
1715 MODULE_DESCRIPTION("Intel Keem Bay SoC pinctrl/GPIO driver");
1716 MODULE_LICENSE("GPL");
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