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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  linux/drivers/pinctrl/pinmux-falcon.c
0004  *  based on linux/drivers/pinctrl/pinmux-pxa910.c
0005  *
0006  *  Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com>
0007  *  Copyright (C) 2012 John Crispin <john@phrozen.org>
0008  */
0009 
0010 #include <linux/gpio/driver.h>
0011 #include <linux/interrupt.h>
0012 #include <linux/slab.h>
0013 #include <linux/export.h>
0014 #include <linux/err.h>
0015 #include <linux/module.h>
0016 #include <linux/of.h>
0017 #include <linux/of_platform.h>
0018 #include <linux/of_address.h>
0019 #include <linux/of_gpio.h>
0020 #include <linux/platform_device.h>
0021 
0022 #include "pinctrl-lantiq.h"
0023 
0024 #include <lantiq_soc.h>
0025 
0026 /* Multiplexer Control Register */
0027 #define LTQ_PADC_MUX(x)         (x * 0x4)
0028 /* Pull Up Enable Register */
0029 #define LTQ_PADC_PUEN       0x80
0030 /* Pull Down Enable Register */
0031 #define LTQ_PADC_PDEN       0x84
0032 /* Slew Rate Control Register */
0033 #define LTQ_PADC_SRC        0x88
0034 /* Drive Current Control Register */
0035 #define LTQ_PADC_DCC        0x8C
0036 /* Pad Control Availability Register */
0037 #define LTQ_PADC_AVAIL          0xF0
0038 
0039 #define pad_r32(p, reg)     ltq_r32(p + reg)
0040 #define pad_w32(p, val, reg)    ltq_w32(val, p + reg)
0041 #define pad_w32_mask(c, clear, set, reg) \
0042         pad_w32(c, (pad_r32(c, reg) & ~(clear)) | (set), reg)
0043 
0044 #define pad_getbit(m, r, p) (!!(ltq_r32(m + r) & (1 << p)))
0045 
0046 #define PORTS           5
0047 #define PINS            32
0048 #define PORT(x)                 (x / PINS)
0049 #define PORT_PIN(x)             (x % PINS)
0050 
0051 #define MFP_FALCON(a, f0, f1, f2, f3)       \
0052 {                       \
0053     .name = #a,             \
0054     .pin = a,               \
0055     .func = {               \
0056         FALCON_MUX_##f0,        \
0057         FALCON_MUX_##f1,        \
0058         FALCON_MUX_##f2,        \
0059         FALCON_MUX_##f3,        \
0060     },                  \
0061 }
0062 
0063 #define GRP_MUX(a, m, p)    \
0064 {               \
0065     .name = a,      \
0066     .mux = FALCON_MUX_##m,  \
0067     .pins = p,      \
0068     .npins = ARRAY_SIZE(p), \
0069 }
0070 
0071 enum falcon_mux {
0072     FALCON_MUX_GPIO = 0,
0073     FALCON_MUX_RST,
0074     FALCON_MUX_NTR,
0075     FALCON_MUX_PPS,
0076     FALCON_MUX_MDIO,
0077     FALCON_MUX_LED,
0078     FALCON_MUX_SPI,
0079     FALCON_MUX_ASC,
0080     FALCON_MUX_I2C,
0081     FALCON_MUX_HOSTIF,
0082     FALCON_MUX_SLIC,
0083     FALCON_MUX_JTAG,
0084     FALCON_MUX_PCM,
0085     FALCON_MUX_MII,
0086     FALCON_MUX_PHY,
0087     FALCON_MUX_NONE = 0xffff,
0088 };
0089 
0090 static struct pinctrl_pin_desc falcon_pads[PORTS * PINS];
0091 static int pad_count[PORTS];
0092 
0093 static void lantiq_load_pin_desc(struct pinctrl_pin_desc *d, int bank, int len)
0094 {
0095     int base = bank * PINS;
0096     int i;
0097 
0098     for (i = 0; i < len; i++) {
0099         d[i].number = base + i;
0100         d[i].name = kasprintf(GFP_KERNEL, "io%d", base + i);
0101     }
0102     pad_count[bank] = len;
0103 }
0104 
0105 static struct ltq_mfp_pin falcon_mfp[] = {
0106     /*  pin     f0  f1  f2  f3 */
0107     MFP_FALCON(GPIO0,   RST,    GPIO,   NONE,   NONE),
0108     MFP_FALCON(GPIO1,   GPIO,   GPIO,   NONE,   NONE),
0109     MFP_FALCON(GPIO2,   GPIO,   GPIO,   NONE,   NONE),
0110     MFP_FALCON(GPIO3,   GPIO,   GPIO,   NONE,   NONE),
0111     MFP_FALCON(GPIO4,   NTR,    GPIO,   NONE,   NONE),
0112     MFP_FALCON(GPIO5,   NTR,    GPIO,   PPS,    NONE),
0113     MFP_FALCON(GPIO6,   RST,    GPIO,   NONE,   NONE),
0114     MFP_FALCON(GPIO7,   MDIO,   GPIO,   NONE,   NONE),
0115     MFP_FALCON(GPIO8,   MDIO,   GPIO,   NONE,   NONE),
0116     MFP_FALCON(GPIO9,   LED,    GPIO,   NONE,   NONE),
0117     MFP_FALCON(GPIO10,  LED,    GPIO,   NONE,   NONE),
0118     MFP_FALCON(GPIO11,  LED,    GPIO,   NONE,   NONE),
0119     MFP_FALCON(GPIO12,  LED,    GPIO,   NONE,   NONE),
0120     MFP_FALCON(GPIO13,  LED,    GPIO,   NONE,   NONE),
0121     MFP_FALCON(GPIO14,  LED,    GPIO,   NONE,   NONE),
0122     MFP_FALCON(GPIO32,  ASC,    GPIO,   NONE,   NONE),
0123     MFP_FALCON(GPIO33,  ASC,    GPIO,   NONE,   NONE),
0124     MFP_FALCON(GPIO34,  SPI,    GPIO,   NONE,   NONE),
0125     MFP_FALCON(GPIO35,  SPI,    GPIO,   NONE,   NONE),
0126     MFP_FALCON(GPIO36,  SPI,    GPIO,   NONE,   NONE),
0127     MFP_FALCON(GPIO37,  SPI,    GPIO,   NONE,   NONE),
0128     MFP_FALCON(GPIO38,  SPI,    GPIO,   NONE,   NONE),
0129     MFP_FALCON(GPIO39,  I2C,    GPIO,   NONE,   NONE),
0130     MFP_FALCON(GPIO40,  I2C,    GPIO,   NONE,   NONE),
0131     MFP_FALCON(GPIO41,  HOSTIF, GPIO,   HOSTIF, JTAG),
0132     MFP_FALCON(GPIO42,  HOSTIF, GPIO,   HOSTIF, NONE),
0133     MFP_FALCON(GPIO43,  SLIC,   GPIO,   NONE,   NONE),
0134     MFP_FALCON(GPIO44,  SLIC,   GPIO,   PCM,    ASC),
0135     MFP_FALCON(GPIO45,  SLIC,   GPIO,   PCM,    ASC),
0136     MFP_FALCON(GPIO64,  MII,    GPIO,   NONE,   NONE),
0137     MFP_FALCON(GPIO65,  MII,    GPIO,   NONE,   NONE),
0138     MFP_FALCON(GPIO66,  MII,    GPIO,   NONE,   NONE),
0139     MFP_FALCON(GPIO67,  MII,    GPIO,   NONE,   NONE),
0140     MFP_FALCON(GPIO68,  MII,    GPIO,   NONE,   NONE),
0141     MFP_FALCON(GPIO69,  MII,    GPIO,   NONE,   NONE),
0142     MFP_FALCON(GPIO70,  MII,    GPIO,   NONE,   NONE),
0143     MFP_FALCON(GPIO71,  MII,    GPIO,   NONE,   NONE),
0144     MFP_FALCON(GPIO72,  MII,    GPIO,   NONE,   NONE),
0145     MFP_FALCON(GPIO73,  MII,    GPIO,   NONE,   NONE),
0146     MFP_FALCON(GPIO74,  MII,    GPIO,   NONE,   NONE),
0147     MFP_FALCON(GPIO75,  MII,    GPIO,   NONE,   NONE),
0148     MFP_FALCON(GPIO76,  MII,    GPIO,   NONE,   NONE),
0149     MFP_FALCON(GPIO77,  MII,    GPIO,   NONE,   NONE),
0150     MFP_FALCON(GPIO78,  MII,    GPIO,   NONE,   NONE),
0151     MFP_FALCON(GPIO79,  MII,    GPIO,   NONE,   NONE),
0152     MFP_FALCON(GPIO80,  MII,    GPIO,   NONE,   NONE),
0153     MFP_FALCON(GPIO81,  MII,    GPIO,   NONE,   NONE),
0154     MFP_FALCON(GPIO82,  MII,    GPIO,   NONE,   NONE),
0155     MFP_FALCON(GPIO83,  MII,    GPIO,   NONE,   NONE),
0156     MFP_FALCON(GPIO84,  MII,    GPIO,   NONE,   NONE),
0157     MFP_FALCON(GPIO85,  MII,    GPIO,   NONE,   NONE),
0158     MFP_FALCON(GPIO86,  MII,    GPIO,   NONE,   NONE),
0159     MFP_FALCON(GPIO87,  MII,    GPIO,   NONE,   NONE),
0160     MFP_FALCON(GPIO88,  PHY,    GPIO,   NONE,   NONE),
0161 };
0162 
0163 static const unsigned pins_por[] = {GPIO0};
0164 static const unsigned pins_ntr[] = {GPIO4};
0165 static const unsigned pins_ntr8k[] = {GPIO5};
0166 static const unsigned pins_pps[] = {GPIO5};
0167 static const unsigned pins_hrst[] = {GPIO6};
0168 static const unsigned pins_mdio[] = {GPIO7, GPIO8};
0169 static const unsigned pins_bled[] = {GPIO9, GPIO10, GPIO11,
0170                     GPIO12, GPIO13, GPIO14};
0171 static const unsigned pins_asc0[] = {GPIO32, GPIO33};
0172 static const unsigned pins_spi[] = {GPIO34, GPIO35, GPIO36};
0173 static const unsigned pins_spi_cs0[] = {GPIO37};
0174 static const unsigned pins_spi_cs1[] = {GPIO38};
0175 static const unsigned pins_i2c[] = {GPIO39, GPIO40};
0176 static const unsigned pins_jtag[] = {GPIO41};
0177 static const unsigned pins_slic[] = {GPIO43, GPIO44, GPIO45};
0178 static const unsigned pins_pcm[] = {GPIO44, GPIO45};
0179 static const unsigned pins_asc1[] = {GPIO44, GPIO45};
0180 
0181 static struct ltq_pin_group falcon_grps[] = {
0182     GRP_MUX("por", RST, pins_por),
0183     GRP_MUX("ntr", NTR, pins_ntr),
0184     GRP_MUX("ntr8k", NTR, pins_ntr8k),
0185     GRP_MUX("pps", PPS, pins_pps),
0186     GRP_MUX("hrst", RST, pins_hrst),
0187     GRP_MUX("mdio", MDIO, pins_mdio),
0188     GRP_MUX("bootled", LED, pins_bled),
0189     GRP_MUX("asc0", ASC, pins_asc0),
0190     GRP_MUX("spi", SPI, pins_spi),
0191     GRP_MUX("spi cs0", SPI, pins_spi_cs0),
0192     GRP_MUX("spi cs1", SPI, pins_spi_cs1),
0193     GRP_MUX("i2c", I2C, pins_i2c),
0194     GRP_MUX("jtag", JTAG, pins_jtag),
0195     GRP_MUX("slic", SLIC, pins_slic),
0196     GRP_MUX("pcm", PCM, pins_pcm),
0197     GRP_MUX("asc1", ASC, pins_asc1),
0198 };
0199 
0200 static const char * const ltq_rst_grps[] = {"por", "hrst"};
0201 static const char * const ltq_ntr_grps[] = {"ntr", "ntr8k", "pps"};
0202 static const char * const ltq_mdio_grps[] = {"mdio"};
0203 static const char * const ltq_bled_grps[] = {"bootled"};
0204 static const char * const ltq_asc_grps[] = {"asc0", "asc1"};
0205 static const char * const ltq_spi_grps[] = {"spi", "spi cs0", "spi cs1"};
0206 static const char * const ltq_i2c_grps[] = {"i2c"};
0207 static const char * const ltq_jtag_grps[] = {"jtag"};
0208 static const char * const ltq_slic_grps[] = {"slic"};
0209 static const char * const ltq_pcm_grps[] = {"pcm"};
0210 
0211 static struct ltq_pmx_func falcon_funcs[] = {
0212     {"rst",     ARRAY_AND_SIZE(ltq_rst_grps)},
0213     {"ntr",     ARRAY_AND_SIZE(ltq_ntr_grps)},
0214     {"mdio",    ARRAY_AND_SIZE(ltq_mdio_grps)},
0215     {"led",     ARRAY_AND_SIZE(ltq_bled_grps)},
0216     {"asc",     ARRAY_AND_SIZE(ltq_asc_grps)},
0217     {"spi",     ARRAY_AND_SIZE(ltq_spi_grps)},
0218     {"i2c",     ARRAY_AND_SIZE(ltq_i2c_grps)},
0219     {"jtag",    ARRAY_AND_SIZE(ltq_jtag_grps)},
0220     {"slic",    ARRAY_AND_SIZE(ltq_slic_grps)},
0221     {"pcm",     ARRAY_AND_SIZE(ltq_pcm_grps)},
0222 };
0223 
0224 
0225 
0226 
0227 /* ---------  pinconf related code --------- */
0228 static int falcon_pinconf_group_get(struct pinctrl_dev *pctrldev,
0229                 unsigned group, unsigned long *config)
0230 {
0231     return -ENOTSUPP;
0232 }
0233 
0234 static int falcon_pinconf_group_set(struct pinctrl_dev *pctrldev,
0235                 unsigned group, unsigned long *configs,
0236                 unsigned num_configs)
0237 {
0238     return -ENOTSUPP;
0239 }
0240 
0241 static int falcon_pinconf_get(struct pinctrl_dev *pctrldev,
0242                 unsigned pin, unsigned long *config)
0243 {
0244     struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
0245     enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(*config);
0246     void __iomem *mem = info->membase[PORT(pin)];
0247 
0248     switch (param) {
0249     case LTQ_PINCONF_PARAM_DRIVE_CURRENT:
0250         *config = LTQ_PINCONF_PACK(param,
0251             !!pad_getbit(mem, LTQ_PADC_DCC, PORT_PIN(pin)));
0252         break;
0253 
0254     case LTQ_PINCONF_PARAM_SLEW_RATE:
0255         *config = LTQ_PINCONF_PACK(param,
0256             !!pad_getbit(mem, LTQ_PADC_SRC, PORT_PIN(pin)));
0257         break;
0258 
0259     case LTQ_PINCONF_PARAM_PULL:
0260         if (pad_getbit(mem, LTQ_PADC_PDEN, PORT_PIN(pin)))
0261             *config = LTQ_PINCONF_PACK(param, 1);
0262         else if (pad_getbit(mem, LTQ_PADC_PUEN, PORT_PIN(pin)))
0263             *config = LTQ_PINCONF_PACK(param, 2);
0264         else
0265             *config = LTQ_PINCONF_PACK(param, 0);
0266 
0267         break;
0268 
0269     default:
0270         return -ENOTSUPP;
0271     }
0272 
0273     return 0;
0274 }
0275 
0276 static int falcon_pinconf_set(struct pinctrl_dev *pctrldev,
0277             unsigned pin, unsigned long *configs,
0278             unsigned num_configs)
0279 {
0280     enum ltq_pinconf_param param;
0281     int arg;
0282     struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
0283     void __iomem *mem = info->membase[PORT(pin)];
0284     u32 reg;
0285     int i;
0286 
0287     for (i = 0; i < num_configs; i++) {
0288         param = LTQ_PINCONF_UNPACK_PARAM(configs[i]);
0289         arg = LTQ_PINCONF_UNPACK_ARG(configs[i]);
0290 
0291         switch (param) {
0292         case LTQ_PINCONF_PARAM_DRIVE_CURRENT:
0293             reg = LTQ_PADC_DCC;
0294             break;
0295 
0296         case LTQ_PINCONF_PARAM_SLEW_RATE:
0297             reg = LTQ_PADC_SRC;
0298             break;
0299 
0300         case LTQ_PINCONF_PARAM_PULL:
0301             if (arg == 1)
0302                 reg = LTQ_PADC_PDEN;
0303             else
0304                 reg = LTQ_PADC_PUEN;
0305             break;
0306 
0307         default:
0308             pr_err("%s: Invalid config param %04x\n",
0309             pinctrl_dev_get_name(pctrldev), param);
0310             return -ENOTSUPP;
0311         }
0312 
0313         pad_w32(mem, BIT(PORT_PIN(pin)), reg);
0314         if (!(pad_r32(mem, reg) & BIT(PORT_PIN(pin))))
0315             return -ENOTSUPP;
0316     } /* for each config */
0317 
0318     return 0;
0319 }
0320 
0321 static void falcon_pinconf_dbg_show(struct pinctrl_dev *pctrldev,
0322             struct seq_file *s, unsigned offset)
0323 {
0324     unsigned long config;
0325     struct pin_desc *desc;
0326 
0327     struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
0328     int port = PORT(offset);
0329 
0330     seq_printf(s, " (port %d) mux %d -- ", port,
0331         pad_r32(info->membase[port], LTQ_PADC_MUX(PORT_PIN(offset))));
0332 
0333     config = LTQ_PINCONF_PACK(LTQ_PINCONF_PARAM_PULL, 0);
0334     if (!falcon_pinconf_get(pctrldev, offset, &config))
0335         seq_printf(s, "pull %d ",
0336             (int)LTQ_PINCONF_UNPACK_ARG(config));
0337 
0338     config = LTQ_PINCONF_PACK(LTQ_PINCONF_PARAM_DRIVE_CURRENT, 0);
0339     if (!falcon_pinconf_get(pctrldev, offset, &config))
0340         seq_printf(s, "drive-current %d ",
0341             (int)LTQ_PINCONF_UNPACK_ARG(config));
0342 
0343     config = LTQ_PINCONF_PACK(LTQ_PINCONF_PARAM_SLEW_RATE, 0);
0344     if (!falcon_pinconf_get(pctrldev, offset, &config))
0345         seq_printf(s, "slew-rate %d ",
0346             (int)LTQ_PINCONF_UNPACK_ARG(config));
0347 
0348     desc = pin_desc_get(pctrldev, offset);
0349     if (desc) {
0350         if (desc->gpio_owner)
0351             seq_printf(s, " owner: %s", desc->gpio_owner);
0352     } else {
0353         seq_printf(s, " not registered");
0354     }
0355 }
0356 
0357 static void falcon_pinconf_group_dbg_show(struct pinctrl_dev *pctrldev,
0358             struct seq_file *s, unsigned selector)
0359 {
0360 }
0361 
0362 static const struct pinconf_ops falcon_pinconf_ops = {
0363     .pin_config_get         = falcon_pinconf_get,
0364     .pin_config_set         = falcon_pinconf_set,
0365     .pin_config_group_get       = falcon_pinconf_group_get,
0366     .pin_config_group_set       = falcon_pinconf_group_set,
0367     .pin_config_dbg_show        = falcon_pinconf_dbg_show,
0368     .pin_config_group_dbg_show  = falcon_pinconf_group_dbg_show,
0369 };
0370 
0371 static struct pinctrl_desc falcon_pctrl_desc = {
0372     .owner      = THIS_MODULE,
0373     .pins       = falcon_pads,
0374     .confops    = &falcon_pinconf_ops,
0375 };
0376 
0377 static inline int falcon_mux_apply(struct pinctrl_dev *pctrldev,
0378             int mfp, int mux)
0379 {
0380     struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
0381     int port = PORT(info->mfp[mfp].pin);
0382 
0383     if ((port >= PORTS) || (!info->membase[port]))
0384         return -ENODEV;
0385 
0386     pad_w32(info->membase[port], mux,
0387         LTQ_PADC_MUX(PORT_PIN(info->mfp[mfp].pin)));
0388     return 0;
0389 }
0390 
0391 static const struct ltq_cfg_param falcon_cfg_params[] = {
0392     {"lantiq,pull",         LTQ_PINCONF_PARAM_PULL},
0393     {"lantiq,drive-current",    LTQ_PINCONF_PARAM_DRIVE_CURRENT},
0394     {"lantiq,slew-rate",        LTQ_PINCONF_PARAM_SLEW_RATE},
0395 };
0396 
0397 static struct ltq_pinmux_info falcon_info = {
0398     .desc       = &falcon_pctrl_desc,
0399     .apply_mux  = falcon_mux_apply,
0400     .params     = falcon_cfg_params,
0401     .num_params = ARRAY_SIZE(falcon_cfg_params),
0402 };
0403 
0404 
0405 
0406 
0407 /* --------- register the pinctrl layer --------- */
0408 
0409 int pinctrl_falcon_get_range_size(int id)
0410 {
0411     u32 avail;
0412 
0413     if ((id >= PORTS) || (!falcon_info.membase[id]))
0414         return -EINVAL;
0415 
0416     avail = pad_r32(falcon_info.membase[id], LTQ_PADC_AVAIL);
0417 
0418     return fls(avail);
0419 }
0420 
0421 void pinctrl_falcon_add_gpio_range(struct pinctrl_gpio_range *range)
0422 {
0423     pinctrl_add_gpio_range(falcon_info.pctrl, range);
0424 }
0425 
0426 static int pinctrl_falcon_probe(struct platform_device *pdev)
0427 {
0428     struct device_node *np;
0429     int pad_count = 0;
0430     int ret = 0;
0431 
0432     /* load and remap the pad resources of the different banks */
0433     for_each_compatible_node(np, NULL, "lantiq,pad-falcon") {
0434         const __be32 *bank = of_get_property(np, "lantiq,bank", NULL);
0435         struct resource res;
0436         struct platform_device *ppdev;
0437         u32 avail;
0438         int pins;
0439 
0440         if (!of_device_is_available(np))
0441             continue;
0442 
0443         if (!bank || *bank >= PORTS)
0444             continue;
0445         if (of_address_to_resource(np, 0, &res))
0446             continue;
0447 
0448         ppdev = of_find_device_by_node(np);
0449         if (!ppdev) {
0450             dev_err(&pdev->dev, "failed to find pad pdev\n");
0451             continue;
0452         }
0453 
0454         falcon_info.clk[*bank] = clk_get(&ppdev->dev, NULL);
0455         put_device(&ppdev->dev);
0456         if (IS_ERR(falcon_info.clk[*bank])) {
0457             dev_err(&ppdev->dev, "failed to get clock\n");
0458             of_node_put(np);
0459             return PTR_ERR(falcon_info.clk[*bank]);
0460         }
0461         falcon_info.membase[*bank] = devm_ioremap_resource(&pdev->dev,
0462                                    &res);
0463         if (IS_ERR(falcon_info.membase[*bank])) {
0464             of_node_put(np);
0465             return PTR_ERR(falcon_info.membase[*bank]);
0466         }
0467 
0468         avail = pad_r32(falcon_info.membase[*bank],
0469                     LTQ_PADC_AVAIL);
0470         pins = fls(avail);
0471         lantiq_load_pin_desc(&falcon_pads[pad_count], *bank, pins);
0472         pad_count += pins;
0473         clk_enable(falcon_info.clk[*bank]);
0474         dev_dbg(&pdev->dev, "found %s with %d pads\n",
0475                 res.name, pins);
0476     }
0477     dev_dbg(&pdev->dev, "found a total of %d pads\n", pad_count);
0478     falcon_pctrl_desc.name  = dev_name(&pdev->dev);
0479     falcon_pctrl_desc.npins = pad_count;
0480 
0481     falcon_info.mfp     = falcon_mfp;
0482     falcon_info.num_mfp = ARRAY_SIZE(falcon_mfp);
0483     falcon_info.grps    = falcon_grps;
0484     falcon_info.num_grps    = ARRAY_SIZE(falcon_grps);
0485     falcon_info.funcs   = falcon_funcs;
0486     falcon_info.num_funcs   = ARRAY_SIZE(falcon_funcs);
0487 
0488     ret = ltq_pinctrl_register(pdev, &falcon_info);
0489     if (!ret)
0490         dev_info(&pdev->dev, "Init done\n");
0491     return ret;
0492 }
0493 
0494 static const struct of_device_id falcon_match[] = {
0495     { .compatible = "lantiq,pinctrl-falcon" },
0496     {},
0497 };
0498 MODULE_DEVICE_TABLE(of, falcon_match);
0499 
0500 static struct platform_driver pinctrl_falcon_driver = {
0501     .probe = pinctrl_falcon_probe,
0502     .driver = {
0503         .name = "pinctrl-falcon",
0504         .of_match_table = falcon_match,
0505     },
0506 };
0507 
0508 int __init pinctrl_falcon_init(void)
0509 {
0510     return platform_driver_register(&pinctrl_falcon_driver);
0511 }
0512 
0513 core_initcall_sync(pinctrl_falcon_init);
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