drivers/pinctrl/pinctrl-equilibrium.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  *  Copyright(c) 2019 Intel Corporation.
0004  */
0005
0006 #ifndef __PINCTRL_EQUILIBRIUM_H
0007 #define __PINCTRL_EQUILIBRIUM_H
0008
0009 /* PINPAD register offset */
0010 #define REG_PMX_BASE    0x0 /* Port Multiplexer Control Register */
0011 #define REG_PUEN    0x80    /* PULL UP Enable Register */
0012 #define REG_PDEN    0x84    /* PULL DOWN Enable Register */
0013 #define REG_SRC     0x88    /* Slew Rate Control Register */
0014 #define REG_DCC0    0x8C    /* Drive Current Control Register 0 */
0015 #define REG_DCC1    0x90    /* Drive Current Control Register 1 */
0016 #define REG_OD      0x94    /* Open Drain Enable Register */
0017 #define REG_AVAIL   0x98    /* Pad Control Availability Register */
0018 #define DRV_CUR_PINS    16  /* Drive Current pin number per register */
0019 #define REG_DRCC(x) (REG_DCC0 + (x) * 4) /* Driver current macro */
0020
0021 /* GPIO register offset */
0022 #define GPIO_OUT    0x0 /* Data Output Register */
0023 #define GPIO_IN     0x4 /* Data Input Register */
0024 #define GPIO_DIR    0x8 /* Direction Register */
0025 #define GPIO_EXINTCR0   0x18    /* External Interrupt Control Register 0 */
0026 #define GPIO_EXINTCR1   0x1C    /* External Interrupt Control Register 1 */
0027 #define GPIO_IRNCR  0x20    /* IRN Capture Register */
0028 #define GPIO_IRNICR 0x24    /* IRN Interrupt Control Register */
0029 #define GPIO_IRNEN  0x28    /* IRN Interrupt Enable Register */
0030 #define GPIO_IRNCFG 0x2C    /* IRN Interrupt Configuration Register */
0031 #define GPIO_IRNRNSET   0x30    /* IRN Interrupt Enable Set Register */
0032 #define GPIO_IRNENCLR   0x34    /* IRN Interrupt Enable Clear Register */
0033 #define GPIO_OUTSET 0x40    /* Output Set Register */
0034 #define GPIO_OUTCLR 0x44    /* Output Clear Register */
0035 #define GPIO_DIRSET 0x48    /* Direction Set Register */
0036 #define GPIO_DIRCLR 0x4C    /* Direction Clear Register */
0037
0038 /* parse given pin's driver current value */
0039 #define PARSE_DRV_CURRENT(val, pin) (((val) >> ((pin) * 2)) & 0x3)
0040
0041 #define GPIO_EDGE_TRIG      0
0042 #define GPIO_LEVEL_TRIG     1
0043 #define GPIO_SINGLE_EDGE    0
0044 #define GPIO_BOTH_EDGE      1
0045 #define GPIO_POSITIVE_TRIG  0
0046 #define GPIO_NEGATIVE_TRIG  1
0047
0048 #define EQBR_GPIO_MODE      0
0049
0050 typedef enum {
0051     OP_COUNT_NR_FUNCS,
0052     OP_ADD_FUNCS,
0053     OP_COUNT_NR_FUNC_GRPS,
0054     OP_ADD_FUNC_GRPS,
0055     OP_NONE,
0056 } funcs_util_ops;
0057
0058 /**
0059  * struct gpio_irq_type: gpio irq configuration
0060  * @trig_type: level trigger or edge trigger
0061  * @edge_type: sigle edge or both edge
0062  * @logic_type: positive trigger or negative trigger
0063  */
0064 struct gpio_irq_type {
0065     unsigned int trig_type;
0066     unsigned int edge_type;
0067     unsigned int logic_type;
0068 };
0069
0070 /**
0071  * struct eqbr_pmx_func: represent a pin function.
0072  * @name: name of the pin function, used to lookup the function.
0073  * @groups: one or more names of pin groups that provide this function.
0074  * @nr_groups: number of groups included in @groups.
0075  */
0076 struct eqbr_pmx_func {
0077     const char      *name;
0078     const char      **groups;
0079     unsigned int        nr_groups;
0080 };
0081
0082 /**
0083  * struct eqbr_pin_bank: represent a pin bank.
0084  * @membase: base address of the pin bank register.
0085  * @id: bank id, to idenify the unique bank.
0086  * @pin_base: starting pin number of the pin bank.
0087  * @nr_pins: number of the pins of the pin bank.
0088  * @aval_pinmap: available pin bitmap of the pin bank.
0089  */
0090 struct eqbr_pin_bank {
0091     void __iomem        *membase;
0092     unsigned int        id;
0093     unsigned int        pin_base;
0094     unsigned int        nr_pins;
0095     u32         aval_pinmap;
0096 };
0097
0098 struct fwnode_handle;
0099
0100 /**
0101  * struct eqbr_gpio_ctrl: represent a gpio controller.
0102  * @chip: gpio chip.
0103  * @fwnode: firmware node of gpio controller.
0104  * @bank: pointer to corresponding pin bank.
0105  * @membase: base address of the gpio controller.
0106  * @ic:   irq chip.
0107  * @name: gpio chip name.
0108  * @virq: irq number of the gpio chip to parent's irq domain.
0109  * @lock: spin lock to protect gpio register write.
0110  */
0111 struct eqbr_gpio_ctrl {
0112     struct gpio_chip    chip;
0113     struct fwnode_handle    *fwnode;
0114     struct eqbr_pin_bank    *bank;
0115     void __iomem        *membase;
0116     struct irq_chip     ic;
0117     const char      *name;
0118     unsigned int        virq;
0119     raw_spinlock_t      lock; /* protect gpio register */
0120 };
0121
0122 /**
0123  * struct eqbr_pinctrl_drv_data:
0124  * @dev: device instance representing the controller.
0125  * @pctl_desc: pin controller descriptor.
0126  * @pctl_dev: pin control class device
0127  * @membase: base address of pin controller
0128  * @pin_banks: list of pin banks of the driver.
0129  * @nr_banks: number of pin banks.
0130  * @gpio_ctrls: list of gpio controllers.
0131  * @nr_gpio_ctrls: number of gpio controllers.
0132  * @lock: protect pinctrl register write
0133  */
0134 struct eqbr_pinctrl_drv_data {
0135     struct device           *dev;
0136     struct pinctrl_desc     pctl_desc;
0137     struct pinctrl_dev      *pctl_dev;
0138     void __iomem            *membase;
0139     struct eqbr_pin_bank        *pin_banks;
0140     unsigned int            nr_banks;
0141     struct eqbr_gpio_ctrl       *gpio_ctrls;
0142     unsigned int            nr_gpio_ctrls;
0143     raw_spinlock_t          lock; /* protect pinpad register */
0144 };
0145
0146 #endif /* __PINCTRL_EQUILIBRIUM_H */