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0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Copyright (C) 2019 Intel Corporation */
0003 
0004 #include <linux/gpio/driver.h>
0005 #include <linux/module.h>
0006 #include <linux/of.h>
0007 #include <linux/of_address.h>
0008 #include <linux/of_irq.h>
0009 #include <linux/pinctrl/pinctrl.h>
0010 #include <linux/pinctrl/pinconf.h>
0011 #include <linux/pinctrl/pinconf-generic.h>
0012 #include <linux/pinctrl/pinmux.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/property.h>
0015 
0016 #include "core.h"
0017 #include "pinconf.h"
0018 #include "pinmux.h"
0019 #include "pinctrl-equilibrium.h"
0020 
0021 #define PIN_NAME_FMT    "io-%d"
0022 #define PIN_NAME_LEN    10
0023 #define PAD_REG_OFF 0x100
0024 
0025 static void eqbr_gpio_disable_irq(struct irq_data *d)
0026 {
0027     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0028     struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc);
0029     unsigned int offset = irqd_to_hwirq(d);
0030     unsigned long flags;
0031 
0032     raw_spin_lock_irqsave(&gctrl->lock, flags);
0033     writel(BIT(offset), gctrl->membase + GPIO_IRNENCLR);
0034     raw_spin_unlock_irqrestore(&gctrl->lock, flags);
0035 }
0036 
0037 static void eqbr_gpio_enable_irq(struct irq_data *d)
0038 {
0039     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0040     struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc);
0041     unsigned int offset = irqd_to_hwirq(d);
0042     unsigned long flags;
0043 
0044     gc->direction_input(gc, offset);
0045     raw_spin_lock_irqsave(&gctrl->lock, flags);
0046     writel(BIT(offset), gctrl->membase + GPIO_IRNRNSET);
0047     raw_spin_unlock_irqrestore(&gctrl->lock, flags);
0048 }
0049 
0050 static void eqbr_gpio_ack_irq(struct irq_data *d)
0051 {
0052     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0053     struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc);
0054     unsigned int offset = irqd_to_hwirq(d);
0055     unsigned long flags;
0056 
0057     raw_spin_lock_irqsave(&gctrl->lock, flags);
0058     writel(BIT(offset), gctrl->membase + GPIO_IRNCR);
0059     raw_spin_unlock_irqrestore(&gctrl->lock, flags);
0060 }
0061 
0062 static void eqbr_gpio_mask_ack_irq(struct irq_data *d)
0063 {
0064     eqbr_gpio_disable_irq(d);
0065     eqbr_gpio_ack_irq(d);
0066 }
0067 
0068 static inline void eqbr_cfg_bit(void __iomem *addr,
0069                 unsigned int offset, unsigned int set)
0070 {
0071     if (set)
0072         writel(readl(addr) | BIT(offset), addr);
0073     else
0074         writel(readl(addr) & ~BIT(offset), addr);
0075 }
0076 
0077 static int eqbr_irq_type_cfg(struct gpio_irq_type *type,
0078                  struct eqbr_gpio_ctrl *gctrl,
0079                  unsigned int offset)
0080 {
0081     unsigned long flags;
0082 
0083     raw_spin_lock_irqsave(&gctrl->lock, flags);
0084     eqbr_cfg_bit(gctrl->membase + GPIO_IRNCFG, offset, type->trig_type);
0085     eqbr_cfg_bit(gctrl->membase + GPIO_EXINTCR1, offset, type->trig_type);
0086     eqbr_cfg_bit(gctrl->membase + GPIO_EXINTCR0, offset, type->logic_type);
0087     raw_spin_unlock_irqrestore(&gctrl->lock, flags);
0088 
0089     return 0;
0090 }
0091 
0092 static int eqbr_gpio_set_irq_type(struct irq_data *d, unsigned int type)
0093 {
0094     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0095     struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc);
0096     unsigned int offset = irqd_to_hwirq(d);
0097     struct gpio_irq_type it;
0098 
0099     memset(&it, 0, sizeof(it));
0100 
0101     if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_NONE)
0102         return 0;
0103 
0104     switch (type) {
0105     case IRQ_TYPE_EDGE_RISING:
0106         it.trig_type = GPIO_EDGE_TRIG;
0107         it.edge_type = GPIO_SINGLE_EDGE;
0108         it.logic_type = GPIO_POSITIVE_TRIG;
0109         break;
0110 
0111     case IRQ_TYPE_EDGE_FALLING:
0112         it.trig_type = GPIO_EDGE_TRIG;
0113         it.edge_type = GPIO_SINGLE_EDGE;
0114         it.logic_type = GPIO_NEGATIVE_TRIG;
0115         break;
0116 
0117     case IRQ_TYPE_EDGE_BOTH:
0118         it.trig_type = GPIO_EDGE_TRIG;
0119         it.edge_type = GPIO_BOTH_EDGE;
0120         it.logic_type = GPIO_POSITIVE_TRIG;
0121         break;
0122 
0123     case IRQ_TYPE_LEVEL_HIGH:
0124         it.trig_type = GPIO_LEVEL_TRIG;
0125         it.edge_type = GPIO_SINGLE_EDGE;
0126         it.logic_type = GPIO_POSITIVE_TRIG;
0127         break;
0128 
0129     case IRQ_TYPE_LEVEL_LOW:
0130         it.trig_type = GPIO_LEVEL_TRIG;
0131         it.edge_type = GPIO_SINGLE_EDGE;
0132         it.logic_type = GPIO_NEGATIVE_TRIG;
0133         break;
0134 
0135     default:
0136         return -EINVAL;
0137     }
0138 
0139     eqbr_irq_type_cfg(&it, gctrl, offset);
0140     if (it.trig_type == GPIO_EDGE_TRIG)
0141         irq_set_handler_locked(d, handle_edge_irq);
0142     else
0143         irq_set_handler_locked(d, handle_level_irq);
0144 
0145     return 0;
0146 }
0147 
0148 static void eqbr_irq_handler(struct irq_desc *desc)
0149 {
0150     struct gpio_chip *gc = irq_desc_get_handler_data(desc);
0151     struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc);
0152     struct irq_chip *ic = irq_desc_get_chip(desc);
0153     unsigned long pins, offset;
0154 
0155     chained_irq_enter(ic, desc);
0156     pins = readl(gctrl->membase + GPIO_IRNCR);
0157 
0158     for_each_set_bit(offset, &pins, gc->ngpio)
0159         generic_handle_domain_irq(gc->irq.domain, offset);
0160 
0161     chained_irq_exit(ic, desc);
0162 }
0163 
0164 static int gpiochip_setup(struct device *dev, struct eqbr_gpio_ctrl *gctrl)
0165 {
0166     struct gpio_irq_chip *girq;
0167     struct gpio_chip *gc;
0168 
0169     gc = &gctrl->chip;
0170     gc->label = gctrl->name;
0171     gc->fwnode = gctrl->fwnode;
0172 
0173     if (!fwnode_property_read_bool(gctrl->fwnode, "interrupt-controller")) {
0174         dev_dbg(dev, "gc %s: doesn't act as interrupt controller!\n",
0175             gctrl->name);
0176         return 0;
0177     }
0178 
0179     gctrl->ic.name = "gpio_irq";
0180     gctrl->ic.irq_mask = eqbr_gpio_disable_irq;
0181     gctrl->ic.irq_unmask = eqbr_gpio_enable_irq;
0182     gctrl->ic.irq_ack = eqbr_gpio_ack_irq;
0183     gctrl->ic.irq_mask_ack = eqbr_gpio_mask_ack_irq;
0184     gctrl->ic.irq_set_type = eqbr_gpio_set_irq_type;
0185 
0186     girq = &gctrl->chip.irq;
0187     girq->chip = &gctrl->ic;
0188     girq->parent_handler = eqbr_irq_handler;
0189     girq->num_parents = 1;
0190     girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), GFP_KERNEL);
0191     if (!girq->parents)
0192         return -ENOMEM;
0193 
0194     girq->default_type = IRQ_TYPE_NONE;
0195     girq->handler = handle_bad_irq;
0196     girq->parents[0] = gctrl->virq;
0197 
0198     return 0;
0199 }
0200 
0201 static int gpiolib_reg(struct eqbr_pinctrl_drv_data *drvdata)
0202 {
0203     struct device *dev = drvdata->dev;
0204     struct eqbr_gpio_ctrl *gctrl;
0205     struct device_node *np;
0206     struct resource res;
0207     int i, ret;
0208 
0209     for (i = 0; i < drvdata->nr_gpio_ctrls; i++) {
0210         gctrl = drvdata->gpio_ctrls + i;
0211         np = to_of_node(gctrl->fwnode);
0212 
0213         gctrl->name = devm_kasprintf(dev, GFP_KERNEL, "gpiochip%d", i);
0214         if (!gctrl->name)
0215             return -ENOMEM;
0216 
0217         if (of_address_to_resource(np, 0, &res)) {
0218             dev_err(dev, "Failed to get GPIO register address\n");
0219             return -ENXIO;
0220         }
0221 
0222         gctrl->membase = devm_ioremap_resource(dev, &res);
0223         if (IS_ERR(gctrl->membase))
0224             return PTR_ERR(gctrl->membase);
0225 
0226         gctrl->virq = irq_of_parse_and_map(np, 0);
0227         if (!gctrl->virq) {
0228             dev_err(dev, "%s: failed to parse and map irq\n",
0229                 gctrl->name);
0230             return -ENXIO;
0231         }
0232         raw_spin_lock_init(&gctrl->lock);
0233 
0234         ret = bgpio_init(&gctrl->chip, dev, gctrl->bank->nr_pins / 8,
0235                  gctrl->membase + GPIO_IN,
0236                  gctrl->membase + GPIO_OUTSET,
0237                  gctrl->membase + GPIO_OUTCLR,
0238                  gctrl->membase + GPIO_DIR,
0239                  NULL, 0);
0240         if (ret) {
0241             dev_err(dev, "unable to init generic GPIO\n");
0242             return ret;
0243         }
0244 
0245         ret = gpiochip_setup(dev, gctrl);
0246         if (ret)
0247             return ret;
0248 
0249         ret = devm_gpiochip_add_data(dev, &gctrl->chip, gctrl);
0250         if (ret)
0251             return ret;
0252     }
0253 
0254     return 0;
0255 }
0256 
0257 static inline struct eqbr_pin_bank
0258 *find_pinbank_via_pin(struct eqbr_pinctrl_drv_data *pctl, unsigned int pin)
0259 {
0260     struct eqbr_pin_bank *bank;
0261     int i;
0262 
0263     for (i = 0; i < pctl->nr_banks; i++) {
0264         bank = &pctl->pin_banks[i];
0265         if (pin >= bank->pin_base &&
0266             (pin - bank->pin_base) < bank->nr_pins)
0267             return bank;
0268     }
0269 
0270     return NULL;
0271 }
0272 
0273 static const struct pinctrl_ops eqbr_pctl_ops = {
0274     .get_groups_count   = pinctrl_generic_get_group_count,
0275     .get_group_name     = pinctrl_generic_get_group_name,
0276     .get_group_pins     = pinctrl_generic_get_group_pins,
0277     .dt_node_to_map     = pinconf_generic_dt_node_to_map_all,
0278     .dt_free_map        = pinconf_generic_dt_free_map,
0279 };
0280 
0281 static int eqbr_set_pin_mux(struct eqbr_pinctrl_drv_data *pctl,
0282                 unsigned int pmx, unsigned int pin)
0283 {
0284     struct eqbr_pin_bank *bank;
0285     unsigned long flags;
0286     unsigned int offset;
0287     void __iomem *mem;
0288 
0289     bank = find_pinbank_via_pin(pctl, pin);
0290     if (!bank) {
0291         dev_err(pctl->dev, "Couldn't find pin bank for pin %u\n", pin);
0292         return -ENODEV;
0293     }
0294     mem = bank->membase;
0295     offset = pin - bank->pin_base;
0296 
0297     if (!(bank->aval_pinmap & BIT(offset))) {
0298         dev_err(pctl->dev,
0299             "PIN: %u is not valid, pinbase: %u, bitmap: %u\n",
0300             pin, bank->pin_base, bank->aval_pinmap);
0301         return -ENODEV;
0302     }
0303 
0304     raw_spin_lock_irqsave(&pctl->lock, flags);
0305     writel(pmx, mem + (offset * 4));
0306     raw_spin_unlock_irqrestore(&pctl->lock, flags);
0307     return 0;
0308 }
0309 
0310 static int eqbr_pinmux_set_mux(struct pinctrl_dev *pctldev,
0311                    unsigned int selector, unsigned int group)
0312 {
0313     struct eqbr_pinctrl_drv_data *pctl = pinctrl_dev_get_drvdata(pctldev);
0314     struct function_desc *func;
0315     struct group_desc *grp;
0316     unsigned int *pinmux;
0317     int i;
0318 
0319     func = pinmux_generic_get_function(pctldev, selector);
0320     if (!func)
0321         return -EINVAL;
0322 
0323     grp = pinctrl_generic_get_group(pctldev, group);
0324     if (!grp)
0325         return -EINVAL;
0326 
0327     pinmux = grp->data;
0328     for (i = 0; i < grp->num_pins; i++)
0329         eqbr_set_pin_mux(pctl, pinmux[i], grp->pins[i]);
0330 
0331     return 0;
0332 }
0333 
0334 static int eqbr_pinmux_gpio_request(struct pinctrl_dev *pctldev,
0335                     struct pinctrl_gpio_range *range,
0336                     unsigned int pin)
0337 {
0338     struct eqbr_pinctrl_drv_data *pctl = pinctrl_dev_get_drvdata(pctldev);
0339 
0340     return eqbr_set_pin_mux(pctl, EQBR_GPIO_MODE, pin);
0341 }
0342 
0343 static const struct pinmux_ops eqbr_pinmux_ops = {
0344     .get_functions_count    = pinmux_generic_get_function_count,
0345     .get_function_name  = pinmux_generic_get_function_name,
0346     .get_function_groups    = pinmux_generic_get_function_groups,
0347     .set_mux        = eqbr_pinmux_set_mux,
0348     .gpio_request_enable    = eqbr_pinmux_gpio_request,
0349     .strict         = true,
0350 };
0351 
0352 static int get_drv_cur(void __iomem *mem, unsigned int offset)
0353 {
0354     unsigned int idx = offset / DRV_CUR_PINS; /* 0-15, 16-31 per register*/
0355     unsigned int pin_offset = offset % DRV_CUR_PINS;
0356 
0357     return PARSE_DRV_CURRENT(readl(mem + REG_DRCC(idx)), pin_offset);
0358 }
0359 
0360 static struct eqbr_gpio_ctrl
0361 *get_gpio_ctrls_via_bank(struct eqbr_pinctrl_drv_data *pctl,
0362             struct eqbr_pin_bank *bank)
0363 {
0364     int i;
0365 
0366     for (i = 0; i < pctl->nr_gpio_ctrls; i++) {
0367         if (pctl->gpio_ctrls[i].bank == bank)
0368             return &pctl->gpio_ctrls[i];
0369     }
0370 
0371     return NULL;
0372 }
0373 
0374 static int eqbr_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
0375                 unsigned long *config)
0376 {
0377     struct eqbr_pinctrl_drv_data *pctl = pinctrl_dev_get_drvdata(pctldev);
0378     enum pin_config_param param = pinconf_to_config_param(*config);
0379     struct eqbr_gpio_ctrl *gctrl;
0380     struct eqbr_pin_bank *bank;
0381     unsigned long flags;
0382     unsigned int offset;
0383     void __iomem *mem;
0384     u32 val;
0385 
0386     bank = find_pinbank_via_pin(pctl, pin);
0387     if (!bank) {
0388         dev_err(pctl->dev, "Couldn't find pin bank for pin %u\n", pin);
0389         return -ENODEV;
0390     }
0391     mem = bank->membase;
0392     offset = pin - bank->pin_base;
0393 
0394     if (!(bank->aval_pinmap & BIT(offset))) {
0395         dev_err(pctl->dev,
0396             "PIN: %u is not valid, pinbase: %u, bitmap: %u\n",
0397             pin, bank->pin_base, bank->aval_pinmap);
0398         return -ENODEV;
0399     }
0400 
0401     raw_spin_lock_irqsave(&pctl->lock, flags);
0402     switch (param) {
0403     case PIN_CONFIG_BIAS_PULL_UP:
0404         val = !!(readl(mem + REG_PUEN) & BIT(offset));
0405         break;
0406     case PIN_CONFIG_BIAS_PULL_DOWN:
0407         val = !!(readl(mem + REG_PDEN) & BIT(offset));
0408         break;
0409     case PIN_CONFIG_DRIVE_OPEN_DRAIN:
0410         val = !!(readl(mem + REG_OD) & BIT(offset));
0411         break;
0412     case PIN_CONFIG_DRIVE_STRENGTH:
0413         val = get_drv_cur(mem, offset);
0414         break;
0415     case PIN_CONFIG_SLEW_RATE:
0416         val = !!(readl(mem + REG_SRC) & BIT(offset));
0417         break;
0418     case PIN_CONFIG_OUTPUT_ENABLE:
0419         gctrl = get_gpio_ctrls_via_bank(pctl, bank);
0420         if (!gctrl) {
0421             dev_err(pctl->dev, "Failed to find gpio via bank pinbase: %u, pin: %u\n",
0422                 bank->pin_base, pin);
0423             raw_spin_unlock_irqrestore(&pctl->lock, flags);
0424             return -ENODEV;
0425         }
0426         val = !!(readl(gctrl->membase + GPIO_DIR) & BIT(offset));
0427         break;
0428     default:
0429         raw_spin_unlock_irqrestore(&pctl->lock, flags);
0430         return -ENOTSUPP;
0431     }
0432     raw_spin_unlock_irqrestore(&pctl->lock, flags);
0433     *config = pinconf_to_config_packed(param, val);
0434 ;
0435     return 0;
0436 }
0437 
0438 static int eqbr_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
0439                 unsigned long *configs, unsigned int num_configs)
0440 {
0441     struct eqbr_pinctrl_drv_data *pctl = pinctrl_dev_get_drvdata(pctldev);
0442     struct eqbr_gpio_ctrl *gctrl;
0443     enum pin_config_param param;
0444     struct eqbr_pin_bank *bank;
0445     unsigned int val, offset;
0446     struct gpio_chip *gc;
0447     unsigned long flags;
0448     void __iomem *mem;
0449     u32 regval, mask;
0450     int i;
0451 
0452     for (i = 0; i < num_configs; i++) {
0453         param = pinconf_to_config_param(configs[i]);
0454         val = pinconf_to_config_argument(configs[i]);
0455 
0456         bank = find_pinbank_via_pin(pctl, pin);
0457         if (!bank) {
0458             dev_err(pctl->dev,
0459                 "Couldn't find pin bank for pin %u\n", pin);
0460             return -ENODEV;
0461         }
0462         mem = bank->membase;
0463         offset = pin - bank->pin_base;
0464 
0465         switch (param) {
0466         case PIN_CONFIG_BIAS_PULL_UP:
0467             mem += REG_PUEN;
0468             mask = BIT(offset);
0469             break;
0470         case PIN_CONFIG_BIAS_PULL_DOWN:
0471             mem += REG_PDEN;
0472             mask = BIT(offset);
0473             break;
0474         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
0475             mem += REG_OD;
0476             mask = BIT(offset);
0477             break;
0478         case PIN_CONFIG_DRIVE_STRENGTH:
0479             mem += REG_DRCC(offset / DRV_CUR_PINS);
0480             offset = (offset % DRV_CUR_PINS) * 2;
0481             mask = GENMASK(1, 0) << offset;
0482             break;
0483         case PIN_CONFIG_SLEW_RATE:
0484             mem += REG_SRC;
0485             mask = BIT(offset);
0486             break;
0487         case PIN_CONFIG_OUTPUT_ENABLE:
0488             gctrl = get_gpio_ctrls_via_bank(pctl, bank);
0489             if (!gctrl) {
0490                 dev_err(pctl->dev, "Failed to find gpio via bank pinbase: %u, pin: %u\n",
0491                     bank->pin_base, pin);
0492                 return -ENODEV;
0493             }
0494             gc = &gctrl->chip;
0495             gc->direction_output(gc, offset, 0);
0496             continue;
0497         default:
0498             return -ENOTSUPP;
0499         }
0500 
0501         raw_spin_lock_irqsave(&pctl->lock, flags);
0502         regval = readl(mem);
0503         regval = (regval & ~mask) | ((val << offset) & mask);
0504         writel(regval, mem);
0505         raw_spin_unlock_irqrestore(&pctl->lock, flags);
0506     }
0507 
0508     return 0;
0509 }
0510 
0511 static int eqbr_pinconf_group_get(struct pinctrl_dev *pctldev,
0512                   unsigned int group, unsigned long *config)
0513 {
0514     unsigned int i, npins, old = 0;
0515     const unsigned int *pins;
0516     int ret;
0517 
0518     ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
0519     if (ret)
0520         return ret;
0521 
0522     for (i = 0; i < npins; i++) {
0523         if (eqbr_pinconf_get(pctldev, pins[i], config))
0524             return -ENOTSUPP;
0525 
0526         if (i && old != *config)
0527             return -ENOTSUPP;
0528 
0529         old = *config;
0530     }
0531     return 0;
0532 }
0533 
0534 static int eqbr_pinconf_group_set(struct pinctrl_dev *pctldev,
0535                   unsigned int group, unsigned long *configs,
0536                   unsigned int num_configs)
0537 {
0538     const unsigned int *pins;
0539     unsigned int i, npins;
0540     int ret;
0541 
0542     ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
0543     if (ret)
0544         return ret;
0545 
0546     for (i = 0; i < npins; i++) {
0547         ret = eqbr_pinconf_set(pctldev, pins[i], configs, num_configs);
0548         if (ret)
0549             return ret;
0550     }
0551     return 0;
0552 }
0553 
0554 static const struct pinconf_ops eqbr_pinconf_ops = {
0555     .is_generic         = true,
0556     .pin_config_get         = eqbr_pinconf_get,
0557     .pin_config_set         = eqbr_pinconf_set,
0558     .pin_config_group_get       = eqbr_pinconf_group_get,
0559     .pin_config_group_set       = eqbr_pinconf_group_set,
0560     .pin_config_config_dbg_show = pinconf_generic_dump_config,
0561 };
0562 
0563 static bool is_func_exist(struct eqbr_pmx_func *funcs, const char *name,
0564              unsigned int nr_funcs, unsigned int *idx)
0565 {
0566     int i;
0567 
0568     if (!funcs)
0569         return false;
0570 
0571     for (i = 0; i < nr_funcs; i++) {
0572         if (funcs[i].name && !strcmp(funcs[i].name, name)) {
0573             *idx = i;
0574             return true;
0575         }
0576     }
0577 
0578     return false;
0579 }
0580 
0581 static int funcs_utils(struct device *dev, struct eqbr_pmx_func *funcs,
0582                unsigned int *nr_funcs, funcs_util_ops op)
0583 {
0584     struct device_node *node = dev->of_node;
0585     struct device_node *np;
0586     struct property *prop;
0587     const char *fn_name;
0588     unsigned int fid;
0589     int i, j;
0590 
0591     i = 0;
0592     for_each_child_of_node(node, np) {
0593         prop = of_find_property(np, "groups", NULL);
0594         if (!prop)
0595             continue;
0596 
0597         if (of_property_read_string(np, "function", &fn_name)) {
0598             /* some groups may not have function, it's OK */
0599             dev_dbg(dev, "Group %s: not function binded!\n",
0600                 (char *)prop->value);
0601             continue;
0602         }
0603 
0604         switch (op) {
0605         case OP_COUNT_NR_FUNCS:
0606             if (!is_func_exist(funcs, fn_name, *nr_funcs, &fid))
0607                 *nr_funcs = *nr_funcs + 1;
0608             break;
0609 
0610         case OP_ADD_FUNCS:
0611             if (!is_func_exist(funcs, fn_name, *nr_funcs, &fid))
0612                 funcs[i].name = fn_name;
0613             break;
0614 
0615         case OP_COUNT_NR_FUNC_GRPS:
0616             if (is_func_exist(funcs, fn_name, *nr_funcs, &fid))
0617                 funcs[fid].nr_groups++;
0618             break;
0619 
0620         case OP_ADD_FUNC_GRPS:
0621             if (is_func_exist(funcs, fn_name, *nr_funcs, &fid)) {
0622                 for (j = 0; j < funcs[fid].nr_groups; j++)
0623                     if (!funcs[fid].groups[j])
0624                         break;
0625                 funcs[fid].groups[j] = prop->value;
0626             }
0627             break;
0628 
0629         default:
0630             of_node_put(np);
0631             return -EINVAL;
0632         }
0633         i++;
0634     }
0635 
0636     return 0;
0637 }
0638 
0639 static int eqbr_build_functions(struct eqbr_pinctrl_drv_data *drvdata)
0640 {
0641     struct device *dev = drvdata->dev;
0642     struct eqbr_pmx_func *funcs = NULL;
0643     unsigned int nr_funcs = 0;
0644     int i, ret;
0645 
0646     ret = funcs_utils(dev, funcs, &nr_funcs, OP_COUNT_NR_FUNCS);
0647     if (ret)
0648         return ret;
0649 
0650     funcs = devm_kcalloc(dev, nr_funcs, sizeof(*funcs), GFP_KERNEL);
0651     if (!funcs)
0652         return -ENOMEM;
0653 
0654     ret = funcs_utils(dev, funcs, &nr_funcs, OP_ADD_FUNCS);
0655     if (ret)
0656         return ret;
0657 
0658     ret = funcs_utils(dev, funcs, &nr_funcs, OP_COUNT_NR_FUNC_GRPS);
0659     if (ret)
0660         return ret;
0661 
0662     for (i = 0; i < nr_funcs; i++) {
0663         if (!funcs[i].nr_groups)
0664             continue;
0665         funcs[i].groups = devm_kcalloc(dev, funcs[i].nr_groups,
0666                            sizeof(*(funcs[i].groups)),
0667                            GFP_KERNEL);
0668         if (!funcs[i].groups)
0669             return -ENOMEM;
0670     }
0671 
0672     ret = funcs_utils(dev, funcs, &nr_funcs, OP_ADD_FUNC_GRPS);
0673     if (ret)
0674         return ret;
0675 
0676     for (i = 0; i < nr_funcs; i++) {
0677 
0678         /* Ignore the same function with multiple groups */
0679         if (funcs[i].name == NULL)
0680             continue;
0681 
0682         ret = pinmux_generic_add_function(drvdata->pctl_dev,
0683                           funcs[i].name,
0684                           funcs[i].groups,
0685                           funcs[i].nr_groups,
0686                           drvdata);
0687         if (ret < 0) {
0688             dev_err(dev, "Failed to register function %s\n",
0689                 funcs[i].name);
0690             return ret;
0691         }
0692     }
0693 
0694     return 0;
0695 }
0696 
0697 static int eqbr_build_groups(struct eqbr_pinctrl_drv_data *drvdata)
0698 {
0699     struct device *dev = drvdata->dev;
0700     struct device_node *node = dev->of_node;
0701     unsigned int *pinmux, pin_id, pinmux_id;
0702     struct group_desc group;
0703     struct device_node *np;
0704     struct property *prop;
0705     int j, err;
0706 
0707     for_each_child_of_node(node, np) {
0708         prop = of_find_property(np, "groups", NULL);
0709         if (!prop)
0710             continue;
0711 
0712         group.num_pins = of_property_count_u32_elems(np, "pins");
0713         if (group.num_pins < 0) {
0714             dev_err(dev, "No pins in the group: %s\n", prop->name);
0715             of_node_put(np);
0716             return -EINVAL;
0717         }
0718         group.name = prop->value;
0719         group.pins = devm_kcalloc(dev, group.num_pins,
0720                       sizeof(*(group.pins)), GFP_KERNEL);
0721         if (!group.pins) {
0722             of_node_put(np);
0723             return -ENOMEM;
0724         }
0725 
0726         pinmux = devm_kcalloc(dev, group.num_pins, sizeof(*pinmux),
0727                       GFP_KERNEL);
0728         if (!pinmux) {
0729             of_node_put(np);
0730             return -ENOMEM;
0731         }
0732 
0733         for (j = 0; j < group.num_pins; j++) {
0734             if (of_property_read_u32_index(np, "pins", j, &pin_id)) {
0735                 dev_err(dev, "Group %s: Read intel pins id failed\n",
0736                     group.name);
0737                 of_node_put(np);
0738                 return -EINVAL;
0739             }
0740             if (pin_id >= drvdata->pctl_desc.npins) {
0741                 dev_err(dev, "Group %s: Invalid pin ID, idx: %d, pin %u\n",
0742                     group.name, j, pin_id);
0743                 of_node_put(np);
0744                 return -EINVAL;
0745             }
0746             group.pins[j] = pin_id;
0747             if (of_property_read_u32_index(np, "pinmux", j, &pinmux_id)) {
0748                 dev_err(dev, "Group %s: Read intel pinmux id failed\n",
0749                     group.name);
0750                 of_node_put(np);
0751                 return -EINVAL;
0752             }
0753             pinmux[j] = pinmux_id;
0754         }
0755 
0756         err = pinctrl_generic_add_group(drvdata->pctl_dev, group.name,
0757                         group.pins, group.num_pins,
0758                         pinmux);
0759         if (err < 0) {
0760             dev_err(dev, "Failed to register group %s\n", group.name);
0761             of_node_put(np);
0762             return err;
0763         }
0764         memset(&group, 0, sizeof(group));
0765         pinmux = NULL;
0766     }
0767 
0768     return 0;
0769 }
0770 
0771 static int pinctrl_reg(struct eqbr_pinctrl_drv_data *drvdata)
0772 {
0773     struct pinctrl_desc *pctl_desc;
0774     struct pinctrl_pin_desc *pdesc;
0775     struct device *dev;
0776     unsigned int nr_pins;
0777     char *pin_names;
0778     int i, ret;
0779 
0780     dev = drvdata->dev;
0781     pctl_desc = &drvdata->pctl_desc;
0782     pctl_desc->name = "eqbr-pinctrl";
0783     pctl_desc->owner = THIS_MODULE;
0784     pctl_desc->pctlops = &eqbr_pctl_ops;
0785     pctl_desc->pmxops = &eqbr_pinmux_ops;
0786     pctl_desc->confops = &eqbr_pinconf_ops;
0787     raw_spin_lock_init(&drvdata->lock);
0788 
0789     for (i = 0, nr_pins = 0; i < drvdata->nr_banks; i++)
0790         nr_pins += drvdata->pin_banks[i].nr_pins;
0791 
0792     pdesc = devm_kcalloc(dev, nr_pins, sizeof(*pdesc), GFP_KERNEL);
0793     if (!pdesc)
0794         return -ENOMEM;
0795     pin_names = devm_kcalloc(dev, nr_pins, PIN_NAME_LEN, GFP_KERNEL);
0796     if (!pin_names)
0797         return -ENOMEM;
0798 
0799     for (i = 0; i < nr_pins; i++) {
0800         sprintf(pin_names, PIN_NAME_FMT, i);
0801         pdesc[i].number = i;
0802         pdesc[i].name = pin_names;
0803         pin_names += PIN_NAME_LEN;
0804     }
0805     pctl_desc->pins = pdesc;
0806     pctl_desc->npins = nr_pins;
0807     dev_dbg(dev, "pinctrl total pin number: %u\n", nr_pins);
0808 
0809     ret = devm_pinctrl_register_and_init(dev, pctl_desc, drvdata,
0810                          &drvdata->pctl_dev);
0811     if (ret)
0812         return ret;
0813 
0814     ret = eqbr_build_groups(drvdata);
0815     if (ret) {
0816         dev_err(dev, "Failed to build groups\n");
0817         return ret;
0818     }
0819 
0820     ret = eqbr_build_functions(drvdata);
0821     if (ret) {
0822         dev_err(dev, "Failed to build functions\n");
0823         return ret;
0824     }
0825 
0826     return pinctrl_enable(drvdata->pctl_dev);
0827 }
0828 
0829 static int pinbank_init(struct device_node *np,
0830             struct eqbr_pinctrl_drv_data *drvdata,
0831             struct eqbr_pin_bank *bank, unsigned int id)
0832 {
0833     struct device *dev = drvdata->dev;
0834     struct of_phandle_args spec;
0835     int ret;
0836 
0837     bank->membase = drvdata->membase + id * PAD_REG_OFF;
0838 
0839     ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &spec);
0840     if (ret) {
0841         dev_err(dev, "gpio-range not available!\n");
0842         return ret;
0843     }
0844 
0845     bank->pin_base = spec.args[1];
0846     bank->nr_pins = spec.args[2];
0847 
0848     bank->aval_pinmap = readl(bank->membase + REG_AVAIL);
0849     bank->id = id;
0850 
0851     dev_dbg(dev, "pinbank id: %d, reg: %px, pinbase: %u, pin number: %u, pinmap: 0x%x\n",
0852         id, bank->membase, bank->pin_base,
0853         bank->nr_pins, bank->aval_pinmap);
0854 
0855     return ret;
0856 }
0857 
0858 static int pinbank_probe(struct eqbr_pinctrl_drv_data *drvdata)
0859 {
0860     struct device *dev = drvdata->dev;
0861     struct device_node *np_gpio;
0862     struct eqbr_gpio_ctrl *gctrls;
0863     struct eqbr_pin_bank *banks;
0864     int i, nr_gpio;
0865 
0866     /* Count gpio bank number */
0867     nr_gpio = 0;
0868     for_each_node_by_name(np_gpio, "gpio") {
0869         if (of_device_is_available(np_gpio))
0870             nr_gpio++;
0871     }
0872 
0873     if (!nr_gpio) {
0874         dev_err(dev, "NO pin bank available!\n");
0875         return -ENODEV;
0876     }
0877 
0878     /* Count pin bank number and gpio controller number */
0879     banks = devm_kcalloc(dev, nr_gpio, sizeof(*banks), GFP_KERNEL);
0880     if (!banks)
0881         return -ENOMEM;
0882 
0883     gctrls = devm_kcalloc(dev, nr_gpio, sizeof(*gctrls), GFP_KERNEL);
0884     if (!gctrls)
0885         return -ENOMEM;
0886 
0887     dev_dbg(dev, "found %d gpio controller!\n", nr_gpio);
0888 
0889     /* Initialize Pin bank */
0890     i = 0;
0891     for_each_node_by_name(np_gpio, "gpio") {
0892         if (!of_device_is_available(np_gpio))
0893             continue;
0894 
0895         pinbank_init(np_gpio, drvdata, banks + i, i);
0896 
0897         gctrls[i].fwnode = of_fwnode_handle(np_gpio);
0898         gctrls[i].bank = banks + i;
0899         i++;
0900     }
0901 
0902     drvdata->pin_banks = banks;
0903     drvdata->nr_banks = nr_gpio;
0904     drvdata->gpio_ctrls = gctrls;
0905     drvdata->nr_gpio_ctrls = nr_gpio;
0906 
0907     return 0;
0908 }
0909 
0910 static int eqbr_pinctrl_probe(struct platform_device *pdev)
0911 {
0912     struct eqbr_pinctrl_drv_data *drvdata;
0913     struct device *dev = &pdev->dev;
0914     int ret;
0915 
0916     drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
0917     if (!drvdata)
0918         return -ENOMEM;
0919 
0920     drvdata->dev = dev;
0921 
0922     drvdata->membase = devm_platform_ioremap_resource(pdev, 0);
0923     if (IS_ERR(drvdata->membase))
0924         return PTR_ERR(drvdata->membase);
0925 
0926     ret = pinbank_probe(drvdata);
0927     if (ret)
0928         return ret;
0929 
0930     ret = pinctrl_reg(drvdata);
0931     if (ret)
0932         return ret;
0933 
0934     ret = gpiolib_reg(drvdata);
0935     if (ret)
0936         return ret;
0937 
0938     platform_set_drvdata(pdev, drvdata);
0939     return 0;
0940 }
0941 
0942 static const struct of_device_id eqbr_pinctrl_dt_match[] = {
0943     { .compatible = "intel,lgm-io" },
0944     {}
0945 };
0946 MODULE_DEVICE_TABLE(of, eqbr_pinctrl_dt_match);
0947 
0948 static struct platform_driver eqbr_pinctrl_driver = {
0949     .probe  = eqbr_pinctrl_probe,
0950     .driver = {
0951         .name = "eqbr-pinctrl",
0952         .of_match_table = eqbr_pinctrl_dt_match,
0953     },
0954 };
0955 
0956 module_platform_driver(eqbr_pinctrl_driver);
0957 
0958 MODULE_AUTHOR("Zhu Yixin <yixin.zhu@intel.com>, Rahul Tanwar <rahul.tanwar@intel.com>");
0959 MODULE_DESCRIPTION("Pinctrl Driver for LGM SoC (Equilibrium)");
0960 MODULE_LICENSE("GPL v2");
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