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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * at91 pinctrl driver based on at91 pinmux core
0004  *
0005  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
0006  */
0007 
0008 #include <linux/clk.h>
0009 #include <linux/err.h>
0010 #include <linux/init.h>
0011 #include <linux/of.h>
0012 #include <linux/of_device.h>
0013 #include <linux/of_address.h>
0014 #include <linux/of_irq.h>
0015 #include <linux/slab.h>
0016 #include <linux/interrupt.h>
0017 #include <linux/io.h>
0018 #include <linux/gpio/driver.h>
0019 #include <linux/pinctrl/machine.h>
0020 #include <linux/pinctrl/pinconf.h>
0021 #include <linux/pinctrl/pinctrl.h>
0022 #include <linux/pinctrl/pinmux.h>
0023 /* Since we request GPIOs from ourself */
0024 #include <linux/pinctrl/consumer.h>
0025 
0026 #include <soc/at91/pm.h>
0027 
0028 #include "pinctrl-at91.h"
0029 #include "core.h"
0030 
0031 #define MAX_GPIO_BANKS      5
0032 #define MAX_NB_GPIO_PER_BANK    32
0033 
0034 struct at91_pinctrl_mux_ops;
0035 
0036 struct at91_gpio_chip {
0037     struct gpio_chip    chip;
0038     struct pinctrl_gpio_range range;
0039     struct at91_gpio_chip   *next;      /* Bank sharing same clock */
0040     int         pioc_hwirq; /* PIO bank interrupt identifier on AIC */
0041     int         pioc_virq;  /* PIO bank Linux virtual interrupt */
0042     int         pioc_idx;   /* PIO bank index */
0043     void __iomem        *regbase;   /* PIO bank virtual address */
0044     struct clk      *clock;     /* associated clock */
0045     const struct at91_pinctrl_mux_ops *ops; /* ops */
0046 };
0047 
0048 static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS];
0049 
0050 static int gpio_banks;
0051 
0052 #define PULL_UP     (1 << 0)
0053 #define MULTI_DRIVE (1 << 1)
0054 #define DEGLITCH    (1 << 2)
0055 #define PULL_DOWN   (1 << 3)
0056 #define DIS_SCHMIT  (1 << 4)
0057 #define DRIVE_STRENGTH_SHIFT    5
0058 #define DRIVE_STRENGTH_MASK     0x3
0059 #define DRIVE_STRENGTH   (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT)
0060 #define OUTPUT      (1 << 7)
0061 #define OUTPUT_VAL_SHIFT    8
0062 #define OUTPUT_VAL  (0x1 << OUTPUT_VAL_SHIFT)
0063 #define SLEWRATE_SHIFT  9
0064 #define SLEWRATE_MASK   0x1
0065 #define SLEWRATE    (SLEWRATE_MASK << SLEWRATE_SHIFT)
0066 #define DEBOUNCE    (1 << 16)
0067 #define DEBOUNCE_VAL_SHIFT  17
0068 #define DEBOUNCE_VAL    (0x3fff << DEBOUNCE_VAL_SHIFT)
0069 
0070 /*
0071  * These defines will translated the dt binding settings to our internal
0072  * settings. They are not necessarily the same value as the register setting.
0073  * The actual drive strength current of low, medium and high must be looked up
0074  * from the corresponding device datasheet. This value is different for pins
0075  * that are even in the same banks. It is also dependent on VCC.
0076  * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
0077  * strength when there is no dt config for it.
0078  */
0079 enum drive_strength_bit {
0080     DRIVE_STRENGTH_BIT_DEF,
0081     DRIVE_STRENGTH_BIT_LOW,
0082     DRIVE_STRENGTH_BIT_MED,
0083     DRIVE_STRENGTH_BIT_HI,
0084 };
0085 
0086 #define DRIVE_STRENGTH_BIT_MSK(name)    (DRIVE_STRENGTH_BIT_##name << \
0087                      DRIVE_STRENGTH_SHIFT)
0088 
0089 enum slewrate_bit {
0090     SLEWRATE_BIT_ENA,
0091     SLEWRATE_BIT_DIS,
0092 };
0093 
0094 #define SLEWRATE_BIT_MSK(name)      (SLEWRATE_BIT_##name << SLEWRATE_SHIFT)
0095 
0096 /**
0097  * struct at91_pmx_func - describes AT91 pinmux functions
0098  * @name: the name of this specific function
0099  * @groups: corresponding pin groups
0100  * @ngroups: the number of groups
0101  */
0102 struct at91_pmx_func {
0103     const char  *name;
0104     const char  **groups;
0105     unsigned    ngroups;
0106 };
0107 
0108 enum at91_mux {
0109     AT91_MUX_GPIO = 0,
0110     AT91_MUX_PERIPH_A = 1,
0111     AT91_MUX_PERIPH_B = 2,
0112     AT91_MUX_PERIPH_C = 3,
0113     AT91_MUX_PERIPH_D = 4,
0114 };
0115 
0116 /**
0117  * struct at91_pmx_pin - describes an At91 pin mux
0118  * @bank: the bank of the pin
0119  * @pin: the pin number in the @bank
0120  * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
0121  * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
0122  */
0123 struct at91_pmx_pin {
0124     uint32_t    bank;
0125     uint32_t    pin;
0126     enum at91_mux   mux;
0127     unsigned long   conf;
0128 };
0129 
0130 /**
0131  * struct at91_pin_group - describes an At91 pin group
0132  * @name: the name of this specific pin group
0133  * @pins_conf: the mux mode for each pin in this group. The size of this
0134  *  array is the same as pins.
0135  * @pins: an array of discrete physical pins used in this group, taken
0136  *  from the driver-local pin enumeration space
0137  * @npins: the number of pins in this group array, i.e. the number of
0138  *  elements in .pins so we can iterate over that array
0139  */
0140 struct at91_pin_group {
0141     const char      *name;
0142     struct at91_pmx_pin *pins_conf;
0143     unsigned int        *pins;
0144     unsigned        npins;
0145 };
0146 
0147 /**
0148  * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
0149  * on new IP with support for periph C and D the way to mux in
0150  * periph A and B has changed
0151  * So provide the right call back
0152  * if not present means the IP does not support it
0153  * @get_periph: return the periph mode configured
0154  * @mux_A_periph: mux as periph A
0155  * @mux_B_periph: mux as periph B
0156  * @mux_C_periph: mux as periph C
0157  * @mux_D_periph: mux as periph D
0158  * @get_deglitch: get deglitch status
0159  * @set_deglitch: enable/disable deglitch
0160  * @get_debounce: get debounce status
0161  * @set_debounce: enable/disable debounce
0162  * @get_pulldown: get pulldown status
0163  * @set_pulldown: enable/disable pulldown
0164  * @get_schmitt_trig: get schmitt trigger status
0165  * @disable_schmitt_trig: disable schmitt trigger
0166  * @get_drivestrength: get driver strength
0167  * @set_drivestrength: set driver strength
0168  * @get_slewrate: get slew rate
0169  * @set_slewrate: set slew rate
0170  * @irq_type: return irq type
0171  */
0172 struct at91_pinctrl_mux_ops {
0173     enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
0174     void (*mux_A_periph)(void __iomem *pio, unsigned mask);
0175     void (*mux_B_periph)(void __iomem *pio, unsigned mask);
0176     void (*mux_C_periph)(void __iomem *pio, unsigned mask);
0177     void (*mux_D_periph)(void __iomem *pio, unsigned mask);
0178     bool (*get_deglitch)(void __iomem *pio, unsigned pin);
0179     void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on);
0180     bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div);
0181     void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div);
0182     bool (*get_pulldown)(void __iomem *pio, unsigned pin);
0183     void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on);
0184     bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
0185     void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
0186     unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin);
0187     void (*set_drivestrength)(void __iomem *pio, unsigned pin,
0188                     u32 strength);
0189     unsigned (*get_slewrate)(void __iomem *pio, unsigned pin);
0190     void (*set_slewrate)(void __iomem *pio, unsigned pin, u32 slewrate);
0191     /* irq */
0192     int (*irq_type)(struct irq_data *d, unsigned type);
0193 };
0194 
0195 static int gpio_irq_type(struct irq_data *d, unsigned type);
0196 static int alt_gpio_irq_type(struct irq_data *d, unsigned type);
0197 
0198 struct at91_pinctrl {
0199     struct device       *dev;
0200     struct pinctrl_dev  *pctl;
0201 
0202     int         nactive_banks;
0203 
0204     uint32_t        *mux_mask;
0205     int         nmux;
0206 
0207     struct at91_pmx_func    *functions;
0208     int         nfunctions;
0209 
0210     struct at91_pin_group   *groups;
0211     int         ngroups;
0212 
0213     const struct at91_pinctrl_mux_ops *ops;
0214 };
0215 
0216 static inline const struct at91_pin_group *at91_pinctrl_find_group_by_name(
0217                 const struct at91_pinctrl *info,
0218                 const char *name)
0219 {
0220     const struct at91_pin_group *grp = NULL;
0221     int i;
0222 
0223     for (i = 0; i < info->ngroups; i++) {
0224         if (strcmp(info->groups[i].name, name))
0225             continue;
0226 
0227         grp = &info->groups[i];
0228         dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]);
0229         break;
0230     }
0231 
0232     return grp;
0233 }
0234 
0235 static int at91_get_groups_count(struct pinctrl_dev *pctldev)
0236 {
0237     struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
0238 
0239     return info->ngroups;
0240 }
0241 
0242 static const char *at91_get_group_name(struct pinctrl_dev *pctldev,
0243                        unsigned selector)
0244 {
0245     struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
0246 
0247     return info->groups[selector].name;
0248 }
0249 
0250 static int at91_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
0251                    const unsigned **pins,
0252                    unsigned *npins)
0253 {
0254     struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
0255 
0256     if (selector >= info->ngroups)
0257         return -EINVAL;
0258 
0259     *pins = info->groups[selector].pins;
0260     *npins = info->groups[selector].npins;
0261 
0262     return 0;
0263 }
0264 
0265 static void at91_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
0266            unsigned offset)
0267 {
0268     seq_printf(s, "%s", dev_name(pctldev->dev));
0269 }
0270 
0271 static int at91_dt_node_to_map(struct pinctrl_dev *pctldev,
0272             struct device_node *np,
0273             struct pinctrl_map **map, unsigned *num_maps)
0274 {
0275     struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
0276     const struct at91_pin_group *grp;
0277     struct pinctrl_map *new_map;
0278     struct device_node *parent;
0279     int map_num = 1;
0280     int i;
0281 
0282     /*
0283      * first find the group of this node and check if we need to create
0284      * config maps for pins
0285      */
0286     grp = at91_pinctrl_find_group_by_name(info, np->name);
0287     if (!grp) {
0288         dev_err(info->dev, "unable to find group for node %pOFn\n",
0289             np);
0290         return -EINVAL;
0291     }
0292 
0293     map_num += grp->npins;
0294     new_map = devm_kcalloc(pctldev->dev, map_num, sizeof(*new_map),
0295                    GFP_KERNEL);
0296     if (!new_map)
0297         return -ENOMEM;
0298 
0299     *map = new_map;
0300     *num_maps = map_num;
0301 
0302     /* create mux map */
0303     parent = of_get_parent(np);
0304     if (!parent) {
0305         devm_kfree(pctldev->dev, new_map);
0306         return -EINVAL;
0307     }
0308     new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
0309     new_map[0].data.mux.function = parent->name;
0310     new_map[0].data.mux.group = np->name;
0311     of_node_put(parent);
0312 
0313     /* create config map */
0314     new_map++;
0315     for (i = 0; i < grp->npins; i++) {
0316         new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
0317         new_map[i].data.configs.group_or_pin =
0318                 pin_get_name(pctldev, grp->pins[i]);
0319         new_map[i].data.configs.configs = &grp->pins_conf[i].conf;
0320         new_map[i].data.configs.num_configs = 1;
0321     }
0322 
0323     dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
0324         (*map)->data.mux.function, (*map)->data.mux.group, map_num);
0325 
0326     return 0;
0327 }
0328 
0329 static void at91_dt_free_map(struct pinctrl_dev *pctldev,
0330                 struct pinctrl_map *map, unsigned num_maps)
0331 {
0332 }
0333 
0334 static const struct pinctrl_ops at91_pctrl_ops = {
0335     .get_groups_count   = at91_get_groups_count,
0336     .get_group_name     = at91_get_group_name,
0337     .get_group_pins     = at91_get_group_pins,
0338     .pin_dbg_show       = at91_pin_dbg_show,
0339     .dt_node_to_map     = at91_dt_node_to_map,
0340     .dt_free_map        = at91_dt_free_map,
0341 };
0342 
0343 static void __iomem *pin_to_controller(struct at91_pinctrl *info,
0344                  unsigned int bank)
0345 {
0346     if (!gpio_chips[bank])
0347         return NULL;
0348 
0349     return gpio_chips[bank]->regbase;
0350 }
0351 
0352 static inline int pin_to_bank(unsigned pin)
0353 {
0354     return pin /= MAX_NB_GPIO_PER_BANK;
0355 }
0356 
0357 static unsigned pin_to_mask(unsigned int pin)
0358 {
0359     return 1 << pin;
0360 }
0361 
0362 static unsigned two_bit_pin_value_shift_amount(unsigned int pin)
0363 {
0364     /* return the shift value for a pin for "two bit" per pin registers,
0365      * i.e. drive strength */
0366     return 2*((pin >= MAX_NB_GPIO_PER_BANK/2)
0367             ? pin - MAX_NB_GPIO_PER_BANK/2 : pin);
0368 }
0369 
0370 static unsigned sama5d3_get_drive_register(unsigned int pin)
0371 {
0372     /* drive strength is split between two registers
0373      * with two bits per pin */
0374     return (pin >= MAX_NB_GPIO_PER_BANK/2)
0375             ? SAMA5D3_PIO_DRIVER2 : SAMA5D3_PIO_DRIVER1;
0376 }
0377 
0378 static unsigned at91sam9x5_get_drive_register(unsigned int pin)
0379 {
0380     /* drive strength is split between two registers
0381      * with two bits per pin */
0382     return (pin >= MAX_NB_GPIO_PER_BANK/2)
0383             ? AT91SAM9X5_PIO_DRIVER2 : AT91SAM9X5_PIO_DRIVER1;
0384 }
0385 
0386 static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
0387 {
0388     writel_relaxed(mask, pio + PIO_IDR);
0389 }
0390 
0391 static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin)
0392 {
0393     return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1);
0394 }
0395 
0396 static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
0397 {
0398     if (on)
0399         writel_relaxed(mask, pio + PIO_PPDDR);
0400 
0401     writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR));
0402 }
0403 
0404 static bool at91_mux_get_output(void __iomem *pio, unsigned int pin, bool *val)
0405 {
0406     *val = (readl_relaxed(pio + PIO_ODSR) >> pin) & 0x1;
0407     return (readl_relaxed(pio + PIO_OSR) >> pin) & 0x1;
0408 }
0409 
0410 static void at91_mux_set_output(void __iomem *pio, unsigned int mask,
0411                 bool is_on, bool val)
0412 {
0413     writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
0414     writel_relaxed(mask, pio + (is_on ? PIO_OER : PIO_ODR));
0415 }
0416 
0417 static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin)
0418 {
0419     return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1;
0420 }
0421 
0422 static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on)
0423 {
0424     writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR));
0425 }
0426 
0427 static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
0428 {
0429     writel_relaxed(mask, pio + PIO_ASR);
0430 }
0431 
0432 static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
0433 {
0434     writel_relaxed(mask, pio + PIO_BSR);
0435 }
0436 
0437 static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask)
0438 {
0439 
0440     writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask,
0441                         pio + PIO_ABCDSR1);
0442     writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
0443                         pio + PIO_ABCDSR2);
0444 }
0445 
0446 static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask)
0447 {
0448     writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask,
0449                         pio + PIO_ABCDSR1);
0450     writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask,
0451                         pio + PIO_ABCDSR2);
0452 }
0453 
0454 static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask)
0455 {
0456     writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
0457     writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
0458 }
0459 
0460 static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask)
0461 {
0462     writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
0463     writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
0464 }
0465 
0466 static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask)
0467 {
0468     unsigned select;
0469 
0470     if (readl_relaxed(pio + PIO_PSR) & mask)
0471         return AT91_MUX_GPIO;
0472 
0473     select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask);
0474     select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1);
0475 
0476     return select + 1;
0477 }
0478 
0479 static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask)
0480 {
0481     unsigned select;
0482 
0483     if (readl_relaxed(pio + PIO_PSR) & mask)
0484         return AT91_MUX_GPIO;
0485 
0486     select = readl_relaxed(pio + PIO_ABSR) & mask;
0487 
0488     return select + 1;
0489 }
0490 
0491 static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin)
0492 {
0493     return (readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1;
0494 }
0495 
0496 static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
0497 {
0498     writel_relaxed(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
0499 }
0500 
0501 static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin)
0502 {
0503     if ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1)
0504         return !((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1);
0505 
0506     return false;
0507 }
0508 
0509 static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
0510 {
0511     if (is_on)
0512         writel_relaxed(mask, pio + PIO_IFSCDR);
0513     at91_mux_set_deglitch(pio, mask, is_on);
0514 }
0515 
0516 static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div)
0517 {
0518     *div = readl_relaxed(pio + PIO_SCDR);
0519 
0520     return ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) &&
0521            ((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1);
0522 }
0523 
0524 static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
0525                 bool is_on, u32 div)
0526 {
0527     if (is_on) {
0528         writel_relaxed(mask, pio + PIO_IFSCER);
0529         writel_relaxed(div & PIO_SCDR_DIV, pio + PIO_SCDR);
0530         writel_relaxed(mask, pio + PIO_IFER);
0531     } else
0532         writel_relaxed(mask, pio + PIO_IFSCDR);
0533 }
0534 
0535 static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin)
0536 {
0537     return !((readl_relaxed(pio + PIO_PPDSR) >> pin) & 0x1);
0538 }
0539 
0540 static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
0541 {
0542     if (is_on)
0543         writel_relaxed(mask, pio + PIO_PUDR);
0544 
0545     writel_relaxed(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
0546 }
0547 
0548 static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask)
0549 {
0550     writel_relaxed(readl_relaxed(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
0551 }
0552 
0553 static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin)
0554 {
0555     return (readl_relaxed(pio + PIO_SCHMITT) >> pin) & 0x1;
0556 }
0557 
0558 static inline u32 read_drive_strength(void __iomem *reg, unsigned pin)
0559 {
0560     unsigned tmp = readl_relaxed(reg);
0561 
0562     tmp = tmp >> two_bit_pin_value_shift_amount(pin);
0563 
0564     return tmp & DRIVE_STRENGTH_MASK;
0565 }
0566 
0567 static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio,
0568                             unsigned pin)
0569 {
0570     unsigned tmp = read_drive_strength(pio +
0571                     sama5d3_get_drive_register(pin), pin);
0572 
0573     /* SAMA5 strength is 1:1 with our defines,
0574      * except 0 is equivalent to low per datasheet */
0575     if (!tmp)
0576         tmp = DRIVE_STRENGTH_BIT_MSK(LOW);
0577 
0578     return tmp;
0579 }
0580 
0581 static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
0582                             unsigned pin)
0583 {
0584     unsigned tmp = read_drive_strength(pio +
0585                 at91sam9x5_get_drive_register(pin), pin);
0586 
0587     /* strength is inverse in SAM9x5s hardware with the pinctrl defines
0588      * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
0589     tmp = DRIVE_STRENGTH_BIT_MSK(HI) - tmp;
0590 
0591     return tmp;
0592 }
0593 
0594 static unsigned at91_mux_sam9x60_get_drivestrength(void __iomem *pio,
0595                            unsigned pin)
0596 {
0597     unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1);
0598 
0599     if (tmp & BIT(pin))
0600         return DRIVE_STRENGTH_BIT_HI;
0601 
0602     return DRIVE_STRENGTH_BIT_LOW;
0603 }
0604 
0605 static unsigned at91_mux_sam9x60_get_slewrate(void __iomem *pio, unsigned pin)
0606 {
0607     unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR);
0608 
0609     if ((tmp & BIT(pin)))
0610         return SLEWRATE_BIT_ENA;
0611 
0612     return SLEWRATE_BIT_DIS;
0613 }
0614 
0615 static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength)
0616 {
0617     unsigned tmp = readl_relaxed(reg);
0618     unsigned shift = two_bit_pin_value_shift_amount(pin);
0619 
0620     tmp &= ~(DRIVE_STRENGTH_MASK  <<  shift);
0621     tmp |= strength << shift;
0622 
0623     writel_relaxed(tmp, reg);
0624 }
0625 
0626 static void at91_mux_sama5d3_set_drivestrength(void __iomem *pio, unsigned pin,
0627                         u32 setting)
0628 {
0629     /* do nothing if setting is zero */
0630     if (!setting)
0631         return;
0632 
0633     /* strength is 1 to 1 with setting for SAMA5 */
0634     set_drive_strength(pio + sama5d3_get_drive_register(pin), pin, setting);
0635 }
0636 
0637 static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
0638                         u32 setting)
0639 {
0640     /* do nothing if setting is zero */
0641     if (!setting)
0642         return;
0643 
0644     /* strength is inverse on SAM9x5s with our defines
0645      * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
0646     setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting;
0647 
0648     set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin,
0649                 setting);
0650 }
0651 
0652 static void at91_mux_sam9x60_set_drivestrength(void __iomem *pio, unsigned pin,
0653                            u32 setting)
0654 {
0655     unsigned int tmp;
0656 
0657     if (setting <= DRIVE_STRENGTH_BIT_DEF ||
0658         setting == DRIVE_STRENGTH_BIT_MED ||
0659         setting > DRIVE_STRENGTH_BIT_HI)
0660         return;
0661 
0662     tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1);
0663 
0664     /* Strength is 0: low, 1: hi */
0665     if (setting == DRIVE_STRENGTH_BIT_LOW)
0666         tmp &= ~BIT(pin);
0667     else
0668         tmp |= BIT(pin);
0669 
0670     writel_relaxed(tmp, pio + SAM9X60_PIO_DRIVER1);
0671 }
0672 
0673 static void at91_mux_sam9x60_set_slewrate(void __iomem *pio, unsigned pin,
0674                       u32 setting)
0675 {
0676     unsigned int tmp;
0677 
0678     if (setting < SLEWRATE_BIT_ENA || setting > SLEWRATE_BIT_DIS)
0679         return;
0680 
0681     tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR);
0682 
0683     if (setting == SLEWRATE_BIT_DIS)
0684         tmp &= ~BIT(pin);
0685     else
0686         tmp |= BIT(pin);
0687 
0688     writel_relaxed(tmp, pio + SAM9X60_PIO_SLEWR);
0689 }
0690 
0691 static const struct at91_pinctrl_mux_ops at91rm9200_ops = {
0692     .get_periph = at91_mux_get_periph,
0693     .mux_A_periph   = at91_mux_set_A_periph,
0694     .mux_B_periph   = at91_mux_set_B_periph,
0695     .get_deglitch   = at91_mux_get_deglitch,
0696     .set_deglitch   = at91_mux_set_deglitch,
0697     .irq_type   = gpio_irq_type,
0698 };
0699 
0700 static const struct at91_pinctrl_mux_ops at91sam9x5_ops = {
0701     .get_periph = at91_mux_pio3_get_periph,
0702     .mux_A_periph   = at91_mux_pio3_set_A_periph,
0703     .mux_B_periph   = at91_mux_pio3_set_B_periph,
0704     .mux_C_periph   = at91_mux_pio3_set_C_periph,
0705     .mux_D_periph   = at91_mux_pio3_set_D_periph,
0706     .get_deglitch   = at91_mux_pio3_get_deglitch,
0707     .set_deglitch   = at91_mux_pio3_set_deglitch,
0708     .get_debounce   = at91_mux_pio3_get_debounce,
0709     .set_debounce   = at91_mux_pio3_set_debounce,
0710     .get_pulldown   = at91_mux_pio3_get_pulldown,
0711     .set_pulldown   = at91_mux_pio3_set_pulldown,
0712     .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
0713     .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
0714     .get_drivestrength = at91_mux_sam9x5_get_drivestrength,
0715     .set_drivestrength = at91_mux_sam9x5_set_drivestrength,
0716     .irq_type   = alt_gpio_irq_type,
0717 };
0718 
0719 static const struct at91_pinctrl_mux_ops sam9x60_ops = {
0720     .get_periph = at91_mux_pio3_get_periph,
0721     .mux_A_periph   = at91_mux_pio3_set_A_periph,
0722     .mux_B_periph   = at91_mux_pio3_set_B_periph,
0723     .mux_C_periph   = at91_mux_pio3_set_C_periph,
0724     .mux_D_periph   = at91_mux_pio3_set_D_periph,
0725     .get_deglitch   = at91_mux_pio3_get_deglitch,
0726     .set_deglitch   = at91_mux_pio3_set_deglitch,
0727     .get_debounce   = at91_mux_pio3_get_debounce,
0728     .set_debounce   = at91_mux_pio3_set_debounce,
0729     .get_pulldown   = at91_mux_pio3_get_pulldown,
0730     .set_pulldown   = at91_mux_pio3_set_pulldown,
0731     .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
0732     .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
0733     .get_drivestrength = at91_mux_sam9x60_get_drivestrength,
0734     .set_drivestrength = at91_mux_sam9x60_set_drivestrength,
0735     .get_slewrate   = at91_mux_sam9x60_get_slewrate,
0736     .set_slewrate   = at91_mux_sam9x60_set_slewrate,
0737     .irq_type   = alt_gpio_irq_type,
0738 };
0739 
0740 static const struct at91_pinctrl_mux_ops sama5d3_ops = {
0741     .get_periph = at91_mux_pio3_get_periph,
0742     .mux_A_periph   = at91_mux_pio3_set_A_periph,
0743     .mux_B_periph   = at91_mux_pio3_set_B_periph,
0744     .mux_C_periph   = at91_mux_pio3_set_C_periph,
0745     .mux_D_periph   = at91_mux_pio3_set_D_periph,
0746     .get_deglitch   = at91_mux_pio3_get_deglitch,
0747     .set_deglitch   = at91_mux_pio3_set_deglitch,
0748     .get_debounce   = at91_mux_pio3_get_debounce,
0749     .set_debounce   = at91_mux_pio3_set_debounce,
0750     .get_pulldown   = at91_mux_pio3_get_pulldown,
0751     .set_pulldown   = at91_mux_pio3_set_pulldown,
0752     .get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
0753     .disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
0754     .get_drivestrength = at91_mux_sama5d3_get_drivestrength,
0755     .set_drivestrength = at91_mux_sama5d3_set_drivestrength,
0756     .irq_type   = alt_gpio_irq_type,
0757 };
0758 
0759 static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin)
0760 {
0761     if (pin->mux) {
0762         dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lx\n",
0763             pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf);
0764     } else {
0765         dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lx\n",
0766             pin->bank + 'A', pin->pin, pin->conf);
0767     }
0768 }
0769 
0770 static int pin_check_config(struct at91_pinctrl *info, const char *name,
0771                 int index, const struct at91_pmx_pin *pin)
0772 {
0773     int mux;
0774 
0775     /* check if it's a valid config */
0776     if (pin->bank >= gpio_banks) {
0777         dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",
0778             name, index, pin->bank, gpio_banks);
0779         return -EINVAL;
0780     }
0781 
0782     if (!gpio_chips[pin->bank]) {
0783         dev_err(info->dev, "%s: pin conf %d bank_id %d not enabled\n",
0784             name, index, pin->bank);
0785         return -ENXIO;
0786     }
0787 
0788     if (pin->pin >= MAX_NB_GPIO_PER_BANK) {
0789         dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n",
0790             name, index, pin->pin, MAX_NB_GPIO_PER_BANK);
0791         return -EINVAL;
0792     }
0793 
0794     if (!pin->mux)
0795         return 0;
0796 
0797     mux = pin->mux - 1;
0798 
0799     if (mux >= info->nmux) {
0800         dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n",
0801             name, index, mux, info->nmux);
0802         return -EINVAL;
0803     }
0804 
0805     if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) {
0806         dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n",
0807             name, index, mux, pin->bank + 'A', pin->pin);
0808         return -EINVAL;
0809     }
0810 
0811     return 0;
0812 }
0813 
0814 static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
0815 {
0816     writel_relaxed(mask, pio + PIO_PDR);
0817 }
0818 
0819 static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input)
0820 {
0821     writel_relaxed(mask, pio + PIO_PER);
0822     writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER));
0823 }
0824 
0825 static int at91_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
0826             unsigned group)
0827 {
0828     struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
0829     const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
0830     const struct at91_pmx_pin *pin;
0831     uint32_t npins = info->groups[group].npins;
0832     int i, ret;
0833     unsigned mask;
0834     void __iomem *pio;
0835 
0836     dev_dbg(info->dev, "enable function %s group %s\n",
0837         info->functions[selector].name, info->groups[group].name);
0838 
0839     /* first check that all the pins of the group are valid with a valid
0840      * parameter */
0841     for (i = 0; i < npins; i++) {
0842         pin = &pins_conf[i];
0843         ret = pin_check_config(info, info->groups[group].name, i, pin);
0844         if (ret)
0845             return ret;
0846     }
0847 
0848     for (i = 0; i < npins; i++) {
0849         pin = &pins_conf[i];
0850         at91_pin_dbg(info->dev, pin);
0851         pio = pin_to_controller(info, pin->bank);
0852 
0853         if (!pio)
0854             continue;
0855 
0856         mask = pin_to_mask(pin->pin);
0857         at91_mux_disable_interrupt(pio, mask);
0858         switch (pin->mux) {
0859         case AT91_MUX_GPIO:
0860             at91_mux_gpio_enable(pio, mask, 1);
0861             break;
0862         case AT91_MUX_PERIPH_A:
0863             info->ops->mux_A_periph(pio, mask);
0864             break;
0865         case AT91_MUX_PERIPH_B:
0866             info->ops->mux_B_periph(pio, mask);
0867             break;
0868         case AT91_MUX_PERIPH_C:
0869             if (!info->ops->mux_C_periph)
0870                 return -EINVAL;
0871             info->ops->mux_C_periph(pio, mask);
0872             break;
0873         case AT91_MUX_PERIPH_D:
0874             if (!info->ops->mux_D_periph)
0875                 return -EINVAL;
0876             info->ops->mux_D_periph(pio, mask);
0877             break;
0878         }
0879         if (pin->mux)
0880             at91_mux_gpio_disable(pio, mask);
0881     }
0882 
0883     return 0;
0884 }
0885 
0886 static int at91_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
0887 {
0888     struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
0889 
0890     return info->nfunctions;
0891 }
0892 
0893 static const char *at91_pmx_get_func_name(struct pinctrl_dev *pctldev,
0894                       unsigned selector)
0895 {
0896     struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
0897 
0898     return info->functions[selector].name;
0899 }
0900 
0901 static int at91_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
0902                    const char * const **groups,
0903                    unsigned * const num_groups)
0904 {
0905     struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
0906 
0907     *groups = info->functions[selector].groups;
0908     *num_groups = info->functions[selector].ngroups;
0909 
0910     return 0;
0911 }
0912 
0913 static int at91_gpio_request_enable(struct pinctrl_dev *pctldev,
0914                     struct pinctrl_gpio_range *range,
0915                     unsigned offset)
0916 {
0917     struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
0918     struct at91_gpio_chip *at91_chip;
0919     struct gpio_chip *chip;
0920     unsigned mask;
0921 
0922     if (!range) {
0923         dev_err(npct->dev, "invalid range\n");
0924         return -EINVAL;
0925     }
0926     if (!range->gc) {
0927         dev_err(npct->dev, "missing GPIO chip in range\n");
0928         return -EINVAL;
0929     }
0930     chip = range->gc;
0931     at91_chip = gpiochip_get_data(chip);
0932 
0933     dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
0934 
0935     mask = 1 << (offset - chip->base);
0936 
0937     dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n",
0938         offset, 'A' + range->id, offset - chip->base, mask);
0939 
0940     writel_relaxed(mask, at91_chip->regbase + PIO_PER);
0941 
0942     return 0;
0943 }
0944 
0945 static void at91_gpio_disable_free(struct pinctrl_dev *pctldev,
0946                    struct pinctrl_gpio_range *range,
0947                    unsigned offset)
0948 {
0949     struct at91_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
0950 
0951     dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
0952     /* Set the pin to some default state, GPIO is usually default */
0953 }
0954 
0955 static const struct pinmux_ops at91_pmx_ops = {
0956     .get_functions_count    = at91_pmx_get_funcs_count,
0957     .get_function_name  = at91_pmx_get_func_name,
0958     .get_function_groups    = at91_pmx_get_groups,
0959     .set_mux        = at91_pmx_set,
0960     .gpio_request_enable    = at91_gpio_request_enable,
0961     .gpio_disable_free  = at91_gpio_disable_free,
0962 };
0963 
0964 static int at91_pinconf_get(struct pinctrl_dev *pctldev,
0965                  unsigned pin_id, unsigned long *config)
0966 {
0967     struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
0968     void __iomem *pio;
0969     unsigned pin;
0970     int div;
0971     bool out;
0972 
0973     *config = 0;
0974     dev_dbg(info->dev, "%s:%d, pin_id=%d", __func__, __LINE__, pin_id);
0975     pio = pin_to_controller(info, pin_to_bank(pin_id));
0976 
0977     if (!pio)
0978         return -EINVAL;
0979 
0980     pin = pin_id % MAX_NB_GPIO_PER_BANK;
0981 
0982     if (at91_mux_get_multidrive(pio, pin))
0983         *config |= MULTI_DRIVE;
0984 
0985     if (at91_mux_get_pullup(pio, pin))
0986         *config |= PULL_UP;
0987 
0988     if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin))
0989         *config |= DEGLITCH;
0990     if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div))
0991         *config |= DEBOUNCE | (div << DEBOUNCE_VAL_SHIFT);
0992     if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin))
0993         *config |= PULL_DOWN;
0994     if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin))
0995         *config |= DIS_SCHMIT;
0996     if (info->ops->get_drivestrength)
0997         *config |= (info->ops->get_drivestrength(pio, pin)
0998                 << DRIVE_STRENGTH_SHIFT);
0999     if (info->ops->get_slewrate)
1000         *config |= (info->ops->get_slewrate(pio, pin) << SLEWRATE_SHIFT);
1001     if (at91_mux_get_output(pio, pin, &out))
1002         *config |= OUTPUT | (out << OUTPUT_VAL_SHIFT);
1003 
1004     return 0;
1005 }
1006 
1007 static int at91_pinconf_set(struct pinctrl_dev *pctldev,
1008                  unsigned pin_id, unsigned long *configs,
1009                  unsigned num_configs)
1010 {
1011     struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1012     unsigned mask;
1013     void __iomem *pio;
1014     int i;
1015     unsigned long config;
1016     unsigned pin;
1017 
1018     for (i = 0; i < num_configs; i++) {
1019         config = configs[i];
1020 
1021         dev_dbg(info->dev,
1022             "%s:%d, pin_id=%d, config=0x%lx",
1023             __func__, __LINE__, pin_id, config);
1024         pio = pin_to_controller(info, pin_to_bank(pin_id));
1025 
1026         if (!pio)
1027             return -EINVAL;
1028 
1029         pin = pin_id % MAX_NB_GPIO_PER_BANK;
1030         mask = pin_to_mask(pin);
1031 
1032         if (config & PULL_UP && config & PULL_DOWN)
1033             return -EINVAL;
1034 
1035         at91_mux_set_output(pio, mask, config & OUTPUT,
1036                     (config & OUTPUT_VAL) >> OUTPUT_VAL_SHIFT);
1037         at91_mux_set_pullup(pio, mask, config & PULL_UP);
1038         at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE);
1039         if (info->ops->set_deglitch)
1040             info->ops->set_deglitch(pio, mask, config & DEGLITCH);
1041         if (info->ops->set_debounce)
1042             info->ops->set_debounce(pio, mask, config & DEBOUNCE,
1043                 (config & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT);
1044         if (info->ops->set_pulldown)
1045             info->ops->set_pulldown(pio, mask, config & PULL_DOWN);
1046         if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT)
1047             info->ops->disable_schmitt_trig(pio, mask);
1048         if (info->ops->set_drivestrength)
1049             info->ops->set_drivestrength(pio, pin,
1050                 (config & DRIVE_STRENGTH)
1051                     >> DRIVE_STRENGTH_SHIFT);
1052         if (info->ops->set_slewrate)
1053             info->ops->set_slewrate(pio, pin,
1054                 (config & SLEWRATE) >> SLEWRATE_SHIFT);
1055 
1056     } /* for each config */
1057 
1058     return 0;
1059 }
1060 
1061 #define DBG_SHOW_FLAG(flag) do {        \
1062     if (config & flag) {            \
1063         if (num_conf)           \
1064             seq_puts(s, "|");   \
1065         seq_puts(s, #flag);     \
1066         num_conf++;         \
1067     }                   \
1068 } while (0)
1069 
1070 #define DBG_SHOW_FLAG_MASKED(mask, flag, name) do { \
1071     if ((config & mask) == flag) {      \
1072         if (num_conf)           \
1073             seq_puts(s, "|");   \
1074         seq_puts(s, #name);     \
1075         num_conf++;         \
1076     }                   \
1077 } while (0)
1078 
1079 static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
1080                    struct seq_file *s, unsigned pin_id)
1081 {
1082     unsigned long config;
1083     int val, num_conf = 0;
1084 
1085     at91_pinconf_get(pctldev, pin_id, &config);
1086 
1087     DBG_SHOW_FLAG(MULTI_DRIVE);
1088     DBG_SHOW_FLAG(PULL_UP);
1089     DBG_SHOW_FLAG(PULL_DOWN);
1090     DBG_SHOW_FLAG(DIS_SCHMIT);
1091     DBG_SHOW_FLAG(DEGLITCH);
1092     DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(LOW),
1093                  DRIVE_STRENGTH_LOW);
1094     DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(MED),
1095                  DRIVE_STRENGTH_MED);
1096     DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(HI),
1097                  DRIVE_STRENGTH_HI);
1098     DBG_SHOW_FLAG(SLEWRATE);
1099     DBG_SHOW_FLAG(DEBOUNCE);
1100     if (config & DEBOUNCE) {
1101         val = config >> DEBOUNCE_VAL_SHIFT;
1102         seq_printf(s, "(%d)", val);
1103     }
1104 
1105     return;
1106 }
1107 
1108 static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
1109                      struct seq_file *s, unsigned group)
1110 {
1111 }
1112 
1113 static const struct pinconf_ops at91_pinconf_ops = {
1114     .pin_config_get         = at91_pinconf_get,
1115     .pin_config_set         = at91_pinconf_set,
1116     .pin_config_dbg_show        = at91_pinconf_dbg_show,
1117     .pin_config_group_dbg_show  = at91_pinconf_group_dbg_show,
1118 };
1119 
1120 static struct pinctrl_desc at91_pinctrl_desc = {
1121     .pctlops    = &at91_pctrl_ops,
1122     .pmxops     = &at91_pmx_ops,
1123     .confops    = &at91_pinconf_ops,
1124     .owner      = THIS_MODULE,
1125 };
1126 
1127 static const char *gpio_compat = "atmel,at91rm9200-gpio";
1128 
1129 static void at91_pinctrl_child_count(struct at91_pinctrl *info,
1130                      struct device_node *np)
1131 {
1132     struct device_node *child;
1133 
1134     for_each_child_of_node(np, child) {
1135         if (of_device_is_compatible(child, gpio_compat)) {
1136             if (of_device_is_available(child))
1137                 info->nactive_banks++;
1138         } else {
1139             info->nfunctions++;
1140             info->ngroups += of_get_child_count(child);
1141         }
1142     }
1143 }
1144 
1145 static int at91_pinctrl_mux_mask(struct at91_pinctrl *info,
1146                  struct device_node *np)
1147 {
1148     int ret = 0;
1149     int size;
1150     const __be32 *list;
1151 
1152     list = of_get_property(np, "atmel,mux-mask", &size);
1153     if (!list) {
1154         dev_err(info->dev, "can not read the mux-mask of %d\n", size);
1155         return -EINVAL;
1156     }
1157 
1158     size /= sizeof(*list);
1159     if (!size || size % gpio_banks) {
1160         dev_err(info->dev, "wrong mux mask array should be by %d\n", gpio_banks);
1161         return -EINVAL;
1162     }
1163     info->nmux = size / gpio_banks;
1164 
1165     info->mux_mask = devm_kcalloc(info->dev, size, sizeof(u32),
1166                       GFP_KERNEL);
1167     if (!info->mux_mask)
1168         return -ENOMEM;
1169 
1170     ret = of_property_read_u32_array(np, "atmel,mux-mask",
1171                       info->mux_mask, size);
1172     if (ret)
1173         dev_err(info->dev, "can not read the mux-mask of %d\n", size);
1174     return ret;
1175 }
1176 
1177 static int at91_pinctrl_parse_groups(struct device_node *np,
1178                      struct at91_pin_group *grp,
1179                      struct at91_pinctrl *info, u32 index)
1180 {
1181     struct at91_pmx_pin *pin;
1182     int size;
1183     const __be32 *list;
1184     int i, j;
1185 
1186     dev_dbg(info->dev, "group(%d): %pOFn\n", index, np);
1187 
1188     /* Initialise group */
1189     grp->name = np->name;
1190 
1191     /*
1192      * the binding format is atmel,pins = <bank pin mux CONFIG ...>,
1193      * do sanity check and calculate pins number
1194      */
1195     list = of_get_property(np, "atmel,pins", &size);
1196     /* we do not check return since it's safe node passed down */
1197     size /= sizeof(*list);
1198     if (!size || size % 4) {
1199         dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
1200         return -EINVAL;
1201     }
1202 
1203     grp->npins = size / 4;
1204     pin = grp->pins_conf = devm_kcalloc(info->dev,
1205                         grp->npins,
1206                         sizeof(struct at91_pmx_pin),
1207                         GFP_KERNEL);
1208     grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int),
1209                  GFP_KERNEL);
1210     if (!grp->pins_conf || !grp->pins)
1211         return -ENOMEM;
1212 
1213     for (i = 0, j = 0; i < size; i += 4, j++) {
1214         pin->bank = be32_to_cpu(*list++);
1215         pin->pin = be32_to_cpu(*list++);
1216         grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin;
1217         pin->mux = be32_to_cpu(*list++);
1218         pin->conf = be32_to_cpu(*list++);
1219 
1220         at91_pin_dbg(info->dev, pin);
1221         pin++;
1222     }
1223 
1224     return 0;
1225 }
1226 
1227 static int at91_pinctrl_parse_functions(struct device_node *np,
1228                     struct at91_pinctrl *info, u32 index)
1229 {
1230     struct device_node *child;
1231     struct at91_pmx_func *func;
1232     struct at91_pin_group *grp;
1233     int ret;
1234     static u32 grp_index;
1235     u32 i = 0;
1236 
1237     dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np);
1238 
1239     func = &info->functions[index];
1240 
1241     /* Initialise function */
1242     func->name = np->name;
1243     func->ngroups = of_get_child_count(np);
1244     if (func->ngroups == 0) {
1245         dev_err(info->dev, "no groups defined\n");
1246         return -EINVAL;
1247     }
1248     func->groups = devm_kcalloc(info->dev,
1249             func->ngroups, sizeof(char *), GFP_KERNEL);
1250     if (!func->groups)
1251         return -ENOMEM;
1252 
1253     for_each_child_of_node(np, child) {
1254         func->groups[i] = child->name;
1255         grp = &info->groups[grp_index++];
1256         ret = at91_pinctrl_parse_groups(child, grp, info, i++);
1257         if (ret) {
1258             of_node_put(child);
1259             return ret;
1260         }
1261     }
1262 
1263     return 0;
1264 }
1265 
1266 static const struct of_device_id at91_pinctrl_of_match[] = {
1267     { .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops },
1268     { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
1269     { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
1270     { .compatible = "microchip,sam9x60-pinctrl", .data = &sam9x60_ops },
1271     { /* sentinel */ }
1272 };
1273 
1274 static int at91_pinctrl_probe_dt(struct platform_device *pdev,
1275                  struct at91_pinctrl *info)
1276 {
1277     int ret = 0;
1278     int i, j;
1279     uint32_t *tmp;
1280     struct device_node *np = pdev->dev.of_node;
1281     struct device_node *child;
1282 
1283     if (!np)
1284         return -ENODEV;
1285 
1286     info->dev = &pdev->dev;
1287     info->ops = (const struct at91_pinctrl_mux_ops *)
1288         of_match_device(at91_pinctrl_of_match, &pdev->dev)->data;
1289     at91_pinctrl_child_count(info, np);
1290 
1291     if (gpio_banks < 1) {
1292         dev_err(&pdev->dev, "you need to specify at least one gpio-controller\n");
1293         return -EINVAL;
1294     }
1295 
1296     ret = at91_pinctrl_mux_mask(info, np);
1297     if (ret)
1298         return ret;
1299 
1300     dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux);
1301 
1302     dev_dbg(&pdev->dev, "mux-mask\n");
1303     tmp = info->mux_mask;
1304     for (i = 0; i < gpio_banks; i++) {
1305         for (j = 0; j < info->nmux; j++, tmp++) {
1306             dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]);
1307         }
1308     }
1309 
1310     dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1311     dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1312     info->functions = devm_kcalloc(&pdev->dev,
1313                     info->nfunctions,
1314                     sizeof(struct at91_pmx_func),
1315                     GFP_KERNEL);
1316     if (!info->functions)
1317         return -ENOMEM;
1318 
1319     info->groups = devm_kcalloc(&pdev->dev,
1320                     info->ngroups,
1321                     sizeof(struct at91_pin_group),
1322                     GFP_KERNEL);
1323     if (!info->groups)
1324         return -ENOMEM;
1325 
1326     dev_dbg(&pdev->dev, "nbanks = %d\n", gpio_banks);
1327     dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1328     dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1329 
1330     i = 0;
1331 
1332     for_each_child_of_node(np, child) {
1333         if (of_device_is_compatible(child, gpio_compat))
1334             continue;
1335         ret = at91_pinctrl_parse_functions(child, info, i++);
1336         if (ret) {
1337             dev_err(&pdev->dev, "failed to parse function\n");
1338             of_node_put(child);
1339             return ret;
1340         }
1341     }
1342 
1343     return 0;
1344 }
1345 
1346 static int at91_pinctrl_probe(struct platform_device *pdev)
1347 {
1348     struct at91_pinctrl *info;
1349     struct pinctrl_pin_desc *pdesc;
1350     int ret, i, j, k, ngpio_chips_enabled = 0;
1351 
1352     info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
1353     if (!info)
1354         return -ENOMEM;
1355 
1356     ret = at91_pinctrl_probe_dt(pdev, info);
1357     if (ret)
1358         return ret;
1359 
1360     /*
1361      * We need all the GPIO drivers to probe FIRST, or we will not be able
1362      * to obtain references to the struct gpio_chip * for them, and we
1363      * need this to proceed.
1364      */
1365     for (i = 0; i < gpio_banks; i++)
1366         if (gpio_chips[i])
1367             ngpio_chips_enabled++;
1368 
1369     if (ngpio_chips_enabled < info->nactive_banks) {
1370         dev_warn(&pdev->dev,
1371              "All GPIO chips are not registered yet (%d/%d)\n",
1372              ngpio_chips_enabled, info->nactive_banks);
1373         devm_kfree(&pdev->dev, info);
1374         return -EPROBE_DEFER;
1375     }
1376 
1377     at91_pinctrl_desc.name = dev_name(&pdev->dev);
1378     at91_pinctrl_desc.npins = gpio_banks * MAX_NB_GPIO_PER_BANK;
1379     at91_pinctrl_desc.pins = pdesc =
1380         devm_kcalloc(&pdev->dev,
1381                  at91_pinctrl_desc.npins, sizeof(*pdesc),
1382                  GFP_KERNEL);
1383 
1384     if (!at91_pinctrl_desc.pins)
1385         return -ENOMEM;
1386 
1387     for (i = 0, k = 0; i < gpio_banks; i++) {
1388         for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) {
1389             pdesc->number = k;
1390             pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j);
1391             pdesc++;
1392         }
1393     }
1394 
1395     platform_set_drvdata(pdev, info);
1396     info->pctl = devm_pinctrl_register(&pdev->dev, &at91_pinctrl_desc,
1397                        info);
1398 
1399     if (IS_ERR(info->pctl)) {
1400         dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n");
1401         return PTR_ERR(info->pctl);
1402     }
1403 
1404     /* We will handle a range of GPIO pins */
1405     for (i = 0; i < gpio_banks; i++)
1406         if (gpio_chips[i])
1407             pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range);
1408 
1409     dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n");
1410 
1411     return 0;
1412 }
1413 
1414 static int at91_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1415 {
1416     struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1417     void __iomem *pio = at91_gpio->regbase;
1418     unsigned mask = 1 << offset;
1419     u32 osr;
1420 
1421     osr = readl_relaxed(pio + PIO_OSR);
1422     if (osr & mask)
1423         return GPIO_LINE_DIRECTION_OUT;
1424 
1425     return GPIO_LINE_DIRECTION_IN;
1426 }
1427 
1428 static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1429 {
1430     struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1431     void __iomem *pio = at91_gpio->regbase;
1432     unsigned mask = 1 << offset;
1433 
1434     writel_relaxed(mask, pio + PIO_ODR);
1435     return 0;
1436 }
1437 
1438 static int at91_gpio_get(struct gpio_chip *chip, unsigned offset)
1439 {
1440     struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1441     void __iomem *pio = at91_gpio->regbase;
1442     unsigned mask = 1 << offset;
1443     u32 pdsr;
1444 
1445     pdsr = readl_relaxed(pio + PIO_PDSR);
1446     return (pdsr & mask) != 0;
1447 }
1448 
1449 static void at91_gpio_set(struct gpio_chip *chip, unsigned offset,
1450                 int val)
1451 {
1452     struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1453     void __iomem *pio = at91_gpio->regbase;
1454     unsigned mask = 1 << offset;
1455 
1456     writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1457 }
1458 
1459 static void at91_gpio_set_multiple(struct gpio_chip *chip,
1460                       unsigned long *mask, unsigned long *bits)
1461 {
1462     struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1463     void __iomem *pio = at91_gpio->regbase;
1464 
1465 #define BITS_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1))
1466     /* Mask additionally to ngpio as not all GPIO controllers have 32 pins */
1467     uint32_t set_mask = (*mask & *bits) & BITS_MASK(chip->ngpio);
1468     uint32_t clear_mask = (*mask & ~(*bits)) & BITS_MASK(chip->ngpio);
1469 
1470     writel_relaxed(set_mask, pio + PIO_SODR);
1471     writel_relaxed(clear_mask, pio + PIO_CODR);
1472 }
1473 
1474 static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
1475                 int val)
1476 {
1477     struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1478     void __iomem *pio = at91_gpio->regbase;
1479     unsigned mask = 1 << offset;
1480 
1481     writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
1482     writel_relaxed(mask, pio + PIO_OER);
1483 
1484     return 0;
1485 }
1486 
1487 #ifdef CONFIG_DEBUG_FS
1488 static void at91_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1489 {
1490     enum at91_mux mode;
1491     int i;
1492     struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
1493     void __iomem *pio = at91_gpio->regbase;
1494     const char *gpio_label;
1495 
1496     for_each_requested_gpio(chip, i, gpio_label) {
1497         unsigned mask = pin_to_mask(i);
1498 
1499         mode = at91_gpio->ops->get_periph(pio, mask);
1500         seq_printf(s, "[%s] GPIO%s%d: ",
1501                gpio_label, chip->label, i);
1502         if (mode == AT91_MUX_GPIO) {
1503             seq_printf(s, "[gpio] ");
1504             seq_printf(s, "%s ",
1505                       readl_relaxed(pio + PIO_OSR) & mask ?
1506                       "output" : "input");
1507             seq_printf(s, "%s\n",
1508                       readl_relaxed(pio + PIO_PDSR) & mask ?
1509                       "set" : "clear");
1510         } else {
1511             seq_printf(s, "[periph %c]\n",
1512                    mode + 'A' - 1);
1513         }
1514     }
1515 }
1516 #else
1517 #define at91_gpio_dbg_show  NULL
1518 #endif
1519 
1520 /* Several AIC controller irqs are dispatched through this GPIO handler.
1521  * To use any AT91_PIN_* as an externally triggered IRQ, first call
1522  * at91_set_gpio_input() then maybe enable its glitch filter.
1523  * Then just request_irq() with the pin ID; it works like any ARM IRQ
1524  * handler.
1525  * First implementation always triggers on rising and falling edges
1526  * whereas the newer PIO3 can be additionally configured to trigger on
1527  * level, edge with any polarity.
1528  *
1529  * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
1530  * configuring them with at91_set_a_periph() or at91_set_b_periph().
1531  * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
1532  */
1533 
1534 static void gpio_irq_mask(struct irq_data *d)
1535 {
1536     struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1537     void __iomem    *pio = at91_gpio->regbase;
1538     unsigned    mask = 1 << d->hwirq;
1539 
1540     if (pio)
1541         writel_relaxed(mask, pio + PIO_IDR);
1542 }
1543 
1544 static void gpio_irq_unmask(struct irq_data *d)
1545 {
1546     struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1547     void __iomem    *pio = at91_gpio->regbase;
1548     unsigned    mask = 1 << d->hwirq;
1549 
1550     if (pio)
1551         writel_relaxed(mask, pio + PIO_IER);
1552 }
1553 
1554 static int gpio_irq_type(struct irq_data *d, unsigned type)
1555 {
1556     switch (type) {
1557     case IRQ_TYPE_NONE:
1558     case IRQ_TYPE_EDGE_BOTH:
1559         return 0;
1560     default:
1561         return -EINVAL;
1562     }
1563 }
1564 
1565 /* Alternate irq type for PIO3 support */
1566 static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
1567 {
1568     struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1569     void __iomem    *pio = at91_gpio->regbase;
1570     unsigned    mask = 1 << d->hwirq;
1571 
1572     switch (type) {
1573     case IRQ_TYPE_EDGE_RISING:
1574         irq_set_handler_locked(d, handle_simple_irq);
1575         writel_relaxed(mask, pio + PIO_ESR);
1576         writel_relaxed(mask, pio + PIO_REHLSR);
1577         break;
1578     case IRQ_TYPE_EDGE_FALLING:
1579         irq_set_handler_locked(d, handle_simple_irq);
1580         writel_relaxed(mask, pio + PIO_ESR);
1581         writel_relaxed(mask, pio + PIO_FELLSR);
1582         break;
1583     case IRQ_TYPE_LEVEL_LOW:
1584         irq_set_handler_locked(d, handle_level_irq);
1585         writel_relaxed(mask, pio + PIO_LSR);
1586         writel_relaxed(mask, pio + PIO_FELLSR);
1587         break;
1588     case IRQ_TYPE_LEVEL_HIGH:
1589         irq_set_handler_locked(d, handle_level_irq);
1590         writel_relaxed(mask, pio + PIO_LSR);
1591         writel_relaxed(mask, pio + PIO_REHLSR);
1592         break;
1593     case IRQ_TYPE_EDGE_BOTH:
1594         /*
1595          * disable additional interrupt modes:
1596          * fall back to default behavior
1597          */
1598         irq_set_handler_locked(d, handle_simple_irq);
1599         writel_relaxed(mask, pio + PIO_AIMDR);
1600         return 0;
1601     case IRQ_TYPE_NONE:
1602     default:
1603         pr_warn("AT91: No type for GPIO irq offset %d\n", d->irq);
1604         return -EINVAL;
1605     }
1606 
1607     /* enable additional interrupt modes */
1608     writel_relaxed(mask, pio + PIO_AIMER);
1609 
1610     return 0;
1611 }
1612 
1613 static void gpio_irq_ack(struct irq_data *d)
1614 {
1615     /* the interrupt is already cleared before by reading ISR */
1616 }
1617 
1618 static u32 wakeups[MAX_GPIO_BANKS];
1619 static u32 backups[MAX_GPIO_BANKS];
1620 
1621 static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
1622 {
1623     struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1624     unsigned    bank = at91_gpio->pioc_idx;
1625     unsigned mask = 1 << d->hwirq;
1626 
1627     if (unlikely(bank >= MAX_GPIO_BANKS))
1628         return -EINVAL;
1629 
1630     if (state)
1631         wakeups[bank] |= mask;
1632     else
1633         wakeups[bank] &= ~mask;
1634 
1635     irq_set_irq_wake(at91_gpio->pioc_virq, state);
1636 
1637     return 0;
1638 }
1639 
1640 void at91_pinctrl_gpio_suspend(void)
1641 {
1642     int i;
1643 
1644     for (i = 0; i < gpio_banks; i++) {
1645         void __iomem  *pio;
1646 
1647         if (!gpio_chips[i])
1648             continue;
1649 
1650         pio = gpio_chips[i]->regbase;
1651 
1652         backups[i] = readl_relaxed(pio + PIO_IMR);
1653         writel_relaxed(backups[i], pio + PIO_IDR);
1654         writel_relaxed(wakeups[i], pio + PIO_IER);
1655 
1656         if (!wakeups[i])
1657             clk_disable_unprepare(gpio_chips[i]->clock);
1658         else
1659             printk(KERN_DEBUG "GPIO-%c may wake for %08x\n",
1660                    'A'+i, wakeups[i]);
1661     }
1662 }
1663 
1664 void at91_pinctrl_gpio_resume(void)
1665 {
1666     int i;
1667 
1668     for (i = 0; i < gpio_banks; i++) {
1669         void __iomem  *pio;
1670 
1671         if (!gpio_chips[i])
1672             continue;
1673 
1674         pio = gpio_chips[i]->regbase;
1675 
1676         if (!wakeups[i])
1677             clk_prepare_enable(gpio_chips[i]->clock);
1678 
1679         writel_relaxed(wakeups[i], pio + PIO_IDR);
1680         writel_relaxed(backups[i], pio + PIO_IER);
1681     }
1682 }
1683 
1684 static void gpio_irq_handler(struct irq_desc *desc)
1685 {
1686     struct irq_chip *chip = irq_desc_get_chip(desc);
1687     struct gpio_chip *gpio_chip = irq_desc_get_handler_data(desc);
1688     struct at91_gpio_chip *at91_gpio = gpiochip_get_data(gpio_chip);
1689     void __iomem    *pio = at91_gpio->regbase;
1690     unsigned long   isr;
1691     int     n;
1692 
1693     chained_irq_enter(chip, desc);
1694     for (;;) {
1695         /* Reading ISR acks pending (edge triggered) GPIO interrupts.
1696          * When there are none pending, we're finished unless we need
1697          * to process multiple banks (like ID_PIOCDE on sam9263).
1698          */
1699         isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR);
1700         if (!isr) {
1701             if (!at91_gpio->next)
1702                 break;
1703             at91_gpio = at91_gpio->next;
1704             pio = at91_gpio->regbase;
1705             gpio_chip = &at91_gpio->chip;
1706             continue;
1707         }
1708 
1709         for_each_set_bit(n, &isr, BITS_PER_LONG)
1710             generic_handle_domain_irq(gpio_chip->irq.domain, n);
1711     }
1712     chained_irq_exit(chip, desc);
1713     /* now it may re-trigger */
1714 }
1715 
1716 static int at91_gpio_of_irq_setup(struct platform_device *pdev,
1717                   struct at91_gpio_chip *at91_gpio)
1718 {
1719     struct gpio_chip    *gpiochip_prev = NULL;
1720     struct at91_gpio_chip   *prev = NULL;
1721     struct irq_data     *d = irq_get_irq_data(at91_gpio->pioc_virq);
1722     struct irq_chip     *gpio_irqchip;
1723     struct gpio_irq_chip    *girq;
1724     int i;
1725 
1726     gpio_irqchip = devm_kzalloc(&pdev->dev, sizeof(*gpio_irqchip),
1727                     GFP_KERNEL);
1728     if (!gpio_irqchip)
1729         return -ENOMEM;
1730 
1731     at91_gpio->pioc_hwirq = irqd_to_hwirq(d);
1732 
1733     gpio_irqchip->name = "GPIO";
1734     gpio_irqchip->irq_ack = gpio_irq_ack;
1735     gpio_irqchip->irq_disable = gpio_irq_mask;
1736     gpio_irqchip->irq_mask = gpio_irq_mask;
1737     gpio_irqchip->irq_unmask = gpio_irq_unmask;
1738     gpio_irqchip->irq_set_wake = pm_ptr(gpio_irq_set_wake);
1739     gpio_irqchip->irq_set_type = at91_gpio->ops->irq_type;
1740 
1741     /* Disable irqs of this PIO controller */
1742     writel_relaxed(~0, at91_gpio->regbase + PIO_IDR);
1743 
1744     /*
1745      * Let the generic code handle this edge IRQ, the chained
1746      * handler will perform the actual work of handling the parent
1747      * interrupt.
1748      */
1749     girq = &at91_gpio->chip.irq;
1750     girq->chip = gpio_irqchip;
1751     girq->default_type = IRQ_TYPE_NONE;
1752     girq->handler = handle_edge_irq;
1753 
1754     /*
1755      * The top level handler handles one bank of GPIOs, except
1756      * on some SoC it can handle up to three...
1757      * We only set up the handler for the first of the list.
1758      */
1759     gpiochip_prev = irq_get_handler_data(at91_gpio->pioc_virq);
1760     if (!gpiochip_prev) {
1761         girq->parent_handler = gpio_irq_handler;
1762         girq->num_parents = 1;
1763         girq->parents = devm_kcalloc(&pdev->dev, 1,
1764                          sizeof(*girq->parents),
1765                          GFP_KERNEL);
1766         if (!girq->parents)
1767             return -ENOMEM;
1768         girq->parents[0] = at91_gpio->pioc_virq;
1769         return 0;
1770     }
1771 
1772     prev = gpiochip_get_data(gpiochip_prev);
1773     /* we can only have 2 banks before */
1774     for (i = 0; i < 2; i++) {
1775         if (prev->next) {
1776             prev = prev->next;
1777         } else {
1778             prev->next = at91_gpio;
1779             return 0;
1780         }
1781     }
1782 
1783     return -EINVAL;
1784 }
1785 
1786 /* This structure is replicated for each GPIO block allocated at probe time */
1787 static const struct gpio_chip at91_gpio_template = {
1788     .request        = gpiochip_generic_request,
1789     .free           = gpiochip_generic_free,
1790     .get_direction      = at91_gpio_get_direction,
1791     .direction_input    = at91_gpio_direction_input,
1792     .get            = at91_gpio_get,
1793     .direction_output   = at91_gpio_direction_output,
1794     .set            = at91_gpio_set,
1795     .set_multiple       = at91_gpio_set_multiple,
1796     .dbg_show       = at91_gpio_dbg_show,
1797     .can_sleep      = false,
1798     .ngpio          = MAX_NB_GPIO_PER_BANK,
1799 };
1800 
1801 static const struct of_device_id at91_gpio_of_match[] = {
1802     { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
1803     { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
1804     { .compatible = "microchip,sam9x60-gpio", .data = &sam9x60_ops },
1805     { /* sentinel */ }
1806 };
1807 
1808 static int at91_gpio_probe(struct platform_device *pdev)
1809 {
1810     struct device_node *np = pdev->dev.of_node;
1811     struct at91_gpio_chip *at91_chip = NULL;
1812     struct gpio_chip *chip;
1813     struct pinctrl_gpio_range *range;
1814     int ret = 0;
1815     int irq, i;
1816     int alias_idx = of_alias_get_id(np, "gpio");
1817     uint32_t ngpio;
1818     char **names;
1819 
1820     BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips));
1821     if (gpio_chips[alias_idx]) {
1822         ret = -EBUSY;
1823         goto err;
1824     }
1825 
1826     irq = platform_get_irq(pdev, 0);
1827     if (irq < 0) {
1828         ret = irq;
1829         goto err;
1830     }
1831 
1832     at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL);
1833     if (!at91_chip) {
1834         ret = -ENOMEM;
1835         goto err;
1836     }
1837 
1838     at91_chip->regbase = devm_platform_ioremap_resource(pdev, 0);
1839     if (IS_ERR(at91_chip->regbase)) {
1840         ret = PTR_ERR(at91_chip->regbase);
1841         goto err;
1842     }
1843 
1844     at91_chip->ops = (const struct at91_pinctrl_mux_ops *)
1845         of_match_device(at91_gpio_of_match, &pdev->dev)->data;
1846     at91_chip->pioc_virq = irq;
1847     at91_chip->pioc_idx = alias_idx;
1848 
1849     at91_chip->clock = devm_clk_get(&pdev->dev, NULL);
1850     if (IS_ERR(at91_chip->clock)) {
1851         dev_err(&pdev->dev, "failed to get clock, ignoring.\n");
1852         ret = PTR_ERR(at91_chip->clock);
1853         goto err;
1854     }
1855 
1856     ret = clk_prepare_enable(at91_chip->clock);
1857     if (ret) {
1858         dev_err(&pdev->dev, "failed to prepare and enable clock, ignoring.\n");
1859         goto clk_enable_err;
1860     }
1861 
1862     at91_chip->chip = at91_gpio_template;
1863 
1864     chip = &at91_chip->chip;
1865     chip->label = dev_name(&pdev->dev);
1866     chip->parent = &pdev->dev;
1867     chip->owner = THIS_MODULE;
1868     chip->base = alias_idx * MAX_NB_GPIO_PER_BANK;
1869 
1870     if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) {
1871         if (ngpio >= MAX_NB_GPIO_PER_BANK)
1872             pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n",
1873                    alias_idx, MAX_NB_GPIO_PER_BANK, MAX_NB_GPIO_PER_BANK);
1874         else
1875             chip->ngpio = ngpio;
1876     }
1877 
1878     names = devm_kcalloc(&pdev->dev, chip->ngpio, sizeof(char *),
1879                  GFP_KERNEL);
1880 
1881     if (!names) {
1882         ret = -ENOMEM;
1883         goto clk_enable_err;
1884     }
1885 
1886     for (i = 0; i < chip->ngpio; i++)
1887         names[i] = kasprintf(GFP_KERNEL, "pio%c%d", alias_idx + 'A', i);
1888 
1889     chip->names = (const char *const *)names;
1890 
1891     range = &at91_chip->range;
1892     range->name = chip->label;
1893     range->id = alias_idx;
1894     range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK;
1895 
1896     range->npins = chip->ngpio;
1897     range->gc = chip;
1898 
1899     ret = at91_gpio_of_irq_setup(pdev, at91_chip);
1900     if (ret)
1901         goto gpiochip_add_err;
1902 
1903     ret = gpiochip_add_data(chip, at91_chip);
1904     if (ret)
1905         goto gpiochip_add_err;
1906 
1907     gpio_chips[alias_idx] = at91_chip;
1908     gpio_banks = max(gpio_banks, alias_idx + 1);
1909 
1910     dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase);
1911 
1912     return 0;
1913 
1914 gpiochip_add_err:
1915 clk_enable_err:
1916     clk_disable_unprepare(at91_chip->clock);
1917 err:
1918     dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx);
1919 
1920     return ret;
1921 }
1922 
1923 static struct platform_driver at91_gpio_driver = {
1924     .driver = {
1925         .name = "gpio-at91",
1926         .of_match_table = at91_gpio_of_match,
1927     },
1928     .probe = at91_gpio_probe,
1929 };
1930 
1931 static struct platform_driver at91_pinctrl_driver = {
1932     .driver = {
1933         .name = "pinctrl-at91",
1934         .of_match_table = at91_pinctrl_of_match,
1935     },
1936     .probe = at91_pinctrl_probe,
1937 };
1938 
1939 static struct platform_driver * const drivers[] = {
1940     &at91_gpio_driver,
1941     &at91_pinctrl_driver,
1942 };
1943 
1944 static int __init at91_pinctrl_init(void)
1945 {
1946     return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
1947 }
1948 arch_initcall(at91_pinctrl_init);
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