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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Driver for the Atmel PIO4 controller
0004  *
0005  * Copyright (C) 2015 Atmel,
0006  *               2015 Ludovic Desroches <ludovic.desroches@atmel.com>
0007  */
0008 
0009 #include <dt-bindings/pinctrl/at91.h>
0010 #include <linux/clk.h>
0011 #include <linux/gpio/driver.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/io.h>
0014 #include <linux/init.h>
0015 #include <linux/of.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/pinctrl/pinconf.h>
0018 #include <linux/pinctrl/pinconf-generic.h>
0019 #include <linux/pinctrl/pinctrl.h>
0020 #include <linux/pinctrl/pinmux.h>
0021 #include <linux/slab.h>
0022 #include "core.h"
0023 #include "pinconf.h"
0024 #include "pinctrl-utils.h"
0025 
0026 /*
0027  * Warning:
0028  * In order to not introduce confusion between Atmel PIO groups and pinctrl
0029  * framework groups, Atmel PIO groups will be called banks, line is kept to
0030  * designed the pin id into this bank.
0031  */
0032 
0033 #define ATMEL_PIO_MSKR      0x0000
0034 #define ATMEL_PIO_CFGR      0x0004
0035 #define     ATMEL_PIO_CFGR_FUNC_MASK    GENMASK(2, 0)
0036 #define     ATMEL_PIO_DIR_MASK      BIT(8)
0037 #define     ATMEL_PIO_PUEN_MASK     BIT(9)
0038 #define     ATMEL_PIO_PDEN_MASK     BIT(10)
0039 #define     ATMEL_PIO_SR_MASK       BIT(11)
0040 #define     ATMEL_PIO_IFEN_MASK     BIT(12)
0041 #define     ATMEL_PIO_IFSCEN_MASK       BIT(13)
0042 #define     ATMEL_PIO_OPD_MASK      BIT(14)
0043 #define     ATMEL_PIO_SCHMITT_MASK      BIT(15)
0044 #define     ATMEL_PIO_DRVSTR_MASK       GENMASK(17, 16)
0045 #define     ATMEL_PIO_DRVSTR_OFFSET     16
0046 #define     ATMEL_PIO_CFGR_EVTSEL_MASK  GENMASK(26, 24)
0047 #define     ATMEL_PIO_CFGR_EVTSEL_FALLING   (0 << 24)
0048 #define     ATMEL_PIO_CFGR_EVTSEL_RISING    (1 << 24)
0049 #define     ATMEL_PIO_CFGR_EVTSEL_BOTH  (2 << 24)
0050 #define     ATMEL_PIO_CFGR_EVTSEL_LOW   (3 << 24)
0051 #define     ATMEL_PIO_CFGR_EVTSEL_HIGH  (4 << 24)
0052 #define ATMEL_PIO_PDSR      0x0008
0053 #define ATMEL_PIO_LOCKSR    0x000C
0054 #define ATMEL_PIO_SODR      0x0010
0055 #define ATMEL_PIO_CODR      0x0014
0056 #define ATMEL_PIO_ODSR      0x0018
0057 #define ATMEL_PIO_IER       0x0020
0058 #define ATMEL_PIO_IDR       0x0024
0059 #define ATMEL_PIO_IMR       0x0028
0060 #define ATMEL_PIO_ISR       0x002C
0061 #define ATMEL_PIO_IOFR      0x003C
0062 
0063 #define ATMEL_PIO_NPINS_PER_BANK    32
0064 #define ATMEL_PIO_BANK(pin_id)      (pin_id / ATMEL_PIO_NPINS_PER_BANK)
0065 #define ATMEL_PIO_LINE(pin_id)      (pin_id % ATMEL_PIO_NPINS_PER_BANK)
0066 #define ATMEL_PIO_BANK_OFFSET       0x40
0067 
0068 #define ATMEL_GET_PIN_NO(pinfunc)   ((pinfunc) & 0xff)
0069 #define ATMEL_GET_PIN_FUNC(pinfunc) ((pinfunc >> 16) & 0xf)
0070 #define ATMEL_GET_PIN_IOSET(pinfunc)    ((pinfunc >> 20) & 0xf)
0071 
0072 /* Custom pinconf parameters */
0073 #define ATMEL_PIN_CONFIG_DRIVE_STRENGTH (PIN_CONFIG_END + 1)
0074 
0075 /**
0076  * struct atmel_pioctrl_data - Atmel PIO controller (pinmux + gpio) data struct
0077  * @nbanks: number of PIO banks
0078  * @last_bank_count: number of lines in the last bank (can be less than
0079  *  the rest of the banks).
0080  * @slew_rate_support: slew rate support
0081  */
0082 struct atmel_pioctrl_data {
0083     unsigned int nbanks;
0084     unsigned int last_bank_count;
0085     unsigned int slew_rate_support;
0086 };
0087 
0088 struct atmel_group {
0089     const char *name;
0090     u32 pin;
0091 };
0092 
0093 struct atmel_pin {
0094     unsigned int pin_id;
0095     unsigned int mux;
0096     unsigned int ioset;
0097     unsigned int bank;
0098     unsigned int line;
0099     const char *device;
0100 };
0101 
0102 /**
0103  * struct atmel_pioctrl - Atmel PIO controller (pinmux + gpio)
0104  * @reg_base: base address of the controller.
0105  * @clk: clock of the controller.
0106  * @nbanks: number of PIO groups, it can vary depending on the SoC.
0107  * @pinctrl_dev: pinctrl device registered.
0108  * @groups: groups table to provide group name and pin in the group to pinctrl.
0109  * @group_names: group names table to provide all the group/pin names to
0110  *     pinctrl or gpio.
0111  * @pins: pins table used for both pinctrl and gpio. pin_id, bank and line
0112  *     fields are set at probe time. Other ones are set when parsing dt
0113  *     pinctrl.
0114  * @npins: number of pins.
0115  * @gpio_chip: gpio chip registered.
0116  * @irq_domain: irq domain for the gpio controller.
0117  * @irqs: table containing the hw irq number of the bank. The index of the
0118  *     table is the bank id.
0119  * @pm_wakeup_sources: bitmap of wakeup sources (lines)
0120  * @pm_suspend_backup: backup/restore register values on suspend/resume
0121  * @dev: device entry for the Atmel PIO controller.
0122  * @node: node of the Atmel PIO controller.
0123  * @slew_rate_support: slew rate support
0124  */
0125 struct atmel_pioctrl {
0126     void __iomem        *reg_base;
0127     struct clk      *clk;
0128     unsigned int        nbanks;
0129     struct pinctrl_dev  *pinctrl_dev;
0130     struct atmel_group  *groups;
0131     const char * const  *group_names;
0132     struct atmel_pin    **pins;
0133     unsigned int        npins;
0134     struct gpio_chip    *gpio_chip;
0135     struct irq_domain   *irq_domain;
0136     int         *irqs;
0137     unsigned int        *pm_wakeup_sources;
0138     struct {
0139         u32     imr;
0140         u32     odsr;
0141         u32     cfgr[ATMEL_PIO_NPINS_PER_BANK];
0142     } *pm_suspend_backup;
0143     struct device       *dev;
0144     struct device_node  *node;
0145     unsigned int        slew_rate_support;
0146 };
0147 
0148 static const char * const atmel_functions[] = {
0149     "GPIO", "A", "B", "C", "D", "E", "F", "G"
0150 };
0151 
0152 static const struct pinconf_generic_params atmel_custom_bindings[] = {
0153     {"atmel,drive-strength", ATMEL_PIN_CONFIG_DRIVE_STRENGTH, 0},
0154 };
0155 
0156 /* --- GPIO --- */
0157 static unsigned int atmel_gpio_read(struct atmel_pioctrl *atmel_pioctrl,
0158                     unsigned int bank, unsigned int reg)
0159 {
0160     return readl_relaxed(atmel_pioctrl->reg_base
0161                  + ATMEL_PIO_BANK_OFFSET * bank + reg);
0162 }
0163 
0164 static void atmel_gpio_write(struct atmel_pioctrl *atmel_pioctrl,
0165                  unsigned int bank, unsigned int reg,
0166                  unsigned int val)
0167 {
0168     writel_relaxed(val, atmel_pioctrl->reg_base
0169                + ATMEL_PIO_BANK_OFFSET * bank + reg);
0170 }
0171 
0172 static void atmel_gpio_irq_ack(struct irq_data *d)
0173 {
0174     /*
0175      * Nothing to do, interrupt is cleared when reading the status
0176      * register.
0177      */
0178 }
0179 
0180 static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned int type)
0181 {
0182     struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
0183     struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
0184     unsigned int reg;
0185 
0186     atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
0187              BIT(pin->line));
0188     reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
0189     reg &= (~ATMEL_PIO_CFGR_EVTSEL_MASK);
0190 
0191     switch (type) {
0192     case IRQ_TYPE_EDGE_RISING:
0193         irq_set_handler_locked(d, handle_edge_irq);
0194         reg |= ATMEL_PIO_CFGR_EVTSEL_RISING;
0195         break;
0196     case IRQ_TYPE_EDGE_FALLING:
0197         irq_set_handler_locked(d, handle_edge_irq);
0198         reg |= ATMEL_PIO_CFGR_EVTSEL_FALLING;
0199         break;
0200     case IRQ_TYPE_EDGE_BOTH:
0201         irq_set_handler_locked(d, handle_edge_irq);
0202         reg |= ATMEL_PIO_CFGR_EVTSEL_BOTH;
0203         break;
0204     case IRQ_TYPE_LEVEL_LOW:
0205         irq_set_handler_locked(d, handle_level_irq);
0206         reg |= ATMEL_PIO_CFGR_EVTSEL_LOW;
0207         break;
0208     case IRQ_TYPE_LEVEL_HIGH:
0209         irq_set_handler_locked(d, handle_level_irq);
0210         reg |= ATMEL_PIO_CFGR_EVTSEL_HIGH;
0211         break;
0212     case IRQ_TYPE_NONE:
0213     default:
0214         return -EINVAL;
0215     }
0216 
0217     atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
0218 
0219     return 0;
0220 }
0221 
0222 static void atmel_gpio_irq_mask(struct irq_data *d)
0223 {
0224     struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
0225     struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
0226 
0227     atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IDR,
0228              BIT(pin->line));
0229 }
0230 
0231 static void atmel_gpio_irq_unmask(struct irq_data *d)
0232 {
0233     struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
0234     struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
0235 
0236     atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_IER,
0237              BIT(pin->line));
0238 }
0239 
0240 static int atmel_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
0241 {
0242     struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
0243     int bank = ATMEL_PIO_BANK(d->hwirq);
0244     int line = ATMEL_PIO_LINE(d->hwirq);
0245 
0246     /* The gpio controller has one interrupt line per bank. */
0247     irq_set_irq_wake(atmel_pioctrl->irqs[bank], on);
0248 
0249     if (on)
0250         atmel_pioctrl->pm_wakeup_sources[bank] |= BIT(line);
0251     else
0252         atmel_pioctrl->pm_wakeup_sources[bank] &= ~(BIT(line));
0253 
0254     return 0;
0255 }
0256 
0257 static struct irq_chip atmel_gpio_irq_chip = {
0258     .name       = "GPIO",
0259     .irq_ack    = atmel_gpio_irq_ack,
0260     .irq_mask   = atmel_gpio_irq_mask,
0261     .irq_unmask = atmel_gpio_irq_unmask,
0262     .irq_set_type   = atmel_gpio_irq_set_type,
0263     .irq_set_wake   = pm_sleep_ptr(atmel_gpio_irq_set_wake),
0264 };
0265 
0266 static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
0267 {
0268     struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
0269 
0270     return irq_find_mapping(atmel_pioctrl->irq_domain, offset);
0271 }
0272 
0273 static void atmel_gpio_irq_handler(struct irq_desc *desc)
0274 {
0275     unsigned int irq = irq_desc_get_irq(desc);
0276     struct atmel_pioctrl *atmel_pioctrl = irq_desc_get_handler_data(desc);
0277     struct irq_chip *chip = irq_desc_get_chip(desc);
0278     unsigned long isr;
0279     int n, bank = -1;
0280 
0281     /* Find from which bank is the irq received. */
0282     for (n = 0; n < atmel_pioctrl->nbanks; n++) {
0283         if (atmel_pioctrl->irqs[n] == irq) {
0284             bank = n;
0285             break;
0286         }
0287     }
0288 
0289     if (bank < 0) {
0290         dev_err(atmel_pioctrl->dev,
0291             "no bank associated to irq %u\n", irq);
0292         return;
0293     }
0294 
0295     chained_irq_enter(chip, desc);
0296 
0297     for (;;) {
0298         isr = (unsigned long)atmel_gpio_read(atmel_pioctrl, bank,
0299                              ATMEL_PIO_ISR);
0300         isr &= (unsigned long)atmel_gpio_read(atmel_pioctrl, bank,
0301                               ATMEL_PIO_IMR);
0302         if (!isr)
0303             break;
0304 
0305         for_each_set_bit(n, &isr, BITS_PER_LONG)
0306             generic_handle_irq(atmel_gpio_to_irq(
0307                     atmel_pioctrl->gpio_chip,
0308                     bank * ATMEL_PIO_NPINS_PER_BANK + n));
0309     }
0310 
0311     chained_irq_exit(chip, desc);
0312 }
0313 
0314 static int atmel_gpio_direction_input(struct gpio_chip *chip,
0315                       unsigned int offset)
0316 {
0317     struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
0318     struct atmel_pin *pin = atmel_pioctrl->pins[offset];
0319     unsigned int reg;
0320 
0321     atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
0322              BIT(pin->line));
0323     reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
0324     reg &= ~ATMEL_PIO_DIR_MASK;
0325     atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
0326 
0327     return 0;
0328 }
0329 
0330 static int atmel_gpio_get(struct gpio_chip *chip, unsigned int offset)
0331 {
0332     struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
0333     struct atmel_pin *pin = atmel_pioctrl->pins[offset];
0334     unsigned int reg;
0335 
0336     reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR);
0337 
0338     return !!(reg & BIT(pin->line));
0339 }
0340 
0341 static int atmel_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
0342                    unsigned long *bits)
0343 {
0344     struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
0345     unsigned int bank;
0346 
0347     bitmap_zero(bits, atmel_pioctrl->npins);
0348 
0349     for (bank = 0; bank < atmel_pioctrl->nbanks; bank++) {
0350         unsigned int word = bank;
0351         unsigned int offset = 0;
0352         unsigned int reg;
0353 
0354 #if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG
0355         word = BIT_WORD(bank * ATMEL_PIO_NPINS_PER_BANK);
0356         offset = bank * ATMEL_PIO_NPINS_PER_BANK % BITS_PER_LONG;
0357 #endif
0358         if (!mask[word])
0359             continue;
0360 
0361         reg = atmel_gpio_read(atmel_pioctrl, bank, ATMEL_PIO_PDSR);
0362         bits[word] |= mask[word] & (reg << offset);
0363     }
0364 
0365     return 0;
0366 }
0367 
0368 static int atmel_gpio_direction_output(struct gpio_chip *chip,
0369                        unsigned int offset,
0370                        int value)
0371 {
0372     struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
0373     struct atmel_pin *pin = atmel_pioctrl->pins[offset];
0374     unsigned int reg;
0375 
0376     atmel_gpio_write(atmel_pioctrl, pin->bank,
0377              value ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,
0378              BIT(pin->line));
0379 
0380     atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
0381              BIT(pin->line));
0382     reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR);
0383     reg |= ATMEL_PIO_DIR_MASK;
0384     atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_CFGR, reg);
0385 
0386     return 0;
0387 }
0388 
0389 static void atmel_gpio_set(struct gpio_chip *chip, unsigned int offset, int val)
0390 {
0391     struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
0392     struct atmel_pin *pin = atmel_pioctrl->pins[offset];
0393 
0394     atmel_gpio_write(atmel_pioctrl, pin->bank,
0395              val ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,
0396              BIT(pin->line));
0397 }
0398 
0399 static void atmel_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask,
0400                     unsigned long *bits)
0401 {
0402     struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
0403     unsigned int bank;
0404 
0405     for (bank = 0; bank < atmel_pioctrl->nbanks; bank++) {
0406         unsigned int bitmask;
0407         unsigned int word = bank;
0408 
0409 /*
0410  * On a 64-bit platform, BITS_PER_LONG is 64 so it is necessary to iterate over
0411  * two 32bit words to handle the whole  bitmask
0412  */
0413 #if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG
0414         word = BIT_WORD(bank * ATMEL_PIO_NPINS_PER_BANK);
0415 #endif
0416         if (!mask[word])
0417             continue;
0418 
0419         bitmask = mask[word] & bits[word];
0420         atmel_gpio_write(atmel_pioctrl, bank, ATMEL_PIO_SODR, bitmask);
0421 
0422         bitmask = mask[word] & ~bits[word];
0423         atmel_gpio_write(atmel_pioctrl, bank, ATMEL_PIO_CODR, bitmask);
0424 
0425 #if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG
0426         mask[word] >>= ATMEL_PIO_NPINS_PER_BANK;
0427         bits[word] >>= ATMEL_PIO_NPINS_PER_BANK;
0428 #endif
0429     }
0430 }
0431 
0432 static struct gpio_chip atmel_gpio_chip = {
0433     .direction_input        = atmel_gpio_direction_input,
0434     .get                    = atmel_gpio_get,
0435     .get_multiple           = atmel_gpio_get_multiple,
0436     .direction_output       = atmel_gpio_direction_output,
0437     .set                    = atmel_gpio_set,
0438     .set_multiple           = atmel_gpio_set_multiple,
0439     .to_irq                 = atmel_gpio_to_irq,
0440     .base                   = 0,
0441 };
0442 
0443 /* --- PINCTRL --- */
0444 static unsigned int atmel_pin_config_read(struct pinctrl_dev *pctldev,
0445                       unsigned int pin_id)
0446 {
0447     struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
0448     unsigned int bank = atmel_pioctrl->pins[pin_id]->bank;
0449     unsigned int line = atmel_pioctrl->pins[pin_id]->line;
0450     void __iomem *addr = atmel_pioctrl->reg_base
0451                  + bank * ATMEL_PIO_BANK_OFFSET;
0452 
0453     writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR);
0454     /* Have to set MSKR first, to access the right pin CFGR. */
0455     wmb();
0456 
0457     return readl_relaxed(addr + ATMEL_PIO_CFGR);
0458 }
0459 
0460 static void atmel_pin_config_write(struct pinctrl_dev *pctldev,
0461                    unsigned int pin_id, u32 conf)
0462 {
0463     struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
0464     unsigned int bank = atmel_pioctrl->pins[pin_id]->bank;
0465     unsigned int line = atmel_pioctrl->pins[pin_id]->line;
0466     void __iomem *addr = atmel_pioctrl->reg_base
0467                  + bank * ATMEL_PIO_BANK_OFFSET;
0468 
0469     writel_relaxed(BIT(line), addr + ATMEL_PIO_MSKR);
0470     /* Have to set MSKR first, to access the right pin CFGR. */
0471     wmb();
0472     writel_relaxed(conf, addr + ATMEL_PIO_CFGR);
0473 }
0474 
0475 static int atmel_pctl_get_groups_count(struct pinctrl_dev *pctldev)
0476 {
0477     struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
0478 
0479     return atmel_pioctrl->npins;
0480 }
0481 
0482 static const char *atmel_pctl_get_group_name(struct pinctrl_dev *pctldev,
0483                          unsigned int selector)
0484 {
0485     struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
0486 
0487     return atmel_pioctrl->groups[selector].name;
0488 }
0489 
0490 static int atmel_pctl_get_group_pins(struct pinctrl_dev *pctldev,
0491                      unsigned int selector,
0492                      const unsigned int **pins,
0493                      unsigned int *num_pins)
0494 {
0495     struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
0496 
0497     *pins = (unsigned int *)&atmel_pioctrl->groups[selector].pin;
0498     *num_pins = 1;
0499 
0500     return 0;
0501 }
0502 
0503 static struct atmel_group *
0504 atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, unsigned int pin)
0505 {
0506     struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
0507     int i;
0508 
0509     for (i = 0; i < atmel_pioctrl->npins; i++) {
0510         struct atmel_group *grp = atmel_pioctrl->groups + i;
0511 
0512         if (grp->pin == pin)
0513             return grp;
0514     }
0515 
0516     return NULL;
0517 }
0518 
0519 static int atmel_pctl_xlate_pinfunc(struct pinctrl_dev *pctldev,
0520                     struct device_node *np,
0521                     u32 pinfunc, const char **grp_name,
0522                     const char **func_name)
0523 {
0524     struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
0525     unsigned int pin_id, func_id;
0526     struct atmel_group *grp;
0527 
0528     pin_id = ATMEL_GET_PIN_NO(pinfunc);
0529     func_id = ATMEL_GET_PIN_FUNC(pinfunc);
0530 
0531     if (func_id >= ARRAY_SIZE(atmel_functions))
0532         return -EINVAL;
0533 
0534     *func_name = atmel_functions[func_id];
0535 
0536     grp = atmel_pctl_find_group_by_pin(pctldev, pin_id);
0537     if (!grp)
0538         return -EINVAL;
0539     *grp_name = grp->name;
0540 
0541     atmel_pioctrl->pins[pin_id]->mux = func_id;
0542     atmel_pioctrl->pins[pin_id]->ioset = ATMEL_GET_PIN_IOSET(pinfunc);
0543     /* Want the device name not the group one. */
0544     if (np->parent == atmel_pioctrl->node)
0545         atmel_pioctrl->pins[pin_id]->device = np->name;
0546     else
0547         atmel_pioctrl->pins[pin_id]->device = np->parent->name;
0548 
0549     return 0;
0550 }
0551 
0552 static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
0553                     struct device_node *np,
0554                     struct pinctrl_map **map,
0555                     unsigned int *reserved_maps,
0556                     unsigned int *num_maps)
0557 {
0558     unsigned int num_pins, num_configs, reserve;
0559     unsigned long *configs;
0560     struct property *pins;
0561     u32 pinfunc;
0562     int ret, i;
0563 
0564     pins = of_find_property(np, "pinmux", NULL);
0565     if (!pins)
0566         return -EINVAL;
0567 
0568     ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
0569                           &num_configs);
0570     if (ret < 0) {
0571         dev_err(pctldev->dev, "%pOF: could not parse node property\n",
0572             np);
0573         return ret;
0574     }
0575 
0576     num_pins = pins->length / sizeof(u32);
0577     if (!num_pins) {
0578         dev_err(pctldev->dev, "no pins found in node %pOF\n", np);
0579         ret = -EINVAL;
0580         goto exit;
0581     }
0582 
0583     /*
0584      * Reserve maps, at least there is a mux map and an optional conf
0585      * map for each pin.
0586      */
0587     reserve = 1;
0588     if (num_configs)
0589         reserve++;
0590     reserve *= num_pins;
0591     ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps,
0592                     reserve);
0593     if (ret < 0)
0594         goto exit;
0595 
0596     for (i = 0; i < num_pins; i++) {
0597         const char *group, *func;
0598 
0599         ret = of_property_read_u32_index(np, "pinmux", i, &pinfunc);
0600         if (ret)
0601             goto exit;
0602 
0603         ret = atmel_pctl_xlate_pinfunc(pctldev, np, pinfunc, &group,
0604                            &func);
0605         if (ret)
0606             goto exit;
0607 
0608         pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps,
0609                       group, func);
0610 
0611         if (num_configs) {
0612             ret = pinctrl_utils_add_map_configs(pctldev, map,
0613                     reserved_maps, num_maps, group,
0614                     configs, num_configs,
0615                     PIN_MAP_TYPE_CONFIGS_GROUP);
0616             if (ret < 0)
0617                 goto exit;
0618         }
0619     }
0620 
0621 exit:
0622     kfree(configs);
0623     return ret;
0624 }
0625 
0626 static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
0627                      struct device_node *np_config,
0628                      struct pinctrl_map **map,
0629                      unsigned int *num_maps)
0630 {
0631     struct device_node *np;
0632     unsigned int reserved_maps;
0633     int ret;
0634 
0635     *map = NULL;
0636     *num_maps = 0;
0637     reserved_maps = 0;
0638 
0639     /*
0640      * If all the pins of a device have the same configuration (or no one),
0641      * it is useless to add a subnode, so directly parse node referenced by
0642      * phandle.
0643      */
0644     ret = atmel_pctl_dt_subnode_to_map(pctldev, np_config, map,
0645                        &reserved_maps, num_maps);
0646     if (ret) {
0647         for_each_child_of_node(np_config, np) {
0648             ret = atmel_pctl_dt_subnode_to_map(pctldev, np, map,
0649                             &reserved_maps, num_maps);
0650             if (ret < 0) {
0651                 of_node_put(np);
0652                 break;
0653             }
0654         }
0655     }
0656 
0657     if (ret < 0) {
0658         pinctrl_utils_free_map(pctldev, *map, *num_maps);
0659         dev_err(pctldev->dev, "can't create maps for node %pOF\n",
0660             np_config);
0661     }
0662 
0663     return ret;
0664 }
0665 
0666 static const struct pinctrl_ops atmel_pctlops = {
0667     .get_groups_count   = atmel_pctl_get_groups_count,
0668     .get_group_name     = atmel_pctl_get_group_name,
0669     .get_group_pins     = atmel_pctl_get_group_pins,
0670     .dt_node_to_map     = atmel_pctl_dt_node_to_map,
0671     .dt_free_map        = pinctrl_utils_free_map,
0672 };
0673 
0674 static int atmel_pmx_get_functions_count(struct pinctrl_dev *pctldev)
0675 {
0676     return ARRAY_SIZE(atmel_functions);
0677 }
0678 
0679 static const char *atmel_pmx_get_function_name(struct pinctrl_dev *pctldev,
0680                            unsigned int selector)
0681 {
0682     return atmel_functions[selector];
0683 }
0684 
0685 static int atmel_pmx_get_function_groups(struct pinctrl_dev *pctldev,
0686                      unsigned int selector,
0687                      const char * const **groups,
0688                      unsigned * const num_groups)
0689 {
0690     struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
0691 
0692     *groups = atmel_pioctrl->group_names;
0693     *num_groups = atmel_pioctrl->npins;
0694 
0695     return 0;
0696 }
0697 
0698 static int atmel_pmx_set_mux(struct pinctrl_dev *pctldev,
0699                  unsigned int function,
0700                  unsigned int group)
0701 {
0702     struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
0703     unsigned int pin;
0704     u32 conf;
0705 
0706     dev_dbg(pctldev->dev, "enable function %s group %s\n",
0707         atmel_functions[function], atmel_pioctrl->groups[group].name);
0708 
0709     pin = atmel_pioctrl->groups[group].pin;
0710     conf = atmel_pin_config_read(pctldev, pin);
0711     conf &= (~ATMEL_PIO_CFGR_FUNC_MASK);
0712     conf |= (function & ATMEL_PIO_CFGR_FUNC_MASK);
0713     dev_dbg(pctldev->dev, "pin: %u, conf: 0x%08x\n", pin, conf);
0714     atmel_pin_config_write(pctldev, pin, conf);
0715 
0716     return 0;
0717 }
0718 
0719 static const struct pinmux_ops atmel_pmxops = {
0720     .get_functions_count    = atmel_pmx_get_functions_count,
0721     .get_function_name  = atmel_pmx_get_function_name,
0722     .get_function_groups    = atmel_pmx_get_function_groups,
0723     .set_mux        = atmel_pmx_set_mux,
0724 };
0725 
0726 static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev,
0727                        unsigned int group,
0728                        unsigned long *config)
0729 {
0730     struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
0731     unsigned int param = pinconf_to_config_param(*config), arg = 0;
0732     struct atmel_group *grp = atmel_pioctrl->groups + group;
0733     unsigned int pin_id = grp->pin;
0734     u32 res;
0735 
0736     res = atmel_pin_config_read(pctldev, pin_id);
0737 
0738     switch (param) {
0739     case PIN_CONFIG_BIAS_PULL_UP:
0740         if (!(res & ATMEL_PIO_PUEN_MASK))
0741             return -EINVAL;
0742         arg = 1;
0743         break;
0744     case PIN_CONFIG_BIAS_PULL_DOWN:
0745         if ((res & ATMEL_PIO_PUEN_MASK) ||
0746             (!(res & ATMEL_PIO_PDEN_MASK)))
0747             return -EINVAL;
0748         arg = 1;
0749         break;
0750     case PIN_CONFIG_BIAS_DISABLE:
0751         if ((res & ATMEL_PIO_PUEN_MASK) ||
0752             ((res & ATMEL_PIO_PDEN_MASK)))
0753             return -EINVAL;
0754         arg = 1;
0755         break;
0756     case PIN_CONFIG_DRIVE_OPEN_DRAIN:
0757         if (!(res & ATMEL_PIO_OPD_MASK))
0758             return -EINVAL;
0759         arg = 1;
0760         break;
0761     case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
0762         if (!(res & ATMEL_PIO_SCHMITT_MASK))
0763             return -EINVAL;
0764         arg = 1;
0765         break;
0766     case PIN_CONFIG_SLEW_RATE:
0767         if (!atmel_pioctrl->slew_rate_support)
0768             return -EOPNOTSUPP;
0769         if (!(res & ATMEL_PIO_SR_MASK))
0770             return -EINVAL;
0771         arg = 1;
0772         break;
0773     case ATMEL_PIN_CONFIG_DRIVE_STRENGTH:
0774         if (!(res & ATMEL_PIO_DRVSTR_MASK))
0775             return -EINVAL;
0776         arg = (res & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET;
0777         break;
0778     default:
0779         return -ENOTSUPP;
0780     }
0781 
0782     *config = pinconf_to_config_packed(param, arg);
0783     return 0;
0784 }
0785 
0786 static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev,
0787                        unsigned int group,
0788                        unsigned long *configs,
0789                        unsigned int num_configs)
0790 {
0791     struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
0792     struct atmel_group *grp = atmel_pioctrl->groups + group;
0793     unsigned int bank, pin, pin_id = grp->pin;
0794     u32 mask, conf = 0;
0795     int i;
0796 
0797     conf = atmel_pin_config_read(pctldev, pin_id);
0798 
0799     /* Keep slew rate enabled by default. */
0800     if (atmel_pioctrl->slew_rate_support)
0801         conf |= ATMEL_PIO_SR_MASK;
0802 
0803     for (i = 0; i < num_configs; i++) {
0804         unsigned int param = pinconf_to_config_param(configs[i]);
0805         unsigned int arg = pinconf_to_config_argument(configs[i]);
0806 
0807         dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n",
0808             __func__, pin_id, configs[i]);
0809 
0810         switch (param) {
0811         case PIN_CONFIG_BIAS_DISABLE:
0812             conf &= (~ATMEL_PIO_PUEN_MASK);
0813             conf &= (~ATMEL_PIO_PDEN_MASK);
0814             break;
0815         case PIN_CONFIG_BIAS_PULL_UP:
0816             conf |= ATMEL_PIO_PUEN_MASK;
0817             conf &= (~ATMEL_PIO_PDEN_MASK);
0818             break;
0819         case PIN_CONFIG_BIAS_PULL_DOWN:
0820             conf |= ATMEL_PIO_PDEN_MASK;
0821             conf &= (~ATMEL_PIO_PUEN_MASK);
0822             break;
0823         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
0824             if (arg == 0)
0825                 conf &= (~ATMEL_PIO_OPD_MASK);
0826             else
0827                 conf |= ATMEL_PIO_OPD_MASK;
0828             break;
0829         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
0830             if (arg == 0)
0831                 conf |= ATMEL_PIO_SCHMITT_MASK;
0832             else
0833                 conf &= (~ATMEL_PIO_SCHMITT_MASK);
0834             break;
0835         case PIN_CONFIG_INPUT_DEBOUNCE:
0836             if (arg == 0) {
0837                 conf &= (~ATMEL_PIO_IFEN_MASK);
0838                 conf &= (~ATMEL_PIO_IFSCEN_MASK);
0839             } else {
0840                 /*
0841                  * We don't care about the debounce value for several reasons:
0842                  * - can't have different debounce periods inside a same group,
0843                  * - the register to configure this period is a secure register.
0844                  * The debouncing filter can filter a pulse with a duration of less
0845                  * than 1/2 slow clock period.
0846                  */
0847                 conf |= ATMEL_PIO_IFEN_MASK;
0848                 conf |= ATMEL_PIO_IFSCEN_MASK;
0849             }
0850             break;
0851         case PIN_CONFIG_OUTPUT:
0852             conf |= ATMEL_PIO_DIR_MASK;
0853             bank = ATMEL_PIO_BANK(pin_id);
0854             pin = ATMEL_PIO_LINE(pin_id);
0855             mask = 1 << pin;
0856 
0857             if (arg == 0) {
0858                 writel_relaxed(mask, atmel_pioctrl->reg_base +
0859                     bank * ATMEL_PIO_BANK_OFFSET +
0860                     ATMEL_PIO_CODR);
0861             } else {
0862                 writel_relaxed(mask, atmel_pioctrl->reg_base +
0863                     bank * ATMEL_PIO_BANK_OFFSET +
0864                     ATMEL_PIO_SODR);
0865             }
0866             break;
0867         case PIN_CONFIG_SLEW_RATE:
0868             if (!atmel_pioctrl->slew_rate_support)
0869                 break;
0870             /* And remove it if explicitly requested. */
0871             if (arg == 0)
0872                 conf &= ~ATMEL_PIO_SR_MASK;
0873             break;
0874         case ATMEL_PIN_CONFIG_DRIVE_STRENGTH:
0875             switch (arg) {
0876             case ATMEL_PIO_DRVSTR_LO:
0877             case ATMEL_PIO_DRVSTR_ME:
0878             case ATMEL_PIO_DRVSTR_HI:
0879                 conf &= (~ATMEL_PIO_DRVSTR_MASK);
0880                 conf |= arg << ATMEL_PIO_DRVSTR_OFFSET;
0881                 break;
0882             default:
0883                 dev_warn(pctldev->dev, "drive strength not updated (incorrect value)\n");
0884             }
0885             break;
0886         default:
0887             dev_warn(pctldev->dev,
0888                  "unsupported configuration parameter: %u\n",
0889                  param);
0890             continue;
0891         }
0892     }
0893 
0894     dev_dbg(pctldev->dev, "%s: reg=0x%08x\n", __func__, conf);
0895     atmel_pin_config_write(pctldev, pin_id, conf);
0896 
0897     return 0;
0898 }
0899 
0900 static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev,
0901                        struct seq_file *s,
0902                        unsigned int pin_id)
0903 {
0904     struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
0905     u32 conf;
0906 
0907     if (!atmel_pioctrl->pins[pin_id]->device)
0908         return;
0909 
0910     if (atmel_pioctrl->pins[pin_id])
0911         seq_printf(s, " (%s, ioset %u) ",
0912                atmel_pioctrl->pins[pin_id]->device,
0913                atmel_pioctrl->pins[pin_id]->ioset);
0914 
0915     conf = atmel_pin_config_read(pctldev, pin_id);
0916     if (conf & ATMEL_PIO_PUEN_MASK)
0917         seq_printf(s, "%s ", "pull-up");
0918     if (conf & ATMEL_PIO_PDEN_MASK)
0919         seq_printf(s, "%s ", "pull-down");
0920     if (conf & ATMEL_PIO_IFEN_MASK)
0921         seq_printf(s, "%s ", "debounce");
0922     if (conf & ATMEL_PIO_OPD_MASK)
0923         seq_printf(s, "%s ", "open-drain");
0924     if (conf & ATMEL_PIO_SCHMITT_MASK)
0925         seq_printf(s, "%s ", "schmitt");
0926     if (atmel_pioctrl->slew_rate_support && (conf & ATMEL_PIO_SR_MASK))
0927         seq_printf(s, "%s ", "slew-rate");
0928     if (conf & ATMEL_PIO_DRVSTR_MASK) {
0929         switch ((conf & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET) {
0930         case ATMEL_PIO_DRVSTR_ME:
0931             seq_printf(s, "%s ", "medium-drive");
0932             break;
0933         case ATMEL_PIO_DRVSTR_HI:
0934             seq_printf(s, "%s ", "high-drive");
0935             break;
0936         /* ATMEL_PIO_DRVSTR_LO and 0 which is the default value at reset */
0937         default:
0938             seq_printf(s, "%s ", "low-drive");
0939         }
0940     }
0941 }
0942 
0943 static const struct pinconf_ops atmel_confops = {
0944     .pin_config_group_get   = atmel_conf_pin_config_group_get,
0945     .pin_config_group_set   = atmel_conf_pin_config_group_set,
0946     .pin_config_dbg_show    = atmel_conf_pin_config_dbg_show,
0947 };
0948 
0949 static struct pinctrl_desc atmel_pinctrl_desc = {
0950     .name       = "atmel_pinctrl",
0951     .confops    = &atmel_confops,
0952     .pctlops    = &atmel_pctlops,
0953     .pmxops     = &atmel_pmxops,
0954 };
0955 
0956 static int __maybe_unused atmel_pctrl_suspend(struct device *dev)
0957 {
0958     struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(dev);
0959     int i, j;
0960 
0961     /*
0962      * For each bank, save IMR to restore it later and disable all GPIO
0963      * interrupts excepting the ones marked as wakeup sources.
0964      */
0965     for (i = 0; i < atmel_pioctrl->nbanks; i++) {
0966         atmel_pioctrl->pm_suspend_backup[i].imr =
0967             atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_IMR);
0968         atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IDR,
0969                  ~atmel_pioctrl->pm_wakeup_sources[i]);
0970         atmel_pioctrl->pm_suspend_backup[i].odsr =
0971             atmel_gpio_read(atmel_pioctrl, i, ATMEL_PIO_ODSR);
0972         for (j = 0; j < ATMEL_PIO_NPINS_PER_BANK; j++) {
0973             atmel_gpio_write(atmel_pioctrl, i,
0974                      ATMEL_PIO_MSKR, BIT(j));
0975             atmel_pioctrl->pm_suspend_backup[i].cfgr[j] =
0976                 atmel_gpio_read(atmel_pioctrl, i,
0977                         ATMEL_PIO_CFGR);
0978         }
0979     }
0980 
0981     return 0;
0982 }
0983 
0984 static int __maybe_unused atmel_pctrl_resume(struct device *dev)
0985 {
0986     struct atmel_pioctrl *atmel_pioctrl = dev_get_drvdata(dev);
0987     int i, j;
0988 
0989     for (i = 0; i < atmel_pioctrl->nbanks; i++) {
0990         atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_IER,
0991                  atmel_pioctrl->pm_suspend_backup[i].imr);
0992         atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_SODR,
0993                  atmel_pioctrl->pm_suspend_backup[i].odsr);
0994         for (j = 0; j < ATMEL_PIO_NPINS_PER_BANK; j++) {
0995             atmel_gpio_write(atmel_pioctrl, i,
0996                      ATMEL_PIO_MSKR, BIT(j));
0997             atmel_gpio_write(atmel_pioctrl, i, ATMEL_PIO_CFGR,
0998                      atmel_pioctrl->pm_suspend_backup[i].cfgr[j]);
0999         }
1000     }
1001 
1002     return 0;
1003 }
1004 
1005 static const struct dev_pm_ops atmel_pctrl_pm_ops = {
1006     SET_SYSTEM_SLEEP_PM_OPS(atmel_pctrl_suspend, atmel_pctrl_resume)
1007 };
1008 
1009 /*
1010  * The number of banks can be different from a SoC to another one.
1011  * We can have up to 16 banks.
1012  */
1013 static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {
1014     .nbanks         = 4,
1015     .last_bank_count    = ATMEL_PIO_NPINS_PER_BANK,
1016 };
1017 
1018 static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = {
1019     .nbanks         = 5,
1020     .last_bank_count    = 8, /* sama7g5 has only PE0 to PE7 */
1021     .slew_rate_support  = 1,
1022 };
1023 
1024 static const struct of_device_id atmel_pctrl_of_match[] = {
1025     {
1026         .compatible = "atmel,sama5d2-pinctrl",
1027         .data = &atmel_sama5d2_pioctrl_data,
1028     }, {
1029         .compatible = "microchip,sama7g5-pinctrl",
1030         .data = &microchip_sama7g5_pioctrl_data,
1031     }, {
1032         /* sentinel */
1033     }
1034 };
1035 
1036 static int atmel_pinctrl_probe(struct platform_device *pdev)
1037 {
1038     struct device *dev = &pdev->dev;
1039     struct pinctrl_pin_desc *pin_desc;
1040     const char **group_names;
1041     const struct of_device_id *match;
1042     int i, ret;
1043     struct atmel_pioctrl *atmel_pioctrl;
1044     const struct atmel_pioctrl_data *atmel_pioctrl_data;
1045 
1046     atmel_pioctrl = devm_kzalloc(dev, sizeof(*atmel_pioctrl), GFP_KERNEL);
1047     if (!atmel_pioctrl)
1048         return -ENOMEM;
1049     atmel_pioctrl->dev = dev;
1050     atmel_pioctrl->node = dev->of_node;
1051     platform_set_drvdata(pdev, atmel_pioctrl);
1052 
1053     match = of_match_node(atmel_pctrl_of_match, dev->of_node);
1054     if (!match) {
1055         dev_err(dev, "unknown compatible string\n");
1056         return -ENODEV;
1057     }
1058     atmel_pioctrl_data = match->data;
1059     atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks;
1060     atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK;
1061     /* if last bank has limited number of pins, adjust accordingly */
1062     if (atmel_pioctrl_data->last_bank_count != ATMEL_PIO_NPINS_PER_BANK) {
1063         atmel_pioctrl->npins -= ATMEL_PIO_NPINS_PER_BANK;
1064         atmel_pioctrl->npins += atmel_pioctrl_data->last_bank_count;
1065     }
1066     atmel_pioctrl->slew_rate_support = atmel_pioctrl_data->slew_rate_support;
1067 
1068     atmel_pioctrl->reg_base = devm_platform_ioremap_resource(pdev, 0);
1069     if (IS_ERR(atmel_pioctrl->reg_base))
1070         return PTR_ERR(atmel_pioctrl->reg_base);
1071 
1072     atmel_pioctrl->clk = devm_clk_get(dev, NULL);
1073     if (IS_ERR(atmel_pioctrl->clk)) {
1074         dev_err(dev, "failed to get clock\n");
1075         return PTR_ERR(atmel_pioctrl->clk);
1076     }
1077 
1078     atmel_pioctrl->pins = devm_kcalloc(dev,
1079                        atmel_pioctrl->npins,
1080                        sizeof(*atmel_pioctrl->pins),
1081                        GFP_KERNEL);
1082     if (!atmel_pioctrl->pins)
1083         return -ENOMEM;
1084 
1085     pin_desc = devm_kcalloc(dev, atmel_pioctrl->npins, sizeof(*pin_desc),
1086                 GFP_KERNEL);
1087     if (!pin_desc)
1088         return -ENOMEM;
1089     atmel_pinctrl_desc.pins = pin_desc;
1090     atmel_pinctrl_desc.npins = atmel_pioctrl->npins;
1091     atmel_pinctrl_desc.num_custom_params = ARRAY_SIZE(atmel_custom_bindings);
1092     atmel_pinctrl_desc.custom_params = atmel_custom_bindings;
1093 
1094     /* One pin is one group since a pin can achieve all functions. */
1095     group_names = devm_kcalloc(dev,
1096                    atmel_pioctrl->npins, sizeof(*group_names),
1097                    GFP_KERNEL);
1098     if (!group_names)
1099         return -ENOMEM;
1100     atmel_pioctrl->group_names = group_names;
1101 
1102     atmel_pioctrl->groups = devm_kcalloc(&pdev->dev,
1103             atmel_pioctrl->npins, sizeof(*atmel_pioctrl->groups),
1104             GFP_KERNEL);
1105     if (!atmel_pioctrl->groups)
1106         return -ENOMEM;
1107     for (i = 0 ; i < atmel_pioctrl->npins; i++) {
1108         struct atmel_group *group = atmel_pioctrl->groups + i;
1109         unsigned int bank = ATMEL_PIO_BANK(i);
1110         unsigned int line = ATMEL_PIO_LINE(i);
1111 
1112         atmel_pioctrl->pins[i] = devm_kzalloc(dev,
1113                 sizeof(**atmel_pioctrl->pins), GFP_KERNEL);
1114         if (!atmel_pioctrl->pins[i])
1115             return -ENOMEM;
1116 
1117         atmel_pioctrl->pins[i]->pin_id = i;
1118         atmel_pioctrl->pins[i]->bank = bank;
1119         atmel_pioctrl->pins[i]->line = line;
1120 
1121         pin_desc[i].number = i;
1122         /* Pin naming convention: P(bank_name)(bank_pin_number). */
1123         pin_desc[i].name = kasprintf(GFP_KERNEL, "P%c%d",
1124                          bank + 'A', line);
1125 
1126         group->name = group_names[i] = pin_desc[i].name;
1127         group->pin = pin_desc[i].number;
1128 
1129         dev_dbg(dev, "pin_id=%u, bank=%u, line=%u", i, bank, line);
1130     }
1131 
1132     atmel_pioctrl->gpio_chip = &atmel_gpio_chip;
1133     atmel_pioctrl->gpio_chip->ngpio = atmel_pioctrl->npins;
1134     atmel_pioctrl->gpio_chip->label = dev_name(dev);
1135     atmel_pioctrl->gpio_chip->parent = dev;
1136     atmel_pioctrl->gpio_chip->names = atmel_pioctrl->group_names;
1137 
1138     atmel_pioctrl->pm_wakeup_sources = devm_kcalloc(dev,
1139             atmel_pioctrl->nbanks,
1140             sizeof(*atmel_pioctrl->pm_wakeup_sources),
1141             GFP_KERNEL);
1142     if (!atmel_pioctrl->pm_wakeup_sources)
1143         return -ENOMEM;
1144 
1145     atmel_pioctrl->pm_suspend_backup = devm_kcalloc(dev,
1146             atmel_pioctrl->nbanks,
1147             sizeof(*atmel_pioctrl->pm_suspend_backup),
1148             GFP_KERNEL);
1149     if (!atmel_pioctrl->pm_suspend_backup)
1150         return -ENOMEM;
1151 
1152     atmel_pioctrl->irqs = devm_kcalloc(dev,
1153                        atmel_pioctrl->nbanks,
1154                        sizeof(*atmel_pioctrl->irqs),
1155                        GFP_KERNEL);
1156     if (!atmel_pioctrl->irqs)
1157         return -ENOMEM;
1158 
1159     /* There is one controller but each bank has its own irq line. */
1160     for (i = 0; i < atmel_pioctrl->nbanks; i++) {
1161         ret = platform_get_irq(pdev, i);
1162         if (ret < 0) {
1163             dev_dbg(dev, "missing irq resource for group %c\n",
1164                 'A' + i);
1165             return ret;
1166         }
1167         atmel_pioctrl->irqs[i] = ret;
1168         irq_set_chained_handler_and_data(ret, atmel_gpio_irq_handler, atmel_pioctrl);
1169         dev_dbg(dev, "bank %i: irq=%d\n", i, ret);
1170     }
1171 
1172     atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node,
1173             atmel_pioctrl->gpio_chip->ngpio,
1174             &irq_domain_simple_ops, NULL);
1175     if (!atmel_pioctrl->irq_domain) {
1176         dev_err(dev, "can't add the irq domain\n");
1177         return -ENODEV;
1178     }
1179     atmel_pioctrl->irq_domain->name = "atmel gpio";
1180 
1181     for (i = 0; i < atmel_pioctrl->npins; i++) {
1182         int irq = irq_create_mapping(atmel_pioctrl->irq_domain, i);
1183 
1184         irq_set_chip_and_handler(irq, &atmel_gpio_irq_chip,
1185                      handle_simple_irq);
1186         irq_set_chip_data(irq, atmel_pioctrl);
1187         dev_dbg(dev,
1188             "atmel gpio irq domain: hwirq: %d, linux irq: %d\n",
1189             i, irq);
1190     }
1191 
1192     ret = clk_prepare_enable(atmel_pioctrl->clk);
1193     if (ret) {
1194         dev_err(dev, "failed to prepare and enable clock\n");
1195         goto clk_prepare_enable_error;
1196     }
1197 
1198     atmel_pioctrl->pinctrl_dev = devm_pinctrl_register(&pdev->dev,
1199                                &atmel_pinctrl_desc,
1200                                atmel_pioctrl);
1201     if (IS_ERR(atmel_pioctrl->pinctrl_dev)) {
1202         ret = PTR_ERR(atmel_pioctrl->pinctrl_dev);
1203         dev_err(dev, "pinctrl registration failed\n");
1204         goto clk_unprep;
1205     }
1206 
1207     ret = gpiochip_add_data(atmel_pioctrl->gpio_chip, atmel_pioctrl);
1208     if (ret) {
1209         dev_err(dev, "failed to add gpiochip\n");
1210         goto clk_unprep;
1211     }
1212 
1213     ret = gpiochip_add_pin_range(atmel_pioctrl->gpio_chip, dev_name(dev),
1214                      0, 0, atmel_pioctrl->gpio_chip->ngpio);
1215     if (ret) {
1216         dev_err(dev, "failed to add gpio pin range\n");
1217         goto gpiochip_add_pin_range_error;
1218     }
1219 
1220     dev_info(&pdev->dev, "atmel pinctrl initialized\n");
1221 
1222     return 0;
1223 
1224 gpiochip_add_pin_range_error:
1225     gpiochip_remove(atmel_pioctrl->gpio_chip);
1226 
1227 clk_unprep:
1228     clk_disable_unprepare(atmel_pioctrl->clk);
1229 
1230 clk_prepare_enable_error:
1231     irq_domain_remove(atmel_pioctrl->irq_domain);
1232 
1233     return ret;
1234 }
1235 
1236 static struct platform_driver atmel_pinctrl_driver = {
1237     .driver = {
1238         .name = "pinctrl-at91-pio4",
1239         .of_match_table = atmel_pctrl_of_match,
1240         .pm = &atmel_pctrl_pm_ops,
1241         .suppress_bind_attrs = true,
1242     },
1243     .probe = atmel_pinctrl_probe,
1244 };
1245 builtin_platform_driver(atmel_pinctrl_driver);
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