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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * ams AS3722 pin control and GPIO driver.
0004  *
0005  * Copyright (c) 2013, NVIDIA Corporation.
0006  *
0007  * Author: Laxman Dewangan <ldewangan@nvidia.com>
0008  */
0009 
0010 #include <linux/delay.h>
0011 #include <linux/gpio/driver.h>
0012 #include <linux/kernel.h>
0013 #include <linux/mod_devicetable.h>
0014 #include <linux/module.h>
0015 #include <linux/mfd/as3722.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/pm.h>
0018 #include <linux/property.h>
0019 #include <linux/slab.h>
0020 
0021 #include <linux/pinctrl/consumer.h>
0022 #include <linux/pinctrl/machine.h>
0023 #include <linux/pinctrl/pinctrl.h>
0024 #include <linux/pinctrl/pinconf-generic.h>
0025 #include <linux/pinctrl/pinconf.h>
0026 #include <linux/pinctrl/pinmux.h>
0027 
0028 #include "core.h"
0029 #include "pinconf.h"
0030 #include "pinctrl-utils.h"
0031 
0032 #define AS3722_PIN_GPIO0        0
0033 #define AS3722_PIN_GPIO1        1
0034 #define AS3722_PIN_GPIO2        2
0035 #define AS3722_PIN_GPIO3        3
0036 #define AS3722_PIN_GPIO4        4
0037 #define AS3722_PIN_GPIO5        5
0038 #define AS3722_PIN_GPIO6        6
0039 #define AS3722_PIN_GPIO7        7
0040 #define AS3722_PIN_NUM          (AS3722_PIN_GPIO7 + 1)
0041 
0042 #define AS3722_GPIO_MODE_PULL_UP           BIT(PIN_CONFIG_BIAS_PULL_UP)
0043 #define AS3722_GPIO_MODE_PULL_DOWN         BIT(PIN_CONFIG_BIAS_PULL_DOWN)
0044 #define AS3722_GPIO_MODE_HIGH_IMPED        BIT(PIN_CONFIG_BIAS_HIGH_IMPEDANCE)
0045 #define AS3722_GPIO_MODE_OPEN_DRAIN        BIT(PIN_CONFIG_DRIVE_OPEN_DRAIN)
0046 
0047 struct as3722_pin_function {
0048     const char *name;
0049     const char * const *groups;
0050     unsigned ngroups;
0051     int mux_option;
0052 };
0053 
0054 struct as3722_gpio_pin_control {
0055     unsigned mode_prop;
0056     int io_function;
0057 };
0058 
0059 struct as3722_pingroup {
0060     const char *name;
0061     const unsigned pins[1];
0062     unsigned npins;
0063 };
0064 
0065 struct as3722_pctrl_info {
0066     struct device *dev;
0067     struct pinctrl_dev *pctl;
0068     struct as3722 *as3722;
0069     struct gpio_chip gpio_chip;
0070     int pins_current_opt[AS3722_PIN_NUM];
0071     const struct as3722_pin_function *functions;
0072     unsigned num_functions;
0073     const struct as3722_pingroup *pin_groups;
0074     int num_pin_groups;
0075     const struct pinctrl_pin_desc *pins;
0076     unsigned num_pins;
0077     struct as3722_gpio_pin_control gpio_control[AS3722_PIN_NUM];
0078 };
0079 
0080 static const struct pinctrl_pin_desc as3722_pins_desc[] = {
0081     PINCTRL_PIN(AS3722_PIN_GPIO0, "gpio0"),
0082     PINCTRL_PIN(AS3722_PIN_GPIO1, "gpio1"),
0083     PINCTRL_PIN(AS3722_PIN_GPIO2, "gpio2"),
0084     PINCTRL_PIN(AS3722_PIN_GPIO3, "gpio3"),
0085     PINCTRL_PIN(AS3722_PIN_GPIO4, "gpio4"),
0086     PINCTRL_PIN(AS3722_PIN_GPIO5, "gpio5"),
0087     PINCTRL_PIN(AS3722_PIN_GPIO6, "gpio6"),
0088     PINCTRL_PIN(AS3722_PIN_GPIO7, "gpio7"),
0089 };
0090 
0091 static const char * const gpio_groups[] = {
0092     "gpio0",
0093     "gpio1",
0094     "gpio2",
0095     "gpio3",
0096     "gpio4",
0097     "gpio5",
0098     "gpio6",
0099     "gpio7",
0100 };
0101 
0102 enum as3722_pinmux_option {
0103     AS3722_PINMUX_GPIO          = 0,
0104     AS3722_PINMUX_INTERRUPT_OUT     = 1,
0105     AS3722_PINMUX_VSUB_VBAT_UNDEB_LOW_OUT   = 2,
0106     AS3722_PINMUX_GPIO_INTERRUPT        = 3,
0107     AS3722_PINMUX_PWM_INPUT         = 4,
0108     AS3722_PINMUX_VOLTAGE_IN_STBY       = 5,
0109     AS3722_PINMUX_OC_PG_SD0         = 6,
0110     AS3722_PINMUX_PG_OUT            = 7,
0111     AS3722_PINMUX_CLK32K_OUT        = 8,
0112     AS3722_PINMUX_WATCHDOG_INPUT        = 9,
0113     AS3722_PINMUX_SOFT_RESET_IN     = 11,
0114     AS3722_PINMUX_PWM_OUTPUT        = 12,
0115     AS3722_PINMUX_VSUB_VBAT_LOW_DEB_OUT = 13,
0116     AS3722_PINMUX_OC_PG_SD6         = 14,
0117 };
0118 
0119 #define FUNCTION_GROUP(fname, mux)          \
0120     {                       \
0121         .name = #fname,             \
0122         .groups = gpio_groups,          \
0123         .ngroups = ARRAY_SIZE(gpio_groups), \
0124         .mux_option = AS3722_PINMUX_##mux,  \
0125     }
0126 
0127 static const struct as3722_pin_function as3722_pin_function[] = {
0128     FUNCTION_GROUP(gpio, GPIO),
0129     FUNCTION_GROUP(interrupt-out, INTERRUPT_OUT),
0130     FUNCTION_GROUP(gpio-in-interrupt, GPIO_INTERRUPT),
0131     FUNCTION_GROUP(vsup-vbat-low-undebounce-out, VSUB_VBAT_UNDEB_LOW_OUT),
0132     FUNCTION_GROUP(vsup-vbat-low-debounce-out, VSUB_VBAT_LOW_DEB_OUT),
0133     FUNCTION_GROUP(voltage-in-standby, VOLTAGE_IN_STBY),
0134     FUNCTION_GROUP(oc-pg-sd0, OC_PG_SD0),
0135     FUNCTION_GROUP(oc-pg-sd6, OC_PG_SD6),
0136     FUNCTION_GROUP(powergood-out, PG_OUT),
0137     FUNCTION_GROUP(pwm-in, PWM_INPUT),
0138     FUNCTION_GROUP(pwm-out, PWM_OUTPUT),
0139     FUNCTION_GROUP(clk32k-out, CLK32K_OUT),
0140     FUNCTION_GROUP(watchdog-in, WATCHDOG_INPUT),
0141     FUNCTION_GROUP(soft-reset-in, SOFT_RESET_IN),
0142 };
0143 
0144 #define AS3722_PINGROUP(pg_name, pin_id) \
0145     {                               \
0146         .name = #pg_name,                   \
0147         .pins = {AS3722_PIN_##pin_id},              \
0148         .npins = 1,                     \
0149     }
0150 
0151 static const struct as3722_pingroup as3722_pingroups[] = {
0152     AS3722_PINGROUP(gpio0,  GPIO0),
0153     AS3722_PINGROUP(gpio1,  GPIO1),
0154     AS3722_PINGROUP(gpio2,  GPIO2),
0155     AS3722_PINGROUP(gpio3,  GPIO3),
0156     AS3722_PINGROUP(gpio4,  GPIO4),
0157     AS3722_PINGROUP(gpio5,  GPIO5),
0158     AS3722_PINGROUP(gpio6,  GPIO6),
0159     AS3722_PINGROUP(gpio7,  GPIO7),
0160 };
0161 
0162 static int as3722_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
0163 {
0164     struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
0165 
0166     return as_pci->num_pin_groups;
0167 }
0168 
0169 static const char *as3722_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
0170         unsigned group)
0171 {
0172     struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
0173 
0174     return as_pci->pin_groups[group].name;
0175 }
0176 
0177 static int as3722_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
0178         unsigned group, const unsigned **pins, unsigned *num_pins)
0179 {
0180     struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
0181 
0182     *pins = as_pci->pin_groups[group].pins;
0183     *num_pins = as_pci->pin_groups[group].npins;
0184     return 0;
0185 }
0186 
0187 static const struct pinctrl_ops as3722_pinctrl_ops = {
0188     .get_groups_count = as3722_pinctrl_get_groups_count,
0189     .get_group_name = as3722_pinctrl_get_group_name,
0190     .get_group_pins = as3722_pinctrl_get_group_pins,
0191     .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
0192     .dt_free_map = pinctrl_utils_free_map,
0193 };
0194 
0195 static int as3722_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
0196 {
0197     struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
0198 
0199     return as_pci->num_functions;
0200 }
0201 
0202 static const char *as3722_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
0203             unsigned function)
0204 {
0205     struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
0206 
0207     return as_pci->functions[function].name;
0208 }
0209 
0210 static int as3722_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
0211         unsigned function, const char * const **groups,
0212         unsigned * const num_groups)
0213 {
0214     struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
0215 
0216     *groups = as_pci->functions[function].groups;
0217     *num_groups = as_pci->functions[function].ngroups;
0218     return 0;
0219 }
0220 
0221 static int as3722_pinctrl_set(struct pinctrl_dev *pctldev, unsigned function,
0222         unsigned group)
0223 {
0224     struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
0225     int gpio_cntr_reg = AS3722_GPIOn_CONTROL_REG(group);
0226     u8 val = AS3722_GPIO_IOSF_VAL(as_pci->functions[function].mux_option);
0227     int ret;
0228 
0229     dev_dbg(as_pci->dev, "%s(): GPIO %u pin to function %u and val %u\n",
0230         __func__, group, function, val);
0231 
0232     ret = as3722_update_bits(as_pci->as3722, gpio_cntr_reg,
0233             AS3722_GPIO_IOSF_MASK, val);
0234     if (ret < 0) {
0235         dev_err(as_pci->dev, "GPIO%d_CTRL_REG update failed %d\n",
0236             group, ret);
0237         return ret;
0238     }
0239     as_pci->gpio_control[group].io_function = function;
0240 
0241     switch (val) {
0242     case AS3722_GPIO_IOSF_SD0_OUT:
0243     case AS3722_GPIO_IOSF_PWR_GOOD_OUT:
0244     case AS3722_GPIO_IOSF_Q32K_OUT:
0245     case AS3722_GPIO_IOSF_PWM_OUT:
0246     case AS3722_GPIO_IOSF_SD6_LOW_VOLT_LOW:
0247         ret = as3722_update_bits(as_pci->as3722, gpio_cntr_reg,
0248             AS3722_GPIO_MODE_MASK, AS3722_GPIO_MODE_OUTPUT_VDDH);
0249         if (ret < 0) {
0250             dev_err(as_pci->dev, "GPIO%d_CTRL update failed %d\n",
0251                 group, ret);
0252             return ret;
0253         }
0254         as_pci->gpio_control[group].mode_prop =
0255                 AS3722_GPIO_MODE_OUTPUT_VDDH;
0256         break;
0257     default:
0258         break;
0259     }
0260     return ret;
0261 }
0262 
0263 static int as3722_pinctrl_gpio_get_mode(unsigned gpio_mode_prop, bool input)
0264 {
0265     if (gpio_mode_prop & AS3722_GPIO_MODE_HIGH_IMPED)
0266         return -EINVAL;
0267 
0268     if (gpio_mode_prop & AS3722_GPIO_MODE_OPEN_DRAIN) {
0269         if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_UP)
0270             return AS3722_GPIO_MODE_IO_OPEN_DRAIN_PULL_UP;
0271         return AS3722_GPIO_MODE_IO_OPEN_DRAIN;
0272     }
0273     if (input) {
0274         if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_UP)
0275             return AS3722_GPIO_MODE_INPUT_PULL_UP;
0276         else if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_DOWN)
0277             return AS3722_GPIO_MODE_INPUT_PULL_DOWN;
0278         return AS3722_GPIO_MODE_INPUT;
0279     }
0280     if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_DOWN)
0281         return AS3722_GPIO_MODE_OUTPUT_VDDL;
0282     return AS3722_GPIO_MODE_OUTPUT_VDDH;
0283 }
0284 
0285 static int as3722_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev,
0286         struct pinctrl_gpio_range *range, unsigned offset)
0287 {
0288     struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
0289 
0290     if (as_pci->gpio_control[offset].io_function)
0291         return -EBUSY;
0292     return 0;
0293 }
0294 
0295 static int as3722_pinctrl_gpio_set_direction(struct pinctrl_dev *pctldev,
0296         struct pinctrl_gpio_range *range, unsigned offset, bool input)
0297 {
0298     struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
0299     struct as3722 *as3722 = as_pci->as3722;
0300     int mode;
0301 
0302     mode = as3722_pinctrl_gpio_get_mode(
0303             as_pci->gpio_control[offset].mode_prop, input);
0304     if (mode < 0) {
0305         dev_err(as_pci->dev, "%s direction for GPIO %d not supported\n",
0306             (input) ? "Input" : "Output", offset);
0307         return mode;
0308     }
0309 
0310     return as3722_update_bits(as3722, AS3722_GPIOn_CONTROL_REG(offset),
0311                 AS3722_GPIO_MODE_MASK, mode);
0312 }
0313 
0314 static const struct pinmux_ops as3722_pinmux_ops = {
0315     .get_functions_count    = as3722_pinctrl_get_funcs_count,
0316     .get_function_name  = as3722_pinctrl_get_func_name,
0317     .get_function_groups    = as3722_pinctrl_get_func_groups,
0318     .set_mux        = as3722_pinctrl_set,
0319     .gpio_request_enable    = as3722_pinctrl_gpio_request_enable,
0320     .gpio_set_direction = as3722_pinctrl_gpio_set_direction,
0321 };
0322 
0323 static int as3722_pinconf_get(struct pinctrl_dev *pctldev,
0324             unsigned pin, unsigned long *config)
0325 {
0326     struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
0327     enum pin_config_param param = pinconf_to_config_param(*config);
0328     int arg = 0;
0329     u16 prop;
0330 
0331     switch (param) {
0332     case PIN_CONFIG_BIAS_DISABLE:
0333         prop = AS3722_GPIO_MODE_PULL_UP |
0334                 AS3722_GPIO_MODE_PULL_DOWN;
0335         if (!(as_pci->gpio_control[pin].mode_prop & prop))
0336             arg = 1;
0337         prop = 0;
0338         break;
0339 
0340     case PIN_CONFIG_BIAS_PULL_UP:
0341         prop = AS3722_GPIO_MODE_PULL_UP;
0342         break;
0343 
0344     case PIN_CONFIG_BIAS_PULL_DOWN:
0345         prop = AS3722_GPIO_MODE_PULL_DOWN;
0346         break;
0347 
0348     case PIN_CONFIG_DRIVE_OPEN_DRAIN:
0349         prop = AS3722_GPIO_MODE_OPEN_DRAIN;
0350         break;
0351 
0352     case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
0353         prop = AS3722_GPIO_MODE_HIGH_IMPED;
0354         break;
0355 
0356     default:
0357         dev_err(as_pci->dev, "Properties not supported\n");
0358         return -ENOTSUPP;
0359     }
0360 
0361     if (as_pci->gpio_control[pin].mode_prop & prop)
0362         arg = 1;
0363 
0364     *config = pinconf_to_config_packed(param, (u16)arg);
0365     return 0;
0366 }
0367 
0368 static int as3722_pinconf_set(struct pinctrl_dev *pctldev,
0369             unsigned pin, unsigned long *configs,
0370             unsigned num_configs)
0371 {
0372     struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
0373     enum pin_config_param param;
0374     int mode_prop;
0375     int i;
0376 
0377     for (i = 0; i < num_configs; i++) {
0378         param = pinconf_to_config_param(configs[i]);
0379         mode_prop = as_pci->gpio_control[pin].mode_prop;
0380 
0381         switch (param) {
0382         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
0383             break;
0384 
0385         case PIN_CONFIG_BIAS_DISABLE:
0386             mode_prop &= ~(AS3722_GPIO_MODE_PULL_UP |
0387                     AS3722_GPIO_MODE_PULL_DOWN);
0388             break;
0389         case PIN_CONFIG_BIAS_PULL_UP:
0390             mode_prop |= AS3722_GPIO_MODE_PULL_UP;
0391             break;
0392 
0393         case PIN_CONFIG_BIAS_PULL_DOWN:
0394             mode_prop |= AS3722_GPIO_MODE_PULL_DOWN;
0395             break;
0396 
0397         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
0398             mode_prop |= AS3722_GPIO_MODE_HIGH_IMPED;
0399             break;
0400 
0401         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
0402             mode_prop |= AS3722_GPIO_MODE_OPEN_DRAIN;
0403             break;
0404 
0405         default:
0406             dev_err(as_pci->dev, "Properties not supported\n");
0407             return -ENOTSUPP;
0408         }
0409 
0410         as_pci->gpio_control[pin].mode_prop = mode_prop;
0411     }
0412     return 0;
0413 }
0414 
0415 static const struct pinconf_ops as3722_pinconf_ops = {
0416     .pin_config_get = as3722_pinconf_get,
0417     .pin_config_set = as3722_pinconf_set,
0418 };
0419 
0420 static struct pinctrl_desc as3722_pinctrl_desc = {
0421     .pctlops = &as3722_pinctrl_ops,
0422     .pmxops = &as3722_pinmux_ops,
0423     .confops = &as3722_pinconf_ops,
0424     .owner = THIS_MODULE,
0425 };
0426 
0427 static int as3722_gpio_get(struct gpio_chip *chip, unsigned offset)
0428 {
0429     struct as3722_pctrl_info *as_pci = gpiochip_get_data(chip);
0430     struct as3722 *as3722 = as_pci->as3722;
0431     int ret;
0432     u32 reg;
0433     u32 control;
0434     u32 val;
0435     int mode;
0436     int invert_enable;
0437 
0438     ret = as3722_read(as3722, AS3722_GPIOn_CONTROL_REG(offset), &control);
0439     if (ret < 0) {
0440         dev_err(as_pci->dev,
0441             "GPIO_CONTROL%d_REG read failed: %d\n", offset, ret);
0442         return ret;
0443     }
0444 
0445     invert_enable = !!(control & AS3722_GPIO_INV);
0446     mode = control & AS3722_GPIO_MODE_MASK;
0447     switch (mode) {
0448     case AS3722_GPIO_MODE_INPUT:
0449     case AS3722_GPIO_MODE_INPUT_PULL_UP:
0450     case AS3722_GPIO_MODE_INPUT_PULL_DOWN:
0451     case AS3722_GPIO_MODE_IO_OPEN_DRAIN:
0452     case AS3722_GPIO_MODE_IO_OPEN_DRAIN_PULL_UP:
0453         reg = AS3722_GPIO_SIGNAL_IN_REG;
0454         break;
0455     case AS3722_GPIO_MODE_OUTPUT_VDDH:
0456     case AS3722_GPIO_MODE_OUTPUT_VDDL:
0457         reg = AS3722_GPIO_SIGNAL_OUT_REG;
0458         break;
0459     default:
0460         return -EINVAL;
0461     }
0462 
0463     ret = as3722_read(as3722, reg, &val);
0464     if (ret < 0) {
0465         dev_err(as_pci->dev,
0466             "GPIO_SIGNAL_IN_REG read failed: %d\n", ret);
0467         return ret;
0468     }
0469 
0470     val = !!(val & AS3722_GPIOn_SIGNAL(offset));
0471     return (invert_enable) ? !val : val;
0472 }
0473 
0474 static void as3722_gpio_set(struct gpio_chip *chip, unsigned offset,
0475         int value)
0476 {
0477     struct as3722_pctrl_info *as_pci = gpiochip_get_data(chip);
0478     struct as3722 *as3722 = as_pci->as3722;
0479     int en_invert;
0480     u32 val;
0481     int ret;
0482 
0483     ret = as3722_read(as3722, AS3722_GPIOn_CONTROL_REG(offset), &val);
0484     if (ret < 0) {
0485         dev_err(as_pci->dev,
0486             "GPIO_CONTROL%d_REG read failed: %d\n", offset, ret);
0487         return;
0488     }
0489     en_invert = !!(val & AS3722_GPIO_INV);
0490 
0491     if (value)
0492         val = (en_invert) ? 0 : AS3722_GPIOn_SIGNAL(offset);
0493     else
0494         val = (en_invert) ? AS3722_GPIOn_SIGNAL(offset) : 0;
0495 
0496     ret = as3722_update_bits(as3722, AS3722_GPIO_SIGNAL_OUT_REG,
0497             AS3722_GPIOn_SIGNAL(offset), val);
0498     if (ret < 0)
0499         dev_err(as_pci->dev,
0500             "GPIO_SIGNAL_OUT_REG update failed: %d\n", ret);
0501 }
0502 
0503 static int as3722_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
0504 {
0505     return pinctrl_gpio_direction_input(chip->base + offset);
0506 }
0507 
0508 static int as3722_gpio_direction_output(struct gpio_chip *chip,
0509         unsigned offset, int value)
0510 {
0511     as3722_gpio_set(chip, offset, value);
0512     return pinctrl_gpio_direction_output(chip->base + offset);
0513 }
0514 
0515 static int as3722_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
0516 {
0517     struct as3722_pctrl_info *as_pci = gpiochip_get_data(chip);
0518 
0519     return as3722_irq_get_virq(as_pci->as3722, offset);
0520 }
0521 
0522 static const struct gpio_chip as3722_gpio_chip = {
0523     .label          = "as3722-gpio",
0524     .owner          = THIS_MODULE,
0525     .request        = gpiochip_generic_request,
0526     .free           = gpiochip_generic_free,
0527     .get            = as3722_gpio_get,
0528     .set            = as3722_gpio_set,
0529     .direction_input    = as3722_gpio_direction_input,
0530     .direction_output   = as3722_gpio_direction_output,
0531     .to_irq         = as3722_gpio_to_irq,
0532     .can_sleep      = true,
0533     .ngpio          = AS3722_PIN_NUM,
0534     .base           = -1,
0535 };
0536 
0537 static int as3722_pinctrl_probe(struct platform_device *pdev)
0538 {
0539     struct as3722_pctrl_info *as_pci;
0540     int ret;
0541 
0542     device_set_node(&pdev->dev, dev_fwnode(pdev->dev.parent));
0543 
0544     as_pci = devm_kzalloc(&pdev->dev, sizeof(*as_pci), GFP_KERNEL);
0545     if (!as_pci)
0546         return -ENOMEM;
0547 
0548     as_pci->dev = &pdev->dev;
0549     as_pci->as3722 = dev_get_drvdata(pdev->dev.parent);
0550     platform_set_drvdata(pdev, as_pci);
0551 
0552     as_pci->pins = as3722_pins_desc;
0553     as_pci->num_pins = ARRAY_SIZE(as3722_pins_desc);
0554     as_pci->functions = as3722_pin_function;
0555     as_pci->num_functions = ARRAY_SIZE(as3722_pin_function);
0556     as_pci->pin_groups = as3722_pingroups;
0557     as_pci->num_pin_groups = ARRAY_SIZE(as3722_pingroups);
0558     as3722_pinctrl_desc.name = dev_name(&pdev->dev);
0559     as3722_pinctrl_desc.pins = as3722_pins_desc;
0560     as3722_pinctrl_desc.npins = ARRAY_SIZE(as3722_pins_desc);
0561     as_pci->pctl = devm_pinctrl_register(&pdev->dev, &as3722_pinctrl_desc,
0562                          as_pci);
0563     if (IS_ERR(as_pci->pctl)) {
0564         dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
0565         return PTR_ERR(as_pci->pctl);
0566     }
0567 
0568     as_pci->gpio_chip = as3722_gpio_chip;
0569     as_pci->gpio_chip.parent = &pdev->dev;
0570     ret = gpiochip_add_data(&as_pci->gpio_chip, as_pci);
0571     if (ret < 0) {
0572         dev_err(&pdev->dev, "Couldn't register gpiochip, %d\n", ret);
0573         return ret;
0574     }
0575 
0576     ret = gpiochip_add_pin_range(&as_pci->gpio_chip, dev_name(&pdev->dev),
0577                 0, 0, AS3722_PIN_NUM);
0578     if (ret < 0) {
0579         dev_err(&pdev->dev, "Couldn't add pin range, %d\n", ret);
0580         goto fail_range_add;
0581     }
0582 
0583     return 0;
0584 
0585 fail_range_add:
0586     gpiochip_remove(&as_pci->gpio_chip);
0587     return ret;
0588 }
0589 
0590 static int as3722_pinctrl_remove(struct platform_device *pdev)
0591 {
0592     struct as3722_pctrl_info *as_pci = platform_get_drvdata(pdev);
0593 
0594     gpiochip_remove(&as_pci->gpio_chip);
0595     return 0;
0596 }
0597 
0598 static const struct of_device_id as3722_pinctrl_of_match[] = {
0599     { .compatible = "ams,as3722-pinctrl", },
0600     { },
0601 };
0602 MODULE_DEVICE_TABLE(of, as3722_pinctrl_of_match);
0603 
0604 static struct platform_driver as3722_pinctrl_driver = {
0605     .driver = {
0606         .name = "as3722-pinctrl",
0607         .of_match_table = as3722_pinctrl_of_match,
0608     },
0609     .probe = as3722_pinctrl_probe,
0610     .remove = as3722_pinctrl_remove,
0611 };
0612 module_platform_driver(as3722_pinctrl_driver);
0613 
0614 MODULE_ALIAS("platform:as3722-pinctrl");
0615 MODULE_DESCRIPTION("AS3722 pin control and GPIO driver");
0616 MODULE_AUTHOR("Laxman Dewangan<ldewangan@nvidia.com>");
0617 MODULE_LICENSE("GPL v2");
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