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OSCL-LXR
 
 

     

0001 /*
0002  * Driver for the Axis ARTPEC-6 pin controller
0003  *
0004  * Author: Chris Paterson <chris.paterson@linux.pieboy.co.uk>
0005  *
0006  * This file is licensed under the terms of the GNU General Public
0007  * License version 2. This program is licensed "as is" without any
0008  * warranty of any kind, whether express or implied.
0009  */
0010 
0011 #include <linux/device.h>
0012 #include <linux/err.h>
0013 #include <linux/init.h>
0014 #include <linux/io.h>
0015 #include <linux/of.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/pinctrl/pinctrl.h>
0018 #include <linux/pinctrl/pinconf-generic.h>
0019 #include <linux/pinctrl/pinconf.h>
0020 #include <linux/pinctrl/pinmux.h>
0021 #include <linux/slab.h>
0022 #include "core.h"
0023 #include "pinconf.h"
0024 #include "pinctrl-utils.h"
0025 
0026 #define ARTPEC6_LAST_PIN    97  /* 97 pins in pinmux */
0027 #define ARTPEC6_MAX_MUXABLE 35  /* Last pin with muxable function */
0028 
0029 /* Pinmux control register bit definitions */
0030 #define ARTPEC6_PINMUX_UDC0_MASK    0x00000001
0031 #define ARTPEC6_PINMUX_UDC0_SHIFT   0
0032 #define ARTPEC6_PINMUX_UDC1_MASK    0x00000002
0033 #define ARTPEC6_PINMUX_UDC1_SHIFT   1
0034 #define ARTPEC6_PINMUX_DRV_MASK     0x00000060
0035 #define ARTPEC6_PINMUX_DRV_SHIFT    5
0036 #define ARTPEC6_PINMUX_SEL_MASK     0x00003000
0037 #define ARTPEC6_PINMUX_SEL_SHIFT    12
0038 
0039 /* Pinmux configurations */
0040 #define ARTPEC6_CONFIG_0        0
0041 #define ARTPEC6_CONFIG_1        1
0042 #define ARTPEC6_CONFIG_2        2
0043 #define ARTPEC6_CONFIG_3        3
0044 
0045 /* Pin drive strength options */
0046 #define ARTPEC6_DRIVE_4mA       4
0047 #define ARTPEC6_DRIVE_4mA_SET       0
0048 #define ARTPEC6_DRIVE_6mA       6
0049 #define ARTPEC6_DRIVE_6mA_SET       1
0050 #define ARTPEC6_DRIVE_8mA       8
0051 #define ARTPEC6_DRIVE_8mA_SET       2
0052 #define ARTPEC6_DRIVE_9mA       9
0053 #define ARTPEC6_DRIVE_9mA_SET       3
0054 
0055 struct artpec6_pmx {
0056     struct device           *dev;
0057     struct pinctrl_dev      *pctl;
0058     void __iomem            *base;
0059     struct pinctrl_pin_desc     *pins;
0060     unsigned int            num_pins;
0061     const struct artpec6_pin_group  *pin_groups;
0062     unsigned int            num_pin_groups;
0063     const struct artpec6_pmx_func   *functions;
0064     unsigned int            num_functions;
0065 };
0066 
0067 struct artpec6_pin_group {
0068     const char     *name;
0069     const unsigned int *pins;
0070     const unsigned int num_pins;
0071     unsigned char      config;
0072 };
0073 
0074 struct artpec6_pmx_func {
0075     const char     *name;
0076     const char * const *groups;
0077     const unsigned int num_groups;
0078 };
0079 
0080 /* pins */
0081 static struct pinctrl_pin_desc artpec6_pins[] = {
0082     PINCTRL_PIN(0, "GPIO0"),
0083     PINCTRL_PIN(1, "GPIO1"),
0084     PINCTRL_PIN(2, "GPIO2"),
0085     PINCTRL_PIN(3, "GPIO3"),
0086     PINCTRL_PIN(4, "GPIO4"),
0087     PINCTRL_PIN(5, "GPIO5"),
0088     PINCTRL_PIN(6, "GPIO6"),
0089     PINCTRL_PIN(7, "GPIO7"),
0090     PINCTRL_PIN(8, "GPIO8"),
0091     PINCTRL_PIN(9, "GPIO9"),
0092     PINCTRL_PIN(10, "GPIO10"),
0093     PINCTRL_PIN(11, "GPIO11"),
0094     PINCTRL_PIN(12, "GPIO12"),
0095     PINCTRL_PIN(13, "GPIO13"),
0096     PINCTRL_PIN(14, "GPIO14"),
0097     PINCTRL_PIN(15, "GPIO15"),
0098     PINCTRL_PIN(16, "GPIO16"),
0099     PINCTRL_PIN(17, "GPIO17"),
0100     PINCTRL_PIN(18, "GPIO18"),
0101     PINCTRL_PIN(19, "GPIO19"),
0102     PINCTRL_PIN(20, "GPIO20"),
0103     PINCTRL_PIN(21, "GPIO21"),
0104     PINCTRL_PIN(22, "GPIO22"),
0105     PINCTRL_PIN(23, "GPIO23"),
0106     PINCTRL_PIN(24, "GPIO24"),
0107     PINCTRL_PIN(25, "GPIO25"),
0108     PINCTRL_PIN(26, "GPIO26"),
0109     PINCTRL_PIN(27, "GPIO27"),
0110     PINCTRL_PIN(28, "GPIO28"),
0111     PINCTRL_PIN(29, "GPIO29"),
0112     PINCTRL_PIN(30, "GPIO30"),
0113     PINCTRL_PIN(31, "GPIO31"),
0114     PINCTRL_PIN(32, "UART3_TXD"),
0115     PINCTRL_PIN(33, "UART3_RXD"),
0116     PINCTRL_PIN(34, "UART3_RTS"),
0117     PINCTRL_PIN(35, "UART3_CTS"),
0118     PINCTRL_PIN(36, "NF_ALE"),
0119     PINCTRL_PIN(37, "NF_CE0_N"),
0120     PINCTRL_PIN(38, "NF_CE1_N"),
0121     PINCTRL_PIN(39, "NF_CLE"),
0122     PINCTRL_PIN(40, "NF_RE_N"),
0123     PINCTRL_PIN(41, "NF_WE_N"),
0124     PINCTRL_PIN(42, "NF_WP0_N"),
0125     PINCTRL_PIN(43, "NF_WP1_N"),
0126     PINCTRL_PIN(44, "NF_IO0"),
0127     PINCTRL_PIN(45, "NF_IO1"),
0128     PINCTRL_PIN(46, "NF_IO2"),
0129     PINCTRL_PIN(47, "NF_IO3"),
0130     PINCTRL_PIN(48, "NF_IO4"),
0131     PINCTRL_PIN(49, "NF_IO5"),
0132     PINCTRL_PIN(50, "NF_IO6"),
0133     PINCTRL_PIN(51, "NF_IO7"),
0134     PINCTRL_PIN(52, "NF_RB0_N"),
0135     PINCTRL_PIN(53, "SDIO0_CLK"),
0136     PINCTRL_PIN(54, "SDIO0_CMD"),
0137     PINCTRL_PIN(55, "SDIO0_DAT0"),
0138     PINCTRL_PIN(56, "SDIO0_DAT1"),
0139     PINCTRL_PIN(57, "SDIO0_DAT2"),
0140     PINCTRL_PIN(58, "SDIO0_DAT3"),
0141     PINCTRL_PIN(59, "SDI0_CD"),
0142     PINCTRL_PIN(60, "SDI0_WP"),
0143     PINCTRL_PIN(61, "SDIO1_CLK"),
0144     PINCTRL_PIN(62, "SDIO1_CMD"),
0145     PINCTRL_PIN(63, "SDIO1_DAT0"),
0146     PINCTRL_PIN(64, "SDIO1_DAT1"),
0147     PINCTRL_PIN(65, "SDIO1_DAT2"),
0148     PINCTRL_PIN(66, "SDIO1_DAT3"),
0149     PINCTRL_PIN(67, "SDIO1_CD"),
0150     PINCTRL_PIN(68, "SDIO1_WP"),
0151     PINCTRL_PIN(69, "GBE_REFCLk"),
0152     PINCTRL_PIN(70, "GBE_GTX_CLK"),
0153     PINCTRL_PIN(71, "GBE_TX_CLK"),
0154     PINCTRL_PIN(72, "GBE_TX_EN"),
0155     PINCTRL_PIN(73, "GBE_TX_ER"),
0156     PINCTRL_PIN(74, "GBE_TXD0"),
0157     PINCTRL_PIN(75, "GBE_TXD1"),
0158     PINCTRL_PIN(76, "GBE_TXD2"),
0159     PINCTRL_PIN(77, "GBE_TXD3"),
0160     PINCTRL_PIN(78, "GBE_TXD4"),
0161     PINCTRL_PIN(79, "GBE_TXD5"),
0162     PINCTRL_PIN(80, "GBE_TXD6"),
0163     PINCTRL_PIN(81, "GBE_TXD7"),
0164     PINCTRL_PIN(82, "GBE_RX_CLK"),
0165     PINCTRL_PIN(83, "GBE_RX_DV"),
0166     PINCTRL_PIN(84, "GBE_RX_ER"),
0167     PINCTRL_PIN(85, "GBE_RXD0"),
0168     PINCTRL_PIN(86, "GBE_RXD1"),
0169     PINCTRL_PIN(87, "GBE_RXD2"),
0170     PINCTRL_PIN(88, "GBE_RXD3"),
0171     PINCTRL_PIN(89, "GBE_RXD4"),
0172     PINCTRL_PIN(90, "GBE_RXD5"),
0173     PINCTRL_PIN(91, "GBE_RXD6"),
0174     PINCTRL_PIN(92, "GBE_RXD7"),
0175     PINCTRL_PIN(93, "GBE_CRS"),
0176     PINCTRL_PIN(94, "GBE_COL"),
0177     PINCTRL_PIN(95, "GBE_MDC"),
0178     PINCTRL_PIN(96, "GBE_MDIO"),
0179 };
0180 
0181 static const unsigned int cpuclkout_pins0[] = { 0 };
0182 static const unsigned int udlclkout_pins0[] = { 1 };
0183 static const unsigned int i2c1_pins0[] = { 2, 3 };
0184 static const unsigned int i2c2_pins0[] = { 4, 5 };
0185 static const unsigned int i2c3_pins0[] = { 6, 7 };
0186 static const unsigned int i2s0_pins0[] = { 8, 9, 10, 11 };
0187 static const unsigned int i2s1_pins0[] = { 12, 13, 14, 15 };
0188 static const unsigned int i2srefclk_pins0[] = { 19 };
0189 static const unsigned int spi0_pins0[] = { 12, 13, 14, 15 };
0190 static const unsigned int spi1_pins0[] = { 16, 17, 18, 19 };
0191 static const unsigned int pciedebug_pins0[] = { 12, 13, 14, 15 };
0192 static const unsigned int uart0_pins0[] = { 16, 17, 18, 19, 20,
0193                         21, 22, 23, 24, 25 };
0194 static const unsigned int uart0_pins1[] = { 20, 21, 22, 23 };
0195 static const unsigned int uart1_pins0[] = { 24, 25, 26, 27 };
0196 static const unsigned int uart2_pins0[] = { 26, 27, 28, 29, 30,
0197                         31, 32, 33, 34, 35 };
0198 static const unsigned int uart2_pins1[] = { 28, 29, 30, 31 };
0199 static const unsigned int uart3_pins0[] = { 32, 33, 34, 35 };
0200 static const unsigned int uart4_pins0[] = { 20, 21, 22, 23 };
0201 static const unsigned int uart5_pins0[] = { 28, 29, 30, 31 };
0202 static const unsigned int nand_pins0[]  = { 36, 37, 38, 39, 40, 41,
0203                         42, 43, 44, 45, 46, 47,
0204                         48, 49, 50, 51, 52 };
0205 static const unsigned int sdio0_pins0[] = { 53, 54, 55, 56, 57, 58, 59, 60 };
0206 static const unsigned int sdio1_pins0[] = { 61, 62, 63, 64, 65, 66, 67, 68 };
0207 static const unsigned int ethernet_pins0[]  = { 69, 70, 71, 72, 73, 74, 75,
0208                         76, 77, 78, 79, 80, 81, 82,
0209                         83, 84, 85, 86, 87, 88, 89,
0210                         90, 91, 92, 93, 94, 95, 96 };
0211 
0212 static const struct artpec6_pin_group artpec6_pin_groups[] = {
0213     {
0214         .name = "cpuclkoutgrp0",
0215         .pins = cpuclkout_pins0,
0216         .num_pins = ARRAY_SIZE(cpuclkout_pins0),
0217         .config = ARTPEC6_CONFIG_1,
0218     },
0219     {
0220         .name = "udlclkoutgrp0",
0221         .pins = udlclkout_pins0,
0222         .num_pins = ARRAY_SIZE(udlclkout_pins0),
0223         .config = ARTPEC6_CONFIG_1,
0224     },
0225     {
0226         .name = "i2c1grp0",
0227         .pins = i2c1_pins0,
0228         .num_pins = ARRAY_SIZE(i2c1_pins0),
0229         .config = ARTPEC6_CONFIG_1,
0230     },
0231     {
0232         .name = "i2c2grp0",
0233         .pins = i2c2_pins0,
0234         .num_pins = ARRAY_SIZE(i2c2_pins0),
0235         .config = ARTPEC6_CONFIG_1,
0236     },
0237     {
0238         .name = "i2c3grp0",
0239         .pins = i2c3_pins0,
0240         .num_pins = ARRAY_SIZE(i2c3_pins0),
0241         .config = ARTPEC6_CONFIG_1,
0242     },
0243     {
0244         .name = "i2s0grp0",
0245         .pins = i2s0_pins0,
0246         .num_pins = ARRAY_SIZE(i2s0_pins0),
0247         .config = ARTPEC6_CONFIG_1,
0248     },
0249     {
0250         .name = "i2s1grp0",
0251         .pins = i2s1_pins0,
0252         .num_pins = ARRAY_SIZE(i2s1_pins0),
0253         .config = ARTPEC6_CONFIG_1,
0254     },
0255     {
0256         .name = "i2srefclkgrp0",
0257         .pins = i2srefclk_pins0,
0258         .num_pins = ARRAY_SIZE(i2srefclk_pins0),
0259         .config = ARTPEC6_CONFIG_3,
0260     },
0261     {
0262         .name = "spi0grp0",
0263         .pins = spi0_pins0,
0264         .num_pins = ARRAY_SIZE(spi0_pins0),
0265         .config = ARTPEC6_CONFIG_2,
0266     },
0267     {
0268         .name = "spi1grp0",
0269         .pins = spi1_pins0,
0270         .num_pins = ARRAY_SIZE(spi1_pins0),
0271         .config = ARTPEC6_CONFIG_2,
0272     },
0273     {
0274         .name = "pciedebuggrp0",
0275         .pins = pciedebug_pins0,
0276         .num_pins = ARRAY_SIZE(pciedebug_pins0),
0277         .config = ARTPEC6_CONFIG_3,
0278     },
0279     {
0280         .name = "uart0grp0",    /* All pins. */
0281         .pins = uart0_pins0,
0282         .num_pins = ARRAY_SIZE(uart0_pins0),
0283         .config = ARTPEC6_CONFIG_1,
0284     },
0285     {
0286         .name = "uart0grp1",    /* RX/TX and RTS/CTS */
0287         .pins = uart0_pins1,
0288         .num_pins = ARRAY_SIZE(uart0_pins1),
0289         .config = ARTPEC6_CONFIG_1,
0290     },
0291     {
0292         .name = "uart0grp2",    /* Only RX/TX pins. */
0293         .pins = uart0_pins1,
0294         .num_pins = ARRAY_SIZE(uart0_pins1) - 2,
0295         .config = ARTPEC6_CONFIG_1,
0296     },
0297     {
0298         .name = "uart1grp0",    /* RX/TX and RTS/CTS */
0299         .pins = uart1_pins0,
0300         .num_pins = ARRAY_SIZE(uart1_pins0),
0301         .config = ARTPEC6_CONFIG_2,
0302     },
0303     {
0304         .name = "uart1grp1",    /* Only RX/TX pins. */
0305         .pins = uart1_pins0,
0306         .num_pins = 2,
0307         .config = ARTPEC6_CONFIG_2,
0308     },
0309     {
0310         .name = "uart2grp0",    /* Full pinout */
0311         .pins = uart2_pins0,
0312         .num_pins = ARRAY_SIZE(uart2_pins0),
0313         .config = ARTPEC6_CONFIG_1,
0314     },
0315     {
0316         .name = "uart2grp1",    /* RX/TX and RTS/CTS */
0317         .pins = uart2_pins1,
0318         .num_pins = ARRAY_SIZE(uart2_pins1),
0319         .config = ARTPEC6_CONFIG_1,
0320     },
0321     {
0322         .name = "uart2grp2",    /* Only RX/TX */
0323         .pins = uart2_pins1,
0324         .num_pins = 2,
0325         .config = ARTPEC6_CONFIG_1,
0326     },
0327     {
0328         .name = "uart3grp0",    /* RX/TX and CTS/RTS */
0329         .pins = uart3_pins0,
0330         .num_pins = ARRAY_SIZE(uart3_pins0),
0331         .config = ARTPEC6_CONFIG_0,
0332     },
0333     {
0334         .name = "uart3grp1",    /* Only RX/TX */
0335         .pins = uart3_pins0,
0336         .num_pins = ARRAY_SIZE(uart3_pins0),
0337         .config = ARTPEC6_CONFIG_0,
0338     },
0339     {
0340         .name = "uart4grp0",
0341         .pins = uart4_pins0,
0342         .num_pins = ARRAY_SIZE(uart4_pins0),
0343         .config = ARTPEC6_CONFIG_2,
0344     },
0345     {
0346         .name = "uart5grp0",    /* TX/RX and RTS/CTS */
0347         .pins = uart5_pins0,
0348         .num_pins = ARRAY_SIZE(uart5_pins0),
0349         .config = ARTPEC6_CONFIG_2,
0350     },
0351     {
0352         .name = "uart5grp1",    /* Only TX/RX */
0353         .pins = uart5_pins0,
0354         .num_pins = 2,
0355         .config = ARTPEC6_CONFIG_2,
0356     },
0357     {
0358         .name = "uart5nocts",   /* TX/RX/RTS */
0359         .pins = uart5_pins0,
0360         .num_pins = ARRAY_SIZE(uart5_pins0) - 1,
0361         .config = ARTPEC6_CONFIG_2,
0362     },
0363     {
0364         .name = "nandgrp0",
0365         .pins = nand_pins0,
0366         .num_pins = ARRAY_SIZE(nand_pins0),
0367         .config = ARTPEC6_CONFIG_0,
0368     },
0369     {
0370         .name = "sdio0grp0",
0371         .pins = sdio0_pins0,
0372         .num_pins = ARRAY_SIZE(sdio0_pins0),
0373         .config = ARTPEC6_CONFIG_0,
0374     },
0375     {
0376         .name = "sdio1grp0",
0377         .pins = sdio1_pins0,
0378         .num_pins = ARRAY_SIZE(sdio1_pins0),
0379         .config = ARTPEC6_CONFIG_0,
0380     },
0381     {
0382         .name = "ethernetgrp0",
0383         .pins = ethernet_pins0,
0384         .num_pins = ARRAY_SIZE(ethernet_pins0),
0385         .config = ARTPEC6_CONFIG_0,
0386     },
0387 };
0388 
0389 struct pin_register {
0390     unsigned int start;
0391     unsigned int end;
0392     unsigned int reg_base;
0393 };
0394 
0395 /*
0396  * The register map has two holes where the pin number
0397  * no longer fits directly with the register offset.
0398  * This table allows us to map this easily.
0399  */
0400 static const struct pin_register pin_register[] = {
0401     { 0, 35, 0x0 },     /* 0x0 - 0x8c */
0402     { 36, 52, 0x100 },  /* 0x100 - 0x140 */
0403     { 53, 96, 0x180 },  /* 0x180 - 0x22c */
0404 };
0405 
0406 static unsigned int artpec6_pmx_reg_offset(unsigned int pin)
0407 {
0408     int i;
0409 
0410     for (i = 0; i < ARRAY_SIZE(pin_register); i++) {
0411         if (pin <= pin_register[i].end) {
0412             return (pin - pin_register[i].start) * 4 +
0413                 pin_register[i].reg_base;
0414         }
0415     }
0416     /*
0417      * Anything we return here is wrong, but we can only
0418      * get here if pin is outside registered range.
0419      */
0420     pr_err("%s: Impossible pin %d\n", __func__, pin);
0421     return 0;
0422 }
0423 
0424 static int artpec6_get_groups_count(struct pinctrl_dev *pctldev)
0425 {
0426     return ARRAY_SIZE(artpec6_pin_groups);
0427 }
0428 
0429 static const char *artpec6_get_group_name(struct pinctrl_dev *pctldev,
0430                       unsigned int group)
0431 {
0432     return artpec6_pin_groups[group].name;
0433 }
0434 
0435 static int artpec6_get_group_pins(struct pinctrl_dev *pctldev,
0436                   unsigned int group,
0437                   const unsigned int **pins,
0438                   unsigned int *num_pins)
0439 {
0440     *pins = (unsigned int *)artpec6_pin_groups[group].pins;
0441     *num_pins = artpec6_pin_groups[group].num_pins;
0442     return 0;
0443 }
0444 
0445 static int artpec6_pconf_drive_mA_to_field(unsigned int mA)
0446 {
0447     switch (mA) {
0448     case ARTPEC6_DRIVE_4mA:
0449         return ARTPEC6_DRIVE_4mA_SET;
0450     case ARTPEC6_DRIVE_6mA:
0451         return ARTPEC6_DRIVE_6mA_SET;
0452     case ARTPEC6_DRIVE_8mA:
0453         return ARTPEC6_DRIVE_8mA_SET;
0454     case ARTPEC6_DRIVE_9mA:
0455         return ARTPEC6_DRIVE_9mA_SET;
0456     default:
0457         return -EINVAL;
0458     }
0459 }
0460 
0461 static unsigned int artpec6_pconf_drive_field_to_mA(int field)
0462 {
0463     switch (field) {
0464     case ARTPEC6_DRIVE_4mA_SET:
0465         return ARTPEC6_DRIVE_4mA;
0466     case ARTPEC6_DRIVE_6mA_SET:
0467         return ARTPEC6_DRIVE_6mA;
0468     case ARTPEC6_DRIVE_8mA_SET:
0469         return ARTPEC6_DRIVE_8mA;
0470     case ARTPEC6_DRIVE_9mA_SET:
0471         return ARTPEC6_DRIVE_9mA;
0472     default:
0473         /* Shouldn't happen */
0474         return 0;
0475     }
0476 }
0477 
0478 static const struct pinctrl_ops artpec6_pctrl_ops = {
0479     .get_group_pins     = artpec6_get_group_pins,
0480     .get_groups_count   = artpec6_get_groups_count,
0481     .get_group_name     = artpec6_get_group_name,
0482     .dt_node_to_map     = pinconf_generic_dt_node_to_map_all,
0483     .dt_free_map        = pinctrl_utils_free_map,
0484 };
0485 
0486 static const char * const gpiogrps[] = {
0487     "cpuclkoutgrp0", "udlclkoutgrp0", "i2c1grp0", "i2c2grp0",
0488     "i2c3grp0", "i2s0grp0", "i2s1grp0", "i2srefclkgrp0",
0489     "spi0grp0", "spi1grp0", "pciedebuggrp0", "uart0grp0",
0490     "uart0grp1", "uart0grp2", "uart1grp0", "uart1grp1",
0491     "uart2grp0", "uart2grp1", "uart2grp2", "uart4grp0", "uart5grp0",
0492     "uart5grp1", "uart5nocts",
0493 };
0494 static const char * const cpuclkoutgrps[] = { "cpuclkoutgrp0" };
0495 static const char * const udlclkoutgrps[] = { "udlclkoutgrp0" };
0496 static const char * const i2c1grps[]      = { "i2c1grp0" };
0497 static const char * const i2c2grps[]      = { "i2c2grp0" };
0498 static const char * const i2c3grps[]      = { "i2c3grp0" };
0499 static const char * const i2s0grps[]      = { "i2s0grp0" };
0500 static const char * const i2s1grps[]      = { "i2s1grp0" };
0501 static const char * const i2srefclkgrps[] = { "i2srefclkgrp0" };
0502 static const char * const spi0grps[]      = { "spi0grp0" };
0503 static const char * const spi1grps[]      = { "spi1grp0" };
0504 static const char * const pciedebuggrps[] = { "pciedebuggrp0" };
0505 static const char * const uart0grps[]     = { "uart0grp0", "uart0grp1",
0506                           "uart0grp2" };
0507 static const char * const uart1grps[]     = { "uart1grp0", "uart1grp1" };
0508 static const char * const uart2grps[]     = { "uart2grp0", "uart2grp1",
0509                           "uart2grp2" };
0510 static const char * const uart3grps[]     = { "uart3grp0" };
0511 static const char * const uart4grps[]     = { "uart4grp0", "uart4grp1" };
0512 static const char * const uart5grps[]     = { "uart5grp0", "uart5grp1",
0513                           "uart5nocts" };
0514 static const char * const nandgrps[]      = { "nandgrp0" };
0515 static const char * const sdio0grps[]     = { "sdio0grp0" };
0516 static const char * const sdio1grps[]     = { "sdio1grp0" };
0517 static const char * const ethernetgrps[]  = { "ethernetgrp0" };
0518 
0519 static const struct artpec6_pmx_func artpec6_pmx_functions[] = {
0520     {
0521         .name = "gpio",
0522         .groups = gpiogrps,
0523         .num_groups = ARRAY_SIZE(gpiogrps),
0524     },
0525     {
0526         .name = "cpuclkout",
0527         .groups = cpuclkoutgrps,
0528         .num_groups = ARRAY_SIZE(cpuclkoutgrps),
0529     },
0530     {
0531         .name = "udlclkout",
0532         .groups = udlclkoutgrps,
0533         .num_groups = ARRAY_SIZE(udlclkoutgrps),
0534     },
0535     {
0536         .name = "i2c1",
0537         .groups = i2c1grps,
0538         .num_groups = ARRAY_SIZE(i2c1grps),
0539     },
0540     {
0541         .name = "i2c2",
0542         .groups = i2c2grps,
0543         .num_groups = ARRAY_SIZE(i2c2grps),
0544     },
0545     {
0546         .name = "i2c3",
0547         .groups = i2c3grps,
0548         .num_groups = ARRAY_SIZE(i2c3grps),
0549     },
0550     {
0551         .name = "i2s0",
0552         .groups = i2s0grps,
0553         .num_groups = ARRAY_SIZE(i2s0grps),
0554     },
0555     {
0556         .name = "i2s1",
0557         .groups = i2s1grps,
0558         .num_groups = ARRAY_SIZE(i2s1grps),
0559     },
0560     {
0561         .name = "i2srefclk",
0562         .groups = i2srefclkgrps,
0563         .num_groups = ARRAY_SIZE(i2srefclkgrps),
0564     },
0565     {
0566         .name = "spi0",
0567         .groups = spi0grps,
0568         .num_groups = ARRAY_SIZE(spi0grps),
0569     },
0570     {
0571         .name = "spi1",
0572         .groups = spi1grps,
0573         .num_groups = ARRAY_SIZE(spi1grps),
0574     },
0575     {
0576         .name = "pciedebug",
0577         .groups = pciedebuggrps,
0578         .num_groups = ARRAY_SIZE(pciedebuggrps),
0579     },
0580     {
0581         .name = "uart0",
0582         .groups = uart0grps,
0583         .num_groups = ARRAY_SIZE(uart0grps),
0584     },
0585     {
0586         .name = "uart1",
0587         .groups = uart1grps,
0588         .num_groups = ARRAY_SIZE(uart1grps),
0589     },
0590     {
0591         .name = "uart2",
0592         .groups = uart2grps,
0593         .num_groups = ARRAY_SIZE(uart2grps),
0594     },
0595     {
0596         .name = "uart3",
0597         .groups = uart3grps,
0598         .num_groups = ARRAY_SIZE(uart3grps),
0599     },
0600     {
0601         .name = "uart4",
0602         .groups = uart4grps,
0603         .num_groups = ARRAY_SIZE(uart4grps),
0604     },
0605     {
0606         .name = "uart5",
0607         .groups = uart5grps,
0608         .num_groups = ARRAY_SIZE(uart5grps),
0609     },
0610     {
0611         .name = "nand",
0612         .groups = nandgrps,
0613         .num_groups = ARRAY_SIZE(nandgrps),
0614     },
0615     {
0616         .name = "sdio0",
0617         .groups = sdio0grps,
0618         .num_groups = ARRAY_SIZE(sdio0grps),
0619     },
0620     {
0621         .name = "sdio1",
0622         .groups = sdio1grps,
0623         .num_groups = ARRAY_SIZE(sdio1grps),
0624     },
0625     {
0626         .name = "ethernet",
0627         .groups = ethernetgrps,
0628         .num_groups = ARRAY_SIZE(ethernetgrps),
0629     },
0630 };
0631 
0632 static int artpec6_pmx_get_functions_count(struct pinctrl_dev *pctldev)
0633 {
0634     return ARRAY_SIZE(artpec6_pmx_functions);
0635 }
0636 
0637 static const char *artpec6_pmx_get_fname(struct pinctrl_dev *pctldev,
0638                      unsigned int function)
0639 {
0640     return artpec6_pmx_functions[function].name;
0641 }
0642 
0643 static int artpec6_pmx_get_fgroups(struct pinctrl_dev *pctldev,
0644                    unsigned int function,
0645                    const char * const **groups,
0646                    unsigned int * const num_groups)
0647 {
0648     *groups = artpec6_pmx_functions[function].groups;
0649     *num_groups = artpec6_pmx_functions[function].num_groups;
0650     return 0;
0651 }
0652 
0653 static void artpec6_pmx_select_func(struct pinctrl_dev *pctldev,
0654                     unsigned int function, unsigned int group,
0655                     bool enable)
0656 {
0657     unsigned int regval, val;
0658     unsigned int reg;
0659     int i;
0660     struct artpec6_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
0661 
0662     for (i = 0; i < artpec6_pin_groups[group].num_pins; i++) {
0663         /*
0664          * Registers for pins above a ARTPEC6_MAX_MUXABLE
0665          * do not have a SEL field and are always selected.
0666          */
0667         if (artpec6_pin_groups[group].pins[i] > ARTPEC6_MAX_MUXABLE)
0668             continue;
0669 
0670         if (!strcmp(artpec6_pmx_get_fname(pctldev, function), "gpio")) {
0671             /* GPIO is always config 0 */
0672             val = ARTPEC6_CONFIG_0 << ARTPEC6_PINMUX_SEL_SHIFT;
0673         } else {
0674             if (enable)
0675                 val = artpec6_pin_groups[group].config
0676                     << ARTPEC6_PINMUX_SEL_SHIFT;
0677             else
0678                 val = ARTPEC6_CONFIG_0
0679                     << ARTPEC6_PINMUX_SEL_SHIFT;
0680         }
0681 
0682         reg = artpec6_pmx_reg_offset(artpec6_pin_groups[group].pins[i]);
0683 
0684         regval = readl(pmx->base + reg);
0685         regval &= ~ARTPEC6_PINMUX_SEL_MASK;
0686         regval |= val;
0687         writel(regval, pmx->base + reg);
0688     }
0689 }
0690 
0691 static int artpec6_pmx_set(struct pinctrl_dev *pctldev,
0692                unsigned int function,
0693                unsigned int group)
0694 {
0695     struct artpec6_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
0696 
0697     dev_dbg(pmx->dev, "enabling %s function for pin group %s\n",
0698         artpec6_pmx_get_fname(pctldev, function),
0699         artpec6_get_group_name(pctldev, group));
0700 
0701     artpec6_pmx_select_func(pctldev, function, group, true);
0702 
0703     return 0;
0704 }
0705 
0706 static int artpec6_pmx_request_gpio(struct pinctrl_dev *pctldev,
0707                     struct pinctrl_gpio_range *range,
0708                     unsigned int pin)
0709 {
0710     struct artpec6_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
0711     unsigned int reg = artpec6_pmx_reg_offset(pin);
0712     u32 val;
0713 
0714     if (pin >= 32)
0715         return -EINVAL;
0716 
0717     val = readl_relaxed(pmx->base + reg);
0718     val &= ~ARTPEC6_PINMUX_SEL_MASK;
0719     val |= ARTPEC6_CONFIG_0 << ARTPEC6_PINMUX_SEL_SHIFT;
0720     writel_relaxed(val, pmx->base + reg);
0721 
0722     return 0;
0723 }
0724 
0725 static const struct pinmux_ops artpec6_pmx_ops = {
0726     .get_functions_count    = artpec6_pmx_get_functions_count,
0727     .get_function_name  = artpec6_pmx_get_fname,
0728     .get_function_groups    = artpec6_pmx_get_fgroups,
0729     .set_mux        = artpec6_pmx_set,
0730     .gpio_request_enable = artpec6_pmx_request_gpio,
0731 };
0732 
0733 static int artpec6_pconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
0734                  unsigned long *config)
0735 {
0736     struct artpec6_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
0737     enum pin_config_param param = pinconf_to_config_param(*config);
0738     unsigned int regval;
0739 
0740     /* Check for valid pin */
0741     if (pin >= pmx->num_pins) {
0742         dev_dbg(pmx->dev, "pinconf is not supported for pin %s\n",
0743             pmx->pins[pin].name);
0744         return -ENOTSUPP;
0745     }
0746 
0747     dev_dbg(pmx->dev, "getting configuration for pin %s\n",
0748         pmx->pins[pin].name);
0749 
0750     /* Read pin register values */
0751     regval = readl(pmx->base + artpec6_pmx_reg_offset(pin));
0752 
0753     /* If valid, get configuration for parameter */
0754     switch (param) {
0755     case PIN_CONFIG_BIAS_DISABLE:
0756         if (!(regval & ARTPEC6_PINMUX_UDC1_MASK))
0757             return -EINVAL;
0758         break;
0759 
0760     case PIN_CONFIG_BIAS_PULL_UP:
0761     case PIN_CONFIG_BIAS_PULL_DOWN:
0762         if (regval & ARTPEC6_PINMUX_UDC1_MASK)
0763             return -EINVAL;
0764 
0765         regval = regval & ARTPEC6_PINMUX_UDC0_MASK;
0766         if ((param == PIN_CONFIG_BIAS_PULL_UP && !regval) ||
0767             (param == PIN_CONFIG_BIAS_PULL_DOWN && regval))
0768             return -EINVAL;
0769         break;
0770     case PIN_CONFIG_DRIVE_STRENGTH:
0771         regval = (regval & ARTPEC6_PINMUX_DRV_MASK)
0772             >> ARTPEC6_PINMUX_DRV_SHIFT;
0773         regval = artpec6_pconf_drive_field_to_mA(regval);
0774         *config = pinconf_to_config_packed(param, regval);
0775         break;
0776     default:
0777         return -ENOTSUPP;
0778     }
0779 
0780     return 0;
0781 }
0782 
0783 /*
0784  * Valid combinations of param and arg:
0785  *
0786  * param             arg
0787  * PIN_CONFIG_BIAS_DISABLE:   x (disable bias)
0788  * PIN_CONFIG_BIAS_PULL_UP:   1 (pull up bias + enable)
0789  * PIN_CONFIG_BIAS_PULL_DOWN: 1 (pull down bias + enable)
0790  * PIN_CONFIG_DRIVE_STRENGTH: x (4mA, 6mA, 8mA, 9mA)
0791  *
0792  * All other args are invalid. All other params are not supported.
0793  */
0794 static int artpec6_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
0795                  unsigned long *configs, unsigned int num_configs)
0796 {
0797     struct artpec6_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
0798     enum pin_config_param param;
0799     unsigned int arg;
0800     unsigned int regval;
0801     void __iomem *reg;
0802     int i;
0803 
0804     /* Check for valid pin */
0805     if (pin >= pmx->num_pins) {
0806         dev_dbg(pmx->dev, "pinconf is not supported for pin %s\n",
0807             pmx->pins[pin].name);
0808         return -ENOTSUPP;
0809     }
0810 
0811     dev_dbg(pmx->dev, "setting configuration for pin %s\n",
0812         pmx->pins[pin].name);
0813 
0814     reg = pmx->base + artpec6_pmx_reg_offset(pin);
0815 
0816     /* For each config */
0817     for (i = 0; i < num_configs; i++) {
0818         int drive;
0819 
0820         param = pinconf_to_config_param(configs[i]);
0821         arg = pinconf_to_config_argument(configs[i]);
0822 
0823         switch (param) {
0824         case PIN_CONFIG_BIAS_DISABLE:
0825             regval = readl(reg);
0826             regval |= (1 << ARTPEC6_PINMUX_UDC1_SHIFT);
0827             writel(regval, reg);
0828             break;
0829 
0830         case PIN_CONFIG_BIAS_PULL_UP:
0831             if (arg != 1) {
0832                 dev_dbg(pctldev->dev, "%s: arg %u out of range\n",
0833                     __func__, arg);
0834                 return -EINVAL;
0835             }
0836 
0837             regval = readl(reg);
0838             regval |= (arg << ARTPEC6_PINMUX_UDC0_SHIFT);
0839             regval &= ~ARTPEC6_PINMUX_UDC1_MASK; /* Enable */
0840             writel(regval, reg);
0841             break;
0842 
0843         case PIN_CONFIG_BIAS_PULL_DOWN:
0844             if (arg != 1) {
0845                 dev_dbg(pctldev->dev, "%s: arg %u out of range\n",
0846                     __func__, arg);
0847                 return -EINVAL;
0848             }
0849 
0850             regval = readl(reg);
0851             regval &= ~(arg << ARTPEC6_PINMUX_UDC0_SHIFT);
0852             regval &= ~ARTPEC6_PINMUX_UDC1_MASK; /* Enable */
0853             writel(regval, reg);
0854             break;
0855 
0856         case PIN_CONFIG_DRIVE_STRENGTH:
0857             drive = artpec6_pconf_drive_mA_to_field(arg);
0858             if (drive < 0) {
0859                 dev_dbg(pctldev->dev, "%s: arg %u out of range\n",
0860                     __func__, arg);
0861                 return -EINVAL;
0862             }
0863 
0864             regval = readl(reg);
0865             regval &= ~ARTPEC6_PINMUX_DRV_MASK;
0866             regval |= (drive << ARTPEC6_PINMUX_DRV_SHIFT);
0867             writel(regval, reg);
0868             break;
0869 
0870         default:
0871             dev_dbg(pmx->dev, "parameter not supported\n");
0872             return -ENOTSUPP;
0873         }
0874     }
0875 
0876     return 0;
0877 }
0878 
0879 static int artpec6_pconf_group_set(struct pinctrl_dev *pctldev,
0880                    unsigned int group, unsigned long *configs,
0881                    unsigned int num_configs)
0882 {
0883     unsigned int num_pins, current_pin;
0884     int ret;
0885 
0886     dev_dbg(pctldev->dev, "setting group %s configuration\n",
0887         artpec6_get_group_name(pctldev, group));
0888 
0889     num_pins = artpec6_pin_groups[group].num_pins;
0890 
0891     for (current_pin = 0; current_pin < num_pins; current_pin++) {
0892         ret = artpec6_pconf_set(pctldev,
0893                 artpec6_pin_groups[group].pins[current_pin],
0894                 configs, num_configs);
0895 
0896         if (ret < 0)
0897             return ret;
0898     }
0899 
0900     return 0;
0901 }
0902 
0903 static const struct pinconf_ops artpec6_pconf_ops = {
0904     .is_generic     = true,
0905     .pin_config_get     = artpec6_pconf_get,
0906     .pin_config_set     = artpec6_pconf_set,
0907     .pin_config_group_set   = artpec6_pconf_group_set,
0908 };
0909 
0910 static struct pinctrl_desc artpec6_desc = {
0911     .name    = "artpec6-pinctrl",
0912     .owner   = THIS_MODULE,
0913     .pins    = artpec6_pins,
0914     .npins   = ARRAY_SIZE(artpec6_pins),
0915     .pctlops = &artpec6_pctrl_ops,
0916     .pmxops  = &artpec6_pmx_ops,
0917     .confops = &artpec6_pconf_ops,
0918 };
0919 
0920 /* The reset values say 4mA, but we want 8mA as default. */
0921 static void artpec6_pmx_reset(struct artpec6_pmx *pmx)
0922 {
0923     void __iomem *base = pmx->base;
0924     int i;
0925 
0926     for (i = 0; i < ARTPEC6_LAST_PIN; i++) {
0927         u32 val;
0928 
0929         val = readl_relaxed(base + artpec6_pmx_reg_offset(i));
0930         val &= ~ARTPEC6_PINMUX_DRV_MASK;
0931         val |= ARTPEC6_DRIVE_8mA_SET << ARTPEC6_PINMUX_DRV_SHIFT;
0932         writel_relaxed(val, base + artpec6_pmx_reg_offset(i));
0933     }
0934 }
0935 
0936 static int artpec6_pmx_probe(struct platform_device *pdev)
0937 {
0938     struct artpec6_pmx *pmx;
0939 
0940     pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
0941     if (!pmx)
0942         return -ENOMEM;
0943 
0944     pmx->dev = &pdev->dev;
0945 
0946     pmx->base = devm_platform_ioremap_resource(pdev, 0);
0947 
0948     if (IS_ERR(pmx->base))
0949         return PTR_ERR(pmx->base);
0950 
0951     artpec6_pmx_reset(pmx);
0952 
0953     pmx->pins       = artpec6_pins;
0954     pmx->num_pins       = ARRAY_SIZE(artpec6_pins);
0955     pmx->functions      = artpec6_pmx_functions;
0956     pmx->num_functions  = ARRAY_SIZE(artpec6_pmx_functions);
0957     pmx->pin_groups     = artpec6_pin_groups;
0958     pmx->num_pin_groups = ARRAY_SIZE(artpec6_pin_groups);
0959     pmx->pctl       = pinctrl_register(&artpec6_desc, &pdev->dev, pmx);
0960 
0961     if (IS_ERR(pmx->pctl)) {
0962         dev_err(&pdev->dev, "could not register pinctrl driver\n");
0963         return PTR_ERR(pmx->pctl);
0964     }
0965 
0966     platform_set_drvdata(pdev, pmx);
0967 
0968     dev_info(&pdev->dev, "initialised Axis ARTPEC-6 pinctrl driver\n");
0969 
0970     return 0;
0971 }
0972 
0973 static int artpec6_pmx_remove(struct platform_device *pdev)
0974 {
0975     struct artpec6_pmx *pmx = platform_get_drvdata(pdev);
0976 
0977     pinctrl_unregister(pmx->pctl);
0978 
0979     return 0;
0980 }
0981 
0982 static const struct of_device_id artpec6_pinctrl_match[] = {
0983     { .compatible = "axis,artpec6-pinctrl" },
0984     {},
0985 };
0986 
0987 static struct platform_driver artpec6_pmx_driver = {
0988     .driver = {
0989         .name = "artpec6-pinctrl",
0990         .of_match_table = artpec6_pinctrl_match,
0991     },
0992     .probe = artpec6_pmx_probe,
0993     .remove = artpec6_pmx_remove,
0994 };
0995 
0996 static int __init artpec6_pmx_init(void)
0997 {
0998     return platform_driver_register(&artpec6_pmx_driver);
0999 }
1000 arch_initcall(artpec6_pmx_init);
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