Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Apple SoC pinctrl+GPIO+external IRQ driver
0004  *
0005  * Copyright (C) The Asahi Linux Contributors
0006  * Copyright (C) 2020 Corellium LLC
0007  *
0008  * Based on: pinctrl-pistachio.c
0009  * Copyright (C) 2014 Imagination Technologies Ltd.
0010  * Copyright (C) 2014 Google, Inc.
0011  */
0012 
0013 #include <dt-bindings/pinctrl/apple.h>
0014 #include <linux/bits.h>
0015 #include <linux/gpio/driver.h>
0016 #include <linux/interrupt.h>
0017 #include <linux/irq.h>
0018 #include <linux/module.h>
0019 #include <linux/of.h>
0020 #include <linux/of_irq.h>
0021 #include <linux/pinctrl/pinctrl.h>
0022 #include <linux/pinctrl/pinmux.h>
0023 #include <linux/platform_device.h>
0024 #include <linux/regmap.h>
0025 
0026 #include "pinctrl-utils.h"
0027 #include "core.h"
0028 #include "pinmux.h"
0029 
0030 struct apple_gpio_pinctrl {
0031     struct device *dev;
0032     struct pinctrl_dev *pctldev;
0033 
0034     void __iomem *base;
0035     struct regmap *map;
0036 
0037     struct pinctrl_desc pinctrl_desc;
0038     struct gpio_chip gpio_chip;
0039     u8 irqgrps[];
0040 };
0041 
0042 #define REG_GPIO(x)          (4 * (x))
0043 #define REG_GPIOx_DATA       BIT(0)
0044 #define REG_GPIOx_MODE       GENMASK(3, 1)
0045 #define REG_GPIOx_OUT        1
0046 #define REG_GPIOx_IN_IRQ_HI  2
0047 #define REG_GPIOx_IN_IRQ_LO  3
0048 #define REG_GPIOx_IN_IRQ_UP  4
0049 #define REG_GPIOx_IN_IRQ_DN  5
0050 #define REG_GPIOx_IN_IRQ_ANY 6
0051 #define REG_GPIOx_IN_IRQ_OFF 7
0052 #define REG_GPIOx_PERIPH     GENMASK(6, 5)
0053 #define REG_GPIOx_PULL       GENMASK(8, 7)
0054 #define REG_GPIOx_PULL_OFF   0
0055 #define REG_GPIOx_PULL_DOWN  1
0056 #define REG_GPIOx_PULL_UP_STRONG 2
0057 #define REG_GPIOx_PULL_UP    3
0058 #define REG_GPIOx_INPUT_ENABLE BIT(9)
0059 #define REG_GPIOx_DRIVE_STRENGTH0 GENMASK(11, 10)
0060 #define REG_GPIOx_SCHMITT    BIT(15)
0061 #define REG_GPIOx_GRP        GENMASK(18, 16)
0062 #define REG_GPIOx_LOCK       BIT(21)
0063 #define REG_GPIOx_DRIVE_STRENGTH1 GENMASK(23, 22)
0064 #define REG_IRQ(g, x)        (0x800 + 0x40 * (g) + 4 * ((x) >> 5))
0065 
0066 struct regmap_config regmap_config = {
0067     .reg_bits = 32,
0068     .val_bits = 32,
0069     .reg_stride = 4,
0070     .cache_type = REGCACHE_FLAT,
0071     .max_register = 512 * sizeof(u32),
0072     .num_reg_defaults_raw = 512,
0073     .use_relaxed_mmio = true,
0074     .use_raw_spinlock = true,
0075 };
0076 
0077 /* No locking needed to mask/unmask IRQs as the interrupt mode is per pin-register. */
0078 static void apple_gpio_set_reg(struct apple_gpio_pinctrl *pctl,
0079                                unsigned int pin, u32 mask, u32 value)
0080 {
0081     regmap_update_bits(pctl->map, REG_GPIO(pin), mask, value);
0082 }
0083 
0084 static u32 apple_gpio_get_reg(struct apple_gpio_pinctrl *pctl,
0085                               unsigned int pin)
0086 {
0087     int ret;
0088     u32 val;
0089 
0090     ret = regmap_read(pctl->map, REG_GPIO(pin), &val);
0091     if (ret)
0092         return 0;
0093 
0094     return val;
0095 }
0096 
0097 /* Pin controller functions */
0098 
0099 static int apple_gpio_dt_node_to_map(struct pinctrl_dev *pctldev,
0100                                      struct device_node *node,
0101                                      struct pinctrl_map **map,
0102                                      unsigned *num_maps)
0103 {
0104     unsigned reserved_maps;
0105     struct apple_gpio_pinctrl *pctl;
0106     u32 pinfunc, pin, func;
0107     int num_pins, i, ret;
0108     const char *group_name;
0109     const char *function_name;
0110 
0111     *map = NULL;
0112     *num_maps = 0;
0113     reserved_maps = 0;
0114 
0115     pctl = pinctrl_dev_get_drvdata(pctldev);
0116 
0117     ret = of_property_count_u32_elems(node, "pinmux");
0118     if (ret <= 0) {
0119         dev_err(pctl->dev,
0120             "missing or empty pinmux property in node %pOFn.\n",
0121             node);
0122         return ret ? ret : -EINVAL;
0123     }
0124 
0125     num_pins = ret;
0126 
0127     ret = pinctrl_utils_reserve_map(pctldev, map, &reserved_maps, num_maps, num_pins);
0128     if (ret)
0129         return ret;
0130 
0131     for (i = 0; i < num_pins; i++) {
0132         ret = of_property_read_u32_index(node, "pinmux", i, &pinfunc);
0133         if (ret)
0134             goto free_map;
0135 
0136         pin = APPLE_PIN(pinfunc);
0137         func = APPLE_FUNC(pinfunc);
0138 
0139         if (func >= pinmux_generic_get_function_count(pctldev)) {
0140             ret = -EINVAL;
0141             goto free_map;
0142         }
0143 
0144         group_name = pinctrl_generic_get_group_name(pctldev, pin);
0145         function_name = pinmux_generic_get_function_name(pctl->pctldev, func);
0146         ret = pinctrl_utils_add_map_mux(pctl->pctldev, map,
0147                                         &reserved_maps, num_maps,
0148                                         group_name, function_name);
0149         if (ret)
0150             goto free_map;
0151     }
0152 
0153 free_map:
0154     if (ret < 0)
0155         pinctrl_utils_free_map(pctldev, *map, *num_maps);
0156 
0157     return ret;
0158 }
0159 
0160 static const struct pinctrl_ops apple_gpio_pinctrl_ops = {
0161     .get_groups_count = pinctrl_generic_get_group_count,
0162     .get_group_name = pinctrl_generic_get_group_name,
0163     .get_group_pins = pinctrl_generic_get_group_pins,
0164     .dt_node_to_map = apple_gpio_dt_node_to_map,
0165     .dt_free_map = pinctrl_utils_free_map,
0166 };
0167 
0168 /* Pin multiplexer functions */
0169 
0170 static int apple_gpio_pinmux_set(struct pinctrl_dev *pctldev, unsigned func,
0171                                  unsigned group)
0172 {
0173     struct apple_gpio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0174 
0175     apple_gpio_set_reg(
0176         pctl, group, REG_GPIOx_PERIPH | REG_GPIOx_INPUT_ENABLE,
0177         FIELD_PREP(REG_GPIOx_PERIPH, func) | REG_GPIOx_INPUT_ENABLE);
0178 
0179     return 0;
0180 }
0181 
0182 static const struct pinmux_ops apple_gpio_pinmux_ops = {
0183     .get_functions_count = pinmux_generic_get_function_count,
0184     .get_function_name = pinmux_generic_get_function_name,
0185     .get_function_groups = pinmux_generic_get_function_groups,
0186     .set_mux = apple_gpio_pinmux_set,
0187     .strict = true,
0188 };
0189 
0190 /* GPIO chip functions */
0191 
0192 static int apple_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
0193 {
0194     struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
0195     unsigned int reg = apple_gpio_get_reg(pctl, offset);
0196 
0197     if (FIELD_GET(REG_GPIOx_MODE, reg) == REG_GPIOx_OUT)
0198         return GPIO_LINE_DIRECTION_OUT;
0199     return GPIO_LINE_DIRECTION_IN;
0200 }
0201 
0202 static int apple_gpio_get(struct gpio_chip *chip, unsigned offset)
0203 {
0204     struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
0205     unsigned int reg = apple_gpio_get_reg(pctl, offset);
0206 
0207     /*
0208      * If this is an input GPIO, read the actual value (not the
0209      * cached regmap value)
0210      */
0211     if (FIELD_GET(REG_GPIOx_MODE, reg) != REG_GPIOx_OUT)
0212         reg = readl_relaxed(pctl->base + REG_GPIO(offset));
0213 
0214     return !!(reg & REG_GPIOx_DATA);
0215 }
0216 
0217 static void apple_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
0218 {
0219     struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
0220 
0221     apple_gpio_set_reg(pctl, offset, REG_GPIOx_DATA, value ? REG_GPIOx_DATA : 0);
0222 }
0223 
0224 static int apple_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
0225 {
0226     struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
0227 
0228     apple_gpio_set_reg(pctl, offset,
0229                REG_GPIOx_PERIPH | REG_GPIOx_MODE | REG_GPIOx_DATA |
0230                    REG_GPIOx_INPUT_ENABLE,
0231                FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_IN_IRQ_OFF) |
0232                    REG_GPIOx_INPUT_ENABLE);
0233     return 0;
0234 }
0235 
0236 static int apple_gpio_direction_output(struct gpio_chip *chip,
0237                                        unsigned int offset, int value)
0238 {
0239     struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
0240 
0241     apple_gpio_set_reg(pctl, offset,
0242                REG_GPIOx_PERIPH | REG_GPIOx_MODE | REG_GPIOx_DATA,
0243                FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_OUT) |
0244                    (value ? REG_GPIOx_DATA : 0));
0245     return 0;
0246 }
0247 
0248 /* IRQ chip functions */
0249 
0250 static void apple_gpio_irq_ack(struct irq_data *data)
0251 {
0252     struct apple_gpio_pinctrl *pctl = gpiochip_get_data(irq_data_get_irq_chip_data(data));
0253     unsigned int irqgrp = FIELD_GET(REG_GPIOx_GRP, apple_gpio_get_reg(pctl, data->hwirq));
0254 
0255     writel(BIT(data->hwirq % 32), pctl->base + REG_IRQ(irqgrp, data->hwirq));
0256 }
0257 
0258 static unsigned int apple_gpio_irq_type(unsigned int type)
0259 {
0260     switch (type & IRQ_TYPE_SENSE_MASK) {
0261     case IRQ_TYPE_EDGE_RISING:
0262         return REG_GPIOx_IN_IRQ_UP;
0263     case IRQ_TYPE_EDGE_FALLING:
0264         return REG_GPIOx_IN_IRQ_DN;
0265     case IRQ_TYPE_EDGE_BOTH:
0266         return REG_GPIOx_IN_IRQ_ANY;
0267     case IRQ_TYPE_LEVEL_HIGH:
0268         return REG_GPIOx_IN_IRQ_HI;
0269     case IRQ_TYPE_LEVEL_LOW:
0270         return REG_GPIOx_IN_IRQ_LO;
0271     default:
0272         return REG_GPIOx_IN_IRQ_OFF;
0273     }
0274 }
0275 
0276 static void apple_gpio_irq_mask(struct irq_data *data)
0277 {
0278     struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
0279     struct apple_gpio_pinctrl *pctl = gpiochip_get_data(gc);
0280 
0281     apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE,
0282                        FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_IN_IRQ_OFF));
0283     gpiochip_disable_irq(gc, data->hwirq);
0284 }
0285 
0286 static void apple_gpio_irq_unmask(struct irq_data *data)
0287 {
0288     struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
0289     struct apple_gpio_pinctrl *pctl = gpiochip_get_data(gc);
0290     unsigned int irqtype = apple_gpio_irq_type(irqd_get_trigger_type(data));
0291 
0292     gpiochip_enable_irq(gc, data->hwirq);
0293     apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE,
0294                        FIELD_PREP(REG_GPIOx_MODE, irqtype));
0295 }
0296 
0297 static unsigned int apple_gpio_irq_startup(struct irq_data *data)
0298 {
0299     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
0300     struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
0301 
0302     apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_GRP,
0303                        FIELD_PREP(REG_GPIOx_GRP, 0));
0304 
0305     apple_gpio_direction_input(chip, data->hwirq);
0306     apple_gpio_irq_unmask(data);
0307 
0308     return 0;
0309 }
0310 
0311 static int apple_gpio_irq_set_type(struct irq_data *data, unsigned int type)
0312 {
0313     struct apple_gpio_pinctrl *pctl = gpiochip_get_data(irq_data_get_irq_chip_data(data));
0314     unsigned int irqtype = apple_gpio_irq_type(type);
0315 
0316     if (irqtype == REG_GPIOx_IN_IRQ_OFF)
0317         return -EINVAL;
0318 
0319     apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE,
0320                        FIELD_PREP(REG_GPIOx_MODE, irqtype));
0321 
0322     if (type & IRQ_TYPE_LEVEL_MASK)
0323         irq_set_handler_locked(data, handle_level_irq);
0324     else
0325         irq_set_handler_locked(data, handle_edge_irq);
0326     return 0;
0327 }
0328 
0329 static void apple_gpio_irq_handler(struct irq_desc *desc)
0330 {
0331     struct irq_chip *chip = irq_desc_get_chip(desc);
0332     u8 *grpp = irq_desc_get_handler_data(desc);
0333     struct apple_gpio_pinctrl *pctl;
0334     unsigned int pinh, pinl;
0335     unsigned long pending;
0336     struct gpio_chip *gc;
0337 
0338     pctl = container_of(grpp - *grpp, typeof(*pctl), irqgrps[0]);
0339     gc = &pctl->gpio_chip;
0340 
0341     chained_irq_enter(chip, desc);
0342     for (pinh = 0; pinh < gc->ngpio; pinh += 32) {
0343         pending = readl_relaxed(pctl->base + REG_IRQ(*grpp, pinh));
0344         for_each_set_bit(pinl, &pending, 32)
0345             generic_handle_domain_irq(gc->irq.domain, pinh + pinl);
0346     }
0347     chained_irq_exit(chip, desc);
0348 }
0349 
0350 static const struct irq_chip apple_gpio_irqchip = {
0351     .name           = "Apple-GPIO",
0352     .irq_startup        = apple_gpio_irq_startup,
0353     .irq_ack        = apple_gpio_irq_ack,
0354     .irq_mask       = apple_gpio_irq_mask,
0355     .irq_unmask     = apple_gpio_irq_unmask,
0356     .irq_set_type       = apple_gpio_irq_set_type,
0357     .flags          = IRQCHIP_IMMUTABLE,
0358     GPIOCHIP_IRQ_RESOURCE_HELPERS,
0359 };
0360 
0361 /* Probe & register */
0362 
0363 static int apple_gpio_register(struct apple_gpio_pinctrl *pctl)
0364 {
0365     struct gpio_irq_chip *girq = &pctl->gpio_chip.irq;
0366     void **irq_data = NULL;
0367     int ret;
0368 
0369     pctl->gpio_chip.label = dev_name(pctl->dev);
0370     pctl->gpio_chip.request = gpiochip_generic_request;
0371     pctl->gpio_chip.free = gpiochip_generic_free;
0372     pctl->gpio_chip.get_direction = apple_gpio_get_direction;
0373     pctl->gpio_chip.direction_input = apple_gpio_direction_input;
0374     pctl->gpio_chip.direction_output = apple_gpio_direction_output;
0375     pctl->gpio_chip.get = apple_gpio_get;
0376     pctl->gpio_chip.set = apple_gpio_set;
0377     pctl->gpio_chip.base = -1;
0378     pctl->gpio_chip.ngpio = pctl->pinctrl_desc.npins;
0379     pctl->gpio_chip.parent = pctl->dev;
0380 
0381     if (girq->num_parents) {
0382         int i;
0383 
0384         gpio_irq_chip_set_chip(girq, &apple_gpio_irqchip);
0385         girq->parent_handler = apple_gpio_irq_handler;
0386 
0387         girq->parents = kmalloc_array(girq->num_parents,
0388                           sizeof(*girq->parents),
0389                           GFP_KERNEL);
0390         irq_data = kmalloc_array(girq->num_parents, sizeof(*irq_data),
0391                      GFP_KERNEL);
0392         if (!girq->parents || !irq_data) {
0393             ret = -ENOMEM;
0394             goto out_free_irq_data;
0395         }
0396 
0397         for (i = 0; i < girq->num_parents; i++) {
0398             ret = platform_get_irq(to_platform_device(pctl->dev), i);
0399             if (ret < 0)
0400                 goto out_free_irq_data;
0401 
0402             girq->parents[i] = ret;
0403             pctl->irqgrps[i] = i;
0404             irq_data[i] = &pctl->irqgrps[i];
0405         }
0406 
0407         girq->parent_handler_data_array = irq_data;
0408         girq->per_parent_data = true;
0409         girq->default_type = IRQ_TYPE_NONE;
0410         girq->handler = handle_level_irq;
0411     }
0412 
0413     ret = devm_gpiochip_add_data(pctl->dev, &pctl->gpio_chip, pctl);
0414 
0415 out_free_irq_data:
0416     kfree(girq->parents);
0417     kfree(irq_data);
0418 
0419     return ret;
0420 }
0421 
0422 static int apple_gpio_pinctrl_probe(struct platform_device *pdev)
0423 {
0424     struct apple_gpio_pinctrl *pctl;
0425     struct pinctrl_pin_desc *pins;
0426     unsigned int npins;
0427     const char **pin_names;
0428     unsigned int *pin_nums;
0429     static const char* pinmux_functions[] = {
0430         "gpio", "periph1", "periph2", "periph3"
0431     };
0432     unsigned int i, nirqs = 0;
0433     int res;
0434 
0435     if (of_property_read_bool(pdev->dev.of_node, "interrupt-controller")) {
0436         res = platform_irq_count(pdev);
0437         if (res > 0)
0438             nirqs = res;
0439     }
0440 
0441     pctl = devm_kzalloc(&pdev->dev, struct_size(pctl, irqgrps, nirqs),
0442                 GFP_KERNEL);
0443     if (!pctl)
0444         return -ENOMEM;
0445     pctl->dev = &pdev->dev;
0446     pctl->gpio_chip.irq.num_parents = nirqs;
0447     dev_set_drvdata(&pdev->dev, pctl);
0448 
0449     if (of_property_read_u32(pdev->dev.of_node, "apple,npins", &npins))
0450         return dev_err_probe(&pdev->dev, -EINVAL,
0451                      "apple,npins property not found\n");
0452 
0453     pins = devm_kmalloc_array(&pdev->dev, npins, sizeof(pins[0]),
0454                   GFP_KERNEL);
0455     pin_names = devm_kmalloc_array(&pdev->dev, npins, sizeof(pin_names[0]),
0456                        GFP_KERNEL);
0457     pin_nums = devm_kmalloc_array(&pdev->dev, npins, sizeof(pin_nums[0]),
0458                       GFP_KERNEL);
0459     if (!pins || !pin_names || !pin_nums)
0460         return -ENOMEM;
0461 
0462     pctl->base = devm_platform_ioremap_resource(pdev, 0);
0463     if (IS_ERR(pctl->base))
0464         return PTR_ERR(pctl->base);
0465 
0466     pctl->map = devm_regmap_init_mmio(&pdev->dev, pctl->base, &regmap_config);
0467     if (IS_ERR(pctl->map))
0468         return dev_err_probe(&pdev->dev, PTR_ERR(pctl->map),
0469                      "Failed to create regmap\n");
0470 
0471     for (i = 0; i < npins; i++) {
0472         pins[i].number = i;
0473         pins[i].name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "PIN%u", i);
0474         pins[i].drv_data = pctl;
0475         pin_names[i] = pins[i].name;
0476         pin_nums[i] = i;
0477     }
0478 
0479     pctl->pinctrl_desc.name = dev_name(pctl->dev);
0480     pctl->pinctrl_desc.pins = pins;
0481     pctl->pinctrl_desc.npins = npins;
0482     pctl->pinctrl_desc.pctlops = &apple_gpio_pinctrl_ops;
0483     pctl->pinctrl_desc.pmxops = &apple_gpio_pinmux_ops;
0484 
0485     pctl->pctldev = devm_pinctrl_register(&pdev->dev, &pctl->pinctrl_desc, pctl);
0486     if (IS_ERR(pctl->pctldev))
0487         return dev_err_probe(&pdev->dev, PTR_ERR(pctl->pctldev),
0488                      "Failed to register pinctrl device.\n");
0489 
0490     for (i = 0; i < npins; i++) {
0491         res = pinctrl_generic_add_group(pctl->pctldev, pins[i].name,
0492                         pin_nums + i, 1, pctl);
0493         if (res < 0)
0494             return dev_err_probe(pctl->dev, res,
0495                          "Failed to register group");
0496     }
0497 
0498     for (i = 0; i < ARRAY_SIZE(pinmux_functions); ++i) {
0499         res = pinmux_generic_add_function(pctl->pctldev, pinmux_functions[i],
0500                           pin_names, npins, pctl);
0501         if (res < 0)
0502             return dev_err_probe(pctl->dev, res,
0503                          "Failed to register function.");
0504     }
0505 
0506     return apple_gpio_register(pctl);
0507 }
0508 
0509 static const struct of_device_id apple_gpio_pinctrl_of_match[] = {
0510     { .compatible = "apple,pinctrl", },
0511     { }
0512 };
0513 MODULE_DEVICE_TABLE(of, apple_gpio_pinctrl_of_match);
0514 
0515 static struct platform_driver apple_gpio_pinctrl_driver = {
0516     .driver = {
0517         .name = "apple-gpio-pinctrl",
0518         .of_match_table = apple_gpio_pinctrl_of_match,
0519         .suppress_bind_attrs = true,
0520     },
0521     .probe = apple_gpio_pinctrl_probe,
0522 };
0523 module_platform_driver(apple_gpio_pinctrl_driver);
0524 
0525 MODULE_DESCRIPTION("Apple pinctrl/GPIO driver");
0526 MODULE_AUTHOR("Stan Skowronek <stan@corellium.com>");
0527 MODULE_AUTHOR("Joey Gouly <joey.gouly@arm.com>");
0528 MODULE_LICENSE("GPL v2");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!