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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * GPIO driver for AMD
0004  *
0005  * Copyright (c) 2014,2015 AMD Corporation.
0006  * Authors: Ken Xue <Ken.Xue@amd.com>
0007  *      Wu, Jeff <Jeff.Wu@amd.com>
0008  *
0009  */
0010 
0011 #include <linux/err.h>
0012 #include <linux/bug.h>
0013 #include <linux/kernel.h>
0014 #include <linux/module.h>
0015 #include <linux/spinlock.h>
0016 #include <linux/compiler.h>
0017 #include <linux/types.h>
0018 #include <linux/errno.h>
0019 #include <linux/log2.h>
0020 #include <linux/io.h>
0021 #include <linux/gpio/driver.h>
0022 #include <linux/slab.h>
0023 #include <linux/platform_device.h>
0024 #include <linux/mutex.h>
0025 #include <linux/acpi.h>
0026 #include <linux/seq_file.h>
0027 #include <linux/interrupt.h>
0028 #include <linux/list.h>
0029 #include <linux/bitops.h>
0030 #include <linux/pinctrl/pinconf.h>
0031 #include <linux/pinctrl/pinconf-generic.h>
0032 #include <linux/pinctrl/pinmux.h>
0033 
0034 #include "core.h"
0035 #include "pinctrl-utils.h"
0036 #include "pinctrl-amd.h"
0037 
0038 static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
0039 {
0040     unsigned long flags;
0041     u32 pin_reg;
0042     struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
0043 
0044     raw_spin_lock_irqsave(&gpio_dev->lock, flags);
0045     pin_reg = readl(gpio_dev->base + offset * 4);
0046     raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
0047 
0048     if (pin_reg & BIT(OUTPUT_ENABLE_OFF))
0049         return GPIO_LINE_DIRECTION_OUT;
0050 
0051     return GPIO_LINE_DIRECTION_IN;
0052 }
0053 
0054 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
0055 {
0056     unsigned long flags;
0057     u32 pin_reg;
0058     struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
0059 
0060     raw_spin_lock_irqsave(&gpio_dev->lock, flags);
0061     pin_reg = readl(gpio_dev->base + offset * 4);
0062     pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
0063     writel(pin_reg, gpio_dev->base + offset * 4);
0064     raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
0065 
0066     return 0;
0067 }
0068 
0069 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
0070         int value)
0071 {
0072     u32 pin_reg;
0073     unsigned long flags;
0074     struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
0075 
0076     raw_spin_lock_irqsave(&gpio_dev->lock, flags);
0077     pin_reg = readl(gpio_dev->base + offset * 4);
0078     pin_reg |= BIT(OUTPUT_ENABLE_OFF);
0079     if (value)
0080         pin_reg |= BIT(OUTPUT_VALUE_OFF);
0081     else
0082         pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
0083     writel(pin_reg, gpio_dev->base + offset * 4);
0084     raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
0085 
0086     return 0;
0087 }
0088 
0089 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
0090 {
0091     u32 pin_reg;
0092     unsigned long flags;
0093     struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
0094 
0095     raw_spin_lock_irqsave(&gpio_dev->lock, flags);
0096     pin_reg = readl(gpio_dev->base + offset * 4);
0097     raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
0098 
0099     return !!(pin_reg & BIT(PIN_STS_OFF));
0100 }
0101 
0102 static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
0103 {
0104     u32 pin_reg;
0105     unsigned long flags;
0106     struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
0107 
0108     raw_spin_lock_irqsave(&gpio_dev->lock, flags);
0109     pin_reg = readl(gpio_dev->base + offset * 4);
0110     if (value)
0111         pin_reg |= BIT(OUTPUT_VALUE_OFF);
0112     else
0113         pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
0114     writel(pin_reg, gpio_dev->base + offset * 4);
0115     raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
0116 }
0117 
0118 static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
0119         unsigned debounce)
0120 {
0121     u32 time;
0122     u32 pin_reg;
0123     int ret = 0;
0124     unsigned long flags;
0125     struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
0126 
0127     raw_spin_lock_irqsave(&gpio_dev->lock, flags);
0128     pin_reg = readl(gpio_dev->base + offset * 4);
0129 
0130     if (debounce) {
0131         pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
0132         pin_reg &= ~DB_TMR_OUT_MASK;
0133         /*
0134         Debounce    Debounce    Timer   Max
0135         TmrLarge    TmrOutUnit  Unit    Debounce
0136                             Time
0137         0   0   61 usec (2 RtcClk)  976 usec
0138         0   1   244 usec (8 RtcClk) 3.9 msec
0139         1   0   15.6 msec (512 RtcClk)  250 msec
0140         1   1   62.5 msec (2048 RtcClk) 1 sec
0141         */
0142 
0143         if (debounce < 61) {
0144             pin_reg |= 1;
0145             pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
0146             pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
0147         } else if (debounce < 976) {
0148             time = debounce / 61;
0149             pin_reg |= time & DB_TMR_OUT_MASK;
0150             pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
0151             pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
0152         } else if (debounce < 3900) {
0153             time = debounce / 244;
0154             pin_reg |= time & DB_TMR_OUT_MASK;
0155             pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
0156             pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
0157         } else if (debounce < 250000) {
0158             time = debounce / 15625;
0159             pin_reg |= time & DB_TMR_OUT_MASK;
0160             pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
0161             pin_reg |= BIT(DB_TMR_LARGE_OFF);
0162         } else if (debounce < 1000000) {
0163             time = debounce / 62500;
0164             pin_reg |= time & DB_TMR_OUT_MASK;
0165             pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
0166             pin_reg |= BIT(DB_TMR_LARGE_OFF);
0167         } else {
0168             pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
0169             ret = -EINVAL;
0170         }
0171     } else {
0172         pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
0173         pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
0174         pin_reg &= ~DB_TMR_OUT_MASK;
0175         pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
0176     }
0177     writel(pin_reg, gpio_dev->base + offset * 4);
0178     raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
0179 
0180     return ret;
0181 }
0182 
0183 static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset,
0184                    unsigned long config)
0185 {
0186     u32 debounce;
0187 
0188     if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
0189         return -ENOTSUPP;
0190 
0191     debounce = pinconf_to_config_argument(config);
0192     return amd_gpio_set_debounce(gc, offset, debounce);
0193 }
0194 
0195 #ifdef CONFIG_DEBUG_FS
0196 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
0197 {
0198     u32 pin_reg;
0199     u32 db_cntrl;
0200     unsigned long flags;
0201     unsigned int bank, i, pin_num;
0202     struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
0203 
0204     bool tmr_out_unit;
0205     bool tmr_large;
0206 
0207     char *level_trig;
0208     char *active_level;
0209     char *interrupt_enable;
0210     char *interrupt_mask;
0211     char *wake_cntrl0;
0212     char *wake_cntrl1;
0213     char *wake_cntrl2;
0214     char *pin_sts;
0215     char *pull_up_sel;
0216     char *pull_up_enable;
0217     char *pull_down_enable;
0218     char *orientation;
0219     char debounce_value[40];
0220     char *debounce_enable;
0221 
0222     for (bank = 0; bank < gpio_dev->hwbank_num; bank++) {
0223         unsigned int time = 0;
0224         unsigned int unit = 0;
0225 
0226         switch (bank) {
0227         case 0:
0228             i = 0;
0229             pin_num = AMD_GPIO_PINS_BANK0;
0230             break;
0231         case 1:
0232             i = 64;
0233             pin_num = AMD_GPIO_PINS_BANK1 + i;
0234             break;
0235         case 2:
0236             i = 128;
0237             pin_num = AMD_GPIO_PINS_BANK2 + i;
0238             break;
0239         case 3:
0240             i = 192;
0241             pin_num = AMD_GPIO_PINS_BANK3 + i;
0242             break;
0243         default:
0244             /* Illegal bank number, ignore */
0245             continue;
0246         }
0247         seq_printf(s, "GPIO bank%d\n", bank);
0248         for (; i < pin_num; i++) {
0249             seq_printf(s, "📌%d\t", i);
0250             raw_spin_lock_irqsave(&gpio_dev->lock, flags);
0251             pin_reg = readl(gpio_dev->base + i * 4);
0252             raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
0253 
0254             if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
0255                 u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) &
0256                         ACTIVE_LEVEL_MASK;
0257                 interrupt_enable = "+";
0258 
0259                 if (level == ACTIVE_LEVEL_HIGH)
0260                     active_level = "↑";
0261                 else if (level == ACTIVE_LEVEL_LOW)
0262                     active_level = "↓";
0263                 else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) &&
0264                      level == ACTIVE_LEVEL_BOTH)
0265                     active_level = "b";
0266                 else
0267                     active_level = "?";
0268 
0269                 if (pin_reg & BIT(LEVEL_TRIG_OFF))
0270                     level_trig = "level";
0271                 else
0272                     level_trig = " edge";
0273 
0274             } else {
0275                 interrupt_enable = "∅";
0276                 active_level = "∅";
0277                 level_trig = "    ∅";
0278             }
0279 
0280             if (pin_reg & BIT(INTERRUPT_MASK_OFF))
0281                 interrupt_mask = "-";
0282             else
0283                 interrupt_mask = "+";
0284             seq_printf(s, "int %s (🎭 %s)| active-%s| %s-🔫| ",
0285                    interrupt_enable,
0286                    interrupt_mask,
0287                    active_level,
0288                    level_trig);
0289 
0290             if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3))
0291                 wake_cntrl0 = "+";
0292             else
0293                 wake_cntrl0 = "∅";
0294             seq_printf(s, "S0i3 🌅 %s| ", wake_cntrl0);
0295 
0296             if (pin_reg & BIT(WAKE_CNTRL_OFF_S3))
0297                 wake_cntrl1 = "+";
0298             else
0299                 wake_cntrl1 = "∅";
0300             seq_printf(s, "S3 🌅 %s| ", wake_cntrl1);
0301 
0302             if (pin_reg & BIT(WAKE_CNTRL_OFF_S4))
0303                 wake_cntrl2 = "+";
0304             else
0305                 wake_cntrl2 = "∅";
0306             seq_printf(s, "S4/S5 🌅 %s| ", wake_cntrl2);
0307 
0308             if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
0309                 pull_up_enable = "+";
0310                 if (pin_reg & BIT(PULL_UP_SEL_OFF))
0311                     pull_up_sel = "8k";
0312                 else
0313                     pull_up_sel = "4k";
0314             } else {
0315                 pull_up_enable = "∅";
0316                 pull_up_sel = "  ";
0317             }
0318             seq_printf(s, "pull-↑ %s (%s)| ",
0319                    pull_up_enable,
0320                    pull_up_sel);
0321 
0322             if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF))
0323                 pull_down_enable = "+";
0324             else
0325                 pull_down_enable = "∅";
0326             seq_printf(s, "pull-↓ %s| ", pull_down_enable);
0327 
0328             if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
0329                 pin_sts = "output";
0330                 if (pin_reg & BIT(OUTPUT_VALUE_OFF))
0331                     orientation = "↑";
0332                 else
0333                     orientation = "↓";
0334             } else {
0335                 pin_sts = "input ";
0336                 if (pin_reg & BIT(PIN_STS_OFF))
0337                     orientation = "↑";
0338                 else
0339                     orientation = "↓";
0340             }
0341             seq_printf(s, "%s %s| ", pin_sts, orientation);
0342 
0343             db_cntrl = (DB_CNTRl_MASK << DB_CNTRL_OFF) & pin_reg;
0344             if (db_cntrl) {
0345                 tmr_out_unit = pin_reg & BIT(DB_TMR_OUT_UNIT_OFF);
0346                 tmr_large = pin_reg & BIT(DB_TMR_LARGE_OFF);
0347                 time = pin_reg & DB_TMR_OUT_MASK;
0348                 if (tmr_large) {
0349                     if (tmr_out_unit)
0350                         unit = 62500;
0351                     else
0352                         unit = 15625;
0353                 } else {
0354                     if (tmr_out_unit)
0355                         unit = 244;
0356                     else
0357                         unit = 61;
0358                 }
0359                 if ((DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF) == db_cntrl)
0360                     debounce_enable = "b +";
0361                 else if ((DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF) == db_cntrl)
0362                     debounce_enable = "↓ +";
0363                 else
0364                     debounce_enable = "↑ +";
0365 
0366             } else {
0367                 debounce_enable = "  ∅";
0368             }
0369             snprintf(debounce_value, sizeof(debounce_value), "%u", time * unit);
0370             seq_printf(s, "debounce %s (⏰ %sus)| ", debounce_enable, debounce_value);
0371             seq_printf(s, " 0x%x\n", pin_reg);
0372         }
0373     }
0374 }
0375 #else
0376 #define amd_gpio_dbg_show NULL
0377 #endif
0378 
0379 static void amd_gpio_irq_enable(struct irq_data *d)
0380 {
0381     u32 pin_reg;
0382     unsigned long flags;
0383     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0384     struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
0385 
0386     gpiochip_enable_irq(gc, d->hwirq);
0387 
0388     raw_spin_lock_irqsave(&gpio_dev->lock, flags);
0389     pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
0390     pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
0391     pin_reg |= BIT(INTERRUPT_MASK_OFF);
0392     writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
0393     raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
0394 }
0395 
0396 static void amd_gpio_irq_disable(struct irq_data *d)
0397 {
0398     u32 pin_reg;
0399     unsigned long flags;
0400     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0401     struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
0402 
0403     raw_spin_lock_irqsave(&gpio_dev->lock, flags);
0404     pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
0405     pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
0406     pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
0407     writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
0408     raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
0409 
0410     gpiochip_disable_irq(gc, d->hwirq);
0411 }
0412 
0413 static void amd_gpio_irq_mask(struct irq_data *d)
0414 {
0415     u32 pin_reg;
0416     unsigned long flags;
0417     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0418     struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
0419 
0420     raw_spin_lock_irqsave(&gpio_dev->lock, flags);
0421     pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
0422     pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
0423     writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
0424     raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
0425 }
0426 
0427 static void amd_gpio_irq_unmask(struct irq_data *d)
0428 {
0429     u32 pin_reg;
0430     unsigned long flags;
0431     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0432     struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
0433 
0434     raw_spin_lock_irqsave(&gpio_dev->lock, flags);
0435     pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
0436     pin_reg |= BIT(INTERRUPT_MASK_OFF);
0437     writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
0438     raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
0439 }
0440 
0441 static int amd_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
0442 {
0443     u32 pin_reg;
0444     unsigned long flags;
0445     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0446     struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
0447     u32 wake_mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3);
0448     int err;
0449 
0450     raw_spin_lock_irqsave(&gpio_dev->lock, flags);
0451     pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
0452 
0453     if (on)
0454         pin_reg |= wake_mask;
0455     else
0456         pin_reg &= ~wake_mask;
0457 
0458     writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
0459     raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
0460 
0461     if (on)
0462         err = enable_irq_wake(gpio_dev->irq);
0463     else
0464         err = disable_irq_wake(gpio_dev->irq);
0465 
0466     if (err)
0467         dev_err(&gpio_dev->pdev->dev, "failed to %s wake-up interrupt\n",
0468             on ? "enable" : "disable");
0469 
0470     return 0;
0471 }
0472 
0473 static void amd_gpio_irq_eoi(struct irq_data *d)
0474 {
0475     u32 reg;
0476     unsigned long flags;
0477     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0478     struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
0479 
0480     raw_spin_lock_irqsave(&gpio_dev->lock, flags);
0481     reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
0482     reg |= EOI_MASK;
0483     writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
0484     raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
0485 }
0486 
0487 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
0488 {
0489     int ret = 0;
0490     u32 pin_reg, pin_reg_irq_en, mask;
0491     unsigned long flags;
0492     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0493     struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
0494 
0495     raw_spin_lock_irqsave(&gpio_dev->lock, flags);
0496     pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
0497 
0498     switch (type & IRQ_TYPE_SENSE_MASK) {
0499     case IRQ_TYPE_EDGE_RISING:
0500         pin_reg &= ~BIT(LEVEL_TRIG_OFF);
0501         pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
0502         pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
0503         irq_set_handler_locked(d, handle_edge_irq);
0504         break;
0505 
0506     case IRQ_TYPE_EDGE_FALLING:
0507         pin_reg &= ~BIT(LEVEL_TRIG_OFF);
0508         pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
0509         pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
0510         irq_set_handler_locked(d, handle_edge_irq);
0511         break;
0512 
0513     case IRQ_TYPE_EDGE_BOTH:
0514         pin_reg &= ~BIT(LEVEL_TRIG_OFF);
0515         pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
0516         pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
0517         irq_set_handler_locked(d, handle_edge_irq);
0518         break;
0519 
0520     case IRQ_TYPE_LEVEL_HIGH:
0521         pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
0522         pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
0523         pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
0524         irq_set_handler_locked(d, handle_level_irq);
0525         break;
0526 
0527     case IRQ_TYPE_LEVEL_LOW:
0528         pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
0529         pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
0530         pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
0531         irq_set_handler_locked(d, handle_level_irq);
0532         break;
0533 
0534     case IRQ_TYPE_NONE:
0535         break;
0536 
0537     default:
0538         dev_err(&gpio_dev->pdev->dev, "Invalid type value\n");
0539         ret = -EINVAL;
0540     }
0541 
0542     pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
0543     /*
0544      * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the
0545      * debounce registers of any GPIO will block wake/interrupt status
0546      * generation for *all* GPIOs for a length of time that depends on
0547      * WAKE_INT_MASTER_REG.MaskStsLength[11:0].  During this period the
0548      * INTERRUPT_ENABLE bit will read as 0.
0549      *
0550      * We temporarily enable irq for the GPIO whose configuration is
0551      * changing, and then wait for it to read back as 1 to know when
0552      * debounce has settled and then disable the irq again.
0553      * We do this polling with the spinlock held to ensure other GPIO
0554      * access routines do not read an incorrect value for the irq enable
0555      * bit of other GPIOs.  We keep the GPIO masked while polling to avoid
0556      * spurious irqs, and disable the irq again after polling.
0557      */
0558     mask = BIT(INTERRUPT_ENABLE_OFF);
0559     pin_reg_irq_en = pin_reg;
0560     pin_reg_irq_en |= mask;
0561     pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF);
0562     writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4);
0563     while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask)
0564         continue;
0565     writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
0566     raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
0567 
0568     return ret;
0569 }
0570 
0571 static void amd_irq_ack(struct irq_data *d)
0572 {
0573     /*
0574      * based on HW design,there is no need to ack HW
0575      * before handle current irq. But this routine is
0576      * necessary for handle_edge_irq
0577     */
0578 }
0579 
0580 static const struct irq_chip amd_gpio_irqchip = {
0581     .name         = "amd_gpio",
0582     .irq_ack      = amd_irq_ack,
0583     .irq_enable   = amd_gpio_irq_enable,
0584     .irq_disable  = amd_gpio_irq_disable,
0585     .irq_mask     = amd_gpio_irq_mask,
0586     .irq_unmask   = amd_gpio_irq_unmask,
0587     .irq_set_wake = amd_gpio_irq_set_wake,
0588     .irq_eoi      = amd_gpio_irq_eoi,
0589     .irq_set_type = amd_gpio_irq_set_type,
0590     /*
0591      * We need to set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND so that a wake event
0592      * also generates an IRQ. We need the IRQ so the irq_handler can clear
0593      * the wake event. Otherwise the wake event will never clear and
0594      * prevent the system from suspending.
0595      */
0596     .flags        = IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND | IRQCHIP_IMMUTABLE,
0597     GPIOCHIP_IRQ_RESOURCE_HELPERS,
0598 };
0599 
0600 #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF))
0601 
0602 static bool do_amd_gpio_irq_handler(int irq, void *dev_id)
0603 {
0604     struct amd_gpio *gpio_dev = dev_id;
0605     struct gpio_chip *gc = &gpio_dev->gc;
0606     unsigned int i, irqnr;
0607     unsigned long flags;
0608     u32 __iomem *regs;
0609     bool ret = false;
0610     u32  regval;
0611     u64 status, mask;
0612 
0613     /* Read the wake status */
0614     raw_spin_lock_irqsave(&gpio_dev->lock, flags);
0615     status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
0616     status <<= 32;
0617     status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
0618     raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
0619 
0620     /* Bit 0-45 contain the relevant status bits */
0621     status &= (1ULL << 46) - 1;
0622     regs = gpio_dev->base;
0623     for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) {
0624         if (!(status & mask))
0625             continue;
0626         status &= ~mask;
0627 
0628         /* Each status bit covers four pins */
0629         for (i = 0; i < 4; i++) {
0630             regval = readl(regs + i);
0631             /* caused wake on resume context for shared IRQ */
0632             if (irq < 0 && (regval & BIT(WAKE_STS_OFF))) {
0633                 dev_dbg(&gpio_dev->pdev->dev,
0634                     "Waking due to GPIO %d: 0x%x",
0635                     irqnr + i, regval);
0636                 return true;
0637             }
0638 
0639             if (!(regval & PIN_IRQ_PENDING) ||
0640                 !(regval & BIT(INTERRUPT_MASK_OFF)))
0641                 continue;
0642             generic_handle_domain_irq(gc->irq.domain, irqnr + i);
0643 
0644             /* Clear interrupt.
0645              * We must read the pin register again, in case the
0646              * value was changed while executing
0647              * generic_handle_domain_irq() above.
0648              * If we didn't find a mapping for the interrupt,
0649              * disable it in order to avoid a system hang caused
0650              * by an interrupt storm.
0651              */
0652             raw_spin_lock_irqsave(&gpio_dev->lock, flags);
0653             regval = readl(regs + i);
0654             if (irq == 0) {
0655                 regval &= ~BIT(INTERRUPT_ENABLE_OFF);
0656                 dev_dbg(&gpio_dev->pdev->dev,
0657                     "Disabling spurious GPIO IRQ %d\n",
0658                     irqnr + i);
0659             }
0660             writel(regval, regs + i);
0661             raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
0662             ret = true;
0663         }
0664     }
0665     /* did not cause wake on resume context for shared IRQ */
0666     if (irq < 0)
0667         return false;
0668 
0669     /* Signal EOI to the GPIO unit */
0670     raw_spin_lock_irqsave(&gpio_dev->lock, flags);
0671     regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
0672     regval |= EOI_MASK;
0673     writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG);
0674     raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
0675 
0676     return ret;
0677 }
0678 
0679 static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id)
0680 {
0681     return IRQ_RETVAL(do_amd_gpio_irq_handler(irq, dev_id));
0682 }
0683 
0684 static bool __maybe_unused amd_gpio_check_wake(void *dev_id)
0685 {
0686     return do_amd_gpio_irq_handler(-1, dev_id);
0687 }
0688 
0689 static int amd_get_groups_count(struct pinctrl_dev *pctldev)
0690 {
0691     struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
0692 
0693     return gpio_dev->ngroups;
0694 }
0695 
0696 static const char *amd_get_group_name(struct pinctrl_dev *pctldev,
0697                       unsigned group)
0698 {
0699     struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
0700 
0701     return gpio_dev->groups[group].name;
0702 }
0703 
0704 static int amd_get_group_pins(struct pinctrl_dev *pctldev,
0705                   unsigned group,
0706                   const unsigned **pins,
0707                   unsigned *num_pins)
0708 {
0709     struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
0710 
0711     *pins = gpio_dev->groups[group].pins;
0712     *num_pins = gpio_dev->groups[group].npins;
0713     return 0;
0714 }
0715 
0716 static const struct pinctrl_ops amd_pinctrl_ops = {
0717     .get_groups_count   = amd_get_groups_count,
0718     .get_group_name     = amd_get_group_name,
0719     .get_group_pins     = amd_get_group_pins,
0720 #ifdef CONFIG_OF
0721     .dt_node_to_map     = pinconf_generic_dt_node_to_map_group,
0722     .dt_free_map        = pinctrl_utils_free_map,
0723 #endif
0724 };
0725 
0726 static int amd_pinconf_get(struct pinctrl_dev *pctldev,
0727               unsigned int pin,
0728               unsigned long *config)
0729 {
0730     u32 pin_reg;
0731     unsigned arg;
0732     unsigned long flags;
0733     struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
0734     enum pin_config_param param = pinconf_to_config_param(*config);
0735 
0736     raw_spin_lock_irqsave(&gpio_dev->lock, flags);
0737     pin_reg = readl(gpio_dev->base + pin*4);
0738     raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
0739     switch (param) {
0740     case PIN_CONFIG_INPUT_DEBOUNCE:
0741         arg = pin_reg & DB_TMR_OUT_MASK;
0742         break;
0743 
0744     case PIN_CONFIG_BIAS_PULL_DOWN:
0745         arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
0746         break;
0747 
0748     case PIN_CONFIG_BIAS_PULL_UP:
0749         arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1));
0750         break;
0751 
0752     case PIN_CONFIG_DRIVE_STRENGTH:
0753         arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
0754         break;
0755 
0756     default:
0757         dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
0758             param);
0759         return -ENOTSUPP;
0760     }
0761 
0762     *config = pinconf_to_config_packed(param, arg);
0763 
0764     return 0;
0765 }
0766 
0767 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
0768                 unsigned long *configs, unsigned num_configs)
0769 {
0770     int i;
0771     u32 arg;
0772     int ret = 0;
0773     u32 pin_reg;
0774     unsigned long flags;
0775     enum pin_config_param param;
0776     struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
0777 
0778     raw_spin_lock_irqsave(&gpio_dev->lock, flags);
0779     for (i = 0; i < num_configs; i++) {
0780         param = pinconf_to_config_param(configs[i]);
0781         arg = pinconf_to_config_argument(configs[i]);
0782         pin_reg = readl(gpio_dev->base + pin*4);
0783 
0784         switch (param) {
0785         case PIN_CONFIG_INPUT_DEBOUNCE:
0786             pin_reg &= ~DB_TMR_OUT_MASK;
0787             pin_reg |= arg & DB_TMR_OUT_MASK;
0788             break;
0789 
0790         case PIN_CONFIG_BIAS_PULL_DOWN:
0791             pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
0792             pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
0793             break;
0794 
0795         case PIN_CONFIG_BIAS_PULL_UP:
0796             pin_reg &= ~BIT(PULL_UP_SEL_OFF);
0797             pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF;
0798             pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
0799             pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF;
0800             break;
0801 
0802         case PIN_CONFIG_DRIVE_STRENGTH:
0803             pin_reg &= ~(DRV_STRENGTH_SEL_MASK
0804                     << DRV_STRENGTH_SEL_OFF);
0805             pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
0806                     << DRV_STRENGTH_SEL_OFF;
0807             break;
0808 
0809         default:
0810             dev_err(&gpio_dev->pdev->dev,
0811                 "Invalid config param %04x\n", param);
0812             ret = -ENOTSUPP;
0813         }
0814 
0815         writel(pin_reg, gpio_dev->base + pin*4);
0816     }
0817     raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
0818 
0819     return ret;
0820 }
0821 
0822 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev,
0823                 unsigned int group,
0824                 unsigned long *config)
0825 {
0826     const unsigned *pins;
0827     unsigned npins;
0828     int ret;
0829 
0830     ret = amd_get_group_pins(pctldev, group, &pins, &npins);
0831     if (ret)
0832         return ret;
0833 
0834     if (amd_pinconf_get(pctldev, pins[0], config))
0835             return -ENOTSUPP;
0836 
0837     return 0;
0838 }
0839 
0840 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev,
0841                 unsigned group, unsigned long *configs,
0842                 unsigned num_configs)
0843 {
0844     const unsigned *pins;
0845     unsigned npins;
0846     int i, ret;
0847 
0848     ret = amd_get_group_pins(pctldev, group, &pins, &npins);
0849     if (ret)
0850         return ret;
0851     for (i = 0; i < npins; i++) {
0852         if (amd_pinconf_set(pctldev, pins[i], configs, num_configs))
0853             return -ENOTSUPP;
0854     }
0855     return 0;
0856 }
0857 
0858 static const struct pinconf_ops amd_pinconf_ops = {
0859     .pin_config_get     = amd_pinconf_get,
0860     .pin_config_set     = amd_pinconf_set,
0861     .pin_config_group_get = amd_pinconf_group_get,
0862     .pin_config_group_set = amd_pinconf_group_set,
0863 };
0864 
0865 static void amd_gpio_irq_init(struct amd_gpio *gpio_dev)
0866 {
0867     struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
0868     unsigned long flags;
0869     u32 pin_reg, mask;
0870     int i;
0871 
0872     mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) |
0873         BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF) |
0874         BIT(WAKE_CNTRL_OFF_S4);
0875 
0876     for (i = 0; i < desc->npins; i++) {
0877         int pin = desc->pins[i].number;
0878         const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
0879 
0880         if (!pd)
0881             continue;
0882 
0883         raw_spin_lock_irqsave(&gpio_dev->lock, flags);
0884 
0885         pin_reg = readl(gpio_dev->base + i * 4);
0886         pin_reg &= ~mask;
0887         writel(pin_reg, gpio_dev->base + i * 4);
0888 
0889         raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
0890     }
0891 }
0892 
0893 #ifdef CONFIG_PM_SLEEP
0894 static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin)
0895 {
0896     const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
0897 
0898     if (!pd)
0899         return false;
0900 
0901     /*
0902      * Only restore the pin if it is actually in use by the kernel (or
0903      * by userspace).
0904      */
0905     if (pd->mux_owner || pd->gpio_owner ||
0906         gpiochip_line_is_irq(&gpio_dev->gc, pin))
0907         return true;
0908 
0909     return false;
0910 }
0911 
0912 static int amd_gpio_suspend(struct device *dev)
0913 {
0914     struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
0915     struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
0916     unsigned long flags;
0917     int i;
0918 
0919     for (i = 0; i < desc->npins; i++) {
0920         int pin = desc->pins[i].number;
0921 
0922         if (!amd_gpio_should_save(gpio_dev, pin))
0923             continue;
0924 
0925         raw_spin_lock_irqsave(&gpio_dev->lock, flags);
0926         gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin * 4) & ~PIN_IRQ_PENDING;
0927         raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
0928     }
0929 
0930     return 0;
0931 }
0932 
0933 static int amd_gpio_resume(struct device *dev)
0934 {
0935     struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
0936     struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
0937     unsigned long flags;
0938     int i;
0939 
0940     for (i = 0; i < desc->npins; i++) {
0941         int pin = desc->pins[i].number;
0942 
0943         if (!amd_gpio_should_save(gpio_dev, pin))
0944             continue;
0945 
0946         raw_spin_lock_irqsave(&gpio_dev->lock, flags);
0947         gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING;
0948         writel(gpio_dev->saved_regs[i], gpio_dev->base + pin * 4);
0949         raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
0950     }
0951 
0952     return 0;
0953 }
0954 
0955 static const struct dev_pm_ops amd_gpio_pm_ops = {
0956     SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend,
0957                      amd_gpio_resume)
0958 };
0959 #endif
0960 
0961 static int amd_get_functions_count(struct pinctrl_dev *pctldev)
0962 {
0963     return ARRAY_SIZE(pmx_functions);
0964 }
0965 
0966 static const char *amd_get_fname(struct pinctrl_dev *pctrldev, unsigned int selector)
0967 {
0968     return pmx_functions[selector].name;
0969 }
0970 
0971 static int amd_get_groups(struct pinctrl_dev *pctrldev, unsigned int selector,
0972               const char * const **groups,
0973               unsigned int * const num_groups)
0974 {
0975     struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev);
0976 
0977     if (!gpio_dev->iomux_base) {
0978         dev_err(&gpio_dev->pdev->dev, "iomux function %d group not supported\n", selector);
0979         return -EINVAL;
0980     }
0981 
0982     *groups = pmx_functions[selector].groups;
0983     *num_groups = pmx_functions[selector].ngroups;
0984     return 0;
0985 }
0986 
0987 static int amd_set_mux(struct pinctrl_dev *pctrldev, unsigned int function, unsigned int group)
0988 {
0989     struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev);
0990     struct device *dev = &gpio_dev->pdev->dev;
0991     struct pin_desc *pd;
0992     int ind, index;
0993 
0994     if (!gpio_dev->iomux_base)
0995         return -EINVAL;
0996 
0997     for (index = 0; index < NSELECTS; index++) {
0998         if (strcmp(gpio_dev->groups[group].name,  pmx_functions[function].groups[index]))
0999             continue;
1000 
1001         if (readb(gpio_dev->iomux_base + pmx_functions[function].index) ==
1002                 FUNCTION_INVALID) {
1003             dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n",
1004                 pmx_functions[function].index);
1005             return -EINVAL;
1006         }
1007 
1008         writeb(index, gpio_dev->iomux_base + pmx_functions[function].index);
1009 
1010         if (index != (readb(gpio_dev->iomux_base + pmx_functions[function].index) &
1011                     FUNCTION_MASK)) {
1012             dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n",
1013                 pmx_functions[function].index);
1014             return -EINVAL;
1015         }
1016 
1017         for (ind = 0; ind < gpio_dev->groups[group].npins; ind++) {
1018             if (strncmp(gpio_dev->groups[group].name, "IMX_F", strlen("IMX_F")))
1019                 continue;
1020 
1021             pd = pin_desc_get(gpio_dev->pctrl, gpio_dev->groups[group].pins[ind]);
1022             pd->mux_owner = gpio_dev->groups[group].name;
1023         }
1024         break;
1025     }
1026 
1027     return 0;
1028 }
1029 
1030 static const struct pinmux_ops amd_pmxops = {
1031     .get_functions_count = amd_get_functions_count,
1032     .get_function_name = amd_get_fname,
1033     .get_function_groups = amd_get_groups,
1034     .set_mux = amd_set_mux,
1035 };
1036 
1037 static struct pinctrl_desc amd_pinctrl_desc = {
1038     .pins   = kerncz_pins,
1039     .npins = ARRAY_SIZE(kerncz_pins),
1040     .pctlops = &amd_pinctrl_ops,
1041     .pmxops = &amd_pmxops,
1042     .confops = &amd_pinconf_ops,
1043     .owner = THIS_MODULE,
1044 };
1045 
1046 static void amd_get_iomux_res(struct amd_gpio *gpio_dev)
1047 {
1048     struct pinctrl_desc *desc = &amd_pinctrl_desc;
1049     struct device *dev = &gpio_dev->pdev->dev;
1050     int index;
1051 
1052     index = device_property_match_string(dev, "pinctrl-resource-names",  "iomux");
1053     if (index < 0) {
1054         dev_warn(dev, "failed to get iomux index\n");
1055         goto out_no_pinmux;
1056     }
1057 
1058     gpio_dev->iomux_base = devm_platform_ioremap_resource(gpio_dev->pdev, index);
1059     if (IS_ERR(gpio_dev->iomux_base)) {
1060         dev_warn(dev, "Failed to get iomux %d io resource\n", index);
1061         goto out_no_pinmux;
1062     }
1063 
1064     return;
1065 
1066 out_no_pinmux:
1067     desc->pmxops = NULL;
1068 }
1069 
1070 static int amd_gpio_probe(struct platform_device *pdev)
1071 {
1072     int ret = 0;
1073     struct resource *res;
1074     struct amd_gpio *gpio_dev;
1075     struct gpio_irq_chip *girq;
1076 
1077     gpio_dev = devm_kzalloc(&pdev->dev,
1078                 sizeof(struct amd_gpio), GFP_KERNEL);
1079     if (!gpio_dev)
1080         return -ENOMEM;
1081 
1082     raw_spin_lock_init(&gpio_dev->lock);
1083 
1084     gpio_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1085     if (IS_ERR(gpio_dev->base)) {
1086         dev_err(&pdev->dev, "Failed to get gpio io resource.\n");
1087         return PTR_ERR(gpio_dev->base);
1088     }
1089 
1090     gpio_dev->irq = platform_get_irq(pdev, 0);
1091     if (gpio_dev->irq < 0)
1092         return gpio_dev->irq;
1093 
1094 #ifdef CONFIG_PM_SLEEP
1095     gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins,
1096                         sizeof(*gpio_dev->saved_regs),
1097                         GFP_KERNEL);
1098     if (!gpio_dev->saved_regs)
1099         return -ENOMEM;
1100 #endif
1101 
1102     gpio_dev->pdev = pdev;
1103     gpio_dev->gc.get_direction  = amd_gpio_get_direction;
1104     gpio_dev->gc.direction_input    = amd_gpio_direction_input;
1105     gpio_dev->gc.direction_output   = amd_gpio_direction_output;
1106     gpio_dev->gc.get            = amd_gpio_get_value;
1107     gpio_dev->gc.set            = amd_gpio_set_value;
1108     gpio_dev->gc.set_config     = amd_gpio_set_config;
1109     gpio_dev->gc.dbg_show       = amd_gpio_dbg_show;
1110 
1111     gpio_dev->gc.base       = -1;
1112     gpio_dev->gc.label          = pdev->name;
1113     gpio_dev->gc.owner          = THIS_MODULE;
1114     gpio_dev->gc.parent         = &pdev->dev;
1115     gpio_dev->gc.ngpio          = resource_size(res) / 4;
1116 
1117     gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64;
1118     gpio_dev->groups = kerncz_groups;
1119     gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
1120 
1121     amd_pinctrl_desc.name = dev_name(&pdev->dev);
1122     amd_get_iomux_res(gpio_dev);
1123     gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc,
1124                         gpio_dev);
1125     if (IS_ERR(gpio_dev->pctrl)) {
1126         dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
1127         return PTR_ERR(gpio_dev->pctrl);
1128     }
1129 
1130     /* Disable and mask interrupts */
1131     amd_gpio_irq_init(gpio_dev);
1132 
1133     girq = &gpio_dev->gc.irq;
1134     gpio_irq_chip_set_chip(girq, &amd_gpio_irqchip);
1135     /* This will let us handle the parent IRQ in the driver */
1136     girq->parent_handler = NULL;
1137     girq->num_parents = 0;
1138     girq->parents = NULL;
1139     girq->default_type = IRQ_TYPE_NONE;
1140     girq->handler = handle_simple_irq;
1141 
1142     ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev);
1143     if (ret)
1144         return ret;
1145 
1146     ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev),
1147                 0, 0, gpio_dev->gc.ngpio);
1148     if (ret) {
1149         dev_err(&pdev->dev, "Failed to add pin range\n");
1150         goto out2;
1151     }
1152 
1153     ret = devm_request_irq(&pdev->dev, gpio_dev->irq, amd_gpio_irq_handler,
1154                    IRQF_SHARED, KBUILD_MODNAME, gpio_dev);
1155     if (ret)
1156         goto out2;
1157 
1158     platform_set_drvdata(pdev, gpio_dev);
1159     acpi_register_wakeup_handler(gpio_dev->irq, amd_gpio_check_wake, gpio_dev);
1160 
1161     dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
1162     return ret;
1163 
1164 out2:
1165     gpiochip_remove(&gpio_dev->gc);
1166 
1167     return ret;
1168 }
1169 
1170 static int amd_gpio_remove(struct platform_device *pdev)
1171 {
1172     struct amd_gpio *gpio_dev;
1173 
1174     gpio_dev = platform_get_drvdata(pdev);
1175 
1176     gpiochip_remove(&gpio_dev->gc);
1177     acpi_unregister_wakeup_handler(amd_gpio_check_wake, gpio_dev);
1178 
1179     return 0;
1180 }
1181 
1182 #ifdef CONFIG_ACPI
1183 static const struct acpi_device_id amd_gpio_acpi_match[] = {
1184     { "AMD0030", 0 },
1185     { "AMDI0030", 0},
1186     { "AMDI0031", 0},
1187     { },
1188 };
1189 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
1190 #endif
1191 
1192 static struct platform_driver amd_gpio_driver = {
1193     .driver     = {
1194         .name   = "amd_gpio",
1195         .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match),
1196 #ifdef CONFIG_PM_SLEEP
1197         .pm = &amd_gpio_pm_ops,
1198 #endif
1199     },
1200     .probe      = amd_gpio_probe,
1201     .remove     = amd_gpio_remove,
1202 };
1203 
1204 module_platform_driver(amd_gpio_driver);
1205 
1206 MODULE_LICENSE("GPL v2");
1207 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>");
1208 MODULE_DESCRIPTION("AMD GPIO pinctrl driver");
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