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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (c) 2016-2018 Nuvoton Technology corporation.
0003 // Copyright (c) 2016, Dell Inc
0004 // Copyright (c) 2021-2022 Jonathan Neuschäfer
0005 //
0006 // This driver uses the following registers:
0007 // - Pin mux registers, in the GCR (general control registers) block
0008 // - GPIO registers, specific to each GPIO bank
0009 // - GPIO event (interrupt) registers, located centrally in the GPIO register
0010 //   block, shared between all GPIO banks
0011 
0012 #include <linux/device.h>
0013 #include <linux/fwnode.h>
0014 #include <linux/gpio/driver.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/irq.h>
0017 #include <linux/mfd/syscon.h>
0018 #include <linux/module.h>
0019 #include <linux/mod_devicetable.h>
0020 #include <linux/platform_device.h>
0021 #include <linux/regmap.h>
0022 
0023 #include <linux/pinctrl/pinconf.h>
0024 #include <linux/pinctrl/pinconf-generic.h>
0025 #include <linux/pinctrl/pinctrl.h>
0026 #include <linux/pinctrl/pinmux.h>
0027 
0028 #include "../core.h"
0029 
0030 /* GCR registers */
0031 #define WPCM450_GCR_MFSEL1  0x0c
0032 #define WPCM450_GCR_MFSEL2  0x10
0033 #define WPCM450_GCR_NONE    0
0034 
0035 /* GPIO event (interrupt) registers */
0036 #define WPCM450_GPEVTYPE    0x00
0037 #define WPCM450_GPEVPOL     0x04
0038 #define WPCM450_GPEVDBNC    0x08
0039 #define WPCM450_GPEVEN      0x0c
0040 #define WPCM450_GPEVST      0x10
0041 
0042 #define WPCM450_NUM_BANKS   8
0043 #define WPCM450_NUM_GPIOS   128
0044 #define WPCM450_NUM_GPIO_IRQS   4
0045 
0046 struct wpcm450_pinctrl;
0047 struct wpcm450_bank;
0048 
0049 struct wpcm450_gpio {
0050     struct gpio_chip    gc;
0051     struct wpcm450_pinctrl  *pctrl;
0052     struct irq_chip     irqc;
0053     const struct wpcm450_bank *bank;
0054 };
0055 
0056 struct wpcm450_pinctrl {
0057     struct pinctrl_dev  *pctldev;
0058     struct device       *dev;
0059     struct irq_domain   *domain;
0060     struct regmap       *gcr_regmap;
0061     void __iomem        *gpio_base;
0062     struct wpcm450_gpio gpio_bank[WPCM450_NUM_BANKS];
0063     unsigned long       both_edges;
0064 
0065     /*
0066      * This spin lock protects registers and struct wpcm450_pinctrl fields
0067      * against concurrent access.
0068      */
0069     raw_spinlock_t      lock;
0070 };
0071 
0072 struct wpcm450_bank {
0073     /* Range of GPIOs in this port */
0074     u8 base;
0075     u8 length;
0076 
0077     /* Register offsets (0 = register doesn't exist in this port) */
0078     u8 cfg0, cfg1, cfg2;
0079     u8 blink;
0080     u8 dataout, datain;
0081 
0082     /* Interrupt bit mapping */
0083     u8 first_irq_bit;   /* First bit in GPEVST that belongs to this bank */
0084     u8 num_irqs;        /* Number of IRQ-capable GPIOs in this bank */
0085     u8 first_irq_gpio;  /* First IRQ-capable GPIO in this bank */
0086 };
0087 
0088 static const struct wpcm450_bank wpcm450_banks[WPCM450_NUM_BANKS] = {
0089     /*  range   cfg0  cfg1  cfg2 blink  out   in     IRQ map */
0090     {   0, 16,  0x14, 0x18,    0,    0, 0x1c, 0x20,  0, 16, 0 },
0091     {  16, 16,  0x24, 0x28, 0x2c, 0x30, 0x34, 0x38, 16,  2, 8 },
0092     {  32, 16,  0x3c, 0x40, 0x44,    0, 0x48, 0x4c,  0,  0, 0 },
0093     {  48, 16,  0x50, 0x54, 0x58,    0, 0x5c, 0x60,  0,  0, 0 },
0094     {  64, 16,  0x64, 0x68, 0x6c,    0, 0x70, 0x74,  0,  0, 0 },
0095     {  80, 16,  0x78, 0x7c, 0x80,    0, 0x84, 0x88,  0,  0, 0 },
0096     {  96, 18,     0,    0,    0,    0,    0, 0x8c,  0,  0, 0 },
0097     { 114, 14,  0x90, 0x94, 0x98,    0, 0x9c, 0xa0,  0,  0, 0 },
0098 };
0099 
0100 static int wpcm450_gpio_irq_bitnum(struct wpcm450_gpio *gpio, struct irq_data *d)
0101 {
0102     const struct wpcm450_bank *bank = gpio->bank;
0103     int hwirq = irqd_to_hwirq(d);
0104 
0105     if (hwirq < bank->first_irq_gpio)
0106         return -EINVAL;
0107 
0108     if (hwirq - bank->first_irq_gpio >= bank->num_irqs)
0109         return -EINVAL;
0110 
0111     return hwirq - bank->first_irq_gpio + bank->first_irq_bit;
0112 }
0113 
0114 static int wpcm450_irq_bitnum_to_gpio(struct wpcm450_gpio *gpio, int bitnum)
0115 {
0116     const struct wpcm450_bank *bank = gpio->bank;
0117 
0118     if (bitnum < bank->first_irq_bit)
0119         return -EINVAL;
0120 
0121     if (bitnum - bank->first_irq_bit > bank->num_irqs)
0122         return -EINVAL;
0123 
0124     return bitnum - bank->first_irq_bit + bank->first_irq_gpio;
0125 }
0126 
0127 static void wpcm450_gpio_irq_ack(struct irq_data *d)
0128 {
0129     struct wpcm450_gpio *gpio = gpiochip_get_data(irq_data_get_irq_chip_data(d));
0130     struct wpcm450_pinctrl *pctrl = gpio->pctrl;
0131     unsigned long flags;
0132     int bit;
0133 
0134     bit = wpcm450_gpio_irq_bitnum(gpio, d);
0135     if (bit < 0)
0136         return;
0137 
0138     raw_spin_lock_irqsave(&pctrl->lock, flags);
0139     iowrite32(BIT(bit), pctrl->gpio_base + WPCM450_GPEVST);
0140     raw_spin_unlock_irqrestore(&pctrl->lock, flags);
0141 }
0142 
0143 static void wpcm450_gpio_irq_mask(struct irq_data *d)
0144 {
0145     struct wpcm450_gpio *gpio = gpiochip_get_data(irq_data_get_irq_chip_data(d));
0146     struct wpcm450_pinctrl *pctrl = gpio->pctrl;
0147     unsigned long flags;
0148     unsigned long even;
0149     int bit;
0150 
0151     bit = wpcm450_gpio_irq_bitnum(gpio, d);
0152     if (bit < 0)
0153         return;
0154 
0155     raw_spin_lock_irqsave(&pctrl->lock, flags);
0156     even = ioread32(pctrl->gpio_base + WPCM450_GPEVEN);
0157     __assign_bit(bit, &even, 0);
0158     iowrite32(even, pctrl->gpio_base + WPCM450_GPEVEN);
0159     raw_spin_unlock_irqrestore(&pctrl->lock, flags);
0160 }
0161 
0162 static void wpcm450_gpio_irq_unmask(struct irq_data *d)
0163 {
0164     struct wpcm450_gpio *gpio = gpiochip_get_data(irq_data_get_irq_chip_data(d));
0165     struct wpcm450_pinctrl *pctrl = gpio->pctrl;
0166     unsigned long flags;
0167     unsigned long even;
0168     int bit;
0169 
0170     bit = wpcm450_gpio_irq_bitnum(gpio, d);
0171     if (bit < 0)
0172         return;
0173 
0174     raw_spin_lock_irqsave(&pctrl->lock, flags);
0175     even = ioread32(pctrl->gpio_base + WPCM450_GPEVEN);
0176     __assign_bit(bit, &even, 1);
0177     iowrite32(even, pctrl->gpio_base + WPCM450_GPEVEN);
0178     raw_spin_unlock_irqrestore(&pctrl->lock, flags);
0179 }
0180 
0181 /*
0182  * This is an implementation of the gpio_chip->get() function, for use in
0183  * wpcm450_gpio_fix_evpol. Unfortunately, we can't use the bgpio-provided
0184  * implementation there, because it would require taking gpio_chip->bgpio_lock,
0185  * which is a spin lock, but wpcm450_gpio_fix_evpol must work in contexts where
0186  * a raw spin lock is held.
0187  */
0188 static int wpcm450_gpio_get(struct wpcm450_gpio *gpio, int offset)
0189 {
0190     void __iomem *reg = gpio->pctrl->gpio_base + gpio->bank->datain;
0191     unsigned long flags;
0192     u32 level;
0193 
0194     raw_spin_lock_irqsave(&gpio->pctrl->lock, flags);
0195     level = !!(ioread32(reg) & BIT(offset));
0196     raw_spin_unlock_irqrestore(&gpio->pctrl->lock, flags);
0197 
0198     return level;
0199 }
0200 
0201 /*
0202  * Since the GPIO controller does not support dual-edge triggered interrupts
0203  * (IRQ_TYPE_EDGE_BOTH), they are emulated using rising/falling edge triggered
0204  * interrupts. wpcm450_gpio_fix_evpol sets the interrupt polarity for the
0205  * specified emulated dual-edge triggered interrupts, so that the next edge can
0206  * be detected.
0207  */
0208 static void wpcm450_gpio_fix_evpol(struct wpcm450_gpio *gpio, unsigned long all)
0209 {
0210     struct wpcm450_pinctrl *pctrl = gpio->pctrl;
0211     unsigned int bit;
0212 
0213     for_each_set_bit(bit, &all, 32) {
0214         int offset = wpcm450_irq_bitnum_to_gpio(gpio, bit);
0215         unsigned long evpol;
0216         unsigned long flags;
0217         int level;
0218 
0219         do {
0220             level = wpcm450_gpio_get(gpio, offset);
0221 
0222             /* Switch event polarity to the opposite of the current level */
0223             raw_spin_lock_irqsave(&pctrl->lock, flags);
0224             evpol = ioread32(pctrl->gpio_base + WPCM450_GPEVPOL);
0225             __assign_bit(bit, &evpol, !level);
0226             iowrite32(evpol, pctrl->gpio_base + WPCM450_GPEVPOL);
0227             raw_spin_unlock_irqrestore(&pctrl->lock, flags);
0228 
0229         } while (wpcm450_gpio_get(gpio, offset) != level);
0230     }
0231 }
0232 
0233 static int wpcm450_gpio_set_irq_type(struct irq_data *d, unsigned int flow_type)
0234 {
0235     struct wpcm450_gpio *gpio = gpiochip_get_data(irq_data_get_irq_chip_data(d));
0236     struct wpcm450_pinctrl *pctrl = gpio->pctrl;
0237     unsigned long evtype, evpol;
0238     unsigned long flags;
0239     int ret = 0;
0240     int bit;
0241 
0242     bit = wpcm450_gpio_irq_bitnum(gpio, d);
0243     if (bit < 0)
0244         return bit;
0245 
0246     irq_set_handler_locked(d, handle_level_irq);
0247 
0248     raw_spin_lock_irqsave(&pctrl->lock, flags);
0249     evtype = ioread32(pctrl->gpio_base + WPCM450_GPEVTYPE);
0250     evpol = ioread32(pctrl->gpio_base + WPCM450_GPEVPOL);
0251     __assign_bit(bit, &pctrl->both_edges, 0);
0252     switch (flow_type) {
0253     case IRQ_TYPE_LEVEL_LOW:
0254         __assign_bit(bit, &evtype, 1);
0255         __assign_bit(bit, &evpol, 0);
0256         break;
0257     case IRQ_TYPE_LEVEL_HIGH:
0258         __assign_bit(bit, &evtype, 1);
0259         __assign_bit(bit, &evpol, 1);
0260         break;
0261     case IRQ_TYPE_EDGE_FALLING:
0262         __assign_bit(bit, &evtype, 0);
0263         __assign_bit(bit, &evpol, 0);
0264         break;
0265     case IRQ_TYPE_EDGE_RISING:
0266         __assign_bit(bit, &evtype, 0);
0267         __assign_bit(bit, &evpol, 1);
0268         break;
0269     case IRQ_TYPE_EDGE_BOTH:
0270         __assign_bit(bit, &evtype, 0);
0271         __assign_bit(bit, &pctrl->both_edges, 1);
0272         break;
0273     default:
0274         ret = -EINVAL;
0275     }
0276     iowrite32(evtype, pctrl->gpio_base + WPCM450_GPEVTYPE);
0277     iowrite32(evpol, pctrl->gpio_base + WPCM450_GPEVPOL);
0278 
0279     /* clear the event status for good measure */
0280     iowrite32(BIT(bit), pctrl->gpio_base + WPCM450_GPEVST);
0281 
0282     raw_spin_unlock_irqrestore(&pctrl->lock, flags);
0283 
0284     /* fix event polarity after clearing event status */
0285     wpcm450_gpio_fix_evpol(gpio, BIT(bit));
0286 
0287     return ret;
0288 }
0289 
0290 static const struct irq_chip wpcm450_gpio_irqchip = {
0291     .name = "WPCM450-GPIO-IRQ",
0292     .irq_ack = wpcm450_gpio_irq_ack,
0293     .irq_unmask = wpcm450_gpio_irq_unmask,
0294     .irq_mask = wpcm450_gpio_irq_mask,
0295     .irq_set_type = wpcm450_gpio_set_irq_type,
0296 };
0297 
0298 static void wpcm450_gpio_irqhandler(struct irq_desc *desc)
0299 {
0300     struct wpcm450_gpio *gpio = gpiochip_get_data(irq_desc_get_handler_data(desc));
0301     struct wpcm450_pinctrl *pctrl = gpio->pctrl;
0302     struct irq_chip *chip = irq_desc_get_chip(desc);
0303     unsigned long pending;
0304     unsigned long flags;
0305     unsigned long ours;
0306     unsigned int bit;
0307 
0308     ours = GENMASK(gpio->bank->num_irqs - 1, 0) << gpio->bank->first_irq_bit;
0309 
0310     raw_spin_lock_irqsave(&pctrl->lock, flags);
0311 
0312     pending = ioread32(pctrl->gpio_base + WPCM450_GPEVST);
0313     pending &= ioread32(pctrl->gpio_base + WPCM450_GPEVEN);
0314     pending &= ours;
0315 
0316     raw_spin_unlock_irqrestore(&pctrl->lock, flags);
0317 
0318     if (pending & pctrl->both_edges)
0319         wpcm450_gpio_fix_evpol(gpio, pending & pctrl->both_edges);
0320 
0321     chained_irq_enter(chip, desc);
0322     for_each_set_bit(bit, &pending, 32) {
0323         int offset = wpcm450_irq_bitnum_to_gpio(gpio, bit);
0324 
0325         generic_handle_domain_irq(gpio->gc.irq.domain, offset);
0326     }
0327     chained_irq_exit(chip, desc);
0328 }
0329 
0330 static int smb0_pins[]  = { 115, 114 };
0331 static int smb1_pins[]  = { 117, 116 };
0332 static int smb2_pins[]  = { 119, 118 };
0333 static int smb3_pins[]  = { 30, 31 };
0334 static int smb4_pins[]  = { 28, 29 };
0335 static int smb5_pins[]  = { 26, 27 };
0336 
0337 static int scs1_pins[] = { 32 };
0338 static int scs2_pins[] = { 33 };
0339 static int scs3_pins[] = { 34 };
0340 
0341 static int bsp_pins[] = { 41, 42 };
0342 static int hsp1_pins[] = { 43, 44, 45, 46, 47, 61, 62, 63 };
0343 static int hsp2_pins[] = { 48, 49, 50, 51, 52, 53, 54, 55 };
0344 
0345 static int r1err_pins[] = { 56 };
0346 static int r1md_pins[] = { 57, 58 };
0347 static int rmii2_pins[] = { 84, 85, 86, 87, 88, 89 };
0348 static int r2err_pins[] = { 90 };
0349 static int r2md_pins[] = { 91, 92 };
0350 
0351 static int kbcc_pins[] = { 94, 93 };
0352 static int clko_pins[] = { 96 };
0353 static int smi_pins[] = { 97 };
0354 static int uinc_pins[] = { 19 };
0355 static int mben_pins[] = {};
0356 
0357 static int gspi_pins[] = { 12, 13, 14, 15 };
0358 static int sspi_pins[] = { 12, 13, 14, 15 };
0359 
0360 static int xcs1_pins[] = { 35 };
0361 static int xcs2_pins[] = { 36 };
0362 
0363 static int sdio_pins[] = { 7, 22, 43, 44, 45, 46, 47, 60 };
0364 
0365 static int fi0_pins[] = { 64 };
0366 static int fi1_pins[] = { 65 };
0367 static int fi2_pins[] = { 66 };
0368 static int fi3_pins[] = { 67 };
0369 static int fi4_pins[] = { 68 };
0370 static int fi5_pins[] = { 69 };
0371 static int fi6_pins[] = { 70 };
0372 static int fi7_pins[] = { 71 };
0373 static int fi8_pins[] = { 72 };
0374 static int fi9_pins[] = { 73 };
0375 static int fi10_pins[] = { 74 };
0376 static int fi11_pins[] = { 75 };
0377 static int fi12_pins[] = { 76 };
0378 static int fi13_pins[] = { 77 };
0379 static int fi14_pins[] = { 78 };
0380 static int fi15_pins[] = { 79 };
0381 
0382 static int pwm0_pins[] = { 80 };
0383 static int pwm1_pins[] = { 81 };
0384 static int pwm2_pins[] = { 82 };
0385 static int pwm3_pins[] = { 83 };
0386 static int pwm4_pins[] = { 20 };
0387 static int pwm5_pins[] = { 21 };
0388 static int pwm6_pins[] = { 16 };
0389 static int pwm7_pins[] = { 17 };
0390 
0391 static int hg0_pins[] = { 20 };
0392 static int hg1_pins[] = { 21 };
0393 static int hg2_pins[] = { 22 };
0394 static int hg3_pins[] = { 23 };
0395 static int hg4_pins[] = { 24 };
0396 static int hg5_pins[] = { 25 };
0397 static int hg6_pins[] = { 59 };
0398 static int hg7_pins[] = { 60 };
0399 
0400 #define WPCM450_GRPS \
0401     WPCM450_GRP(smb3), \
0402     WPCM450_GRP(smb4), \
0403     WPCM450_GRP(smb5), \
0404     WPCM450_GRP(scs1), \
0405     WPCM450_GRP(scs2), \
0406     WPCM450_GRP(scs3), \
0407     WPCM450_GRP(smb0), \
0408     WPCM450_GRP(smb1), \
0409     WPCM450_GRP(smb2), \
0410     WPCM450_GRP(bsp), \
0411     WPCM450_GRP(hsp1), \
0412     WPCM450_GRP(hsp2), \
0413     WPCM450_GRP(r1err), \
0414     WPCM450_GRP(r1md), \
0415     WPCM450_GRP(rmii2), \
0416     WPCM450_GRP(r2err), \
0417     WPCM450_GRP(r2md), \
0418     WPCM450_GRP(kbcc), \
0419     WPCM450_GRP(clko), \
0420     WPCM450_GRP(smi), \
0421     WPCM450_GRP(uinc), \
0422     WPCM450_GRP(gspi), \
0423     WPCM450_GRP(mben), \
0424     WPCM450_GRP(xcs2), \
0425     WPCM450_GRP(xcs1), \
0426     WPCM450_GRP(sdio), \
0427     WPCM450_GRP(sspi), \
0428     WPCM450_GRP(fi0), \
0429     WPCM450_GRP(fi1), \
0430     WPCM450_GRP(fi2), \
0431     WPCM450_GRP(fi3), \
0432     WPCM450_GRP(fi4), \
0433     WPCM450_GRP(fi5), \
0434     WPCM450_GRP(fi6), \
0435     WPCM450_GRP(fi7), \
0436     WPCM450_GRP(fi8), \
0437     WPCM450_GRP(fi9), \
0438     WPCM450_GRP(fi10), \
0439     WPCM450_GRP(fi11), \
0440     WPCM450_GRP(fi12), \
0441     WPCM450_GRP(fi13), \
0442     WPCM450_GRP(fi14), \
0443     WPCM450_GRP(fi15), \
0444     WPCM450_GRP(pwm0), \
0445     WPCM450_GRP(pwm1), \
0446     WPCM450_GRP(pwm2), \
0447     WPCM450_GRP(pwm3), \
0448     WPCM450_GRP(pwm4), \
0449     WPCM450_GRP(pwm5), \
0450     WPCM450_GRP(pwm6), \
0451     WPCM450_GRP(pwm7), \
0452     WPCM450_GRP(hg0), \
0453     WPCM450_GRP(hg1), \
0454     WPCM450_GRP(hg2), \
0455     WPCM450_GRP(hg3), \
0456     WPCM450_GRP(hg4), \
0457     WPCM450_GRP(hg5), \
0458     WPCM450_GRP(hg6), \
0459     WPCM450_GRP(hg7), \
0460 
0461 enum {
0462 #define WPCM450_GRP(x) fn_ ## x
0463     WPCM450_GRPS
0464     /* add placeholder for none/gpio */
0465     WPCM450_GRP(gpio),
0466     WPCM450_GRP(none),
0467 #undef WPCM450_GRP
0468 };
0469 
0470 static struct group_desc wpcm450_groups[] = {
0471 #define WPCM450_GRP(x) { .name = #x, .pins = x ## _pins, \
0472             .num_pins = ARRAY_SIZE(x ## _pins) }
0473     WPCM450_GRPS
0474 #undef WPCM450_GRP
0475 };
0476 
0477 #define WPCM450_SFUNC(a) WPCM450_FUNC(a, #a)
0478 #define WPCM450_FUNC(a, b...) static const char *a ## _grp[] = { b }
0479 #define WPCM450_MKFUNC(nm) { .name = #nm, .ngroups = ARRAY_SIZE(nm ## _grp), \
0480             .groups = nm ## _grp }
0481 struct wpcm450_func {
0482     const char *name;
0483     const unsigned int ngroups;
0484     const char *const *groups;
0485 };
0486 
0487 WPCM450_SFUNC(smb3);
0488 WPCM450_SFUNC(smb4);
0489 WPCM450_SFUNC(smb5);
0490 WPCM450_SFUNC(scs1);
0491 WPCM450_SFUNC(scs2);
0492 WPCM450_SFUNC(scs3);
0493 WPCM450_SFUNC(smb0);
0494 WPCM450_SFUNC(smb1);
0495 WPCM450_SFUNC(smb2);
0496 WPCM450_SFUNC(bsp);
0497 WPCM450_SFUNC(hsp1);
0498 WPCM450_SFUNC(hsp2);
0499 WPCM450_SFUNC(r1err);
0500 WPCM450_SFUNC(r1md);
0501 WPCM450_SFUNC(rmii2);
0502 WPCM450_SFUNC(r2err);
0503 WPCM450_SFUNC(r2md);
0504 WPCM450_SFUNC(kbcc);
0505 WPCM450_SFUNC(clko);
0506 WPCM450_SFUNC(smi);
0507 WPCM450_SFUNC(uinc);
0508 WPCM450_SFUNC(gspi);
0509 WPCM450_SFUNC(mben);
0510 WPCM450_SFUNC(xcs2);
0511 WPCM450_SFUNC(xcs1);
0512 WPCM450_SFUNC(sdio);
0513 WPCM450_SFUNC(sspi);
0514 WPCM450_SFUNC(fi0);
0515 WPCM450_SFUNC(fi1);
0516 WPCM450_SFUNC(fi2);
0517 WPCM450_SFUNC(fi3);
0518 WPCM450_SFUNC(fi4);
0519 WPCM450_SFUNC(fi5);
0520 WPCM450_SFUNC(fi6);
0521 WPCM450_SFUNC(fi7);
0522 WPCM450_SFUNC(fi8);
0523 WPCM450_SFUNC(fi9);
0524 WPCM450_SFUNC(fi10);
0525 WPCM450_SFUNC(fi11);
0526 WPCM450_SFUNC(fi12);
0527 WPCM450_SFUNC(fi13);
0528 WPCM450_SFUNC(fi14);
0529 WPCM450_SFUNC(fi15);
0530 WPCM450_SFUNC(pwm0);
0531 WPCM450_SFUNC(pwm1);
0532 WPCM450_SFUNC(pwm2);
0533 WPCM450_SFUNC(pwm3);
0534 WPCM450_SFUNC(pwm4);
0535 WPCM450_SFUNC(pwm5);
0536 WPCM450_SFUNC(pwm6);
0537 WPCM450_SFUNC(pwm7);
0538 WPCM450_SFUNC(hg0);
0539 WPCM450_SFUNC(hg1);
0540 WPCM450_SFUNC(hg2);
0541 WPCM450_SFUNC(hg3);
0542 WPCM450_SFUNC(hg4);
0543 WPCM450_SFUNC(hg5);
0544 WPCM450_SFUNC(hg6);
0545 WPCM450_SFUNC(hg7);
0546 
0547 #define WPCM450_GRP(x) #x
0548 WPCM450_FUNC(gpio, WPCM450_GRPS);
0549 #undef WPCM450_GRP
0550 
0551 /* Function names */
0552 static struct wpcm450_func wpcm450_funcs[] = {
0553     WPCM450_MKFUNC(smb3),
0554     WPCM450_MKFUNC(smb4),
0555     WPCM450_MKFUNC(smb5),
0556     WPCM450_MKFUNC(scs1),
0557     WPCM450_MKFUNC(scs2),
0558     WPCM450_MKFUNC(scs3),
0559     WPCM450_MKFUNC(smb0),
0560     WPCM450_MKFUNC(smb1),
0561     WPCM450_MKFUNC(smb2),
0562     WPCM450_MKFUNC(bsp),
0563     WPCM450_MKFUNC(hsp1),
0564     WPCM450_MKFUNC(hsp2),
0565     WPCM450_MKFUNC(r1err),
0566     WPCM450_MKFUNC(r1md),
0567     WPCM450_MKFUNC(rmii2),
0568     WPCM450_MKFUNC(r2err),
0569     WPCM450_MKFUNC(r2md),
0570     WPCM450_MKFUNC(kbcc),
0571     WPCM450_MKFUNC(clko),
0572     WPCM450_MKFUNC(smi),
0573     WPCM450_MKFUNC(uinc),
0574     WPCM450_MKFUNC(gspi),
0575     WPCM450_MKFUNC(mben),
0576     WPCM450_MKFUNC(xcs2),
0577     WPCM450_MKFUNC(xcs1),
0578     WPCM450_MKFUNC(sdio),
0579     WPCM450_MKFUNC(sspi),
0580     WPCM450_MKFUNC(fi0),
0581     WPCM450_MKFUNC(fi1),
0582     WPCM450_MKFUNC(fi2),
0583     WPCM450_MKFUNC(fi3),
0584     WPCM450_MKFUNC(fi4),
0585     WPCM450_MKFUNC(fi5),
0586     WPCM450_MKFUNC(fi6),
0587     WPCM450_MKFUNC(fi7),
0588     WPCM450_MKFUNC(fi8),
0589     WPCM450_MKFUNC(fi9),
0590     WPCM450_MKFUNC(fi10),
0591     WPCM450_MKFUNC(fi11),
0592     WPCM450_MKFUNC(fi12),
0593     WPCM450_MKFUNC(fi13),
0594     WPCM450_MKFUNC(fi14),
0595     WPCM450_MKFUNC(fi15),
0596     WPCM450_MKFUNC(pwm0),
0597     WPCM450_MKFUNC(pwm1),
0598     WPCM450_MKFUNC(pwm2),
0599     WPCM450_MKFUNC(pwm3),
0600     WPCM450_MKFUNC(pwm4),
0601     WPCM450_MKFUNC(pwm5),
0602     WPCM450_MKFUNC(pwm6),
0603     WPCM450_MKFUNC(pwm7),
0604     WPCM450_MKFUNC(hg0),
0605     WPCM450_MKFUNC(hg1),
0606     WPCM450_MKFUNC(hg2),
0607     WPCM450_MKFUNC(hg3),
0608     WPCM450_MKFUNC(hg4),
0609     WPCM450_MKFUNC(hg5),
0610     WPCM450_MKFUNC(hg6),
0611     WPCM450_MKFUNC(hg7),
0612     WPCM450_MKFUNC(gpio),
0613 };
0614 
0615 #define WPCM450_PINCFG(a, b, c, d, e, f, g) \
0616     [a] = { .fn0 = fn_ ## b, .reg0 = WPCM450_GCR_ ## c, .bit0 = d, \
0617             .fn1 = fn_ ## e, .reg1 = WPCM450_GCR_ ## f, .bit1 = g }
0618 
0619 struct wpcm450_pincfg {
0620     int fn0, reg0, bit0;
0621     int fn1, reg1, bit1;
0622 };
0623 
0624 static const struct wpcm450_pincfg pincfg[] = {
0625     /*      PIN   FUNCTION 1           FUNCTION 2 */
0626     WPCM450_PINCFG(0,    none, NONE, 0,       none, NONE, 0),
0627     WPCM450_PINCFG(1,    none, NONE, 0,       none, NONE, 0),
0628     WPCM450_PINCFG(2,    none, NONE, 0,       none, NONE, 0),
0629     WPCM450_PINCFG(3,    none, NONE, 0,       none, NONE, 0),
0630     WPCM450_PINCFG(4,    none, NONE, 0,       none, NONE, 0),
0631     WPCM450_PINCFG(5,    none, NONE, 0,       none, NONE, 0),
0632     WPCM450_PINCFG(6,    none, NONE, 0,       none, NONE, 0),
0633     WPCM450_PINCFG(7,    none, NONE, 0,       sdio, MFSEL1, 30),
0634     WPCM450_PINCFG(8,    none, NONE, 0,       none, NONE, 0),
0635     WPCM450_PINCFG(9,    none, NONE, 0,       none, NONE, 0),
0636     WPCM450_PINCFG(10,   none, NONE, 0,       none, NONE, 0),
0637     WPCM450_PINCFG(11,   none, NONE, 0,       none, NONE, 0),
0638     WPCM450_PINCFG(12,   gspi, MFSEL1, 24,    sspi, MFSEL1, 31),
0639     WPCM450_PINCFG(13,   gspi, MFSEL1, 24,    sspi, MFSEL1, 31),
0640     WPCM450_PINCFG(14,   gspi, MFSEL1, 24,    sspi, MFSEL1, 31),
0641     WPCM450_PINCFG(15,   gspi, MFSEL1, 24,    sspi, MFSEL1, 31),
0642     WPCM450_PINCFG(16,   none, NONE, 0,       pwm6, MFSEL2, 22),
0643     WPCM450_PINCFG(17,   none, NONE, 0,       pwm7, MFSEL2, 23),
0644     WPCM450_PINCFG(18,   none, NONE, 0,       none, NONE, 0),
0645     WPCM450_PINCFG(19,   uinc, MFSEL1, 23,    none, NONE, 0),
0646     WPCM450_PINCFG(20,    hg0, MFSEL2, 24,    pwm4, MFSEL2, 20),
0647     WPCM450_PINCFG(21,    hg1, MFSEL2, 25,    pwm5, MFSEL2, 21),
0648     WPCM450_PINCFG(22,    hg2, MFSEL2, 26,    none, NONE, 0),
0649     WPCM450_PINCFG(23,    hg3, MFSEL2, 27,    none, NONE, 0),
0650     WPCM450_PINCFG(24,    hg4, MFSEL2, 28,    none, NONE, 0),
0651     WPCM450_PINCFG(25,    hg5, MFSEL2, 29,    none, NONE, 0),
0652     WPCM450_PINCFG(26,   smb5, MFSEL1, 2,     none, NONE, 0),
0653     WPCM450_PINCFG(27,   smb5, MFSEL1, 2,     none, NONE, 0),
0654     WPCM450_PINCFG(28,   smb4, MFSEL1, 1,     none, NONE, 0),
0655     WPCM450_PINCFG(29,   smb4, MFSEL1, 1,     none, NONE, 0),
0656     WPCM450_PINCFG(30,   smb3, MFSEL1, 0,     none, NONE, 0),
0657     WPCM450_PINCFG(31,   smb3, MFSEL1, 0,     none, NONE, 0),
0658 
0659     WPCM450_PINCFG(32,   scs1, MFSEL1, 3,     none, NONE, 0),
0660     WPCM450_PINCFG(33,   scs2, MFSEL1, 4,     none, NONE, 0),
0661     WPCM450_PINCFG(34,   scs3, MFSEL1, 5,     none, NONE, 0),
0662     WPCM450_PINCFG(35,   xcs1, MFSEL1, 29,    none, NONE, 0),
0663     WPCM450_PINCFG(36,   xcs2, MFSEL1, 28,    none, NONE, 0),
0664     WPCM450_PINCFG(37,   none, NONE, 0,       none, NONE, 0), /* DVO */
0665     WPCM450_PINCFG(38,   none, NONE, 0,       none, NONE, 0), /* DVO */
0666     WPCM450_PINCFG(39,   none, NONE, 0,       none, NONE, 0), /* DVO */
0667     WPCM450_PINCFG(40,   none, NONE, 0,       none, NONE, 0), /* DVO */
0668     WPCM450_PINCFG(41,    bsp, MFSEL1, 9,     none, NONE, 0),
0669     WPCM450_PINCFG(42,    bsp, MFSEL1, 9,     none, NONE, 0),
0670     WPCM450_PINCFG(43,   hsp1, MFSEL1, 10,    sdio, MFSEL1, 30),
0671     WPCM450_PINCFG(44,   hsp1, MFSEL1, 10,    sdio, MFSEL1, 30),
0672     WPCM450_PINCFG(45,   hsp1, MFSEL1, 10,    sdio, MFSEL1, 30),
0673     WPCM450_PINCFG(46,   hsp1, MFSEL1, 10,    sdio, MFSEL1, 30),
0674     WPCM450_PINCFG(47,   hsp1, MFSEL1, 10,    sdio, MFSEL1, 30),
0675     WPCM450_PINCFG(48,   hsp2, MFSEL1, 11,    none, NONE, 0),
0676     WPCM450_PINCFG(49,   hsp2, MFSEL1, 11,    none, NONE, 0),
0677     WPCM450_PINCFG(50,   hsp2, MFSEL1, 11,    none, NONE, 0),
0678     WPCM450_PINCFG(51,   hsp2, MFSEL1, 11,    none, NONE, 0),
0679     WPCM450_PINCFG(52,   hsp2, MFSEL1, 11,    none, NONE, 0),
0680     WPCM450_PINCFG(53,   hsp2, MFSEL1, 11,    none, NONE, 0),
0681     WPCM450_PINCFG(54,   hsp2, MFSEL1, 11,    none, NONE, 0),
0682     WPCM450_PINCFG(55,   hsp2, MFSEL1, 11,    none, NONE, 0),
0683     WPCM450_PINCFG(56,  r1err, MFSEL1, 12,    none, NONE, 0),
0684     WPCM450_PINCFG(57,   r1md, MFSEL1, 13,    none, NONE, 0),
0685     WPCM450_PINCFG(58,   r1md, MFSEL1, 13,    none, NONE, 0),
0686     WPCM450_PINCFG(59,    hg6, MFSEL2, 30,    none, NONE, 0),
0687     WPCM450_PINCFG(60,    hg7, MFSEL2, 31,    sdio, MFSEL1, 30),
0688     WPCM450_PINCFG(61,   hsp1, MFSEL1, 10,    none, NONE, 0),
0689     WPCM450_PINCFG(62,   hsp1, MFSEL1, 10,    none, NONE, 0),
0690     WPCM450_PINCFG(63,   hsp1, MFSEL1, 10,    none, NONE, 0),
0691 
0692     WPCM450_PINCFG(64,    fi0, MFSEL2, 0,     none, NONE, 0),
0693     WPCM450_PINCFG(65,    fi1, MFSEL2, 1,     none, NONE, 0),
0694     WPCM450_PINCFG(66,    fi2, MFSEL2, 2,     none, NONE, 0),
0695     WPCM450_PINCFG(67,    fi3, MFSEL2, 3,     none, NONE, 0),
0696     WPCM450_PINCFG(68,    fi4, MFSEL2, 4,     none, NONE, 0),
0697     WPCM450_PINCFG(69,    fi5, MFSEL2, 5,     none, NONE, 0),
0698     WPCM450_PINCFG(70,    fi6, MFSEL2, 6,     none, NONE, 0),
0699     WPCM450_PINCFG(71,    fi7, MFSEL2, 7,     none, NONE, 0),
0700     WPCM450_PINCFG(72,    fi8, MFSEL2, 8,     none, NONE, 0),
0701     WPCM450_PINCFG(73,    fi9, MFSEL2, 9,     none, NONE, 0),
0702     WPCM450_PINCFG(74,   fi10, MFSEL2, 10,    none, NONE, 0),
0703     WPCM450_PINCFG(75,   fi11, MFSEL2, 11,    none, NONE, 0),
0704     WPCM450_PINCFG(76,   fi12, MFSEL2, 12,    none, NONE, 0),
0705     WPCM450_PINCFG(77,   fi13, MFSEL2, 13,    none, NONE, 0),
0706     WPCM450_PINCFG(78,   fi14, MFSEL2, 14,    none, NONE, 0),
0707     WPCM450_PINCFG(79,   fi15, MFSEL2, 15,    none, NONE, 0),
0708     WPCM450_PINCFG(80,   pwm0, MFSEL2, 16,    none, NONE, 0),
0709     WPCM450_PINCFG(81,   pwm1, MFSEL2, 17,    none, NONE, 0),
0710     WPCM450_PINCFG(82,   pwm2, MFSEL2, 18,    none, NONE, 0),
0711     WPCM450_PINCFG(83,   pwm3, MFSEL2, 19,    none, NONE, 0),
0712     WPCM450_PINCFG(84,  rmii2, MFSEL1, 14,    none, NONE, 0),
0713     WPCM450_PINCFG(85,  rmii2, MFSEL1, 14,    none, NONE, 0),
0714     WPCM450_PINCFG(86,  rmii2, MFSEL1, 14,    none, NONE, 0),
0715     WPCM450_PINCFG(87,  rmii2, MFSEL1, 14,    none, NONE, 0),
0716     WPCM450_PINCFG(88,  rmii2, MFSEL1, 14,    none, NONE, 0),
0717     WPCM450_PINCFG(89,  rmii2, MFSEL1, 14,    none, NONE, 0),
0718     WPCM450_PINCFG(90,  r2err, MFSEL1, 15,    none, NONE, 0),
0719     WPCM450_PINCFG(91,   r2md, MFSEL1, 16,    none, NONE, 0),
0720     WPCM450_PINCFG(92,   r2md, MFSEL1, 16,    none, NONE, 0),
0721     WPCM450_PINCFG(93,   kbcc, MFSEL1, 17,    none, NONE, 0),
0722     WPCM450_PINCFG(94,   kbcc, MFSEL1, 17,    none, NONE, 0),
0723     WPCM450_PINCFG(95,   none, NONE, 0,       none, NONE, 0),
0724 
0725     WPCM450_PINCFG(96,   none, NONE, 0,       none, NONE, 0),
0726     WPCM450_PINCFG(97,   none, NONE, 0,       none, NONE, 0),
0727     WPCM450_PINCFG(98,   none, NONE, 0,       none, NONE, 0),
0728     WPCM450_PINCFG(99,   none, NONE, 0,       none, NONE, 0),
0729     WPCM450_PINCFG(100,  none, NONE, 0,       none, NONE, 0),
0730     WPCM450_PINCFG(101,  none, NONE, 0,       none, NONE, 0),
0731     WPCM450_PINCFG(102,  none, NONE, 0,       none, NONE, 0),
0732     WPCM450_PINCFG(103,  none, NONE, 0,       none, NONE, 0),
0733     WPCM450_PINCFG(104,  none, NONE, 0,       none, NONE, 0),
0734     WPCM450_PINCFG(105,  none, NONE, 0,       none, NONE, 0),
0735     WPCM450_PINCFG(106,  none, NONE, 0,       none, NONE, 0),
0736     WPCM450_PINCFG(107,  none, NONE, 0,       none, NONE, 0),
0737     WPCM450_PINCFG(108,  none, NONE, 0,       none, NONE, 0), /* DVO */
0738     WPCM450_PINCFG(109,  none, NONE, 0,       none, NONE, 0), /* DVO */
0739     WPCM450_PINCFG(110,  none, NONE, 0,       none, NONE, 0), /* DVO */
0740     WPCM450_PINCFG(111,  none, NONE, 0,       none, NONE, 0), /* DVO */
0741     WPCM450_PINCFG(112,  none, NONE, 0,       none, NONE, 0), /* DVO */
0742     WPCM450_PINCFG(113,  none, NONE, 0,       none, NONE, 0), /* DVO */
0743     WPCM450_PINCFG(114,  smb0, MFSEL1, 6,     none, NONE, 0),
0744     WPCM450_PINCFG(115,  smb0, MFSEL1, 6,     none, NONE, 0),
0745     WPCM450_PINCFG(116,  smb1, MFSEL1, 7,     none, NONE, 0),
0746     WPCM450_PINCFG(117,  smb1, MFSEL1, 7,     none, NONE, 0),
0747     WPCM450_PINCFG(118,  smb2, MFSEL1, 8,     none, NONE, 0),
0748     WPCM450_PINCFG(119,  smb2, MFSEL1, 8,     none, NONE, 0),
0749     WPCM450_PINCFG(120,  none, NONE, 0,       none, NONE, 0), /* DVO */
0750     WPCM450_PINCFG(121,  none, NONE, 0,       none, NONE, 0), /* DVO */
0751     WPCM450_PINCFG(122,  none, NONE, 0,       none, NONE, 0), /* DVO */
0752     WPCM450_PINCFG(123,  none, NONE, 0,       none, NONE, 0), /* DVO */
0753     WPCM450_PINCFG(124,  none, NONE, 0,       none, NONE, 0), /* DVO */
0754     WPCM450_PINCFG(125,  none, NONE, 0,       none, NONE, 0), /* DVO */
0755     WPCM450_PINCFG(126,  none, NONE, 0,       none, NONE, 0), /* DVO */
0756     WPCM450_PINCFG(127,  none, NONE, 0,       none, NONE, 0), /* DVO */
0757 };
0758 
0759 #define WPCM450_PIN(n)      PINCTRL_PIN(n, "gpio" #n)
0760 
0761 static const struct pinctrl_pin_desc wpcm450_pins[] = {
0762     WPCM450_PIN(0),   WPCM450_PIN(1),   WPCM450_PIN(2),   WPCM450_PIN(3),
0763     WPCM450_PIN(4),   WPCM450_PIN(5),   WPCM450_PIN(6),   WPCM450_PIN(7),
0764     WPCM450_PIN(8),   WPCM450_PIN(9),   WPCM450_PIN(10),  WPCM450_PIN(11),
0765     WPCM450_PIN(12),  WPCM450_PIN(13),  WPCM450_PIN(14),  WPCM450_PIN(15),
0766     WPCM450_PIN(16),  WPCM450_PIN(17),  WPCM450_PIN(18),  WPCM450_PIN(19),
0767     WPCM450_PIN(20),  WPCM450_PIN(21),  WPCM450_PIN(22),  WPCM450_PIN(23),
0768     WPCM450_PIN(24),  WPCM450_PIN(25),  WPCM450_PIN(26),  WPCM450_PIN(27),
0769     WPCM450_PIN(28),  WPCM450_PIN(29),  WPCM450_PIN(30),  WPCM450_PIN(31),
0770     WPCM450_PIN(32),  WPCM450_PIN(33),  WPCM450_PIN(34),  WPCM450_PIN(35),
0771     WPCM450_PIN(36),  WPCM450_PIN(37),  WPCM450_PIN(38),  WPCM450_PIN(39),
0772     WPCM450_PIN(40),  WPCM450_PIN(41),  WPCM450_PIN(42),  WPCM450_PIN(43),
0773     WPCM450_PIN(44),  WPCM450_PIN(45),  WPCM450_PIN(46),  WPCM450_PIN(47),
0774     WPCM450_PIN(48),  WPCM450_PIN(49),  WPCM450_PIN(50),  WPCM450_PIN(51),
0775     WPCM450_PIN(52),  WPCM450_PIN(53),  WPCM450_PIN(54),  WPCM450_PIN(55),
0776     WPCM450_PIN(56),  WPCM450_PIN(57),  WPCM450_PIN(58),  WPCM450_PIN(59),
0777     WPCM450_PIN(60),  WPCM450_PIN(61),  WPCM450_PIN(62),  WPCM450_PIN(63),
0778     WPCM450_PIN(64),  WPCM450_PIN(65),  WPCM450_PIN(66),  WPCM450_PIN(67),
0779     WPCM450_PIN(68),  WPCM450_PIN(69),  WPCM450_PIN(70),  WPCM450_PIN(71),
0780     WPCM450_PIN(72),  WPCM450_PIN(73),  WPCM450_PIN(74),  WPCM450_PIN(75),
0781     WPCM450_PIN(76),  WPCM450_PIN(77),  WPCM450_PIN(78),  WPCM450_PIN(79),
0782     WPCM450_PIN(80),  WPCM450_PIN(81),  WPCM450_PIN(82),  WPCM450_PIN(83),
0783     WPCM450_PIN(84),  WPCM450_PIN(85),  WPCM450_PIN(86),  WPCM450_PIN(87),
0784     WPCM450_PIN(88),  WPCM450_PIN(89),  WPCM450_PIN(90),  WPCM450_PIN(91),
0785     WPCM450_PIN(92),  WPCM450_PIN(93),  WPCM450_PIN(94),  WPCM450_PIN(95),
0786     WPCM450_PIN(96),  WPCM450_PIN(97),  WPCM450_PIN(98),  WPCM450_PIN(99),
0787     WPCM450_PIN(100), WPCM450_PIN(101), WPCM450_PIN(102), WPCM450_PIN(103),
0788     WPCM450_PIN(104), WPCM450_PIN(105), WPCM450_PIN(106), WPCM450_PIN(107),
0789     WPCM450_PIN(108), WPCM450_PIN(109), WPCM450_PIN(110), WPCM450_PIN(111),
0790     WPCM450_PIN(112), WPCM450_PIN(113), WPCM450_PIN(114), WPCM450_PIN(115),
0791     WPCM450_PIN(116), WPCM450_PIN(117), WPCM450_PIN(118), WPCM450_PIN(119),
0792     WPCM450_PIN(120), WPCM450_PIN(121), WPCM450_PIN(122), WPCM450_PIN(123),
0793     WPCM450_PIN(124), WPCM450_PIN(125), WPCM450_PIN(126), WPCM450_PIN(127),
0794 };
0795 
0796 /* Enable mode in pin group */
0797 static void wpcm450_setfunc(struct regmap *gcr_regmap, const unsigned int *pin,
0798                 int npins, int func)
0799 {
0800     const struct wpcm450_pincfg *cfg;
0801     int i;
0802 
0803     for (i = 0; i < npins; i++) {
0804         cfg = &pincfg[pin[i]];
0805         if (func == fn_gpio || cfg->fn0 == func || cfg->fn1 == func) {
0806             if (cfg->reg0)
0807                 regmap_update_bits(gcr_regmap, cfg->reg0,
0808                            BIT(cfg->bit0),
0809                            (cfg->fn0 == func) ?  BIT(cfg->bit0) : 0);
0810             if (cfg->reg1)
0811                 regmap_update_bits(gcr_regmap, cfg->reg1,
0812                            BIT(cfg->bit1),
0813                            (cfg->fn1 == func) ?  BIT(cfg->bit1) : 0);
0814         }
0815     }
0816 }
0817 
0818 static int wpcm450_get_groups_count(struct pinctrl_dev *pctldev)
0819 {
0820     return ARRAY_SIZE(wpcm450_groups);
0821 }
0822 
0823 static const char *wpcm450_get_group_name(struct pinctrl_dev *pctldev,
0824                       unsigned int selector)
0825 {
0826     return wpcm450_groups[selector].name;
0827 }
0828 
0829 static int wpcm450_get_group_pins(struct pinctrl_dev *pctldev,
0830                   unsigned int selector,
0831                   const unsigned int **pins,
0832                   unsigned int *npins)
0833 {
0834     *npins = wpcm450_groups[selector].num_pins;
0835     *pins  = wpcm450_groups[selector].pins;
0836 
0837     return 0;
0838 }
0839 
0840 static int wpcm450_dt_node_to_map(struct pinctrl_dev *pctldev,
0841                   struct device_node *np_config,
0842                   struct pinctrl_map **map,
0843                   u32 *num_maps)
0844 {
0845     return pinconf_generic_dt_node_to_map(pctldev, np_config,
0846                           map, num_maps,
0847                           PIN_MAP_TYPE_INVALID);
0848 }
0849 
0850 static void wpcm450_dt_free_map(struct pinctrl_dev *pctldev,
0851                 struct pinctrl_map *map, u32 num_maps)
0852 {
0853     kfree(map);
0854 }
0855 
0856 static const struct pinctrl_ops wpcm450_pinctrl_ops = {
0857     .get_groups_count = wpcm450_get_groups_count,
0858     .get_group_name = wpcm450_get_group_name,
0859     .get_group_pins = wpcm450_get_group_pins,
0860     .dt_node_to_map = wpcm450_dt_node_to_map,
0861     .dt_free_map = wpcm450_dt_free_map,
0862 };
0863 
0864 static int wpcm450_get_functions_count(struct pinctrl_dev *pctldev)
0865 {
0866     return ARRAY_SIZE(wpcm450_funcs);
0867 }
0868 
0869 static const char *wpcm450_get_function_name(struct pinctrl_dev *pctldev,
0870                          unsigned int function)
0871 {
0872     return wpcm450_funcs[function].name;
0873 }
0874 
0875 static int wpcm450_get_function_groups(struct pinctrl_dev *pctldev,
0876                        unsigned int function,
0877                        const char * const **groups,
0878                        unsigned int * const ngroups)
0879 {
0880     *ngroups = wpcm450_funcs[function].ngroups;
0881     *groups  = wpcm450_funcs[function].groups;
0882 
0883     return 0;
0884 }
0885 
0886 static int wpcm450_pinmux_set_mux(struct pinctrl_dev *pctldev,
0887                   unsigned int function,
0888                   unsigned int group)
0889 {
0890     struct wpcm450_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0891 
0892     wpcm450_setfunc(pctrl->gcr_regmap, wpcm450_groups[group].pins,
0893             wpcm450_groups[group].num_pins, function);
0894 
0895     return 0;
0896 }
0897 
0898 static const struct pinmux_ops wpcm450_pinmux_ops = {
0899     .get_functions_count = wpcm450_get_functions_count,
0900     .get_function_name = wpcm450_get_function_name,
0901     .get_function_groups = wpcm450_get_function_groups,
0902     .set_mux = wpcm450_pinmux_set_mux,
0903 };
0904 
0905 static int debounce_bitnum(int gpio)
0906 {
0907     if (gpio >= 0 && gpio < 16)
0908         return gpio;
0909     return -EINVAL;
0910 }
0911 
0912 static int wpcm450_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
0913                   unsigned long *config)
0914 {
0915     struct wpcm450_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0916     enum pin_config_param param = pinconf_to_config_param(*config);
0917     unsigned long flags;
0918     int bit;
0919     u32 reg;
0920 
0921     switch (param) {
0922     case PIN_CONFIG_INPUT_DEBOUNCE:
0923         bit = debounce_bitnum(pin);
0924         if (bit < 0)
0925             return bit;
0926 
0927         raw_spin_lock_irqsave(&pctrl->lock, flags);
0928         reg = ioread32(pctrl->gpio_base + WPCM450_GPEVDBNC);
0929         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
0930 
0931         *config = pinconf_to_config_packed(param, !!(reg & BIT(bit)));
0932         return 0;
0933     default:
0934         return -ENOTSUPP;
0935     }
0936 }
0937 
0938 static int wpcm450_config_set_one(struct wpcm450_pinctrl *pctrl,
0939                   unsigned int pin, unsigned long config)
0940 {
0941     enum pin_config_param param = pinconf_to_config_param(config);
0942     unsigned long flags;
0943     unsigned long reg;
0944     int bit;
0945     int arg;
0946 
0947     switch (param) {
0948     case PIN_CONFIG_INPUT_DEBOUNCE:
0949         bit = debounce_bitnum(pin);
0950         if (bit < 0)
0951             return bit;
0952 
0953         arg = pinconf_to_config_argument(config);
0954 
0955         raw_spin_lock_irqsave(&pctrl->lock, flags);
0956         reg = ioread32(pctrl->gpio_base + WPCM450_GPEVDBNC);
0957         __assign_bit(bit, &reg, arg);
0958         iowrite32(reg, pctrl->gpio_base + WPCM450_GPEVDBNC);
0959         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
0960         return 0;
0961     default:
0962         return -ENOTSUPP;
0963     }
0964 }
0965 
0966 static int wpcm450_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
0967                   unsigned long *configs, unsigned int num_configs)
0968 {
0969     struct wpcm450_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0970     int ret;
0971 
0972     while (num_configs--) {
0973         ret = wpcm450_config_set_one(pctrl, pin, *configs++);
0974         if (ret)
0975             return ret;
0976     }
0977 
0978     return 0;
0979 }
0980 
0981 static const struct pinconf_ops wpcm450_pinconf_ops = {
0982     .is_generic = true,
0983     .pin_config_get = wpcm450_config_get,
0984     .pin_config_set = wpcm450_config_set,
0985 };
0986 
0987 static struct pinctrl_desc wpcm450_pinctrl_desc = {
0988     .name = "wpcm450-pinctrl",
0989     .pins = wpcm450_pins,
0990     .npins = ARRAY_SIZE(wpcm450_pins),
0991     .pctlops = &wpcm450_pinctrl_ops,
0992     .pmxops = &wpcm450_pinmux_ops,
0993     .confops = &wpcm450_pinconf_ops,
0994     .owner = THIS_MODULE,
0995 };
0996 
0997 static int wpcm450_gpio_set_config(struct gpio_chip *chip,
0998                    unsigned int offset, unsigned long config)
0999 {
1000     struct wpcm450_gpio *gpio = gpiochip_get_data(chip);
1001 
1002     return wpcm450_config_set_one(gpio->pctrl, offset, config);
1003 }
1004 
1005 static int wpcm450_gpio_add_pin_ranges(struct gpio_chip *chip)
1006 {
1007     struct wpcm450_gpio *gpio = gpiochip_get_data(chip);
1008     const struct wpcm450_bank *bank = gpio->bank;
1009 
1010     return gpiochip_add_pin_range(&gpio->gc, dev_name(gpio->pctrl->dev),
1011                       0, bank->base, bank->length);
1012 }
1013 
1014 static int wpcm450_gpio_register(struct platform_device *pdev,
1015                  struct wpcm450_pinctrl *pctrl)
1016 {
1017     struct device *dev = &pdev->dev;
1018     struct fwnode_handle *child;
1019     int ret;
1020 
1021     pctrl->gpio_base = devm_platform_ioremap_resource(pdev, 0);
1022     if (IS_ERR(pctrl->gpio_base))
1023         return dev_err_probe(dev, PTR_ERR(pctrl->gpio_base),
1024                      "Resource fail for GPIO controller\n");
1025 
1026     device_for_each_child_node(dev, child)  {
1027         void __iomem *dat = NULL;
1028         void __iomem *set = NULL;
1029         void __iomem *dirout = NULL;
1030         unsigned long flags = 0;
1031         const struct wpcm450_bank *bank;
1032         struct wpcm450_gpio *gpio;
1033         struct gpio_irq_chip *girq;
1034         u32 reg;
1035         int i;
1036 
1037         if (!fwnode_property_read_bool(child, "gpio-controller"))
1038             continue;
1039 
1040         ret = fwnode_property_read_u32(child, "reg", &reg);
1041         if (ret < 0)
1042             return ret;
1043 
1044         gpio = &pctrl->gpio_bank[reg];
1045         gpio->pctrl = pctrl;
1046 
1047         if (reg >= WPCM450_NUM_BANKS)
1048             return dev_err_probe(dev, -EINVAL,
1049                          "GPIO index %d out of range!\n", reg);
1050 
1051         bank = &wpcm450_banks[reg];
1052         gpio->bank = bank;
1053 
1054         dat = pctrl->gpio_base + bank->datain;
1055         if (bank->dataout) {
1056             set = pctrl->gpio_base + bank->dataout;
1057             dirout = pctrl->gpio_base + bank->cfg0;
1058         } else {
1059             flags = BGPIOF_NO_OUTPUT;
1060         }
1061         ret = bgpio_init(&gpio->gc, dev, 4,
1062                  dat, set, NULL, dirout, NULL, flags);
1063         if (ret < 0)
1064             return dev_err_probe(dev, ret, "GPIO initialization failed\n");
1065 
1066         gpio->gc.ngpio = bank->length;
1067         gpio->gc.set_config = wpcm450_gpio_set_config;
1068         gpio->gc.fwnode = child;
1069         gpio->gc.add_pin_ranges = wpcm450_gpio_add_pin_ranges;
1070 
1071         gpio->irqc = wpcm450_gpio_irqchip;
1072         girq = &gpio->gc.irq;
1073         girq->chip = &gpio->irqc;
1074         girq->parent_handler = wpcm450_gpio_irqhandler;
1075         girq->parents = devm_kcalloc(dev, WPCM450_NUM_GPIO_IRQS,
1076                          sizeof(*girq->parents), GFP_KERNEL);
1077         if (!girq->parents)
1078             return -ENOMEM;
1079         girq->default_type = IRQ_TYPE_NONE;
1080         girq->handler = handle_bad_irq;
1081 
1082         girq->num_parents = 0;
1083         for (i = 0; i < WPCM450_NUM_GPIO_IRQS; i++) {
1084             int irq = fwnode_irq_get(child, i);
1085 
1086             if (irq < 0)
1087                 break;
1088 
1089             girq->parents[i] = irq;
1090             girq->num_parents++;
1091         }
1092 
1093         ret = devm_gpiochip_add_data(dev, &gpio->gc, gpio);
1094         if (ret)
1095             return dev_err_probe(dev, ret, "Failed to add GPIO chip\n");
1096     }
1097 
1098     return 0;
1099 }
1100 
1101 static int wpcm450_pinctrl_probe(struct platform_device *pdev)
1102 {
1103     struct device *dev = &pdev->dev;
1104     struct wpcm450_pinctrl *pctrl;
1105     int ret;
1106 
1107     pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
1108     if (!pctrl)
1109         return -ENOMEM;
1110 
1111     pctrl->dev = &pdev->dev;
1112     raw_spin_lock_init(&pctrl->lock);
1113     dev_set_drvdata(dev, pctrl);
1114 
1115     pctrl->gcr_regmap =
1116         syscon_regmap_lookup_by_compatible("nuvoton,wpcm450-gcr");
1117     if (IS_ERR(pctrl->gcr_regmap))
1118         return dev_err_probe(dev, PTR_ERR(pctrl->gcr_regmap),
1119                      "Failed to find nuvoton,wpcm450-gcr\n");
1120 
1121     pctrl->pctldev = devm_pinctrl_register(dev,
1122                            &wpcm450_pinctrl_desc, pctrl);
1123     if (IS_ERR(pctrl->pctldev))
1124         return dev_err_probe(dev, PTR_ERR(pctrl->pctldev),
1125                      "Failed to register pinctrl device\n");
1126 
1127     ret = wpcm450_gpio_register(pdev, pctrl);
1128     if (ret < 0)
1129         return ret;
1130 
1131     return 0;
1132 }
1133 
1134 static const struct of_device_id wpcm450_pinctrl_match[] = {
1135     { .compatible = "nuvoton,wpcm450-pinctrl" },
1136     { }
1137 };
1138 MODULE_DEVICE_TABLE(of, wpcm450_pinctrl_match);
1139 
1140 static struct platform_driver wpcm450_pinctrl_driver = {
1141     .probe = wpcm450_pinctrl_probe,
1142     .driver = {
1143         .name = "wpcm450-pinctrl",
1144         .of_match_table = wpcm450_pinctrl_match,
1145     },
1146 };
1147 module_platform_driver(wpcm450_pinctrl_driver);
1148 
1149 MODULE_LICENSE("GPL v2");
1150 MODULE_AUTHOR("Jonathan Neuschäfer <j.neuschaefer@gmx.net>");
1151 MODULE_DESCRIPTION("Nuvoton WPCM450 Pinctrl and GPIO driver");
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