pinctrl/nuvoton/pinctrl-npcm7xx.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (c) 2016-2018 Nuvoton Technology corporation.
0003 // Copyright (c) 2016, Dell Inc
0004
0005 #include <linux/device.h>
0006 #include <linux/gpio/driver.h>
0007 #include <linux/interrupt.h>
0008 #include <linux/irq.h>
0009 #include <linux/mfd/syscon.h>
0010 #include <linux/module.h>
0011 #include <linux/of.h>
0012 #include <linux/of_address.h>
0013 #include <linux/of_irq.h>
0014 #include <linux/pinctrl/machine.h>
0015 #include <linux/pinctrl/pinconf.h>
0016 #include <linux/pinctrl/pinconf-generic.h>
0017 #include <linux/pinctrl/pinctrl.h>
0018 #include <linux/pinctrl/pinmux.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/property.h>
0021 #include <linux/regmap.h>
0022
0023 /* GCR registers */
0024 #define NPCM7XX_GCR_PDID    0x00
0025 #define NPCM7XX_GCR_MFSEL1  0x0C
0026 #define NPCM7XX_GCR_MFSEL2  0x10
0027 #define NPCM7XX_GCR_MFSEL3  0x64
0028 #define NPCM7XX_GCR_MFSEL4  0xb0
0029 #define NPCM7XX_GCR_CPCTL   0xD0
0030 #define NPCM7XX_GCR_CP2BST  0xD4
0031 #define NPCM7XX_GCR_B2CPNT  0xD8
0032 #define NPCM7XX_GCR_I2CSEGSEL   0xE0
0033 #define NPCM7XX_GCR_I2CSEGCTL   0xE4
0034 #define NPCM7XX_GCR_SRCNT   0x68
0035 #define NPCM7XX_GCR_FLOCKR1 0x74
0036 #define NPCM7XX_GCR_DSCNT   0x78
0037
0038 #define SRCNT_ESPI      BIT(3)
0039
0040 /* GPIO registers */
0041 #define NPCM7XX_GP_N_TLOCK1 0x00
0042 #define NPCM7XX_GP_N_DIN    0x04 /* Data IN */
0043 #define NPCM7XX_GP_N_POL    0x08 /* Polarity */
0044 #define NPCM7XX_GP_N_DOUT   0x0c /* Data OUT */
0045 #define NPCM7XX_GP_N_OE     0x10 /* Output Enable */
0046 #define NPCM7XX_GP_N_OTYP   0x14
0047 #define NPCM7XX_GP_N_MP     0x18
0048 #define NPCM7XX_GP_N_PU     0x1c /* Pull-up */
0049 #define NPCM7XX_GP_N_PD     0x20 /* Pull-down */
0050 #define NPCM7XX_GP_N_DBNC   0x24 /* Debounce */
0051 #define NPCM7XX_GP_N_EVTYP  0x28 /* Event Type */
0052 #define NPCM7XX_GP_N_EVBE   0x2c /* Event Both Edge */
0053 #define NPCM7XX_GP_N_OBL0   0x30
0054 #define NPCM7XX_GP_N_OBL1   0x34
0055 #define NPCM7XX_GP_N_OBL2   0x38
0056 #define NPCM7XX_GP_N_OBL3   0x3c
0057 #define NPCM7XX_GP_N_EVEN   0x40 /* Event Enable */
0058 #define NPCM7XX_GP_N_EVENS  0x44 /* Event Set (enable) */
0059 #define NPCM7XX_GP_N_EVENC  0x48 /* Event Clear (disable) */
0060 #define NPCM7XX_GP_N_EVST   0x4c /* Event Status */
0061 #define NPCM7XX_GP_N_SPLCK  0x50
0062 #define NPCM7XX_GP_N_MPLCK  0x54
0063 #define NPCM7XX_GP_N_IEM    0x58 /* Input Enable */
0064 #define NPCM7XX_GP_N_OSRC   0x5c
0065 #define NPCM7XX_GP_N_ODSC   0x60
0066 #define NPCM7XX_GP_N_DOS    0x68 /* Data OUT Set */
0067 #define NPCM7XX_GP_N_DOC    0x6c /* Data OUT Clear */
0068 #define NPCM7XX_GP_N_OES    0x70 /* Output Enable Set */
0069 #define NPCM7XX_GP_N_OEC    0x74 /* Output Enable Clear */
0070 #define NPCM7XX_GP_N_TLOCK2 0x7c
0071
0072 #define NPCM7XX_GPIO_PER_BANK   32
0073 #define NPCM7XX_GPIO_BANK_NUM   8
0074 #define NPCM7XX_GCR_NONE    0
0075
0076 /* Structure for register banks */
0077 struct npcm7xx_gpio {
0078     void __iomem        *base;
0079     struct gpio_chip    gc;
0080     int         irqbase;
0081     int         irq;
0082     struct irq_chip     irq_chip;
0083     u32         pinctrl_id;
0084     int (*direction_input)(struct gpio_chip *chip, unsigned offset);
0085     int (*direction_output)(struct gpio_chip *chip, unsigned offset,
0086                 int value);
0087     int (*request)(struct gpio_chip *chip, unsigned offset);
0088     void (*free)(struct gpio_chip *chip, unsigned offset);
0089 };
0090
0091 struct npcm7xx_pinctrl {
0092     struct pinctrl_dev  *pctldev;
0093     struct device       *dev;
0094     struct npcm7xx_gpio gpio_bank[NPCM7XX_GPIO_BANK_NUM];
0095     struct irq_domain   *domain;
0096     struct regmap       *gcr_regmap;
0097     void __iomem        *regs;
0098     u32         bank_num;
0099 };
0100
0101 /* GPIO handling in the pinctrl driver */
0102 static void npcm_gpio_set(struct gpio_chip *gc, void __iomem *reg,
0103               unsigned int pinmask)
0104 {
0105     unsigned long flags;
0106     unsigned long val;
0107
0108     raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
0109
0110     val = ioread32(reg) | pinmask;
0111     iowrite32(val, reg);
0112
0113     raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
0114 }
0115
0116 static void npcm_gpio_clr(struct gpio_chip *gc, void __iomem *reg,
0117               unsigned int pinmask)
0118 {
0119     unsigned long flags;
0120     unsigned long val;
0121
0122     raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
0123
0124     val = ioread32(reg) & ~pinmask;
0125     iowrite32(val, reg);
0126
0127     raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
0128 }
0129
0130 static void npcmgpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
0131 {
0132     struct npcm7xx_gpio *bank = gpiochip_get_data(chip);
0133
0134     seq_printf(s, "-- module %d [gpio%d - %d]\n",
0135            bank->gc.base / bank->gc.ngpio,
0136            bank->gc.base,
0137            bank->gc.base + bank->gc.ngpio);
0138     seq_printf(s, "DIN :%.8x DOUT:%.8x IE  :%.8x OE  :%.8x\n",
0139            ioread32(bank->base + NPCM7XX_GP_N_DIN),
0140            ioread32(bank->base + NPCM7XX_GP_N_DOUT),
0141            ioread32(bank->base + NPCM7XX_GP_N_IEM),
0142            ioread32(bank->base + NPCM7XX_GP_N_OE));
0143     seq_printf(s, "PU  :%.8x PD  :%.8x DB  :%.8x POL :%.8x\n",
0144            ioread32(bank->base + NPCM7XX_GP_N_PU),
0145            ioread32(bank->base + NPCM7XX_GP_N_PD),
0146            ioread32(bank->base + NPCM7XX_GP_N_DBNC),
0147            ioread32(bank->base + NPCM7XX_GP_N_POL));
0148     seq_printf(s, "ETYP:%.8x EVBE:%.8x EVEN:%.8x EVST:%.8x\n",
0149            ioread32(bank->base + NPCM7XX_GP_N_EVTYP),
0150            ioread32(bank->base + NPCM7XX_GP_N_EVBE),
0151            ioread32(bank->base + NPCM7XX_GP_N_EVEN),
0152            ioread32(bank->base + NPCM7XX_GP_N_EVST));
0153     seq_printf(s, "OTYP:%.8x OSRC:%.8x ODSC:%.8x\n",
0154            ioread32(bank->base + NPCM7XX_GP_N_OTYP),
0155            ioread32(bank->base + NPCM7XX_GP_N_OSRC),
0156            ioread32(bank->base + NPCM7XX_GP_N_ODSC));
0157     seq_printf(s, "OBL0:%.8x OBL1:%.8x OBL2:%.8x OBL3:%.8x\n",
0158            ioread32(bank->base + NPCM7XX_GP_N_OBL0),
0159            ioread32(bank->base + NPCM7XX_GP_N_OBL1),
0160            ioread32(bank->base + NPCM7XX_GP_N_OBL2),
0161            ioread32(bank->base + NPCM7XX_GP_N_OBL3));
0162     seq_printf(s, "SLCK:%.8x MLCK:%.8x\n",
0163            ioread32(bank->base + NPCM7XX_GP_N_SPLCK),
0164            ioread32(bank->base + NPCM7XX_GP_N_MPLCK));
0165 }
0166
0167 static int npcmgpio_direction_input(struct gpio_chip *chip, unsigned int offset)
0168 {
0169     struct npcm7xx_gpio *bank = gpiochip_get_data(chip);
0170     int ret;
0171
0172     ret = pinctrl_gpio_direction_input(offset + chip->base);
0173     if (ret)
0174         return ret;
0175
0176     return bank->direction_input(chip, offset);
0177 }
0178
0179 /* Set GPIO to Output with initial value */
0180 static int npcmgpio_direction_output(struct gpio_chip *chip,
0181                      unsigned int offset, int value)
0182 {
0183     struct npcm7xx_gpio *bank = gpiochip_get_data(chip);
0184     int ret;
0185
0186     dev_dbg(chip->parent, "gpio_direction_output: offset%d = %x\n", offset,
0187         value);
0188
0189     ret = pinctrl_gpio_direction_output(offset + chip->base);
0190     if (ret)
0191         return ret;
0192
0193     return bank->direction_output(chip, offset, value);
0194 }
0195
0196 static int npcmgpio_gpio_request(struct gpio_chip *chip, unsigned int offset)
0197 {
0198     struct npcm7xx_gpio *bank = gpiochip_get_data(chip);
0199     int ret;
0200
0201     dev_dbg(chip->parent, "gpio_request: offset%d\n", offset);
0202     ret = pinctrl_gpio_request(offset + chip->base);
0203     if (ret)
0204         return ret;
0205
0206     return bank->request(chip, offset);
0207 }
0208
0209 static void npcmgpio_gpio_free(struct gpio_chip *chip, unsigned int offset)
0210 {
0211     dev_dbg(chip->parent, "gpio_free: offset%d\n", offset);
0212     pinctrl_gpio_free(offset + chip->base);
0213 }
0214
0215 static void npcmgpio_irq_handler(struct irq_desc *desc)
0216 {
0217     struct gpio_chip *gc;
0218     struct irq_chip *chip;
0219     struct npcm7xx_gpio *bank;
0220     unsigned long sts, en, bit;
0221
0222     gc = irq_desc_get_handler_data(desc);
0223     bank = gpiochip_get_data(gc);
0224     chip = irq_desc_get_chip(desc);
0225
0226     chained_irq_enter(chip, desc);
0227     sts = ioread32(bank->base + NPCM7XX_GP_N_EVST);
0228     en  = ioread32(bank->base + NPCM7XX_GP_N_EVEN);
0229     dev_dbg(bank->gc.parent, "==> got irq sts %.8lx %.8lx\n", sts,
0230         en);
0231
0232     sts &= en;
0233     for_each_set_bit(bit, &sts, NPCM7XX_GPIO_PER_BANK)
0234         generic_handle_domain_irq(gc->irq.domain, bit);
0235     chained_irq_exit(chip, desc);
0236 }
0237
0238 static int npcmgpio_set_irq_type(struct irq_data *d, unsigned int type)
0239 {
0240     struct npcm7xx_gpio *bank =
0241         gpiochip_get_data(irq_data_get_irq_chip_data(d));
0242     unsigned int gpio = BIT(d->hwirq);
0243
0244     dev_dbg(bank->gc.parent, "setirqtype: %u.%u = %u\n", gpio,
0245         d->irq, type);
0246     switch (type) {
0247     case IRQ_TYPE_EDGE_RISING:
0248         dev_dbg(bank->gc.parent, "edge.rising\n");
0249         npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio);
0250         npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio);
0251         break;
0252     case IRQ_TYPE_EDGE_FALLING:
0253         dev_dbg(bank->gc.parent, "edge.falling\n");
0254         npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio);
0255         npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio);
0256         break;
0257     case IRQ_TYPE_EDGE_BOTH:
0258         dev_dbg(bank->gc.parent, "edge.both\n");
0259         npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_EVBE, gpio);
0260         break;
0261     case IRQ_TYPE_LEVEL_LOW:
0262         dev_dbg(bank->gc.parent, "level.low\n");
0263         npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio);
0264         break;
0265     case IRQ_TYPE_LEVEL_HIGH:
0266         dev_dbg(bank->gc.parent, "level.high\n");
0267         npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_POL, gpio);
0268         break;
0269     default:
0270         dev_dbg(bank->gc.parent, "invalid irq type\n");
0271         return -EINVAL;
0272     }
0273
0274     if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
0275         npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_EVTYP, gpio);
0276         irq_set_handler_locked(d, handle_level_irq);
0277     } else if (type & (IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_EDGE_RISING
0278                | IRQ_TYPE_EDGE_FALLING)) {
0279         npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_EVTYP, gpio);
0280         irq_set_handler_locked(d, handle_edge_irq);
0281     }
0282
0283     return 0;
0284 }
0285
0286 static void npcmgpio_irq_ack(struct irq_data *d)
0287 {
0288     struct npcm7xx_gpio *bank =
0289         gpiochip_get_data(irq_data_get_irq_chip_data(d));
0290     unsigned int gpio = d->hwirq;
0291
0292     dev_dbg(bank->gc.parent, "irq_ack: %u.%u\n", gpio, d->irq);
0293     iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVST);
0294 }
0295
0296 /* Disable GPIO interrupt */
0297 static void npcmgpio_irq_mask(struct irq_data *d)
0298 {
0299     struct npcm7xx_gpio *bank =
0300         gpiochip_get_data(irq_data_get_irq_chip_data(d));
0301     unsigned int gpio = d->hwirq;
0302
0303     /* Clear events */
0304     dev_dbg(bank->gc.parent, "irq_mask: %u.%u\n", gpio, d->irq);
0305     iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENC);
0306 }
0307
0308 /* Enable GPIO interrupt */
0309 static void npcmgpio_irq_unmask(struct irq_data *d)
0310 {
0311     struct npcm7xx_gpio *bank =
0312         gpiochip_get_data(irq_data_get_irq_chip_data(d));
0313     unsigned int gpio = d->hwirq;
0314
0315     /* Enable events */
0316     dev_dbg(bank->gc.parent, "irq_unmask: %u.%u\n", gpio, d->irq);
0317     iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENS);
0318 }
0319
0320 static unsigned int npcmgpio_irq_startup(struct irq_data *d)
0321 {
0322     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0323     unsigned int gpio = d->hwirq;
0324
0325     /* active-high, input, clear interrupt, enable interrupt */
0326     dev_dbg(gc->parent, "startup: %u.%u\n", gpio, d->irq);
0327     npcmgpio_direction_input(gc, gpio);
0328     npcmgpio_irq_ack(d);
0329     npcmgpio_irq_unmask(d);
0330
0331     return 0;
0332 }
0333
0334 static const struct irq_chip npcmgpio_irqchip = {
0335     .name = "NPCM7XX-GPIO-IRQ",
0336     .irq_ack = npcmgpio_irq_ack,
0337     .irq_unmask = npcmgpio_irq_unmask,
0338     .irq_mask = npcmgpio_irq_mask,
0339     .irq_set_type = npcmgpio_set_irq_type,
0340     .irq_startup = npcmgpio_irq_startup,
0341 };
0342
0343 /* pinmux handing in the pinctrl driver*/
0344 static const int smb0_pins[]  = { 115, 114 };
0345 static const int smb0b_pins[] = { 195, 194 };
0346 static const int smb0c_pins[] = { 202, 196 };
0347 static const int smb0d_pins[] = { 198, 199 };
0348 static const int smb0den_pins[] = { 197 };
0349
0350 static const int smb1_pins[]  = { 117, 116 };
0351 static const int smb1b_pins[] = { 126, 127 };
0352 static const int smb1c_pins[] = { 124, 125 };
0353 static const int smb1d_pins[] = { 4, 5 };
0354
0355 static const int smb2_pins[]  = { 119, 118 };
0356 static const int smb2b_pins[] = { 122, 123 };
0357 static const int smb2c_pins[] = { 120, 121 };
0358 static const int smb2d_pins[] = { 6, 7 };
0359
0360 static const int smb3_pins[]  = { 30, 31 };
0361 static const int smb3b_pins[] = { 39, 40 };
0362 static const int smb3c_pins[] = { 37, 38 };
0363 static const int smb3d_pins[] = { 59, 60 };
0364
0365 static const int smb4_pins[]  = { 28, 29 };
0366 static const int smb4b_pins[] = { 18, 19 };
0367 static const int smb4c_pins[] = { 20, 21 };
0368 static const int smb4d_pins[] = { 22, 23 };
0369 static const int smb4den_pins[] = { 17 };
0370
0371 static const int smb5_pins[]  = { 26, 27 };
0372 static const int smb5b_pins[] = { 13, 12 };
0373 static const int smb5c_pins[] = { 15, 14 };
0374 static const int smb5d_pins[] = { 94, 93 };
0375 static const int ga20kbc_pins[] = { 94, 93 };
0376
0377 static const int smb6_pins[]  = { 172, 171 };
0378 static const int smb7_pins[]  = { 174, 173 };
0379 static const int smb8_pins[]  = { 129, 128 };
0380 static const int smb9_pins[]  = { 131, 130 };
0381 static const int smb10_pins[] = { 133, 132 };
0382 static const int smb11_pins[] = { 135, 134 };
0383 static const int smb12_pins[] = { 221, 220 };
0384 static const int smb13_pins[] = { 223, 222 };
0385 static const int smb14_pins[] = { 22, 23 };
0386 static const int smb15_pins[] = { 20, 21 };
0387
0388 static const int fanin0_pins[] = { 64 };
0389 static const int fanin1_pins[] = { 65 };
0390 static const int fanin2_pins[] = { 66 };
0391 static const int fanin3_pins[] = { 67 };
0392 static const int fanin4_pins[] = { 68 };
0393 static const int fanin5_pins[] = { 69 };
0394 static const int fanin6_pins[] = { 70 };
0395 static const int fanin7_pins[] = { 71 };
0396 static const int fanin8_pins[] = { 72 };
0397 static const int fanin9_pins[] = { 73 };
0398 static const int fanin10_pins[] = { 74 };
0399 static const int fanin11_pins[] = { 75 };
0400 static const int fanin12_pins[] = { 76 };
0401 static const int fanin13_pins[] = { 77 };
0402 static const int fanin14_pins[] = { 78 };
0403 static const int fanin15_pins[] = { 79 };
0404 static const int faninx_pins[] = { 175, 176, 177, 203 };
0405
0406 static const int pwm0_pins[] = { 80 };
0407 static const int pwm1_pins[] = { 81 };
0408 static const int pwm2_pins[] = { 82 };
0409 static const int pwm3_pins[] = { 83 };
0410 static const int pwm4_pins[] = { 144 };
0411 static const int pwm5_pins[] = { 145 };
0412 static const int pwm6_pins[] = { 146 };
0413 static const int pwm7_pins[] = { 147 };
0414
0415 static const int uart1_pins[] = { 43, 44, 45, 46, 47, 61, 62, 63 };
0416 static const int uart2_pins[] = { 48, 49, 50, 51, 52, 53, 54, 55 };
0417
0418 /* RGMII 1 pin group */
0419 static const int rg1_pins[] = { 96, 97, 98, 99, 100, 101, 102, 103, 104, 105,
0420     106, 107 };
0421 /* RGMII 1 MD interface pin group */
0422 static const int rg1mdio_pins[] = { 108, 109 };
0423
0424 /* RGMII 2 pin group */
0425 static const int rg2_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212,
0426     213, 214, 215 };
0427 /* RGMII 2 MD interface pin group */
0428 static const int rg2mdio_pins[] = { 216, 217 };
0429
0430 static const int ddr_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212,
0431     213, 214, 215, 216, 217 };
0432 /* Serial I/O Expander 1 */
0433 static const int iox1_pins[] = { 0, 1, 2, 3 };
0434 /* Serial I/O Expander 2 */
0435 static const int iox2_pins[] = { 4, 5, 6, 7 };
0436 /* Host Serial I/O Expander 2 */
0437 static const int ioxh_pins[] = { 10, 11, 24, 25 };
0438
0439 static const int mmc_pins[] = { 152, 154, 156, 157, 158, 159 };
0440 static const int mmcwp_pins[] = { 153 };
0441 static const int mmccd_pins[] = { 155 };
0442 static const int mmcrst_pins[] = { 155 };
0443 static const int mmc8_pins[] = { 148, 149, 150, 151 };
0444
0445 /* RMII 1 pin groups */
0446 static const int r1_pins[] = { 178, 179, 180, 181, 182, 193, 201 };
0447 static const int r1err_pins[] = { 56 };
0448 static const int r1md_pins[] = { 57, 58 };
0449
0450 /* RMII 2 pin groups */
0451 static const int r2_pins[] = { 84, 85, 86, 87, 88, 89, 200 };
0452 static const int r2err_pins[] = { 90 };
0453 static const int r2md_pins[] = { 91, 92 };
0454
0455 static const int sd1_pins[] = { 136, 137, 138, 139, 140, 141, 142, 143 };
0456 static const int sd1pwr_pins[] = { 143 };
0457
0458 static const int wdog1_pins[] = { 218 };
0459 static const int wdog2_pins[] = { 219 };
0460
0461 /* BMC serial port 0 */
0462 static const int bmcuart0a_pins[] = { 41, 42 };
0463 static const int bmcuart0b_pins[] = { 48, 49 };
0464
0465 static const int bmcuart1_pins[] = { 43, 44, 62, 63 };
0466
0467 /* System Control Interrupt and Power Management Event pin group */
0468 static const int scipme_pins[] = { 169 };
0469 /* System Management Interrupt pin group */
0470 static const int sci_pins[] = { 170 };
0471 /* Serial Interrupt Line pin group */
0472 static const int serirq_pins[] = { 162 };
0473
0474 static const int clkout_pins[] = { 160 };
0475 static const int clkreq_pins[] = { 231 };
0476
0477 static const int jtag2_pins[] = { 43, 44, 45, 46, 47 };
0478 /* Graphics SPI Clock pin group */
0479 static const int gspi_pins[] = { 12, 13, 14, 15 };
0480
0481 static const int spix_pins[] = { 224, 225, 226, 227, 229, 230 };
0482 static const int spixcs1_pins[] = { 228 };
0483
0484 static const int pspi1_pins[] = { 175, 176, 177 };
0485 static const int pspi2_pins[] = { 17, 18, 19 };
0486
0487 static const int spi0cs1_pins[] = { 32 };
0488
0489 static const int spi3_pins[] = { 183, 184, 185, 186 };
0490 static const int spi3cs1_pins[] = { 187 };
0491 static const int spi3quad_pins[] = { 188, 189 };
0492 static const int spi3cs2_pins[] = { 188 };
0493 static const int spi3cs3_pins[] = { 189 };
0494
0495 static const int ddc_pins[] = { 204, 205, 206, 207 };
0496
0497 static const int lpc_pins[] = { 95, 161, 163, 164, 165, 166, 167 };
0498 static const int lpcclk_pins[] = { 168 };
0499 static const int espi_pins[] = { 95, 161, 163, 164, 165, 166, 167, 168 };
0500
0501 static const int lkgpo0_pins[] = { 16 };
0502 static const int lkgpo1_pins[] = { 8 };
0503 static const int lkgpo2_pins[] = { 9 };
0504
0505 static const int nprd_smi_pins[] = { 190 };
0506
0507 /*
0508  * pin:      name, number
0509  * group:    name, npins,   pins
0510  * function: name, ngroups, groups
0511  */
0512 struct npcm7xx_group {
0513     const char *name;
0514     const unsigned int *pins;
0515     int npins;
0516 };
0517
0518 #define NPCM7XX_GRPS \
0519     NPCM7XX_GRP(smb0), \
0520     NPCM7XX_GRP(smb0b), \
0521     NPCM7XX_GRP(smb0c), \
0522     NPCM7XX_GRP(smb0d), \
0523     NPCM7XX_GRP(smb0den), \
0524     NPCM7XX_GRP(smb1), \
0525     NPCM7XX_GRP(smb1b), \
0526     NPCM7XX_GRP(smb1c), \
0527     NPCM7XX_GRP(smb1d), \
0528     NPCM7XX_GRP(smb2), \
0529     NPCM7XX_GRP(smb2b), \
0530     NPCM7XX_GRP(smb2c), \
0531     NPCM7XX_GRP(smb2d), \
0532     NPCM7XX_GRP(smb3), \
0533     NPCM7XX_GRP(smb3b), \
0534     NPCM7XX_GRP(smb3c), \
0535     NPCM7XX_GRP(smb3d), \
0536     NPCM7XX_GRP(smb4), \
0537     NPCM7XX_GRP(smb4b), \
0538     NPCM7XX_GRP(smb4c), \
0539     NPCM7XX_GRP(smb4d), \
0540     NPCM7XX_GRP(smb4den), \
0541     NPCM7XX_GRP(smb5), \
0542     NPCM7XX_GRP(smb5b), \
0543     NPCM7XX_GRP(smb5c), \
0544     NPCM7XX_GRP(smb5d), \
0545     NPCM7XX_GRP(ga20kbc), \
0546     NPCM7XX_GRP(smb6), \
0547     NPCM7XX_GRP(smb7), \
0548     NPCM7XX_GRP(smb8), \
0549     NPCM7XX_GRP(smb9), \
0550     NPCM7XX_GRP(smb10), \
0551     NPCM7XX_GRP(smb11), \
0552     NPCM7XX_GRP(smb12), \
0553     NPCM7XX_GRP(smb13), \
0554     NPCM7XX_GRP(smb14), \
0555     NPCM7XX_GRP(smb15), \
0556     NPCM7XX_GRP(fanin0), \
0557     NPCM7XX_GRP(fanin1), \
0558     NPCM7XX_GRP(fanin2), \
0559     NPCM7XX_GRP(fanin3), \
0560     NPCM7XX_GRP(fanin4), \
0561     NPCM7XX_GRP(fanin5), \
0562     NPCM7XX_GRP(fanin6), \
0563     NPCM7XX_GRP(fanin7), \
0564     NPCM7XX_GRP(fanin8), \
0565     NPCM7XX_GRP(fanin9), \
0566     NPCM7XX_GRP(fanin10), \
0567     NPCM7XX_GRP(fanin11), \
0568     NPCM7XX_GRP(fanin12), \
0569     NPCM7XX_GRP(fanin13), \
0570     NPCM7XX_GRP(fanin14), \
0571     NPCM7XX_GRP(fanin15), \
0572     NPCM7XX_GRP(faninx), \
0573     NPCM7XX_GRP(pwm0), \
0574     NPCM7XX_GRP(pwm1), \
0575     NPCM7XX_GRP(pwm2), \
0576     NPCM7XX_GRP(pwm3), \
0577     NPCM7XX_GRP(pwm4), \
0578     NPCM7XX_GRP(pwm5), \
0579     NPCM7XX_GRP(pwm6), \
0580     NPCM7XX_GRP(pwm7), \
0581     NPCM7XX_GRP(rg1), \
0582     NPCM7XX_GRP(rg1mdio), \
0583     NPCM7XX_GRP(rg2), \
0584     NPCM7XX_GRP(rg2mdio), \
0585     NPCM7XX_GRP(ddr), \
0586     NPCM7XX_GRP(uart1), \
0587     NPCM7XX_GRP(uart2), \
0588     NPCM7XX_GRP(bmcuart0a), \
0589     NPCM7XX_GRP(bmcuart0b), \
0590     NPCM7XX_GRP(bmcuart1), \
0591     NPCM7XX_GRP(iox1), \
0592     NPCM7XX_GRP(iox2), \
0593     NPCM7XX_GRP(ioxh), \
0594     NPCM7XX_GRP(gspi), \
0595     NPCM7XX_GRP(mmc), \
0596     NPCM7XX_GRP(mmcwp), \
0597     NPCM7XX_GRP(mmccd), \
0598     NPCM7XX_GRP(mmcrst), \
0599     NPCM7XX_GRP(mmc8), \
0600     NPCM7XX_GRP(r1), \
0601     NPCM7XX_GRP(r1err), \
0602     NPCM7XX_GRP(r1md), \
0603     NPCM7XX_GRP(r2), \
0604     NPCM7XX_GRP(r2err), \
0605     NPCM7XX_GRP(r2md), \
0606     NPCM7XX_GRP(sd1), \
0607     NPCM7XX_GRP(sd1pwr), \
0608     NPCM7XX_GRP(wdog1), \
0609     NPCM7XX_GRP(wdog2), \
0610     NPCM7XX_GRP(scipme), \
0611     NPCM7XX_GRP(sci), \
0612     NPCM7XX_GRP(serirq), \
0613     NPCM7XX_GRP(jtag2), \
0614     NPCM7XX_GRP(spix), \
0615     NPCM7XX_GRP(spixcs1), \
0616     NPCM7XX_GRP(pspi1), \
0617     NPCM7XX_GRP(pspi2), \
0618     NPCM7XX_GRP(ddc), \
0619     NPCM7XX_GRP(clkreq), \
0620     NPCM7XX_GRP(clkout), \
0621     NPCM7XX_GRP(spi3), \
0622     NPCM7XX_GRP(spi3cs1), \
0623     NPCM7XX_GRP(spi3quad), \
0624     NPCM7XX_GRP(spi3cs2), \
0625     NPCM7XX_GRP(spi3cs3), \
0626     NPCM7XX_GRP(spi0cs1), \
0627     NPCM7XX_GRP(lpc), \
0628     NPCM7XX_GRP(lpcclk), \
0629     NPCM7XX_GRP(espi), \
0630     NPCM7XX_GRP(lkgpo0), \
0631     NPCM7XX_GRP(lkgpo1), \
0632     NPCM7XX_GRP(lkgpo2), \
0633     NPCM7XX_GRP(nprd_smi), \
0634     \
0635
0636 enum {
0637 #define NPCM7XX_GRP(x) fn_ ## x
0638     NPCM7XX_GRPS
0639     /* add placeholder for none/gpio */
0640     NPCM7XX_GRP(none),
0641     NPCM7XX_GRP(gpio),
0642 #undef NPCM7XX_GRP
0643 };
0644
0645 static struct npcm7xx_group npcm7xx_groups[] = {
0646 #define NPCM7XX_GRP(x) { .name = #x, .pins = x ## _pins, \
0647             .npins = ARRAY_SIZE(x ## _pins) }
0648     NPCM7XX_GRPS
0649 #undef NPCM7XX_GRP
0650 };
0651
0652 #define NPCM7XX_SFUNC(a) NPCM7XX_FUNC(a, #a)
0653 #define NPCM7XX_FUNC(a, b...) static const char *a ## _grp[] = { b }
0654 #define NPCM7XX_MKFUNC(nm) { .name = #nm, .ngroups = ARRAY_SIZE(nm ## _grp), \
0655             .groups = nm ## _grp }
0656 struct npcm7xx_func {
0657     const char *name;
0658     const unsigned int ngroups;
0659     const char *const *groups;
0660 };
0661
0662 NPCM7XX_SFUNC(smb0);
0663 NPCM7XX_SFUNC(smb0b);
0664 NPCM7XX_SFUNC(smb0c);
0665 NPCM7XX_SFUNC(smb0d);
0666 NPCM7XX_SFUNC(smb0den);
0667 NPCM7XX_SFUNC(smb1);
0668 NPCM7XX_SFUNC(smb1b);
0669 NPCM7XX_SFUNC(smb1c);
0670 NPCM7XX_SFUNC(smb1d);
0671 NPCM7XX_SFUNC(smb2);
0672 NPCM7XX_SFUNC(smb2b);
0673 NPCM7XX_SFUNC(smb2c);
0674 NPCM7XX_SFUNC(smb2d);
0675 NPCM7XX_SFUNC(smb3);
0676 NPCM7XX_SFUNC(smb3b);
0677 NPCM7XX_SFUNC(smb3c);
0678 NPCM7XX_SFUNC(smb3d);
0679 NPCM7XX_SFUNC(smb4);
0680 NPCM7XX_SFUNC(smb4b);
0681 NPCM7XX_SFUNC(smb4c);
0682 NPCM7XX_SFUNC(smb4d);
0683 NPCM7XX_SFUNC(smb4den);
0684 NPCM7XX_SFUNC(smb5);
0685 NPCM7XX_SFUNC(smb5b);
0686 NPCM7XX_SFUNC(smb5c);
0687 NPCM7XX_SFUNC(smb5d);
0688 NPCM7XX_SFUNC(ga20kbc);
0689 NPCM7XX_SFUNC(smb6);
0690 NPCM7XX_SFUNC(smb7);
0691 NPCM7XX_SFUNC(smb8);
0692 NPCM7XX_SFUNC(smb9);
0693 NPCM7XX_SFUNC(smb10);
0694 NPCM7XX_SFUNC(smb11);
0695 NPCM7XX_SFUNC(smb12);
0696 NPCM7XX_SFUNC(smb13);
0697 NPCM7XX_SFUNC(smb14);
0698 NPCM7XX_SFUNC(smb15);
0699 NPCM7XX_SFUNC(fanin0);
0700 NPCM7XX_SFUNC(fanin1);
0701 NPCM7XX_SFUNC(fanin2);
0702 NPCM7XX_SFUNC(fanin3);
0703 NPCM7XX_SFUNC(fanin4);
0704 NPCM7XX_SFUNC(fanin5);
0705 NPCM7XX_SFUNC(fanin6);
0706 NPCM7XX_SFUNC(fanin7);
0707 NPCM7XX_SFUNC(fanin8);
0708 NPCM7XX_SFUNC(fanin9);
0709 NPCM7XX_SFUNC(fanin10);
0710 NPCM7XX_SFUNC(fanin11);
0711 NPCM7XX_SFUNC(fanin12);
0712 NPCM7XX_SFUNC(fanin13);
0713 NPCM7XX_SFUNC(fanin14);
0714 NPCM7XX_SFUNC(fanin15);
0715 NPCM7XX_SFUNC(faninx);
0716 NPCM7XX_SFUNC(pwm0);
0717 NPCM7XX_SFUNC(pwm1);
0718 NPCM7XX_SFUNC(pwm2);
0719 NPCM7XX_SFUNC(pwm3);
0720 NPCM7XX_SFUNC(pwm4);
0721 NPCM7XX_SFUNC(pwm5);
0722 NPCM7XX_SFUNC(pwm6);
0723 NPCM7XX_SFUNC(pwm7);
0724 NPCM7XX_SFUNC(rg1);
0725 NPCM7XX_SFUNC(rg1mdio);
0726 NPCM7XX_SFUNC(rg2);
0727 NPCM7XX_SFUNC(rg2mdio);
0728 NPCM7XX_SFUNC(ddr);
0729 NPCM7XX_SFUNC(uart1);
0730 NPCM7XX_SFUNC(uart2);
0731 NPCM7XX_SFUNC(bmcuart0a);
0732 NPCM7XX_SFUNC(bmcuart0b);
0733 NPCM7XX_SFUNC(bmcuart1);
0734 NPCM7XX_SFUNC(iox1);
0735 NPCM7XX_SFUNC(iox2);
0736 NPCM7XX_SFUNC(ioxh);
0737 NPCM7XX_SFUNC(gspi);
0738 NPCM7XX_SFUNC(mmc);
0739 NPCM7XX_SFUNC(mmcwp);
0740 NPCM7XX_SFUNC(mmccd);
0741 NPCM7XX_SFUNC(mmcrst);
0742 NPCM7XX_SFUNC(mmc8);
0743 NPCM7XX_SFUNC(r1);
0744 NPCM7XX_SFUNC(r1err);
0745 NPCM7XX_SFUNC(r1md);
0746 NPCM7XX_SFUNC(r2);
0747 NPCM7XX_SFUNC(r2err);
0748 NPCM7XX_SFUNC(r2md);
0749 NPCM7XX_SFUNC(sd1);
0750 NPCM7XX_SFUNC(sd1pwr);
0751 NPCM7XX_SFUNC(wdog1);
0752 NPCM7XX_SFUNC(wdog2);
0753 NPCM7XX_SFUNC(scipme);
0754 NPCM7XX_SFUNC(sci);
0755 NPCM7XX_SFUNC(serirq);
0756 NPCM7XX_SFUNC(jtag2);
0757 NPCM7XX_SFUNC(spix);
0758 NPCM7XX_SFUNC(spixcs1);
0759 NPCM7XX_SFUNC(pspi1);
0760 NPCM7XX_SFUNC(pspi2);
0761 NPCM7XX_SFUNC(ddc);
0762 NPCM7XX_SFUNC(clkreq);
0763 NPCM7XX_SFUNC(clkout);
0764 NPCM7XX_SFUNC(spi3);
0765 NPCM7XX_SFUNC(spi3cs1);
0766 NPCM7XX_SFUNC(spi3quad);
0767 NPCM7XX_SFUNC(spi3cs2);
0768 NPCM7XX_SFUNC(spi3cs3);
0769 NPCM7XX_SFUNC(spi0cs1);
0770 NPCM7XX_SFUNC(lpc);
0771 NPCM7XX_SFUNC(lpcclk);
0772 NPCM7XX_SFUNC(espi);
0773 NPCM7XX_SFUNC(lkgpo0);
0774 NPCM7XX_SFUNC(lkgpo1);
0775 NPCM7XX_SFUNC(lkgpo2);
0776 NPCM7XX_SFUNC(nprd_smi);
0777
0778 /* Function names */
0779 static struct npcm7xx_func npcm7xx_funcs[] = {
0780     NPCM7XX_MKFUNC(smb0),
0781     NPCM7XX_MKFUNC(smb0b),
0782     NPCM7XX_MKFUNC(smb0c),
0783     NPCM7XX_MKFUNC(smb0d),
0784     NPCM7XX_MKFUNC(smb0den),
0785     NPCM7XX_MKFUNC(smb1),
0786     NPCM7XX_MKFUNC(smb1b),
0787     NPCM7XX_MKFUNC(smb1c),
0788     NPCM7XX_MKFUNC(smb1d),
0789     NPCM7XX_MKFUNC(smb2),
0790     NPCM7XX_MKFUNC(smb2b),
0791     NPCM7XX_MKFUNC(smb2c),
0792     NPCM7XX_MKFUNC(smb2d),
0793     NPCM7XX_MKFUNC(smb3),
0794     NPCM7XX_MKFUNC(smb3b),
0795     NPCM7XX_MKFUNC(smb3c),
0796     NPCM7XX_MKFUNC(smb3d),
0797     NPCM7XX_MKFUNC(smb4),
0798     NPCM7XX_MKFUNC(smb4b),
0799     NPCM7XX_MKFUNC(smb4c),
0800     NPCM7XX_MKFUNC(smb4d),
0801     NPCM7XX_MKFUNC(smb4den),
0802     NPCM7XX_MKFUNC(smb5),
0803     NPCM7XX_MKFUNC(smb5b),
0804     NPCM7XX_MKFUNC(smb5c),
0805     NPCM7XX_MKFUNC(smb5d),
0806     NPCM7XX_MKFUNC(ga20kbc),
0807     NPCM7XX_MKFUNC(smb6),
0808     NPCM7XX_MKFUNC(smb7),
0809     NPCM7XX_MKFUNC(smb8),
0810     NPCM7XX_MKFUNC(smb9),
0811     NPCM7XX_MKFUNC(smb10),
0812     NPCM7XX_MKFUNC(smb11),
0813     NPCM7XX_MKFUNC(smb12),
0814     NPCM7XX_MKFUNC(smb13),
0815     NPCM7XX_MKFUNC(smb14),
0816     NPCM7XX_MKFUNC(smb15),
0817     NPCM7XX_MKFUNC(fanin0),
0818     NPCM7XX_MKFUNC(fanin1),
0819     NPCM7XX_MKFUNC(fanin2),
0820     NPCM7XX_MKFUNC(fanin3),
0821     NPCM7XX_MKFUNC(fanin4),
0822     NPCM7XX_MKFUNC(fanin5),
0823     NPCM7XX_MKFUNC(fanin6),
0824     NPCM7XX_MKFUNC(fanin7),
0825     NPCM7XX_MKFUNC(fanin8),
0826     NPCM7XX_MKFUNC(fanin9),
0827     NPCM7XX_MKFUNC(fanin10),
0828     NPCM7XX_MKFUNC(fanin11),
0829     NPCM7XX_MKFUNC(fanin12),
0830     NPCM7XX_MKFUNC(fanin13),
0831     NPCM7XX_MKFUNC(fanin14),
0832     NPCM7XX_MKFUNC(fanin15),
0833     NPCM7XX_MKFUNC(faninx),
0834     NPCM7XX_MKFUNC(pwm0),
0835     NPCM7XX_MKFUNC(pwm1),
0836     NPCM7XX_MKFUNC(pwm2),
0837     NPCM7XX_MKFUNC(pwm3),
0838     NPCM7XX_MKFUNC(pwm4),
0839     NPCM7XX_MKFUNC(pwm5),
0840     NPCM7XX_MKFUNC(pwm6),
0841     NPCM7XX_MKFUNC(pwm7),
0842     NPCM7XX_MKFUNC(rg1),
0843     NPCM7XX_MKFUNC(rg1mdio),
0844     NPCM7XX_MKFUNC(rg2),
0845     NPCM7XX_MKFUNC(rg2mdio),
0846     NPCM7XX_MKFUNC(ddr),
0847     NPCM7XX_MKFUNC(uart1),
0848     NPCM7XX_MKFUNC(uart2),
0849     NPCM7XX_MKFUNC(bmcuart0a),
0850     NPCM7XX_MKFUNC(bmcuart0b),
0851     NPCM7XX_MKFUNC(bmcuart1),
0852     NPCM7XX_MKFUNC(iox1),
0853     NPCM7XX_MKFUNC(iox2),
0854     NPCM7XX_MKFUNC(ioxh),
0855     NPCM7XX_MKFUNC(gspi),
0856     NPCM7XX_MKFUNC(mmc),
0857     NPCM7XX_MKFUNC(mmcwp),
0858     NPCM7XX_MKFUNC(mmccd),
0859     NPCM7XX_MKFUNC(mmcrst),
0860     NPCM7XX_MKFUNC(mmc8),
0861     NPCM7XX_MKFUNC(r1),
0862     NPCM7XX_MKFUNC(r1err),
0863     NPCM7XX_MKFUNC(r1md),
0864     NPCM7XX_MKFUNC(r2),
0865     NPCM7XX_MKFUNC(r2err),
0866     NPCM7XX_MKFUNC(r2md),
0867     NPCM7XX_MKFUNC(sd1),
0868     NPCM7XX_MKFUNC(sd1pwr),
0869     NPCM7XX_MKFUNC(wdog1),
0870     NPCM7XX_MKFUNC(wdog2),
0871     NPCM7XX_MKFUNC(scipme),
0872     NPCM7XX_MKFUNC(sci),
0873     NPCM7XX_MKFUNC(serirq),
0874     NPCM7XX_MKFUNC(jtag2),
0875     NPCM7XX_MKFUNC(spix),
0876     NPCM7XX_MKFUNC(spixcs1),
0877     NPCM7XX_MKFUNC(pspi1),
0878     NPCM7XX_MKFUNC(pspi2),
0879     NPCM7XX_MKFUNC(ddc),
0880     NPCM7XX_MKFUNC(clkreq),
0881     NPCM7XX_MKFUNC(clkout),
0882     NPCM7XX_MKFUNC(spi3),
0883     NPCM7XX_MKFUNC(spi3cs1),
0884     NPCM7XX_MKFUNC(spi3quad),
0885     NPCM7XX_MKFUNC(spi3cs2),
0886     NPCM7XX_MKFUNC(spi3cs3),
0887     NPCM7XX_MKFUNC(spi0cs1),
0888     NPCM7XX_MKFUNC(lpc),
0889     NPCM7XX_MKFUNC(lpcclk),
0890     NPCM7XX_MKFUNC(espi),
0891     NPCM7XX_MKFUNC(lkgpo0),
0892     NPCM7XX_MKFUNC(lkgpo1),
0893     NPCM7XX_MKFUNC(lkgpo2),
0894     NPCM7XX_MKFUNC(nprd_smi),
0895 };
0896
0897 #define NPCM7XX_PINCFG(a, b, c, d, e, f, g, h, i, j, k) \
0898     [a] = { .fn0 = fn_ ## b, .reg0 = NPCM7XX_GCR_ ## c, .bit0 = d, \
0899             .fn1 = fn_ ## e, .reg1 = NPCM7XX_GCR_ ## f, .bit1 = g, \
0900             .fn2 = fn_ ## h, .reg2 = NPCM7XX_GCR_ ## i, .bit2 = j, \
0901             .flag = k }
0902
0903 /* Drive strength controlled by NPCM7XX_GP_N_ODSC */
0904 #define DRIVE_STRENGTH_LO_SHIFT     8
0905 #define DRIVE_STRENGTH_HI_SHIFT     12
0906 #define DRIVE_STRENGTH_MASK     0x0000FF00
0907
0908 #define DSTR(lo, hi)    (((lo) << DRIVE_STRENGTH_LO_SHIFT) | \
0909              ((hi) << DRIVE_STRENGTH_HI_SHIFT))
0910 #define DSLO(x)     (((x) >> DRIVE_STRENGTH_LO_SHIFT) & 0xF)
0911 #define DSHI(x)     (((x) >> DRIVE_STRENGTH_HI_SHIFT) & 0xF)
0912
0913 #define GPI     0x1 /* Not GPO */
0914 #define GPO     0x2 /* Not GPI */
0915 #define SLEW        0x4 /* Has Slew Control, NPCM7XX_GP_N_OSRC */
0916 #define SLEWLPC     0x8 /* Has Slew Control, SRCNT.3 */
0917
0918 struct npcm7xx_pincfg {
0919     int flag;
0920     int fn0, reg0, bit0;
0921     int fn1, reg1, bit1;
0922     int fn2, reg2, bit2;
0923 };
0924
0925 static const struct npcm7xx_pincfg pincfg[] = {
0926     /*      PIN   FUNCTION 1           FUNCTION 2         FUNCTION 3        FLAGS */
0927     NPCM7XX_PINCFG(0,    iox1, MFSEL1, 30,    none, NONE, 0,    none, NONE, 0,       0),
0928     NPCM7XX_PINCFG(1,    iox1, MFSEL1, 30,    none, NONE, 0,    none, NONE, 0,       DSTR(8, 12)),
0929     NPCM7XX_PINCFG(2,    iox1, MFSEL1, 30,    none, NONE, 0,    none, NONE, 0,       DSTR(8, 12)),
0930     NPCM7XX_PINCFG(3,    iox1, MFSEL1, 30,    none, NONE, 0,    none, NONE, 0,       0),
0931     NPCM7XX_PINCFG(4,    iox2, MFSEL3, 14,   smb1d, I2CSEGSEL, 7,   none, NONE, 0,       SLEW),
0932     NPCM7XX_PINCFG(5,    iox2, MFSEL3, 14,   smb1d, I2CSEGSEL, 7,   none, NONE, 0,       SLEW),
0933     NPCM7XX_PINCFG(6,    iox2, MFSEL3, 14,   smb2d, I2CSEGSEL, 10,  none, NONE, 0,       SLEW),
0934     NPCM7XX_PINCFG(7,    iox2, MFSEL3, 14,   smb2d, I2CSEGSEL, 10,  none, NONE, 0,       SLEW),
0935     NPCM7XX_PINCFG(8,      lkgpo1, FLOCKR1, 4,        none, NONE, 0,    none, NONE, 0,       DSTR(8, 12)),
0936     NPCM7XX_PINCFG(9,      lkgpo2, FLOCKR1, 8,        none, NONE, 0,    none, NONE, 0,       DSTR(8, 12)),
0937     NPCM7XX_PINCFG(10,   ioxh, MFSEL3, 18,    none, NONE, 0,    none, NONE, 0,       DSTR(8, 12)),
0938     NPCM7XX_PINCFG(11,   ioxh, MFSEL3, 18,    none, NONE, 0,    none, NONE, 0,       DSTR(8, 12)),
0939     NPCM7XX_PINCFG(12,   gspi, MFSEL1, 24,   smb5b, I2CSEGSEL, 19,  none, NONE, 0,       SLEW),
0940     NPCM7XX_PINCFG(13,   gspi, MFSEL1, 24,   smb5b, I2CSEGSEL, 19,  none, NONE, 0,       SLEW),
0941     NPCM7XX_PINCFG(14,   gspi, MFSEL1, 24,   smb5c, I2CSEGSEL, 20,  none, NONE, 0,       SLEW),
0942     NPCM7XX_PINCFG(15,   gspi, MFSEL1, 24,   smb5c, I2CSEGSEL, 20,  none, NONE, 0,       SLEW),
0943     NPCM7XX_PINCFG(16,     lkgpo0, FLOCKR1, 0,        none, NONE, 0,    none, NONE, 0,       DSTR(8, 12)),
0944     NPCM7XX_PINCFG(17,      pspi2, MFSEL3, 13,     smb4den, I2CSEGSEL, 23,  none, NONE, 0,       DSTR(8, 12)),
0945     NPCM7XX_PINCFG(18,      pspi2, MFSEL3, 13,   smb4b, I2CSEGSEL, 14,  none, NONE, 0,       DSTR(8, 12)),
0946     NPCM7XX_PINCFG(19,      pspi2, MFSEL3, 13,   smb4b, I2CSEGSEL, 14,  none, NONE, 0,       DSTR(8, 12)),
0947     NPCM7XX_PINCFG(20,  smb4c, I2CSEGSEL, 15,    smb15, MFSEL3, 8,      none, NONE, 0,       0),
0948     NPCM7XX_PINCFG(21,  smb4c, I2CSEGSEL, 15,    smb15, MFSEL3, 8,      none, NONE, 0,       0),
0949     NPCM7XX_PINCFG(22,      smb4d, I2CSEGSEL, 16,    smb14, MFSEL3, 7,      none, NONE, 0,       0),
0950     NPCM7XX_PINCFG(23,      smb4d, I2CSEGSEL, 16,    smb14, MFSEL3, 7,      none, NONE, 0,       0),
0951     NPCM7XX_PINCFG(24,   ioxh, MFSEL3, 18,    none, NONE, 0,    none, NONE, 0,       DSTR(8, 12)),
0952     NPCM7XX_PINCFG(25,   ioxh, MFSEL3, 18,    none, NONE, 0,    none, NONE, 0,       DSTR(8, 12)),
0953     NPCM7XX_PINCFG(26,   smb5, MFSEL1, 2,     none, NONE, 0,    none, NONE, 0,       0),
0954     NPCM7XX_PINCFG(27,   smb5, MFSEL1, 2,     none, NONE, 0,    none, NONE, 0,       0),
0955     NPCM7XX_PINCFG(28,   smb4, MFSEL1, 1,     none, NONE, 0,    none, NONE, 0,       0),
0956     NPCM7XX_PINCFG(29,   smb4, MFSEL1, 1,     none, NONE, 0,    none, NONE, 0,       0),
0957     NPCM7XX_PINCFG(30,   smb3, MFSEL1, 0,     none, NONE, 0,    none, NONE, 0,       0),
0958     NPCM7XX_PINCFG(31,   smb3, MFSEL1, 0,     none, NONE, 0,    none, NONE, 0,       0),
0959
0960     NPCM7XX_PINCFG(32,    spi0cs1, MFSEL1, 3,     none, NONE, 0,    none, NONE, 0,       0),
0961     NPCM7XX_PINCFG(33,   none, NONE, 0,           none, NONE, 0,    none, NONE, 0,       SLEW),
0962     NPCM7XX_PINCFG(34,   none, NONE, 0,           none, NONE, 0,    none, NONE, 0,       SLEW),
0963     NPCM7XX_PINCFG(37,  smb3c, I2CSEGSEL, 12,     none, NONE, 0,    none, NONE, 0,       SLEW),
0964     NPCM7XX_PINCFG(38,  smb3c, I2CSEGSEL, 12,     none, NONE, 0,    none, NONE, 0,       SLEW),
0965     NPCM7XX_PINCFG(39,  smb3b, I2CSEGSEL, 11,     none, NONE, 0,    none, NONE, 0,       SLEW),
0966     NPCM7XX_PINCFG(40,  smb3b, I2CSEGSEL, 11,     none, NONE, 0,    none, NONE, 0,       SLEW),
0967     NPCM7XX_PINCFG(41,  bmcuart0a, MFSEL1, 9,         none, NONE, 0,    none, NONE, 0,       0),
0968     NPCM7XX_PINCFG(42,  bmcuart0a, MFSEL1, 9,         none, NONE, 0,    none, NONE, 0,       DSTR(2, 4) | GPO),
0969     NPCM7XX_PINCFG(43,      uart1, MFSEL1, 10,   jtag2, MFSEL4, 0,  bmcuart1, MFSEL3, 24,    0),
0970     NPCM7XX_PINCFG(44,      uart1, MFSEL1, 10,   jtag2, MFSEL4, 0,  bmcuart1, MFSEL3, 24,    0),
0971     NPCM7XX_PINCFG(45,      uart1, MFSEL1, 10,   jtag2, MFSEL4, 0,  none, NONE, 0,       0),
0972     NPCM7XX_PINCFG(46,      uart1, MFSEL1, 10,   jtag2, MFSEL4, 0,  none, NONE, 0,       DSTR(2, 8)),
0973     NPCM7XX_PINCFG(47,      uart1, MFSEL1, 10,   jtag2, MFSEL4, 0,  none, NONE, 0,       DSTR(2, 8)),
0974     NPCM7XX_PINCFG(48,  uart2, MFSEL1, 11,   bmcuart0b, MFSEL4, 1,      none, NONE, 0,       GPO),
0975     NPCM7XX_PINCFG(49,  uart2, MFSEL1, 11,   bmcuart0b, MFSEL4, 1,      none, NONE, 0,       0),
0976     NPCM7XX_PINCFG(50,  uart2, MFSEL1, 11,    none, NONE, 0,        none, NONE, 0,       0),
0977     NPCM7XX_PINCFG(51,  uart2, MFSEL1, 11,    none, NONE, 0,        none, NONE, 0,       GPO),
0978     NPCM7XX_PINCFG(52,  uart2, MFSEL1, 11,    none, NONE, 0,        none, NONE, 0,       0),
0979     NPCM7XX_PINCFG(53,  uart2, MFSEL1, 11,    none, NONE, 0,        none, NONE, 0,       GPO),
0980     NPCM7XX_PINCFG(54,  uart2, MFSEL1, 11,    none, NONE, 0,        none, NONE, 0,       0),
0981     NPCM7XX_PINCFG(55,  uart2, MFSEL1, 11,    none, NONE, 0,        none, NONE, 0,       0),
0982     NPCM7XX_PINCFG(56,  r1err, MFSEL1, 12,    none, NONE, 0,    none, NONE, 0,       0),
0983     NPCM7XX_PINCFG(57,       r1md, MFSEL1, 13,        none, NONE, 0,        none, NONE, 0,       DSTR(2, 4)),
0984     NPCM7XX_PINCFG(58,       r1md, MFSEL1, 13,        none, NONE, 0,    none, NONE, 0,       DSTR(2, 4)),
0985     NPCM7XX_PINCFG(59,  smb3d, I2CSEGSEL, 13,     none, NONE, 0,    none, NONE, 0,       0),
0986     NPCM7XX_PINCFG(60,  smb3d, I2CSEGSEL, 13,     none, NONE, 0,    none, NONE, 0,       0),
0987     NPCM7XX_PINCFG(61,      uart1, MFSEL1, 10,    none, NONE, 0,    none, NONE, 0,     GPO),
0988     NPCM7XX_PINCFG(62,      uart1, MFSEL1, 10,    bmcuart1, MFSEL3, 24, none, NONE, 0,     GPO),
0989     NPCM7XX_PINCFG(63,      uart1, MFSEL1, 10,    bmcuart1, MFSEL3, 24, none, NONE, 0,     GPO),
0990
0991     NPCM7XX_PINCFG(64,    fanin0, MFSEL2, 0,          none, NONE, 0,    none, NONE, 0,       0),
0992     NPCM7XX_PINCFG(65,    fanin1, MFSEL2, 1,          none, NONE, 0,    none, NONE, 0,       0),
0993     NPCM7XX_PINCFG(66,    fanin2, MFSEL2, 2,          none, NONE, 0,    none, NONE, 0,       0),
0994     NPCM7XX_PINCFG(67,    fanin3, MFSEL2, 3,          none, NONE, 0,    none, NONE, 0,       0),
0995     NPCM7XX_PINCFG(68,    fanin4, MFSEL2, 4,          none, NONE, 0,    none, NONE, 0,       0),
0996     NPCM7XX_PINCFG(69,    fanin5, MFSEL2, 5,          none, NONE, 0,    none, NONE, 0,       0),
0997     NPCM7XX_PINCFG(70,    fanin6, MFSEL2, 6,          none, NONE, 0,    none, NONE, 0,       0),
0998     NPCM7XX_PINCFG(71,    fanin7, MFSEL2, 7,          none, NONE, 0,    none, NONE, 0,       0),
0999     NPCM7XX_PINCFG(72,    fanin8, MFSEL2, 8,          none, NONE, 0,    none, NONE, 0,       0),
1000     NPCM7XX_PINCFG(73,    fanin9, MFSEL2, 9,          none, NONE, 0,    none, NONE, 0,       0),
1001     NPCM7XX_PINCFG(74,    fanin10, MFSEL2, 10,        none, NONE, 0,    none, NONE, 0,       0),
1002     NPCM7XX_PINCFG(75,    fanin11, MFSEL2, 11,        none, NONE, 0,    none, NONE, 0,       0),
1003     NPCM7XX_PINCFG(76,    fanin12, MFSEL2, 12,        none, NONE, 0,    none, NONE, 0,       0),
1004     NPCM7XX_PINCFG(77,    fanin13, MFSEL2, 13,        none, NONE, 0,    none, NONE, 0,       0),
1005     NPCM7XX_PINCFG(78,    fanin14, MFSEL2, 14,        none, NONE, 0,    none, NONE, 0,       0),
1006     NPCM7XX_PINCFG(79,    fanin15, MFSEL2, 15,        none, NONE, 0,    none, NONE, 0,       0),
1007     NPCM7XX_PINCFG(80,   pwm0, MFSEL2, 16,        none, NONE, 0,    none, NONE, 0,       DSTR(4, 8)),
1008     NPCM7XX_PINCFG(81,   pwm1, MFSEL2, 17,        none, NONE, 0,    none, NONE, 0,       DSTR(4, 8)),
1009     NPCM7XX_PINCFG(82,   pwm2, MFSEL2, 18,        none, NONE, 0,    none, NONE, 0,       DSTR(4, 8)),
1010     NPCM7XX_PINCFG(83,   pwm3, MFSEL2, 19,        none, NONE, 0,    none, NONE, 0,       DSTR(4, 8)),
1011     NPCM7XX_PINCFG(84,         r2, MFSEL1, 14,        none, NONE, 0,        none, NONE, 0,       DSTR(8, 12) | SLEW),
1012     NPCM7XX_PINCFG(85,         r2, MFSEL1, 14,        none, NONE, 0,        none, NONE, 0,       DSTR(8, 12) | SLEW),
1013     NPCM7XX_PINCFG(86,         r2, MFSEL1, 14,        none, NONE, 0,        none, NONE, 0,       DSTR(8, 12) | SLEW),
1014     NPCM7XX_PINCFG(87,         r2, MFSEL1, 14,        none, NONE, 0,        none, NONE, 0,       0),
1015     NPCM7XX_PINCFG(88,         r2, MFSEL1, 14,        none, NONE, 0,        none, NONE, 0,       0),
1016     NPCM7XX_PINCFG(89,         r2, MFSEL1, 14,        none, NONE, 0,        none, NONE, 0,       0),
1017     NPCM7XX_PINCFG(90,      r2err, MFSEL1, 15,        none, NONE, 0,        none, NONE, 0,       0),
1018     NPCM7XX_PINCFG(91,       r2md, MFSEL1, 16,    none, NONE, 0,        none, NONE, 0,       DSTR(2, 4)),
1019     NPCM7XX_PINCFG(92,       r2md, MFSEL1, 16,    none, NONE, 0,        none, NONE, 0,       DSTR(2, 4)),
1020     NPCM7XX_PINCFG(93,    ga20kbc, MFSEL1, 17,   smb5d, I2CSEGSEL, 21,  none, NONE, 0,       0),
1021     NPCM7XX_PINCFG(94,    ga20kbc, MFSEL1, 17,   smb5d, I2CSEGSEL, 21,  none, NONE, 0,       0),
1022     NPCM7XX_PINCFG(95,    lpc, NONE, 0,       espi, MFSEL4, 8,      gpio, MFSEL1, 26,    0),
1023
1024     NPCM7XX_PINCFG(96,    rg1, MFSEL4, 22,    none, NONE, 0,    none, NONE, 0,       0),
1025     NPCM7XX_PINCFG(97,    rg1, MFSEL4, 22,    none, NONE, 0,    none, NONE, 0,       0),
1026     NPCM7XX_PINCFG(98,    rg1, MFSEL4, 22,    none, NONE, 0,    none, NONE, 0,       0),
1027     NPCM7XX_PINCFG(99,    rg1, MFSEL4, 22,    none, NONE, 0,    none, NONE, 0,       0),
1028     NPCM7XX_PINCFG(100,   rg1, MFSEL4, 22,    none, NONE, 0,    none, NONE, 0,       0),
1029     NPCM7XX_PINCFG(101,   rg1, MFSEL4, 22,    none, NONE, 0,    none, NONE, 0,       0),
1030     NPCM7XX_PINCFG(102,   rg1, MFSEL4, 22,    none, NONE, 0,    none, NONE, 0,       0),
1031     NPCM7XX_PINCFG(103,   rg1, MFSEL4, 22,    none, NONE, 0,    none, NONE, 0,       0),
1032     NPCM7XX_PINCFG(104,   rg1, MFSEL4, 22,    none, NONE, 0,    none, NONE, 0,       0),
1033     NPCM7XX_PINCFG(105,   rg1, MFSEL4, 22,    none, NONE, 0,    none, NONE, 0,       0),
1034     NPCM7XX_PINCFG(106,   rg1, MFSEL4, 22,    none, NONE, 0,    none, NONE, 0,       0),
1035     NPCM7XX_PINCFG(107,   rg1, MFSEL4, 22,    none, NONE, 0,    none, NONE, 0,       0),
1036     NPCM7XX_PINCFG(108,   rg1mdio, MFSEL4, 21,        none, NONE, 0,    none, NONE, 0,       0),
1037     NPCM7XX_PINCFG(109,   rg1mdio, MFSEL4, 21,        none, NONE, 0,    none, NONE, 0,       0),
1038     NPCM7XX_PINCFG(110,       rg2, MFSEL4, 24,         ddr, MFSEL3, 26,     none, NONE, 0,       0),
1039     NPCM7XX_PINCFG(111,       rg2, MFSEL4, 24,         ddr, MFSEL3, 26,     none, NONE, 0,       0),
1040     NPCM7XX_PINCFG(112,       rg2, MFSEL4, 24,         ddr, MFSEL3, 26,     none, NONE, 0,       0),
1041     NPCM7XX_PINCFG(113,       rg2, MFSEL4, 24,         ddr, MFSEL3, 26,     none, NONE, 0,       0),
1042     NPCM7XX_PINCFG(114,  smb0, MFSEL1, 6,     none, NONE, 0,    none, NONE, 0,       0),
1043     NPCM7XX_PINCFG(115,  smb0, MFSEL1, 6,     none, NONE, 0,    none, NONE, 0,       0),
1044     NPCM7XX_PINCFG(116,  smb1, MFSEL1, 7,     none, NONE, 0,    none, NONE, 0,       0),
1045     NPCM7XX_PINCFG(117,  smb1, MFSEL1, 7,     none, NONE, 0,    none, NONE, 0,       0),
1046     NPCM7XX_PINCFG(118,  smb2, MFSEL1, 8,     none, NONE, 0,    none, NONE, 0,       0),
1047     NPCM7XX_PINCFG(119,  smb2, MFSEL1, 8,     none, NONE, 0,    none, NONE, 0,       0),
1048     NPCM7XX_PINCFG(120, smb2c, I2CSEGSEL, 9,      none, NONE, 0,    none, NONE, 0,       SLEW),
1049     NPCM7XX_PINCFG(121, smb2c, I2CSEGSEL, 9,      none, NONE, 0,    none, NONE, 0,       SLEW),
1050     NPCM7XX_PINCFG(122, smb2b, I2CSEGSEL, 8,      none, NONE, 0,    none, NONE, 0,       SLEW),
1051     NPCM7XX_PINCFG(123, smb2b, I2CSEGSEL, 8,      none, NONE, 0,    none, NONE, 0,       SLEW),
1052     NPCM7XX_PINCFG(124, smb1c, I2CSEGSEL, 6,      none, NONE, 0,    none, NONE, 0,       SLEW),
1053     NPCM7XX_PINCFG(125, smb1c, I2CSEGSEL, 6,      none, NONE, 0,    none, NONE, 0,       SLEW),
1054     NPCM7XX_PINCFG(126, smb1b, I2CSEGSEL, 5,      none, NONE, 0,    none, NONE, 0,       SLEW),
1055     NPCM7XX_PINCFG(127, smb1b, I2CSEGSEL, 5,      none, NONE, 0,    none, NONE, 0,       SLEW),
1056
1057     NPCM7XX_PINCFG(128,  smb8, MFSEL4, 11,    none, NONE, 0,    none, NONE, 0,       0),
1058     NPCM7XX_PINCFG(129,  smb8, MFSEL4, 11,    none, NONE, 0,    none, NONE, 0,       0),
1059     NPCM7XX_PINCFG(130,  smb9, MFSEL4, 12,        none, NONE, 0,    none, NONE, 0,       0),
1060     NPCM7XX_PINCFG(131,  smb9, MFSEL4, 12,        none, NONE, 0,    none, NONE, 0,       0),
1061     NPCM7XX_PINCFG(132, smb10, MFSEL4, 13,    none, NONE, 0,    none, NONE, 0,       0),
1062     NPCM7XX_PINCFG(133, smb10, MFSEL4, 13,    none, NONE, 0,    none, NONE, 0,       0),
1063     NPCM7XX_PINCFG(134, smb11, MFSEL4, 14,    none, NONE, 0,    none, NONE, 0,       0),
1064     NPCM7XX_PINCFG(135, smb11, MFSEL4, 14,    none, NONE, 0,    none, NONE, 0,       0),
1065     NPCM7XX_PINCFG(136,   sd1, MFSEL3, 12,    none, NONE, 0,    none, NONE, 0,       DSTR(8, 12) | SLEW),
1066     NPCM7XX_PINCFG(137,   sd1, MFSEL3, 12,    none, NONE, 0,    none, NONE, 0,       DSTR(8, 12) | SLEW),
1067     NPCM7XX_PINCFG(138,   sd1, MFSEL3, 12,    none, NONE, 0,    none, NONE, 0,       DSTR(8, 12) | SLEW),
1068     NPCM7XX_PINCFG(139,   sd1, MFSEL3, 12,    none, NONE, 0,    none, NONE, 0,       DSTR(8, 12) | SLEW),
1069     NPCM7XX_PINCFG(140,   sd1, MFSEL3, 12,    none, NONE, 0,    none, NONE, 0,       DSTR(8, 12) | SLEW),
1070     NPCM7XX_PINCFG(141,   sd1, MFSEL3, 12,    none, NONE, 0,    none, NONE, 0,       0),
1071     NPCM7XX_PINCFG(142,   sd1, MFSEL3, 12,    none, NONE, 0,    none, NONE, 0,       DSTR(8, 12) | SLEW),
1072     NPCM7XX_PINCFG(143,       sd1, MFSEL3, 12,      sd1pwr, MFSEL4, 5,      none, NONE, 0,       0),
1073     NPCM7XX_PINCFG(144,  pwm4, MFSEL2, 20,    none, NONE, 0,    none, NONE, 0,       DSTR(4, 8)),
1074     NPCM7XX_PINCFG(145,  pwm5, MFSEL2, 21,    none, NONE, 0,    none, NONE, 0,       DSTR(4, 8)),
1075     NPCM7XX_PINCFG(146,  pwm6, MFSEL2, 22,    none, NONE, 0,    none, NONE, 0,       DSTR(4, 8)),
1076     NPCM7XX_PINCFG(147,  pwm7, MFSEL2, 23,    none, NONE, 0,    none, NONE, 0,       DSTR(4, 8)),
1077     NPCM7XX_PINCFG(148,  mmc8, MFSEL3, 11,    none, NONE, 0,    none, NONE, 0,       DSTR(8, 12) | SLEW),
1078     NPCM7XX_PINCFG(149,  mmc8, MFSEL3, 11,    none, NONE, 0,    none, NONE, 0,       DSTR(8, 12) | SLEW),
1079     NPCM7XX_PINCFG(150,  mmc8, MFSEL3, 11,    none, NONE, 0,    none, NONE, 0,       DSTR(8, 12) | SLEW),
1080     NPCM7XX_PINCFG(151,  mmc8, MFSEL3, 11,    none, NONE, 0,    none, NONE, 0,       DSTR(8, 12) | SLEW),
1081     NPCM7XX_PINCFG(152,   mmc, MFSEL3, 10,    none, NONE, 0,    none, NONE, 0,       DSTR(8, 12) | SLEW),
1082     NPCM7XX_PINCFG(153,     mmcwp, FLOCKR1, 24,       none, NONE, 0,    none, NONE, 0,       0),  /* Z1/A1 */
1083     NPCM7XX_PINCFG(154,   mmc, MFSEL3, 10,    none, NONE, 0,    none, NONE, 0,       DSTR(8, 12) | SLEW),
1084     NPCM7XX_PINCFG(155,     mmccd, MFSEL3, 25,      mmcrst, MFSEL4, 6,      none, NONE, 0,       0),  /* Z1/A1 */
1085     NPCM7XX_PINCFG(156,   mmc, MFSEL3, 10,    none, NONE, 0,    none, NONE, 0,       DSTR(8, 12) | SLEW),
1086     NPCM7XX_PINCFG(157,   mmc, MFSEL3, 10,    none, NONE, 0,    none, NONE, 0,       DSTR(8, 12) | SLEW),
1087     NPCM7XX_PINCFG(158,   mmc, MFSEL3, 10,    none, NONE, 0,    none, NONE, 0,       DSTR(8, 12) | SLEW),
1088     NPCM7XX_PINCFG(159,   mmc, MFSEL3, 10,    none, NONE, 0,    none, NONE, 0,       DSTR(8, 12) | SLEW),
1089
1090     NPCM7XX_PINCFG(160,    clkout, MFSEL1, 21,        none, NONE, 0,        none, NONE, 0,       DSTR(8, 12) | SLEW),
1091     NPCM7XX_PINCFG(161,   lpc, NONE, 0,       espi, MFSEL4, 8,      gpio, MFSEL1, 26,    DSTR(8, 12)),
1092     NPCM7XX_PINCFG(162,    serirq, NONE, 0,           gpio, MFSEL1, 31, none, NONE, 0,       DSTR(8, 12)),
1093     NPCM7XX_PINCFG(163,   lpc, NONE, 0,       espi, MFSEL4, 8,      gpio, MFSEL1, 26,    0),
1094     NPCM7XX_PINCFG(164,   lpc, NONE, 0,       espi, MFSEL4, 8,      gpio, MFSEL1, 26,    SLEWLPC),
1095     NPCM7XX_PINCFG(165,   lpc, NONE, 0,       espi, MFSEL4, 8,      gpio, MFSEL1, 26,    SLEWLPC),
1096     NPCM7XX_PINCFG(166,   lpc, NONE, 0,       espi, MFSEL4, 8,      gpio, MFSEL1, 26,    SLEWLPC),
1097     NPCM7XX_PINCFG(167,   lpc, NONE, 0,       espi, MFSEL4, 8,      gpio, MFSEL1, 26,    SLEWLPC),
1098     NPCM7XX_PINCFG(168,    lpcclk, NONE, 0,           espi, MFSEL4, 8,      gpio, MFSEL3, 16,    0),
1099     NPCM7XX_PINCFG(169,    scipme, MFSEL3, 0,         none, NONE, 0,    none, NONE, 0,       0),
1100     NPCM7XX_PINCFG(170,   sci, MFSEL1, 22,        none, NONE, 0,        none, NONE, 0,       0),
1101     NPCM7XX_PINCFG(171,  smb6, MFSEL3, 1,     none, NONE, 0,    none, NONE, 0,       0),
1102     NPCM7XX_PINCFG(172,  smb6, MFSEL3, 1,     none, NONE, 0,    none, NONE, 0,       0),
1103     NPCM7XX_PINCFG(173,  smb7, MFSEL3, 2,     none, NONE, 0,    none, NONE, 0,       0),
1104     NPCM7XX_PINCFG(174,  smb7, MFSEL3, 2,     none, NONE, 0,    none, NONE, 0,       0),
1105     NPCM7XX_PINCFG(175, pspi1, MFSEL3, 4,       faninx, MFSEL3, 3,      none, NONE, 0,       DSTR(8, 12)),
1106     NPCM7XX_PINCFG(176,     pspi1, MFSEL3, 4,       faninx, MFSEL3, 3,      none, NONE, 0,       DSTR(8, 12)),
1107     NPCM7XX_PINCFG(177,     pspi1, MFSEL3, 4,       faninx, MFSEL3, 3,      none, NONE, 0,       DSTR(8, 12)),
1108     NPCM7XX_PINCFG(178,    r1, MFSEL3, 9,     none, NONE, 0,    none, NONE, 0,       DSTR(8, 12) | SLEW),
1109     NPCM7XX_PINCFG(179,    r1, MFSEL3, 9,     none, NONE, 0,    none, NONE, 0,       DSTR(8, 12) | SLEW),
1110     NPCM7XX_PINCFG(180,    r1, MFSEL3, 9,     none, NONE, 0,    none, NONE, 0,       DSTR(8, 12) | SLEW),
1111     NPCM7XX_PINCFG(181,    r1, MFSEL3, 9,     none, NONE, 0,    none, NONE, 0,       0),
1112     NPCM7XX_PINCFG(182,    r1, MFSEL3, 9,     none, NONE, 0,    none, NONE, 0,       0),
1113     NPCM7XX_PINCFG(183,     spi3, MFSEL4, 16,     none, NONE, 0,    none, NONE, 0,       DSTR(8, 12) | SLEW),
1114     NPCM7XX_PINCFG(184,     spi3, MFSEL4, 16,     none, NONE, 0,    none, NONE, 0,       DSTR(8, 12) | SLEW | GPO),
1115     NPCM7XX_PINCFG(185,     spi3, MFSEL4, 16,     none, NONE, 0,    none, NONE, 0,       DSTR(8, 12) | SLEW | GPO),
1116     NPCM7XX_PINCFG(186,     spi3, MFSEL4, 16,     none, NONE, 0,    none, NONE, 0,       DSTR(8, 12)),
1117     NPCM7XX_PINCFG(187,   spi3cs1, MFSEL4, 17,        none, NONE, 0,    none, NONE, 0,       DSTR(8, 12)),
1118     NPCM7XX_PINCFG(188,  spi3quad, MFSEL4, 20,     spi3cs2, MFSEL4, 18,     none, NONE, 0,    DSTR(8, 12) | SLEW),
1119     NPCM7XX_PINCFG(189,  spi3quad, MFSEL4, 20,     spi3cs3, MFSEL4, 19,     none, NONE, 0,    DSTR(8, 12) | SLEW),
1120     NPCM7XX_PINCFG(190,      gpio, FLOCKR1, 20,   nprd_smi, NONE, 0,    none, NONE, 0,       DSTR(2, 4)),
1121     NPCM7XX_PINCFG(191,  none, NONE, 0,       none, NONE, 0,    none, NONE, 0,       DSTR(8, 12)),  /* XX */
1122
1123     NPCM7XX_PINCFG(192,  none, NONE, 0,       none, NONE, 0,    none, NONE, 0,       DSTR(8, 12)),  /* XX */
1124     NPCM7XX_PINCFG(193,    r1, MFSEL3, 9,     none, NONE, 0,    none, NONE, 0,       0),
1125     NPCM7XX_PINCFG(194, smb0b, I2CSEGSEL, 0,      none, NONE, 0,    none, NONE, 0,       0),
1126     NPCM7XX_PINCFG(195, smb0b, I2CSEGSEL, 0,      none, NONE, 0,    none, NONE, 0,       0),
1127     NPCM7XX_PINCFG(196, smb0c, I2CSEGSEL, 1,      none, NONE, 0,    none, NONE, 0,       0),
1128     NPCM7XX_PINCFG(197,   smb0den, I2CSEGSEL, 22,     none, NONE, 0,    none, NONE, 0,       SLEW),
1129     NPCM7XX_PINCFG(198, smb0d, I2CSEGSEL, 2,      none, NONE, 0,    none, NONE, 0,       0),
1130     NPCM7XX_PINCFG(199, smb0d, I2CSEGSEL, 2,      none, NONE, 0,    none, NONE, 0,       0),
1131     NPCM7XX_PINCFG(200,        r2, MFSEL1, 14,        none, NONE, 0,        none, NONE, 0,       0),
1132     NPCM7XX_PINCFG(201,    r1, MFSEL3, 9,     none, NONE, 0,    none, NONE, 0,       0),
1133     NPCM7XX_PINCFG(202, smb0c, I2CSEGSEL, 1,      none, NONE, 0,    none, NONE, 0,       0),
1134     NPCM7XX_PINCFG(203,    faninx, MFSEL3, 3,         none, NONE, 0,    none, NONE, 0,       DSTR(8, 12)),
1135     NPCM7XX_PINCFG(204,   ddc, NONE, 0,           gpio, MFSEL3, 22, none, NONE, 0,       SLEW),
1136     NPCM7XX_PINCFG(205,   ddc, NONE, 0,           gpio, MFSEL3, 22, none, NONE, 0,       SLEW),
1137     NPCM7XX_PINCFG(206,   ddc, NONE, 0,           gpio, MFSEL3, 22, none, NONE, 0,       DSTR(4, 8)),
1138     NPCM7XX_PINCFG(207,   ddc, NONE, 0,           gpio, MFSEL3, 22, none, NONE, 0,       DSTR(4, 8)),
1139     NPCM7XX_PINCFG(208,       rg2, MFSEL4, 24,         ddr, MFSEL3, 26,     none, NONE, 0,       0),
1140     NPCM7XX_PINCFG(209,       rg2, MFSEL4, 24,         ddr, MFSEL3, 26,     none, NONE, 0,       0),
1141     NPCM7XX_PINCFG(210,       rg2, MFSEL4, 24,         ddr, MFSEL3, 26,     none, NONE, 0,       0),
1142     NPCM7XX_PINCFG(211,       rg2, MFSEL4, 24,         ddr, MFSEL3, 26,     none, NONE, 0,       0),
1143     NPCM7XX_PINCFG(212,       rg2, MFSEL4, 24,         ddr, MFSEL3, 26,     none, NONE, 0,       0),
1144     NPCM7XX_PINCFG(213,       rg2, MFSEL4, 24,         ddr, MFSEL3, 26,     none, NONE, 0,       0),
1145     NPCM7XX_PINCFG(214,       rg2, MFSEL4, 24,         ddr, MFSEL3, 26,     none, NONE, 0,       0),
1146     NPCM7XX_PINCFG(215,       rg2, MFSEL4, 24,         ddr, MFSEL3, 26,     none, NONE, 0,       0),
1147     NPCM7XX_PINCFG(216,   rg2mdio, MFSEL4, 23,         ddr, MFSEL3, 26,     none, NONE, 0,       0),
1148     NPCM7XX_PINCFG(217,   rg2mdio, MFSEL4, 23,         ddr, MFSEL3, 26,     none, NONE, 0,       0),
1149     NPCM7XX_PINCFG(218,     wdog1, MFSEL3, 19,        none, NONE, 0,    none, NONE, 0,       0),
1150     NPCM7XX_PINCFG(219,     wdog2, MFSEL3, 20,        none, NONE, 0,    none, NONE, 0,       DSTR(4, 8)),
1151     NPCM7XX_PINCFG(220, smb12, MFSEL3, 5,     none, NONE, 0,    none, NONE, 0,       0),
1152     NPCM7XX_PINCFG(221, smb12, MFSEL3, 5,     none, NONE, 0,    none, NONE, 0,       0),
1153     NPCM7XX_PINCFG(222,     smb13, MFSEL3, 6,         none, NONE, 0,    none, NONE, 0,       0),
1154     NPCM7XX_PINCFG(223,     smb13, MFSEL3, 6,         none, NONE, 0,    none, NONE, 0,       0),
1155
1156     NPCM7XX_PINCFG(224,  spix, MFSEL4, 27,        none, NONE, 0,    none, NONE, 0,       SLEW),
1157     NPCM7XX_PINCFG(225,  spix, MFSEL4, 27,        none, NONE, 0,    none, NONE, 0,       DSTR(8, 12) | SLEW | GPO),
1158     NPCM7XX_PINCFG(226,  spix, MFSEL4, 27,        none, NONE, 0,    none, NONE, 0,       DSTR(8, 12) | SLEW | GPO),
1159     NPCM7XX_PINCFG(227,  spix, MFSEL4, 27,        none, NONE, 0,    none, NONE, 0,       DSTR(8, 12) | SLEW),
1160     NPCM7XX_PINCFG(228,   spixcs1, MFSEL4, 28,        none, NONE, 0,    none, NONE, 0,       DSTR(8, 12) | SLEW),
1161     NPCM7XX_PINCFG(229,  spix, MFSEL4, 27,        none, NONE, 0,    none, NONE, 0,       DSTR(8, 12) | SLEW),
1162     NPCM7XX_PINCFG(230,  spix, MFSEL4, 27,        none, NONE, 0,    none, NONE, 0,       DSTR(8, 12) | SLEW),
1163     NPCM7XX_PINCFG(231,    clkreq, MFSEL4, 9,         none, NONE, 0,        none, NONE, 0,       DSTR(8, 12)),
1164     NPCM7XX_PINCFG(253,  none, NONE, 0,       none, NONE, 0,    none, NONE, 0,       GPI), /* SDHC1 power */
1165     NPCM7XX_PINCFG(254,  none, NONE, 0,       none, NONE, 0,    none, NONE, 0,       GPI), /* SDHC2 power */
1166     NPCM7XX_PINCFG(255,  none, NONE, 0,       none, NONE, 0,    none, NONE, 0,       GPI), /* DACOSEL */
1167 };
1168
1169 /* number, name, drv_data */
1170 static const struct pinctrl_pin_desc npcm7xx_pins[] = {
1171     PINCTRL_PIN(0,  "GPIO0/IOX1DI"),
1172     PINCTRL_PIN(1,  "GPIO1/IOX1LD"),
1173     PINCTRL_PIN(2,  "GPIO2/IOX1CK"),
1174     PINCTRL_PIN(3,  "GPIO3/IOX1D0"),
1175     PINCTRL_PIN(4,  "GPIO4/IOX2DI/SMB1DSDA"),
1176     PINCTRL_PIN(5,  "GPIO5/IOX2LD/SMB1DSCL"),
1177     PINCTRL_PIN(6,  "GPIO6/IOX2CK/SMB2DSDA"),
1178     PINCTRL_PIN(7,  "GPIO7/IOX2D0/SMB2DSCL"),
1179     PINCTRL_PIN(8,  "GPIO8/LKGPO1"),
1180     PINCTRL_PIN(9,  "GPIO9/LKGPO2"),
1181     PINCTRL_PIN(10, "GPIO10/IOXHLD"),
1182     PINCTRL_PIN(11, "GPIO11/IOXHCK"),
1183     PINCTRL_PIN(12, "GPIO12/GSPICK/SMB5BSCL"),
1184     PINCTRL_PIN(13, "GPIO13/GSPIDO/SMB5BSDA"),
1185     PINCTRL_PIN(14, "GPIO14/GSPIDI/SMB5CSCL"),
1186     PINCTRL_PIN(15, "GPIO15/GSPICS/SMB5CSDA"),
1187     PINCTRL_PIN(16, "GPIO16/LKGPO0"),
1188     PINCTRL_PIN(17, "GPIO17/PSPI2DI/SMB4DEN"),
1189     PINCTRL_PIN(18, "GPIO18/PSPI2D0/SMB4BSDA"),
1190     PINCTRL_PIN(19, "GPIO19/PSPI2CK/SMB4BSCL"),
1191     PINCTRL_PIN(20, "GPIO20/SMB4CSDA/SMB15SDA"),
1192     PINCTRL_PIN(21, "GPIO21/SMB4CSCL/SMB15SCL"),
1193     PINCTRL_PIN(22, "GPIO22/SMB4DSDA/SMB14SDA"),
1194     PINCTRL_PIN(23, "GPIO23/SMB4DSCL/SMB14SCL"),
1195     PINCTRL_PIN(24, "GPIO24/IOXHDO"),
1196     PINCTRL_PIN(25, "GPIO25/IOXHDI"),
1197     PINCTRL_PIN(26, "GPIO26/SMB5SDA"),
1198     PINCTRL_PIN(27, "GPIO27/SMB5SCL"),
1199     PINCTRL_PIN(28, "GPIO28/SMB4SDA"),
1200     PINCTRL_PIN(29, "GPIO29/SMB4SCL"),
1201     PINCTRL_PIN(30, "GPIO30/SMB3SDA"),
1202     PINCTRL_PIN(31, "GPIO31/SMB3SCL"),
1203
1204     PINCTRL_PIN(32, "GPIO32/nSPI0CS1"),
1205     PINCTRL_PIN(33, "SPI0D2"),
1206     PINCTRL_PIN(34, "SPI0D3"),
1207     PINCTRL_PIN(37, "GPIO37/SMB3CSDA"),
1208     PINCTRL_PIN(38, "GPIO38/SMB3CSCL"),
1209     PINCTRL_PIN(39, "GPIO39/SMB3BSDA"),
1210     PINCTRL_PIN(40, "GPIO40/SMB3BSCL"),
1211     PINCTRL_PIN(41, "GPIO41/BSPRXD"),
1212     PINCTRL_PIN(42, "GPO42/BSPTXD/STRAP11"),
1213     PINCTRL_PIN(43, "GPIO43/RXD1/JTMS2/BU1RXD"),
1214     PINCTRL_PIN(44, "GPIO44/nCTS1/JTDI2/BU1CTS"),
1215     PINCTRL_PIN(45, "GPIO45/nDCD1/JTDO2"),
1216     PINCTRL_PIN(46, "GPIO46/nDSR1/JTCK2"),
1217     PINCTRL_PIN(47, "GPIO47/nRI1/JCP_RDY2"),
1218     PINCTRL_PIN(48, "GPIO48/TXD2/BSPTXD"),
1219     PINCTRL_PIN(49, "GPIO49/RXD2/BSPRXD"),
1220     PINCTRL_PIN(50, "GPIO50/nCTS2"),
1221     PINCTRL_PIN(51, "GPO51/nRTS2/STRAP2"),
1222     PINCTRL_PIN(52, "GPIO52/nDCD2"),
1223     PINCTRL_PIN(53, "GPO53/nDTR2_BOUT2/STRAP1"),
1224     PINCTRL_PIN(54, "GPIO54/nDSR2"),
1225     PINCTRL_PIN(55, "GPIO55/nRI2"),
1226     PINCTRL_PIN(56, "GPIO56/R1RXERR"),
1227     PINCTRL_PIN(57, "GPIO57/R1MDC"),
1228     PINCTRL_PIN(58, "GPIO58/R1MDIO"),
1229     PINCTRL_PIN(59, "GPIO59/SMB3DSDA"),
1230     PINCTRL_PIN(60, "GPIO60/SMB3DSCL"),
1231     PINCTRL_PIN(61, "GPO61/nDTR1_BOUT1/STRAP6"),
1232     PINCTRL_PIN(62, "GPO62/nRTST1/STRAP5"),
1233     PINCTRL_PIN(63, "GPO63/TXD1/STRAP4"),
1234
1235     PINCTRL_PIN(64, "GPIO64/FANIN0"),
1236     PINCTRL_PIN(65, "GPIO65/FANIN1"),
1237     PINCTRL_PIN(66, "GPIO66/FANIN2"),
1238     PINCTRL_PIN(67, "GPIO67/FANIN3"),
1239     PINCTRL_PIN(68, "GPIO68/FANIN4"),
1240     PINCTRL_PIN(69, "GPIO69/FANIN5"),
1241     PINCTRL_PIN(70, "GPIO70/FANIN6"),
1242     PINCTRL_PIN(71, "GPIO71/FANIN7"),
1243     PINCTRL_PIN(72, "GPIO72/FANIN8"),
1244     PINCTRL_PIN(73, "GPIO73/FANIN9"),
1245     PINCTRL_PIN(74, "GPIO74/FANIN10"),
1246     PINCTRL_PIN(75, "GPIO75/FANIN11"),
1247     PINCTRL_PIN(76, "GPIO76/FANIN12"),
1248     PINCTRL_PIN(77, "GPIO77/FANIN13"),
1249     PINCTRL_PIN(78, "GPIO78/FANIN14"),
1250     PINCTRL_PIN(79, "GPIO79/FANIN15"),
1251     PINCTRL_PIN(80, "GPIO80/PWM0"),
1252     PINCTRL_PIN(81, "GPIO81/PWM1"),
1253     PINCTRL_PIN(82, "GPIO82/PWM2"),
1254     PINCTRL_PIN(83, "GPIO83/PWM3"),
1255     PINCTRL_PIN(84, "GPIO84/R2TXD0"),
1256     PINCTRL_PIN(85, "GPIO85/R2TXD1"),
1257     PINCTRL_PIN(86, "GPIO86/R2TXEN"),
1258     PINCTRL_PIN(87, "GPIO87/R2RXD0"),
1259     PINCTRL_PIN(88, "GPIO88/R2RXD1"),
1260     PINCTRL_PIN(89, "GPIO89/R2CRSDV"),
1261     PINCTRL_PIN(90, "GPIO90/R2RXERR"),
1262     PINCTRL_PIN(91, "GPIO91/R2MDC"),
1263     PINCTRL_PIN(92, "GPIO92/R2MDIO"),
1264     PINCTRL_PIN(93, "GPIO93/GA20/SMB5DSCL"),
1265     PINCTRL_PIN(94, "GPIO94/nKBRST/SMB5DSDA"),
1266     PINCTRL_PIN(95, "GPIO95/nLRESET/nESPIRST"),
1267
1268     PINCTRL_PIN(96, "GPIO96/RG1TXD0"),
1269     PINCTRL_PIN(97, "GPIO97/RG1TXD1"),
1270     PINCTRL_PIN(98, "GPIO98/RG1TXD2"),
1271     PINCTRL_PIN(99, "GPIO99/RG1TXD3"),
1272     PINCTRL_PIN(100, "GPIO100/RG1TXC"),
1273     PINCTRL_PIN(101, "GPIO101/RG1TXCTL"),
1274     PINCTRL_PIN(102, "GPIO102/RG1RXD0"),
1275     PINCTRL_PIN(103, "GPIO103/RG1RXD1"),
1276     PINCTRL_PIN(104, "GPIO104/RG1RXD2"),
1277     PINCTRL_PIN(105, "GPIO105/RG1RXD3"),
1278     PINCTRL_PIN(106, "GPIO106/RG1RXC"),
1279     PINCTRL_PIN(107, "GPIO107/RG1RXCTL"),
1280     PINCTRL_PIN(108, "GPIO108/RG1MDC"),
1281     PINCTRL_PIN(109, "GPIO109/RG1MDIO"),
1282     PINCTRL_PIN(110, "GPIO110/RG2TXD0/DDRV0"),
1283     PINCTRL_PIN(111, "GPIO111/RG2TXD1/DDRV1"),
1284     PINCTRL_PIN(112, "GPIO112/RG2TXD2/DDRV2"),
1285     PINCTRL_PIN(113, "GPIO113/RG2TXD3/DDRV3"),
1286     PINCTRL_PIN(114, "GPIO114/SMB0SCL"),
1287     PINCTRL_PIN(115, "GPIO115/SMB0SDA"),
1288     PINCTRL_PIN(116, "GPIO116/SMB1SCL"),
1289     PINCTRL_PIN(117, "GPIO117/SMB1SDA"),
1290     PINCTRL_PIN(118, "GPIO118/SMB2SCL"),
1291     PINCTRL_PIN(119, "GPIO119/SMB2SDA"),
1292     PINCTRL_PIN(120, "GPIO120/SMB2CSDA"),
1293     PINCTRL_PIN(121, "GPIO121/SMB2CSCL"),
1294     PINCTRL_PIN(122, "GPIO122/SMB2BSDA"),
1295     PINCTRL_PIN(123, "GPIO123/SMB2BSCL"),
1296     PINCTRL_PIN(124, "GPIO124/SMB1CSDA"),
1297     PINCTRL_PIN(125, "GPIO125/SMB1CSCL"),
1298     PINCTRL_PIN(126, "GPIO126/SMB1BSDA"),
1299     PINCTRL_PIN(127, "GPIO127/SMB1BSCL"),
1300
1301     PINCTRL_PIN(128, "GPIO128/SMB8SCL"),
1302     PINCTRL_PIN(129, "GPIO129/SMB8SDA"),
1303     PINCTRL_PIN(130, "GPIO130/SMB9SCL"),
1304     PINCTRL_PIN(131, "GPIO131/SMB9SDA"),
1305     PINCTRL_PIN(132, "GPIO132/SMB10SCL"),
1306     PINCTRL_PIN(133, "GPIO133/SMB10SDA"),
1307     PINCTRL_PIN(134, "GPIO134/SMB11SCL"),
1308     PINCTRL_PIN(135, "GPIO135/SMB11SDA"),
1309     PINCTRL_PIN(136, "GPIO136/SD1DT0"),
1310     PINCTRL_PIN(137, "GPIO137/SD1DT1"),
1311     PINCTRL_PIN(138, "GPIO138/SD1DT2"),
1312     PINCTRL_PIN(139, "GPIO139/SD1DT3"),
1313     PINCTRL_PIN(140, "GPIO140/SD1CLK"),
1314     PINCTRL_PIN(141, "GPIO141/SD1WP"),
1315     PINCTRL_PIN(142, "GPIO142/SD1CMD"),
1316     PINCTRL_PIN(143, "GPIO143/SD1CD/SD1PWR"),
1317     PINCTRL_PIN(144, "GPIO144/PWM4"),
1318     PINCTRL_PIN(145, "GPIO145/PWM5"),
1319     PINCTRL_PIN(146, "GPIO146/PWM6"),
1320     PINCTRL_PIN(147, "GPIO147/PWM7"),
1321     PINCTRL_PIN(148, "GPIO148/MMCDT4"),
1322     PINCTRL_PIN(149, "GPIO149/MMCDT5"),
1323     PINCTRL_PIN(150, "GPIO150/MMCDT6"),
1324     PINCTRL_PIN(151, "GPIO151/MMCDT7"),
1325     PINCTRL_PIN(152, "GPIO152/MMCCLK"),
1326     PINCTRL_PIN(153, "GPIO153/MMCWP"),
1327     PINCTRL_PIN(154, "GPIO154/MMCCMD"),
1328     PINCTRL_PIN(155, "GPIO155/nMMCCD/nMMCRST"),
1329     PINCTRL_PIN(156, "GPIO156/MMCDT0"),
1330     PINCTRL_PIN(157, "GPIO157/MMCDT1"),
1331     PINCTRL_PIN(158, "GPIO158/MMCDT2"),
1332     PINCTRL_PIN(159, "GPIO159/MMCDT3"),
1333
1334     PINCTRL_PIN(160, "GPIO160/CLKOUT/RNGOSCOUT"),
1335     PINCTRL_PIN(161, "GPIO161/nLFRAME/nESPICS"),
1336     PINCTRL_PIN(162, "GPIO162/SERIRQ"),
1337     PINCTRL_PIN(163, "GPIO163/LCLK/ESPICLK"),
1338     PINCTRL_PIN(164, "GPIO164/LAD0/ESPI_IO0"/*dscnt6*/),
1339     PINCTRL_PIN(165, "GPIO165/LAD1/ESPI_IO1"/*dscnt6*/),
1340     PINCTRL_PIN(166, "GPIO166/LAD2/ESPI_IO2"/*dscnt6*/),
1341     PINCTRL_PIN(167, "GPIO167/LAD3/ESPI_IO3"/*dscnt6*/),
1342     PINCTRL_PIN(168, "GPIO168/nCLKRUN/nESPIALERT"),
1343     PINCTRL_PIN(169, "GPIO169/nSCIPME"),
1344     PINCTRL_PIN(170, "GPIO170/nSMI"),
1345     PINCTRL_PIN(171, "GPIO171/SMB6SCL"),
1346     PINCTRL_PIN(172, "GPIO172/SMB6SDA"),
1347     PINCTRL_PIN(173, "GPIO173/SMB7SCL"),
1348     PINCTRL_PIN(174, "GPIO174/SMB7SDA"),
1349     PINCTRL_PIN(175, "GPIO175/PSPI1CK/FANIN19"),
1350     PINCTRL_PIN(176, "GPIO176/PSPI1DO/FANIN18"),
1351     PINCTRL_PIN(177, "GPIO177/PSPI1DI/FANIN17"),
1352     PINCTRL_PIN(178, "GPIO178/R1TXD0"),
1353     PINCTRL_PIN(179, "GPIO179/R1TXD1"),
1354     PINCTRL_PIN(180, "GPIO180/R1TXEN"),
1355     PINCTRL_PIN(181, "GPIO181/R1RXD0"),
1356     PINCTRL_PIN(182, "GPIO182/R1RXD1"),
1357     PINCTRL_PIN(183, "GPIO183/SPI3CK"),
1358     PINCTRL_PIN(184, "GPO184/SPI3D0/STRAP9"),
1359     PINCTRL_PIN(185, "GPO185/SPI3D1/STRAP10"),
1360     PINCTRL_PIN(186, "GPIO186/nSPI3CS0"),
1361     PINCTRL_PIN(187, "GPIO187/nSPI3CS1"),
1362     PINCTRL_PIN(188, "GPIO188/SPI3D2/nSPI3CS2"),
1363     PINCTRL_PIN(189, "GPIO189/SPI3D3/nSPI3CS3"),
1364     PINCTRL_PIN(190, "GPIO190/nPRD_SMI"),
1365     PINCTRL_PIN(191, "GPIO191"),
1366
1367     PINCTRL_PIN(192, "GPIO192"),
1368     PINCTRL_PIN(193, "GPIO193/R1CRSDV"),
1369     PINCTRL_PIN(194, "GPIO194/SMB0BSCL"),
1370     PINCTRL_PIN(195, "GPIO195/SMB0BSDA"),
1371     PINCTRL_PIN(196, "GPIO196/SMB0CSCL"),
1372     PINCTRL_PIN(197, "GPIO197/SMB0DEN"),
1373     PINCTRL_PIN(198, "GPIO198/SMB0DSDA"),
1374     PINCTRL_PIN(199, "GPIO199/SMB0DSCL"),
1375     PINCTRL_PIN(200, "GPIO200/R2CK"),
1376     PINCTRL_PIN(201, "GPIO201/R1CK"),
1377     PINCTRL_PIN(202, "GPIO202/SMB0CSDA"),
1378     PINCTRL_PIN(203, "GPIO203/FANIN16"),
1379     PINCTRL_PIN(204, "GPIO204/DDC2SCL"),
1380     PINCTRL_PIN(205, "GPIO205/DDC2SDA"),
1381     PINCTRL_PIN(206, "GPIO206/HSYNC2"),
1382     PINCTRL_PIN(207, "GPIO207/VSYNC2"),
1383     PINCTRL_PIN(208, "GPIO208/RG2TXC/DVCK"),
1384     PINCTRL_PIN(209, "GPIO209/RG2TXCTL/DDRV4"),
1385     PINCTRL_PIN(210, "GPIO210/RG2RXD0/DDRV5"),
1386     PINCTRL_PIN(211, "GPIO211/RG2RXD1/DDRV6"),
1387     PINCTRL_PIN(212, "GPIO212/RG2RXD2/DDRV7"),
1388     PINCTRL_PIN(213, "GPIO213/RG2RXD3/DDRV8"),
1389     PINCTRL_PIN(214, "GPIO214/RG2RXC/DDRV9"),
1390     PINCTRL_PIN(215, "GPIO215/RG2RXCTL/DDRV10"),
1391     PINCTRL_PIN(216, "GPIO216/RG2MDC/DDRV11"),
1392     PINCTRL_PIN(217, "GPIO217/RG2MDIO/DVHSYNC"),
1393     PINCTRL_PIN(218, "GPIO218/nWDO1"),
1394     PINCTRL_PIN(219, "GPIO219/nWDO2"),
1395     PINCTRL_PIN(220, "GPIO220/SMB12SCL"),
1396     PINCTRL_PIN(221, "GPIO221/SMB12SDA"),
1397     PINCTRL_PIN(222, "GPIO222/SMB13SCL"),
1398     PINCTRL_PIN(223, "GPIO223/SMB13SDA"),
1399
1400     PINCTRL_PIN(224, "GPIO224/SPIXCK"),
1401     PINCTRL_PIN(225, "GPO225/SPIXD0/STRAP12"),
1402     PINCTRL_PIN(226, "GPO226/SPIXD1/STRAP13"),
1403     PINCTRL_PIN(227, "GPIO227/nSPIXCS0"),
1404     PINCTRL_PIN(228, "GPIO228/nSPIXCS1"),
1405     PINCTRL_PIN(229, "GPO229/SPIXD2/STRAP3"),
1406     PINCTRL_PIN(230, "GPIO230/SPIXD3"),
1407     PINCTRL_PIN(231, "GPIO231/nCLKREQ"),
1408     PINCTRL_PIN(255, "GPI255/DACOSEL"),
1409 };
1410
1411 /* Enable mode in pin group */
1412 static void npcm7xx_setfunc(struct regmap *gcr_regmap, const unsigned int *pin,
1413                 int pin_number, int mode)
1414 {
1415     const struct npcm7xx_pincfg *cfg;
1416     int i;
1417
1418     for (i = 0 ; i < pin_number ; i++) {
1419         cfg = &pincfg[pin[i]];
1420         if (mode == fn_gpio || cfg->fn0 == mode || cfg->fn1 == mode || cfg->fn2 == mode) {
1421             if (cfg->reg0)
1422                 regmap_update_bits(gcr_regmap, cfg->reg0,
1423                            BIT(cfg->bit0),
1424                            !!(cfg->fn0 == mode) ?
1425                            BIT(cfg->bit0) : 0);
1426             if (cfg->reg1)
1427                 regmap_update_bits(gcr_regmap, cfg->reg1,
1428                            BIT(cfg->bit1),
1429                            !!(cfg->fn1 == mode) ?
1430                            BIT(cfg->bit1) : 0);
1431             if (cfg->reg2)
1432                 regmap_update_bits(gcr_regmap, cfg->reg2,
1433                            BIT(cfg->bit2),
1434                            !!(cfg->fn2 == mode) ?
1435                            BIT(cfg->bit2) : 0);
1436         }
1437     }
1438 }
1439
1440 /* Get slew rate of pin (high/low) */
1441 static int npcm7xx_get_slew_rate(struct npcm7xx_gpio *bank,
1442                  struct regmap *gcr_regmap, unsigned int pin)
1443 {
1444     u32 val;
1445     int gpio = (pin % bank->gc.ngpio);
1446     unsigned long pinmask = BIT(gpio);
1447
1448     if (pincfg[pin].flag & SLEW)
1449         return ioread32(bank->base + NPCM7XX_GP_N_OSRC)
1450         & pinmask;
1451     /* LPC Slew rate in SRCNT register */
1452     if (pincfg[pin].flag & SLEWLPC) {
1453         regmap_read(gcr_regmap, NPCM7XX_GCR_SRCNT, &val);
1454         return !!(val & SRCNT_ESPI);
1455     }
1456
1457     return -EINVAL;
1458 }
1459
1460 /* Set slew rate of pin (high/low) */
1461 static int npcm7xx_set_slew_rate(struct npcm7xx_gpio *bank,
1462                  struct regmap *gcr_regmap, unsigned int pin,
1463                  int arg)
1464 {
1465     int gpio = BIT(pin % bank->gc.ngpio);
1466
1467     if (pincfg[pin].flag & SLEW) {
1468         switch (arg) {
1469         case 0:
1470             npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_OSRC,
1471                       gpio);
1472             return 0;
1473         case 1:
1474             npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_OSRC,
1475                       gpio);
1476             return 0;
1477         default:
1478             return -EINVAL;
1479         }
1480     }
1481     /* LPC Slew rate in SRCNT register */
1482     if (pincfg[pin].flag & SLEWLPC) {
1483         switch (arg) {
1484         case 0:
1485             regmap_update_bits(gcr_regmap, NPCM7XX_GCR_SRCNT,
1486                        SRCNT_ESPI, 0);
1487             return 0;
1488         case 1:
1489             regmap_update_bits(gcr_regmap, NPCM7XX_GCR_SRCNT,
1490                        SRCNT_ESPI, SRCNT_ESPI);
1491             return 0;
1492         default:
1493             return -EINVAL;
1494         }
1495     }
1496
1497     return -EINVAL;
1498 }
1499
1500 /* Get drive strength for a pin, if supported */
1501 static int npcm7xx_get_drive_strength(struct pinctrl_dev *pctldev,
1502                       unsigned int pin)
1503 {
1504     struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
1505     struct npcm7xx_gpio *bank =
1506         &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK];
1507     int gpio = (pin % bank->gc.ngpio);
1508     unsigned long pinmask = BIT(gpio);
1509     u32 ds = 0;
1510     int flg, val;
1511
1512     flg = pincfg[pin].flag;
1513     if (flg & DRIVE_STRENGTH_MASK) {
1514         /* Get standard reading */
1515         val = ioread32(bank->base + NPCM7XX_GP_N_ODSC)
1516         & pinmask;
1517         ds = val ? DSHI(flg) : DSLO(flg);
1518         dev_dbg(bank->gc.parent,
1519             "pin %d strength %d = %d\n", pin, val, ds);
1520         return ds;
1521     }
1522
1523     return -EINVAL;
1524 }
1525
1526 /* Set drive strength for a pin, if supported */
1527 static int npcm7xx_set_drive_strength(struct npcm7xx_pinctrl *npcm,
1528                       unsigned int pin, int nval)
1529 {
1530     int v;
1531     struct npcm7xx_gpio *bank =
1532         &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK];
1533     int gpio = BIT(pin % bank->gc.ngpio);
1534
1535     v = (pincfg[pin].flag & DRIVE_STRENGTH_MASK);
1536     if (!nval || !v)
1537         return -ENOTSUPP;
1538     if (DSLO(v) == nval) {
1539         dev_dbg(bank->gc.parent,
1540             "setting pin %d to low strength [%d]\n", pin, nval);
1541         npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_ODSC, gpio);
1542         return 0;
1543     } else if (DSHI(v) == nval) {
1544         dev_dbg(bank->gc.parent,
1545             "setting pin %d to high strength [%d]\n", pin, nval);
1546         npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_ODSC, gpio);
1547         return 0;
1548     }
1549
1550     return -ENOTSUPP;
1551 }
1552
1553 /* pinctrl_ops */
1554 static void npcm7xx_pin_dbg_show(struct pinctrl_dev *pctldev,
1555                  struct seq_file *s, unsigned int offset)
1556 {
1557     seq_printf(s, "pinctrl_ops.dbg: %d", offset);
1558 }
1559
1560 static int npcm7xx_get_groups_count(struct pinctrl_dev *pctldev)
1561 {
1562     struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
1563
1564     dev_dbg(npcm->dev, "group size: %zu\n", ARRAY_SIZE(npcm7xx_groups));
1565     return ARRAY_SIZE(npcm7xx_groups);
1566 }
1567
1568 static const char *npcm7xx_get_group_name(struct pinctrl_dev *pctldev,
1569                       unsigned int selector)
1570 {
1571     return npcm7xx_groups[selector].name;
1572 }
1573
1574 static int npcm7xx_get_group_pins(struct pinctrl_dev *pctldev,
1575                   unsigned int selector,
1576                   const unsigned int **pins,
1577                   unsigned int *npins)
1578 {
1579     *npins = npcm7xx_groups[selector].npins;
1580     *pins  = npcm7xx_groups[selector].pins;
1581
1582     return 0;
1583 }
1584
1585 static int npcm7xx_dt_node_to_map(struct pinctrl_dev *pctldev,
1586                   struct device_node *np_config,
1587                   struct pinctrl_map **map,
1588                   u32 *num_maps)
1589 {
1590     struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
1591
1592     dev_dbg(npcm->dev, "dt_node_to_map: %s\n", np_config->name);
1593     return pinconf_generic_dt_node_to_map(pctldev, np_config,
1594                           map, num_maps,
1595                           PIN_MAP_TYPE_INVALID);
1596 }
1597
1598 static void npcm7xx_dt_free_map(struct pinctrl_dev *pctldev,
1599                 struct pinctrl_map *map, u32 num_maps)
1600 {
1601     kfree(map);
1602 }
1603
1604 static const struct pinctrl_ops npcm7xx_pinctrl_ops = {
1605     .get_groups_count = npcm7xx_get_groups_count,
1606     .get_group_name = npcm7xx_get_group_name,
1607     .get_group_pins = npcm7xx_get_group_pins,
1608     .pin_dbg_show = npcm7xx_pin_dbg_show,
1609     .dt_node_to_map = npcm7xx_dt_node_to_map,
1610     .dt_free_map = npcm7xx_dt_free_map,
1611 };
1612
1613 /* pinmux_ops  */
1614 static int npcm7xx_get_functions_count(struct pinctrl_dev *pctldev)
1615 {
1616     return ARRAY_SIZE(npcm7xx_funcs);
1617 }
1618
1619 static const char *npcm7xx_get_function_name(struct pinctrl_dev *pctldev,
1620                          unsigned int function)
1621 {
1622     return npcm7xx_funcs[function].name;
1623 }
1624
1625 static int npcm7xx_get_function_groups(struct pinctrl_dev *pctldev,
1626                        unsigned int function,
1627                        const char * const **groups,
1628                        unsigned int * const ngroups)
1629 {
1630     *ngroups = npcm7xx_funcs[function].ngroups;
1631     *groups  = npcm7xx_funcs[function].groups;
1632
1633     return 0;
1634 }
1635
1636 static int npcm7xx_pinmux_set_mux(struct pinctrl_dev *pctldev,
1637                   unsigned int function,
1638                   unsigned int group)
1639 {
1640     struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
1641
1642     dev_dbg(npcm->dev, "set_mux: %d, %d[%s]\n", function, group,
1643         npcm7xx_groups[group].name);
1644
1645     npcm7xx_setfunc(npcm->gcr_regmap, npcm7xx_groups[group].pins,
1646             npcm7xx_groups[group].npins, group);
1647
1648     return 0;
1649 }
1650
1651 static int npcm7xx_gpio_request_enable(struct pinctrl_dev *pctldev,
1652                        struct pinctrl_gpio_range *range,
1653                        unsigned int offset)
1654 {
1655     struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
1656
1657     if (!range) {
1658         dev_err(npcm->dev, "invalid range\n");
1659         return -EINVAL;
1660     }
1661     if (!range->gc) {
1662         dev_err(npcm->dev, "invalid gpiochip\n");
1663         return -EINVAL;
1664     }
1665
1666     npcm7xx_setfunc(npcm->gcr_regmap, &offset, 1, fn_gpio);
1667
1668     return 0;
1669 }
1670
1671 /* Release GPIO back to pinctrl mode */
1672 static void npcm7xx_gpio_request_free(struct pinctrl_dev *pctldev,
1673                       struct pinctrl_gpio_range *range,
1674                       unsigned int offset)
1675 {
1676     struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
1677     int virq;
1678
1679     virq = irq_find_mapping(npcm->domain, offset);
1680     if (virq)
1681         irq_dispose_mapping(virq);
1682 }
1683
1684 /* Set GPIO direction */
1685 static int npcm_gpio_set_direction(struct pinctrl_dev *pctldev,
1686                    struct pinctrl_gpio_range *range,
1687                    unsigned int offset, bool input)
1688 {
1689     struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
1690     struct npcm7xx_gpio *bank =
1691         &npcm->gpio_bank[offset / NPCM7XX_GPIO_PER_BANK];
1692     int gpio = BIT(offset % bank->gc.ngpio);
1693
1694     dev_dbg(bank->gc.parent, "GPIO Set Direction: %d = %d\n", offset,
1695         input);
1696     if (input)
1697         iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC);
1698     else
1699         iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES);
1700
1701     return 0;
1702 }
1703
1704 static const struct pinmux_ops npcm7xx_pinmux_ops = {
1705     .get_functions_count = npcm7xx_get_functions_count,
1706     .get_function_name = npcm7xx_get_function_name,
1707     .get_function_groups = npcm7xx_get_function_groups,
1708     .set_mux = npcm7xx_pinmux_set_mux,
1709     .gpio_request_enable = npcm7xx_gpio_request_enable,
1710     .gpio_disable_free = npcm7xx_gpio_request_free,
1711     .gpio_set_direction = npcm_gpio_set_direction,
1712 };
1713
1714 /* pinconf_ops */
1715 static int npcm7xx_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
1716                   unsigned long *config)
1717 {
1718     enum pin_config_param param = pinconf_to_config_param(*config);
1719     struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
1720     struct npcm7xx_gpio *bank =
1721         &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK];
1722     int gpio = (pin % bank->gc.ngpio);
1723     unsigned long pinmask = BIT(gpio);
1724     u32 ie, oe, pu, pd;
1725     int rc = 0;
1726
1727     switch (param) {
1728     case PIN_CONFIG_BIAS_DISABLE:
1729     case PIN_CONFIG_BIAS_PULL_UP:
1730     case PIN_CONFIG_BIAS_PULL_DOWN:
1731         pu = ioread32(bank->base + NPCM7XX_GP_N_PU) & pinmask;
1732         pd = ioread32(bank->base + NPCM7XX_GP_N_PD) & pinmask;
1733         if (param == PIN_CONFIG_BIAS_DISABLE)
1734             rc = (!pu && !pd);
1735         else if (param == PIN_CONFIG_BIAS_PULL_UP)
1736             rc = (pu && !pd);
1737         else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
1738             rc = (!pu && pd);
1739         break;
1740     case PIN_CONFIG_OUTPUT:
1741     case PIN_CONFIG_INPUT_ENABLE:
1742         ie = ioread32(bank->base + NPCM7XX_GP_N_IEM) & pinmask;
1743         oe = ioread32(bank->base + NPCM7XX_GP_N_OE) & pinmask;
1744         if (param == PIN_CONFIG_INPUT_ENABLE)
1745             rc = (ie && !oe);
1746         else if (param == PIN_CONFIG_OUTPUT)
1747             rc = (!ie && oe);
1748         break;
1749     case PIN_CONFIG_DRIVE_PUSH_PULL:
1750         rc = !(ioread32(bank->base + NPCM7XX_GP_N_OTYP) & pinmask);
1751         break;
1752     case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1753         rc = ioread32(bank->base + NPCM7XX_GP_N_OTYP) & pinmask;
1754         break;
1755     case PIN_CONFIG_INPUT_DEBOUNCE:
1756         rc = ioread32(bank->base + NPCM7XX_GP_N_DBNC) & pinmask;
1757         break;
1758     case PIN_CONFIG_DRIVE_STRENGTH:
1759         rc = npcm7xx_get_drive_strength(pctldev, pin);
1760         if (rc)
1761             *config = pinconf_to_config_packed(param, rc);
1762         break;
1763     case PIN_CONFIG_SLEW_RATE:
1764         rc = npcm7xx_get_slew_rate(bank, npcm->gcr_regmap, pin);
1765         if (rc >= 0)
1766             *config = pinconf_to_config_packed(param, rc);
1767         break;
1768     default:
1769         return -ENOTSUPP;
1770     }
1771
1772     if (!rc)
1773         return -EINVAL;
1774
1775     return 0;
1776 }
1777
1778 static int npcm7xx_config_set_one(struct npcm7xx_pinctrl *npcm,
1779                   unsigned int pin, unsigned long config)
1780 {
1781     enum pin_config_param param = pinconf_to_config_param(config);
1782     u16 arg = pinconf_to_config_argument(config);
1783     struct npcm7xx_gpio *bank =
1784         &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK];
1785     int gpio = BIT(pin % bank->gc.ngpio);
1786
1787     dev_dbg(bank->gc.parent, "param=%d %d[GPIO]\n", param, pin);
1788     switch (param) {
1789     case PIN_CONFIG_BIAS_DISABLE:
1790         npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio);
1791         npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio);
1792         break;
1793     case PIN_CONFIG_BIAS_PULL_DOWN:
1794         npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio);
1795         npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio);
1796         break;
1797     case PIN_CONFIG_BIAS_PULL_UP:
1798         npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_PD, gpio);
1799         npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_PU, gpio);
1800         break;
1801     case PIN_CONFIG_INPUT_ENABLE:
1802         iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC);
1803         bank->direction_input(&bank->gc, pin % bank->gc.ngpio);
1804         break;
1805     case PIN_CONFIG_OUTPUT:
1806         iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES);
1807         bank->direction_output(&bank->gc, pin % bank->gc.ngpio, arg);
1808         break;
1809     case PIN_CONFIG_DRIVE_PUSH_PULL:
1810         npcm_gpio_clr(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio);
1811         break;
1812     case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1813         npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_OTYP, gpio);
1814         break;
1815     case PIN_CONFIG_INPUT_DEBOUNCE:
1816         npcm_gpio_set(&bank->gc, bank->base + NPCM7XX_GP_N_DBNC, gpio);
1817         break;
1818     case PIN_CONFIG_SLEW_RATE:
1819         return npcm7xx_set_slew_rate(bank, npcm->gcr_regmap, pin, arg);
1820     case PIN_CONFIG_DRIVE_STRENGTH:
1821         return npcm7xx_set_drive_strength(npcm, pin, arg);
1822     default:
1823         return -ENOTSUPP;
1824     }
1825
1826     return 0;
1827 }
1828
1829 /* Set multiple configuration settings for a pin */
1830 static int npcm7xx_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
1831                   unsigned long *configs, unsigned int num_configs)
1832 {
1833     struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
1834     int rc;
1835
1836     while (num_configs--) {
1837         rc = npcm7xx_config_set_one(npcm, pin, *configs++);
1838         if (rc)
1839             return rc;
1840     }
1841
1842     return 0;
1843 }
1844
1845 static const struct pinconf_ops npcm7xx_pinconf_ops = {
1846     .is_generic = true,
1847     .pin_config_get = npcm7xx_config_get,
1848     .pin_config_set = npcm7xx_config_set,
1849 };
1850
1851 /* pinctrl_desc */
1852 static struct pinctrl_desc npcm7xx_pinctrl_desc = {
1853     .name = "npcm7xx-pinctrl",
1854     .pins = npcm7xx_pins,
1855     .npins = ARRAY_SIZE(npcm7xx_pins),
1856     .pctlops = &npcm7xx_pinctrl_ops,
1857     .pmxops = &npcm7xx_pinmux_ops,
1858     .confops = &npcm7xx_pinconf_ops,
1859     .owner = THIS_MODULE,
1860 };
1861
1862 static int npcm7xx_gpio_of(struct npcm7xx_pinctrl *pctrl)
1863 {
1864     int ret = -ENXIO;
1865     struct resource res;
1866     struct device *dev = pctrl->dev;
1867     struct fwnode_reference_args args;
1868     struct fwnode_handle *child;
1869     int id = 0;
1870
1871     for_each_gpiochip_node(dev, child) {
1872         struct device_node *np = to_of_node(child);
1873
1874         ret = of_address_to_resource(np, 0, &res);
1875         if (ret < 0) {
1876             dev_err(dev, "Resource fail for GPIO bank %u\n", id);
1877             return ret;
1878         }
1879
1880         pctrl->gpio_bank[id].base = ioremap(res.start, resource_size(&res));
1881
1882         ret = bgpio_init(&pctrl->gpio_bank[id].gc, dev, 4,
1883                  pctrl->gpio_bank[id].base + NPCM7XX_GP_N_DIN,
1884                  pctrl->gpio_bank[id].base + NPCM7XX_GP_N_DOUT,
1885                  NULL,
1886                  NULL,
1887                  pctrl->gpio_bank[id].base + NPCM7XX_GP_N_IEM,
1888                  BGPIOF_READ_OUTPUT_REG_SET);
1889         if (ret) {
1890             dev_err(dev, "bgpio_init() failed\n");
1891             return ret;
1892         }
1893
1894         ret = fwnode_property_get_reference_args(child, "gpio-ranges", NULL, 3, 0, &args);
1895         if (ret < 0) {
1896             dev_err(dev, "gpio-ranges fail for GPIO bank %u\n", id);
1897             return ret;
1898         }
1899
1900         ret = irq_of_parse_and_map(np, 0);
1901         if (!ret) {
1902             dev_err(dev, "No IRQ for GPIO bank %u\n", id);
1903             return -EINVAL;
1904         }
1905         pctrl->gpio_bank[id].irq = ret;
1906         pctrl->gpio_bank[id].irq_chip = npcmgpio_irqchip;
1907         pctrl->gpio_bank[id].irqbase = id * NPCM7XX_GPIO_PER_BANK;
1908         pctrl->gpio_bank[id].pinctrl_id = args.args[0];
1909         pctrl->gpio_bank[id].gc.base = args.args[1];
1910         pctrl->gpio_bank[id].gc.ngpio = args.args[2];
1911         pctrl->gpio_bank[id].gc.owner = THIS_MODULE;
1912         pctrl->gpio_bank[id].gc.parent = dev;
1913         pctrl->gpio_bank[id].gc.fwnode = child;
1914         pctrl->gpio_bank[id].gc.label = devm_kasprintf(dev, GFP_KERNEL, "%pfw", child);
1915         if (pctrl->gpio_bank[id].gc.label == NULL)
1916             return -ENOMEM;
1917
1918         pctrl->gpio_bank[id].gc.dbg_show = npcmgpio_dbg_show;
1919         pctrl->gpio_bank[id].direction_input = pctrl->gpio_bank[id].gc.direction_input;
1920         pctrl->gpio_bank[id].gc.direction_input = npcmgpio_direction_input;
1921         pctrl->gpio_bank[id].direction_output = pctrl->gpio_bank[id].gc.direction_output;
1922         pctrl->gpio_bank[id].gc.direction_output = npcmgpio_direction_output;
1923         pctrl->gpio_bank[id].request = pctrl->gpio_bank[id].gc.request;
1924         pctrl->gpio_bank[id].gc.request = npcmgpio_gpio_request;
1925         pctrl->gpio_bank[id].gc.free = npcmgpio_gpio_free;
1926         id++;
1927     }
1928
1929     pctrl->bank_num = id;
1930     return ret;
1931 }
1932
1933 static int npcm7xx_gpio_register(struct npcm7xx_pinctrl *pctrl)
1934 {
1935     int ret, id;
1936
1937     for (id = 0 ; id < pctrl->bank_num ; id++) {
1938         struct gpio_irq_chip *girq;
1939
1940         girq = &pctrl->gpio_bank[id].gc.irq;
1941         girq->chip = &pctrl->gpio_bank[id].irq_chip;
1942         girq->parent_handler = npcmgpio_irq_handler;
1943         girq->num_parents = 1;
1944         girq->parents = devm_kcalloc(pctrl->dev, 1,
1945                          sizeof(*girq->parents),
1946                          GFP_KERNEL);
1947         if (!girq->parents) {
1948             ret = -ENOMEM;
1949             goto err_register;
1950         }
1951         girq->parents[0] = pctrl->gpio_bank[id].irq;
1952         girq->default_type = IRQ_TYPE_NONE;
1953         girq->handler = handle_level_irq;
1954         ret = devm_gpiochip_add_data(pctrl->dev,
1955                          &pctrl->gpio_bank[id].gc,
1956                          &pctrl->gpio_bank[id]);
1957         if (ret) {
1958             dev_err(pctrl->dev, "Failed to add GPIO chip %u\n", id);
1959             goto err_register;
1960         }
1961
1962         ret = gpiochip_add_pin_range(&pctrl->gpio_bank[id].gc,
1963                          dev_name(pctrl->dev),
1964                          pctrl->gpio_bank[id].pinctrl_id,
1965                          pctrl->gpio_bank[id].gc.base,
1966                          pctrl->gpio_bank[id].gc.ngpio);
1967         if (ret < 0) {
1968             dev_err(pctrl->dev, "Failed to add GPIO bank %u\n", id);
1969             gpiochip_remove(&pctrl->gpio_bank[id].gc);
1970             goto err_register;
1971         }
1972     }
1973
1974     return 0;
1975
1976 err_register:
1977     for (; id > 0; id--)
1978         gpiochip_remove(&pctrl->gpio_bank[id - 1].gc);
1979
1980     return ret;
1981 }
1982
1983 static int npcm7xx_pinctrl_probe(struct platform_device *pdev)
1984 {
1985     struct npcm7xx_pinctrl *pctrl;
1986     int ret;
1987
1988     pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1989     if (!pctrl)
1990         return -ENOMEM;
1991
1992     pctrl->dev = &pdev->dev;
1993     dev_set_drvdata(&pdev->dev, pctrl);
1994
1995     pctrl->gcr_regmap =
1996         syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr");
1997     if (IS_ERR(pctrl->gcr_regmap)) {
1998         dev_err(pctrl->dev, "didn't find nuvoton,npcm750-gcr\n");
1999         return PTR_ERR(pctrl->gcr_regmap);
2000     }
2001
2002     ret = npcm7xx_gpio_of(pctrl);
2003     if (ret < 0) {
2004         dev_err(pctrl->dev, "Failed to gpio dt-binding %u\n", ret);
2005         return ret;
2006     }
2007
2008     pctrl->pctldev = devm_pinctrl_register(&pdev->dev,
2009                            &npcm7xx_pinctrl_desc, pctrl);
2010     if (IS_ERR(pctrl->pctldev)) {
2011         dev_err(&pdev->dev, "Failed to register pinctrl device\n");
2012         return PTR_ERR(pctrl->pctldev);
2013     }
2014
2015     ret = npcm7xx_gpio_register(pctrl);
2016     if (ret < 0) {
2017         dev_err(pctrl->dev, "Failed to register gpio %u\n", ret);
2018         return ret;
2019     }
2020
2021     pr_info("NPCM7xx Pinctrl driver probed\n");
2022     return 0;
2023 }
2024
2025 static const struct of_device_id npcm7xx_pinctrl_match[] = {
2026     { .compatible = "nuvoton,npcm750-pinctrl" },
2027     { },
2028 };
2029 MODULE_DEVICE_TABLE(of, npcm7xx_pinctrl_match);
2030
2031 static struct platform_driver npcm7xx_pinctrl_driver = {
2032     .probe = npcm7xx_pinctrl_probe,
2033     .driver = {
2034         .name = "npcm7xx-pinctrl",
2035         .of_match_table = npcm7xx_pinctrl_match,
2036         .suppress_bind_attrs = true,
2037     },
2038 };
2039
2040 static int __init npcm7xx_pinctrl_register(void)
2041 {
2042     return platform_driver_register(&npcm7xx_pinctrl_driver);
2043 }
2044 arch_initcall(npcm7xx_pinctrl_register);
2045
2046 MODULE_LICENSE("GPL v2");
2047 MODULE_AUTHOR("jordan_hargrave@dell.com");
2048 MODULE_AUTHOR("tomer.maimon@nuvoton.com");
2049 MODULE_DESCRIPTION("Nuvoton NPCM7XX Pinctrl and GPIO driver");