pinctrl/nomadik/pinctrl-abx500.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef PINCTRL_PINCTRL_ABx500_H
0003 #define PINCTRL_PINCTRL_ABx500_H
0004
0005 /* Package definitions */
0006 #define PINCTRL_AB8500  0
0007 #define PINCTRL_AB8505  1
0008
0009 /* pins alternate function */
0010 enum abx500_pin_func {
0011     ABX500_DEFAULT,
0012     ABX500_ALT_A,
0013     ABX500_ALT_B,
0014     ABX500_ALT_C,
0015 };
0016
0017 enum abx500_gpio_pull_updown {
0018     ABX500_GPIO_PULL_DOWN = 0x0,
0019     ABX500_GPIO_PULL_NONE = 0x1,
0020     ABX500_GPIO_PULL_UP = 0x3,
0021 };
0022
0023 enum abx500_gpio_vinsel {
0024     ABX500_GPIO_VINSEL_VBAT = 0x0,
0025     ABX500_GPIO_VINSEL_VIN_1V8 = 0x1,
0026     ABX500_GPIO_VINSEL_VDD_BIF = 0x2,
0027 };
0028
0029 /**
0030  * struct abx500_function - ABx500 pinctrl mux function
0031  * @name: The name of the function, exported to pinctrl core.
0032  * @groups: An array of pin groups that may select this function.
0033  * @ngroups: The number of entries in @groups.
0034  */
0035 struct abx500_function {
0036     const char *name;
0037     const char * const *groups;
0038     unsigned ngroups;
0039 };
0040
0041 /**
0042  * struct abx500_pingroup - describes a ABx500 pin group
0043  * @name: the name of this specific pin group
0044  * @pins: an array of discrete physical pins used in this group, taken
0045  *  from the driver-local pin enumeration space
0046  * @num_pins: the number of pins in this group array, i.e. the number of
0047  *  elements in .pins so we can iterate over that array
0048  * @altsetting: the altsetting to apply to all pins in this group to
0049  *  configure them to be used by a function
0050  */
0051 struct abx500_pingroup {
0052     const char *name;
0053     const unsigned int *pins;
0054     const unsigned npins;
0055     int altsetting;
0056 };
0057
0058 #define ALTERNATE_FUNCTIONS(pin, sel_bit, alt1, alt2, alta, altb, altc) \
0059 {                                   \
0060     .pin_number = pin,                      \
0061     .gpiosel_bit = sel_bit,                     \
0062     .alt_bit1 = alt1,                       \
0063     .alt_bit2 = alt2,                       \
0064     .alta_val = alta,                       \
0065     .altb_val = altb,                       \
0066     .altc_val = altc,                       \
0067 }
0068
0069 #define UNUSED -1
0070 /**
0071  * struct alternate_functions
0072  * @pin_number:     The pin number
0073  * @gpiosel_bit:    Control bit in GPIOSEL register,
0074  * @alt_bit1:       First AlternateFunction bit used to select the
0075  *          alternate function
0076  * @alt_bit2:       Second AlternateFunction bit used to select the
0077  *          alternate function
0078  *
0079  *          these 3 following fields are necessary due to none
0080  *          coherency on how to select the altA, altB and altC
0081  *          function between the ABx500 SOC family when using
0082  *          alternatfunc register.
0083  * @alta_val:       value to write in alternatfunc to select altA function
0084  * @altb_val:       value to write in alternatfunc to select altB function
0085  * @altc_val:       value to write in alternatfunc to select altC function
0086  */
0087 struct alternate_functions {
0088     unsigned pin_number;
0089     s8 gpiosel_bit;
0090     s8 alt_bit1;
0091     s8 alt_bit2;
0092     u8 alta_val;
0093     u8 altb_val;
0094     u8 altc_val;
0095 };
0096
0097 #define GPIO_IRQ_CLUSTER(a, b, c)   \
0098 {                   \
0099     .start = a,         \
0100     .end = b,           \
0101     .to_irq = c,            \
0102 }
0103
0104 /**
0105  * struct abx500_gpio_irq_cluster - indicates GPIOs which are interrupt
0106  *          capable
0107  * @start:      The pin number of the first pin interrupt capable
0108  * @end:        The pin number of the last pin interrupt capable
0109  * @to_irq:     The ABx500 GPIO's associated IRQs are clustered
0110  *                      together throughout the interrupt numbers at irregular
0111  *                      intervals. To solve this quandary, we will place the
0112  *                      read-in values into the cluster information table
0113  */
0114
0115 struct abx500_gpio_irq_cluster {
0116     int start;
0117     int end;
0118     int to_irq;
0119 };
0120
0121 /**
0122  * struct abx500_pinrange - map pin numbers to GPIO offsets
0123  * @offset:     offset into the GPIO local numberspace, incidentally
0124  *          identical to the offset into the local pin numberspace
0125  * @npins:      number of pins to map from both offsets
0126  * @altfunc:        altfunc setting to be used to enable GPIO on a pin in
0127  *          this range (may vary)
0128  */
0129 struct abx500_pinrange {
0130     unsigned int offset;
0131     unsigned int npins;
0132     int altfunc;
0133 };
0134
0135 #define ABX500_PINRANGE(a, b, c) { .offset = a, .npins = b, .altfunc = c }
0136
0137 /**
0138  * struct abx500_pinctrl_soc_data - ABx500 pin controller per-SoC configuration
0139  * @gpio_ranges:    An array of GPIO ranges for this SoC
0140  * @gpio_num_ranges:    The number of GPIO ranges for this SoC
0141  * @pins:       An array describing all pins the pin controller affects.
0142  *          All pins which are also GPIOs must be listed first within the
0143  *          array, and be numbered identically to the GPIO controller's
0144  *          numbering.
0145  * @npins:      The number of entries in @pins.
0146  * @functions:      The functions supported on this SoC.
0147  * @nfunction:      The number of entries in @functions.
0148  * @groups:     An array describing all pin groups the pin SoC supports.
0149  * @ngroups:        The number of entries in @groups.
0150  * @alternate_functions: array describing pins which supports alternate and
0151  *          how to set it.
0152  * @gpio_irq_cluster:   An array of GPIO interrupt capable for this SoC
0153  * @ngpio_irq_cluster:  The number of GPIO inetrrupt capable for this SoC
0154  * @irq_gpio_rising_offset: Interrupt offset used as base to compute specific
0155  *          setting strategy of the rising interrupt line
0156  * @irq_gpio_falling_offset: Interrupt offset used as base to compute specific
0157  *          setting strategy of the falling interrupt line
0158  * @irq_gpio_factor:    Factor used to compute specific setting strategy of
0159  *          the interrupt line
0160  */
0161
0162 struct abx500_pinctrl_soc_data {
0163     const struct abx500_pinrange *gpio_ranges;
0164     unsigned gpio_num_ranges;
0165     const struct pinctrl_pin_desc *pins;
0166     unsigned npins;
0167     const struct abx500_function *functions;
0168     unsigned nfunctions;
0169     const struct abx500_pingroup *groups;
0170     unsigned ngroups;
0171     struct alternate_functions *alternate_functions;
0172     struct abx500_gpio_irq_cluster *gpio_irq_cluster;
0173     unsigned ngpio_irq_cluster;
0174     int irq_gpio_rising_offset;
0175     int irq_gpio_falling_offset;
0176     int irq_gpio_factor;
0177 };
0178
0179 #ifdef CONFIG_PINCTRL_AB8500
0180
0181 void abx500_pinctrl_ab8500_init(struct abx500_pinctrl_soc_data **soc);
0182
0183 #else
0184
0185 static inline void
0186 abx500_pinctrl_ab8500_init(struct abx500_pinctrl_soc_data **soc)
0187 {
0188 }
0189
0190 #endif
0191
0192 #ifdef CONFIG_PINCTRL_AB8505
0193
0194 void abx500_pinctrl_ab8505_init(struct abx500_pinctrl_soc_data **soc);
0195
0196 #else
0197
0198 static inline void
0199 abx500_pinctrl_ab8505_init(struct abx500_pinctrl_soc_data **soc)
0200 {
0201 }
0202
0203 #endif
0204
0205 #endif /* PINCTRL_PINCTRL_ABx500_H */