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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Marvell Dove pinctrl driver based on mvebu pinctrl core
0004  *
0005  * Author: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
0006  */
0007 
0008 #include <linux/err.h>
0009 #include <linux/init.h>
0010 #include <linux/io.h>
0011 #include <linux/bitops.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/clk.h>
0014 #include <linux/of.h>
0015 #include <linux/of_device.h>
0016 #include <linux/mfd/syscon.h>
0017 #include <linux/pinctrl/pinctrl.h>
0018 #include <linux/regmap.h>
0019 
0020 #include "pinctrl-mvebu.h"
0021 
0022 /* Internal registers can be configured at any 1 MiB aligned address */
0023 #define INT_REGS_MASK       ~(SZ_1M - 1)
0024 #define MPP4_REGS_OFFS      0xd0440
0025 #define PMU_REGS_OFFS       0xd802c
0026 #define GC_REGS_OFFS        0xe802c
0027 
0028 /* MPP Base registers */
0029 #define PMU_MPP_GENERAL_CTRL    0x10
0030 #define  AU0_AC97_SEL       BIT(16)
0031 
0032 /* MPP Control 4 register */
0033 #define SPI_GPIO_SEL        BIT(5)
0034 #define UART1_GPIO_SEL      BIT(4)
0035 #define AU1_GPIO_SEL        BIT(3)
0036 #define CAM_GPIO_SEL        BIT(2)
0037 #define SD1_GPIO_SEL        BIT(1)
0038 #define SD0_GPIO_SEL        BIT(0)
0039 
0040 /* PMU Signal Select registers */
0041 #define PMU_SIGNAL_SELECT_0 0x00
0042 #define PMU_SIGNAL_SELECT_1 0x04
0043 
0044 /* Global Config regmap registers */
0045 #define GLOBAL_CONFIG_1     0x00
0046 #define  TWSI_ENABLE_OPTION1    BIT(7)
0047 #define GLOBAL_CONFIG_2     0x04
0048 #define  TWSI_ENABLE_OPTION2    BIT(20)
0049 #define  TWSI_ENABLE_OPTION3    BIT(21)
0050 #define  TWSI_OPTION3_GPIO  BIT(22)
0051 #define SSP_CTRL_STATUS_1   0x08
0052 #define  SSP_ON_AU1     BIT(0)
0053 #define MPP_GENERAL_CONFIG  0x10
0054 #define  AU1_SPDIFO_GPIO_EN BIT(1)
0055 #define  NAND_GPIO_EN       BIT(0)
0056 
0057 #define CONFIG_PMU  BIT(4)
0058 
0059 static void __iomem *mpp4_base;
0060 static void __iomem *pmu_base;
0061 static struct regmap *gconfmap;
0062 
0063 static int dove_pmu_mpp_ctrl_get(struct mvebu_mpp_ctrl_data *data,
0064                  unsigned pid, unsigned long *config)
0065 {
0066     unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
0067     unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
0068     unsigned long pmu = readl(data->base + PMU_MPP_GENERAL_CTRL);
0069     unsigned long func;
0070 
0071     if ((pmu & BIT(pid)) == 0)
0072         return mvebu_mmio_mpp_ctrl_get(data, pid, config);
0073 
0074     func = readl(pmu_base + PMU_SIGNAL_SELECT_0 + off);
0075     *config = (func >> shift) & MVEBU_MPP_MASK;
0076     *config |= CONFIG_PMU;
0077 
0078     return 0;
0079 }
0080 
0081 static int dove_pmu_mpp_ctrl_set(struct mvebu_mpp_ctrl_data *data,
0082                  unsigned pid, unsigned long config)
0083 {
0084     unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
0085     unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
0086     unsigned long pmu = readl(data->base + PMU_MPP_GENERAL_CTRL);
0087     unsigned long func;
0088 
0089     if ((config & CONFIG_PMU) == 0) {
0090         writel(pmu & ~BIT(pid), data->base + PMU_MPP_GENERAL_CTRL);
0091         return mvebu_mmio_mpp_ctrl_set(data, pid, config);
0092     }
0093 
0094     writel(pmu | BIT(pid), data->base + PMU_MPP_GENERAL_CTRL);
0095     func = readl(pmu_base + PMU_SIGNAL_SELECT_0 + off);
0096     func &= ~(MVEBU_MPP_MASK << shift);
0097     func |= (config & MVEBU_MPP_MASK) << shift;
0098     writel(func, pmu_base + PMU_SIGNAL_SELECT_0 + off);
0099 
0100     return 0;
0101 }
0102 
0103 static int dove_mpp4_ctrl_get(struct mvebu_mpp_ctrl_data *data, unsigned pid,
0104                   unsigned long *config)
0105 {
0106     unsigned long mpp4 = readl(mpp4_base);
0107     unsigned long mask;
0108 
0109     switch (pid) {
0110     case 24: /* mpp_camera */
0111         mask = CAM_GPIO_SEL;
0112         break;
0113     case 40: /* mpp_sdio0 */
0114         mask = SD0_GPIO_SEL;
0115         break;
0116     case 46: /* mpp_sdio1 */
0117         mask = SD1_GPIO_SEL;
0118         break;
0119     case 58: /* mpp_spi0 */
0120         mask = SPI_GPIO_SEL;
0121         break;
0122     case 62: /* mpp_uart1 */
0123         mask = UART1_GPIO_SEL;
0124         break;
0125     default:
0126         return -EINVAL;
0127     }
0128 
0129     *config = ((mpp4 & mask) != 0);
0130 
0131     return 0;
0132 }
0133 
0134 static int dove_mpp4_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid,
0135                   unsigned long config)
0136 {
0137     unsigned long mpp4 = readl(mpp4_base);
0138     unsigned long mask;
0139 
0140     switch (pid) {
0141     case 24: /* mpp_camera */
0142         mask = CAM_GPIO_SEL;
0143         break;
0144     case 40: /* mpp_sdio0 */
0145         mask = SD0_GPIO_SEL;
0146         break;
0147     case 46: /* mpp_sdio1 */
0148         mask = SD1_GPIO_SEL;
0149         break;
0150     case 58: /* mpp_spi0 */
0151         mask = SPI_GPIO_SEL;
0152         break;
0153     case 62: /* mpp_uart1 */
0154         mask = UART1_GPIO_SEL;
0155         break;
0156     default:
0157         return -EINVAL;
0158     }
0159 
0160     mpp4 &= ~mask;
0161     if (config)
0162         mpp4 |= mask;
0163 
0164     writel(mpp4, mpp4_base);
0165 
0166     return 0;
0167 }
0168 
0169 static int dove_nand_ctrl_get(struct mvebu_mpp_ctrl_data *data, unsigned pid,
0170                   unsigned long *config)
0171 {
0172     unsigned int gmpp;
0173 
0174     regmap_read(gconfmap, MPP_GENERAL_CONFIG, &gmpp);
0175     *config = ((gmpp & NAND_GPIO_EN) != 0);
0176 
0177     return 0;
0178 }
0179 
0180 static int dove_nand_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid,
0181                   unsigned long config)
0182 {
0183     regmap_update_bits(gconfmap, MPP_GENERAL_CONFIG,
0184                NAND_GPIO_EN,
0185                (config) ? NAND_GPIO_EN : 0);
0186     return 0;
0187 }
0188 
0189 static int dove_audio0_ctrl_get(struct mvebu_mpp_ctrl_data *data, unsigned pid,
0190                 unsigned long *config)
0191 {
0192     unsigned long pmu = readl(data->base + PMU_MPP_GENERAL_CTRL);
0193 
0194     *config = ((pmu & AU0_AC97_SEL) != 0);
0195 
0196     return 0;
0197 }
0198 
0199 static int dove_audio0_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid,
0200                 unsigned long config)
0201 {
0202     unsigned long pmu = readl(data->base + PMU_MPP_GENERAL_CTRL);
0203 
0204     pmu &= ~AU0_AC97_SEL;
0205     if (config)
0206         pmu |= AU0_AC97_SEL;
0207     writel(pmu, data->base + PMU_MPP_GENERAL_CTRL);
0208 
0209     return 0;
0210 }
0211 
0212 static int dove_audio1_ctrl_get(struct mvebu_mpp_ctrl_data *data, unsigned pid,
0213                 unsigned long *config)
0214 {
0215     unsigned int mpp4 = readl(mpp4_base);
0216     unsigned int sspc1;
0217     unsigned int gmpp;
0218     unsigned int gcfg2;
0219 
0220     regmap_read(gconfmap, SSP_CTRL_STATUS_1, &sspc1);
0221     regmap_read(gconfmap, MPP_GENERAL_CONFIG, &gmpp);
0222     regmap_read(gconfmap, GLOBAL_CONFIG_2, &gcfg2);
0223 
0224     *config = 0;
0225     if (mpp4 & AU1_GPIO_SEL)
0226         *config |= BIT(3);
0227     if (sspc1 & SSP_ON_AU1)
0228         *config |= BIT(2);
0229     if (gmpp & AU1_SPDIFO_GPIO_EN)
0230         *config |= BIT(1);
0231     if (gcfg2 & TWSI_OPTION3_GPIO)
0232         *config |= BIT(0);
0233 
0234     /* SSP/TWSI only if I2S1 not set*/
0235     if ((*config & BIT(3)) == 0)
0236         *config &= ~(BIT(2) | BIT(0));
0237     /* TWSI only if SPDIFO not set*/
0238     if ((*config & BIT(1)) == 0)
0239         *config &= ~BIT(0);
0240     return 0;
0241 }
0242 
0243 static int dove_audio1_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid,
0244                 unsigned long config)
0245 {
0246     unsigned int mpp4 = readl(mpp4_base);
0247 
0248     mpp4 &= ~AU1_GPIO_SEL;
0249     if (config & BIT(3))
0250         mpp4 |= AU1_GPIO_SEL;
0251     writel(mpp4, mpp4_base);
0252 
0253     regmap_update_bits(gconfmap, SSP_CTRL_STATUS_1,
0254                SSP_ON_AU1,
0255                (config & BIT(2)) ? SSP_ON_AU1 : 0);
0256     regmap_update_bits(gconfmap, MPP_GENERAL_CONFIG,
0257                AU1_SPDIFO_GPIO_EN,
0258                (config & BIT(1)) ? AU1_SPDIFO_GPIO_EN : 0);
0259     regmap_update_bits(gconfmap, GLOBAL_CONFIG_2,
0260                TWSI_OPTION3_GPIO,
0261                (config & BIT(0)) ? TWSI_OPTION3_GPIO : 0);
0262 
0263     return 0;
0264 }
0265 
0266 /* mpp[52:57] gpio pins depend heavily on current config;
0267  * gpio_req does not try to mux in gpio capabilities to not
0268  * break other functions. If you require all mpps as gpio
0269  * enforce gpio setting by pinctrl mapping.
0270  */
0271 static int dove_audio1_ctrl_gpio_req(struct mvebu_mpp_ctrl_data *data,
0272                      unsigned pid)
0273 {
0274     unsigned long config;
0275 
0276     dove_audio1_ctrl_get(data, pid, &config);
0277 
0278     switch (config) {
0279     case 0x02: /* i2s1 : gpio[56:57] */
0280     case 0x0e: /* ssp  : gpio[56:57] */
0281         if (pid >= 56)
0282             return 0;
0283         return -ENOTSUPP;
0284     case 0x08: /* spdifo : gpio[52:55] */
0285     case 0x0b: /* twsi   : gpio[52:55] */
0286         if (pid <= 55)
0287             return 0;
0288         return -ENOTSUPP;
0289     case 0x0a: /* all gpio */
0290         return 0;
0291     /* 0x00 : i2s1/spdifo : no gpio */
0292     /* 0x0c : ssp/spdifo  : no gpio */
0293     /* 0x0f : ssp/twsi    : no gpio */
0294     }
0295     return -ENOTSUPP;
0296 }
0297 
0298 /* mpp[52:57] has gpio pins capable of in and out */
0299 static int dove_audio1_ctrl_gpio_dir(struct mvebu_mpp_ctrl_data *data,
0300                      unsigned pid, bool input)
0301 {
0302     if (pid < 52 || pid > 57)
0303         return -ENOTSUPP;
0304     return 0;
0305 }
0306 
0307 static int dove_twsi_ctrl_get(struct mvebu_mpp_ctrl_data *data, unsigned pid,
0308                   unsigned long *config)
0309 {
0310     unsigned int gcfg1;
0311     unsigned int gcfg2;
0312 
0313     regmap_read(gconfmap, GLOBAL_CONFIG_1, &gcfg1);
0314     regmap_read(gconfmap, GLOBAL_CONFIG_2, &gcfg2);
0315 
0316     *config = 0;
0317     if (gcfg1 & TWSI_ENABLE_OPTION1)
0318         *config = 1;
0319     else if (gcfg2 & TWSI_ENABLE_OPTION2)
0320         *config = 2;
0321     else if (gcfg2 & TWSI_ENABLE_OPTION3)
0322         *config = 3;
0323 
0324     return 0;
0325 }
0326 
0327 static int dove_twsi_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid,
0328                   unsigned long config)
0329 {
0330     unsigned int gcfg1 = 0;
0331     unsigned int gcfg2 = 0;
0332 
0333     switch (config) {
0334     case 1:
0335         gcfg1 = TWSI_ENABLE_OPTION1;
0336         break;
0337     case 2:
0338         gcfg2 = TWSI_ENABLE_OPTION2;
0339         break;
0340     case 3:
0341         gcfg2 = TWSI_ENABLE_OPTION3;
0342         break;
0343     }
0344 
0345     regmap_update_bits(gconfmap, GLOBAL_CONFIG_1,
0346                TWSI_ENABLE_OPTION1,
0347                gcfg1);
0348     regmap_update_bits(gconfmap, GLOBAL_CONFIG_2,
0349                TWSI_ENABLE_OPTION2 | TWSI_ENABLE_OPTION3,
0350                gcfg2);
0351 
0352     return 0;
0353 }
0354 
0355 static const struct mvebu_mpp_ctrl dove_mpp_controls[] = {
0356     MPP_FUNC_CTRL(0, 15, NULL, dove_pmu_mpp_ctrl),
0357     MPP_FUNC_CTRL(16, 23, NULL, mvebu_mmio_mpp_ctrl),
0358     MPP_FUNC_CTRL(24, 39, "mpp_camera", dove_mpp4_ctrl),
0359     MPP_FUNC_CTRL(40, 45, "mpp_sdio0", dove_mpp4_ctrl),
0360     MPP_FUNC_CTRL(46, 51, "mpp_sdio1", dove_mpp4_ctrl),
0361     MPP_FUNC_GPIO_CTRL(52, 57, "mpp_audio1", dove_audio1_ctrl),
0362     MPP_FUNC_CTRL(58, 61, "mpp_spi0", dove_mpp4_ctrl),
0363     MPP_FUNC_CTRL(62, 63, "mpp_uart1", dove_mpp4_ctrl),
0364     MPP_FUNC_CTRL(64, 71, "mpp_nand", dove_nand_ctrl),
0365     MPP_FUNC_CTRL(72, 72, "audio0", dove_audio0_ctrl),
0366     MPP_FUNC_CTRL(73, 73, "twsi", dove_twsi_ctrl),
0367 };
0368 
0369 static struct mvebu_mpp_mode dove_mpp_modes[] = {
0370     MPP_MODE(0,
0371         MPP_FUNCTION(0x00, "gpio", NULL),
0372         MPP_FUNCTION(0x02, "uart2", "rts"),
0373         MPP_FUNCTION(0x03, "sdio0", "cd"),
0374         MPP_FUNCTION(0x0f, "lcd0", "pwm"),
0375         MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
0376         MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
0377         MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
0378         MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
0379         MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
0380         MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
0381         MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
0382         MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
0383         MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
0384         MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
0385         MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
0386         MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
0387     MPP_MODE(1,
0388         MPP_FUNCTION(0x00, "gpio", NULL),
0389         MPP_FUNCTION(0x02, "uart2", "cts"),
0390         MPP_FUNCTION(0x03, "sdio0", "wp"),
0391         MPP_FUNCTION(0x0f, "lcd1", "pwm"),
0392         MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
0393         MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
0394         MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
0395         MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
0396         MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
0397         MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
0398         MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
0399         MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
0400         MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
0401         MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
0402         MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
0403         MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
0404     MPP_MODE(2,
0405         MPP_FUNCTION(0x00, "gpio", NULL),
0406         MPP_FUNCTION(0x01, "sata", "prsnt"),
0407         MPP_FUNCTION(0x02, "uart2", "txd"),
0408         MPP_FUNCTION(0x03, "sdio0", "buspwr"),
0409         MPP_FUNCTION(0x04, "uart1", "rts"),
0410         MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
0411         MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
0412         MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
0413         MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
0414         MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
0415         MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
0416         MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
0417         MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
0418         MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
0419         MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
0420         MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
0421         MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
0422     MPP_MODE(3,
0423         MPP_FUNCTION(0x00, "gpio", NULL),
0424         MPP_FUNCTION(0x01, "sata", "act"),
0425         MPP_FUNCTION(0x02, "uart2", "rxd"),
0426         MPP_FUNCTION(0x03, "sdio0", "ledctrl"),
0427         MPP_FUNCTION(0x04, "uart1", "cts"),
0428         MPP_FUNCTION(0x0f, "lcd-spi", "cs1"),
0429         MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
0430         MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
0431         MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
0432         MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
0433         MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
0434         MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
0435         MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
0436         MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
0437         MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
0438         MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
0439         MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
0440         MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
0441     MPP_MODE(4,
0442         MPP_FUNCTION(0x00, "gpio", NULL),
0443         MPP_FUNCTION(0x02, "uart3", "rts"),
0444         MPP_FUNCTION(0x03, "sdio1", "cd"),
0445         MPP_FUNCTION(0x04, "spi1", "miso"),
0446         MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
0447         MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
0448         MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
0449         MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
0450         MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
0451         MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
0452         MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
0453         MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
0454         MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
0455         MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
0456         MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
0457         MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
0458     MPP_MODE(5,
0459         MPP_FUNCTION(0x00, "gpio", NULL),
0460         MPP_FUNCTION(0x02, "uart3", "cts"),
0461         MPP_FUNCTION(0x03, "sdio1", "wp"),
0462         MPP_FUNCTION(0x04, "spi1", "cs"),
0463         MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
0464         MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
0465         MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
0466         MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
0467         MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
0468         MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
0469         MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
0470         MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
0471         MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
0472         MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
0473         MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
0474         MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
0475     MPP_MODE(6,
0476         MPP_FUNCTION(0x00, "gpio", NULL),
0477         MPP_FUNCTION(0x02, "uart3", "txd"),
0478         MPP_FUNCTION(0x03, "sdio1", "buspwr"),
0479         MPP_FUNCTION(0x04, "spi1", "mosi"),
0480         MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
0481         MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
0482         MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
0483         MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
0484         MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
0485         MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
0486         MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
0487         MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
0488         MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
0489         MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
0490         MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
0491         MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
0492     MPP_MODE(7,
0493         MPP_FUNCTION(0x00, "gpio", NULL),
0494         MPP_FUNCTION(0x02, "uart3", "rxd"),
0495         MPP_FUNCTION(0x03, "sdio1", "ledctrl"),
0496         MPP_FUNCTION(0x04, "spi1", "sck"),
0497         MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
0498         MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
0499         MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
0500         MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
0501         MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
0502         MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
0503         MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL),
0504         MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
0505         MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
0506         MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
0507         MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
0508         MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
0509     MPP_MODE(8,
0510         MPP_FUNCTION(0x00, "gpio", NULL),
0511         MPP_FUNCTION(0x01, "watchdog", "rstout"),
0512         MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
0513         MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
0514         MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
0515         MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
0516         MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
0517         MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
0518         MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
0519         MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
0520         MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
0521         MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
0522         MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
0523         MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
0524     MPP_MODE(9,
0525         MPP_FUNCTION(0x00, "gpio", NULL),
0526         MPP_FUNCTION(0x05, "pex1", "clkreq"),
0527         MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
0528         MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
0529         MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
0530         MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
0531         MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
0532         MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
0533         MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
0534         MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
0535         MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
0536         MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
0537         MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
0538         MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
0539     MPP_MODE(10,
0540         MPP_FUNCTION(0x00, "gpio", NULL),
0541         MPP_FUNCTION(0x05, "ssp", "sclk"),
0542         MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
0543         MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
0544         MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
0545         MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
0546         MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
0547         MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
0548         MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
0549         MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
0550         MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
0551         MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
0552         MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
0553         MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
0554     MPP_MODE(11,
0555         MPP_FUNCTION(0x00, "gpio", NULL),
0556         MPP_FUNCTION(0x01, "sata", "prsnt"),
0557         MPP_FUNCTION(0x02, "sata-1", "act"),
0558         MPP_FUNCTION(0x03, "sdio0", "ledctrl"),
0559         MPP_FUNCTION(0x04, "sdio1", "ledctrl"),
0560         MPP_FUNCTION(0x05, "pex0", "clkreq"),
0561         MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
0562         MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
0563         MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
0564         MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
0565         MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
0566         MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
0567         MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
0568         MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
0569         MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
0570         MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
0571         MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
0572         MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
0573     MPP_MODE(12,
0574         MPP_FUNCTION(0x00, "gpio", NULL),
0575         MPP_FUNCTION(0x01, "sata", "act"),
0576         MPP_FUNCTION(0x02, "uart2", "rts"),
0577         MPP_FUNCTION(0x03, "audio0", "extclk"),
0578         MPP_FUNCTION(0x04, "sdio1", "cd"),
0579         MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
0580         MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
0581         MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
0582         MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
0583         MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
0584         MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
0585         MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
0586         MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
0587         MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
0588         MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
0589         MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
0590         MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
0591     MPP_MODE(13,
0592         MPP_FUNCTION(0x00, "gpio", NULL),
0593         MPP_FUNCTION(0x02, "uart2", "cts"),
0594         MPP_FUNCTION(0x03, "audio1", "extclk"),
0595         MPP_FUNCTION(0x04, "sdio1", "wp"),
0596         MPP_FUNCTION(0x05, "ssp", "extclk"),
0597         MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
0598         MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
0599         MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
0600         MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
0601         MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
0602         MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
0603         MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
0604         MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
0605         MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
0606         MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
0607         MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
0608         MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
0609     MPP_MODE(14,
0610         MPP_FUNCTION(0x00, "gpio", NULL),
0611         MPP_FUNCTION(0x02, "uart2", "txd"),
0612         MPP_FUNCTION(0x04, "sdio1", "buspwr"),
0613         MPP_FUNCTION(0x05, "ssp", "rxd"),
0614         MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
0615         MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
0616         MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
0617         MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
0618         MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
0619         MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
0620         MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
0621         MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
0622         MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
0623         MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
0624         MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
0625         MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
0626     MPP_MODE(15,
0627         MPP_FUNCTION(0x00, "gpio", NULL),
0628         MPP_FUNCTION(0x02, "uart2", "rxd"),
0629         MPP_FUNCTION(0x04, "sdio1", "ledctrl"),
0630         MPP_FUNCTION(0x05, "ssp", "sfrm"),
0631         MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL),
0632         MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL),
0633         MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL),
0634         MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"),
0635         MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL),
0636         MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL),
0637         MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL),
0638         MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL),
0639         MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL),
0640         MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL),
0641         MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL),
0642         MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)),
0643     MPP_MODE(16,
0644         MPP_FUNCTION(0x00, "gpio", NULL),
0645         MPP_FUNCTION(0x02, "uart3", "rts"),
0646         MPP_FUNCTION(0x03, "sdio0", "cd"),
0647         MPP_FUNCTION(0x04, "lcd-spi", "cs1"),
0648         MPP_FUNCTION(0x05, "ac97", "sdi1")),
0649     MPP_MODE(17,
0650         MPP_FUNCTION(0x00, "gpio", NULL),
0651         MPP_FUNCTION(0x01, "ac97-1", "sysclko"),
0652         MPP_FUNCTION(0x02, "uart3", "cts"),
0653         MPP_FUNCTION(0x03, "sdio0", "wp"),
0654         MPP_FUNCTION(0x04, "twsi", "sda"),
0655         MPP_FUNCTION(0x05, "ac97", "sdi2")),
0656     MPP_MODE(18,
0657         MPP_FUNCTION(0x00, "gpio", NULL),
0658         MPP_FUNCTION(0x02, "uart3", "txd"),
0659         MPP_FUNCTION(0x03, "sdio0", "buspwr"),
0660         MPP_FUNCTION(0x04, "lcd0", "pwm"),
0661         MPP_FUNCTION(0x05, "ac97", "sdi3")),
0662     MPP_MODE(19,
0663         MPP_FUNCTION(0x00, "gpio", NULL),
0664         MPP_FUNCTION(0x02, "uart3", "rxd"),
0665         MPP_FUNCTION(0x03, "sdio0", "ledctrl"),
0666         MPP_FUNCTION(0x04, "twsi", "sck")),
0667     MPP_MODE(20,
0668         MPP_FUNCTION(0x00, "gpio", NULL),
0669         MPP_FUNCTION(0x01, "ac97", "sysclko"),
0670         MPP_FUNCTION(0x02, "lcd-spi", "miso"),
0671         MPP_FUNCTION(0x03, "sdio1", "cd"),
0672         MPP_FUNCTION(0x05, "sdio0", "cd"),
0673         MPP_FUNCTION(0x06, "spi1", "miso")),
0674     MPP_MODE(21,
0675         MPP_FUNCTION(0x00, "gpio", NULL),
0676         MPP_FUNCTION(0x01, "uart1", "rts"),
0677         MPP_FUNCTION(0x02, "lcd-spi", "cs0"),
0678         MPP_FUNCTION(0x03, "sdio1", "wp"),
0679         MPP_FUNCTION(0x04, "ssp", "sfrm"),
0680         MPP_FUNCTION(0x05, "sdio0", "wp"),
0681         MPP_FUNCTION(0x06, "spi1", "cs")),
0682     MPP_MODE(22,
0683         MPP_FUNCTION(0x00, "gpio", NULL),
0684         MPP_FUNCTION(0x01, "uart1", "cts"),
0685         MPP_FUNCTION(0x02, "lcd-spi", "mosi"),
0686         MPP_FUNCTION(0x03, "sdio1", "buspwr"),
0687         MPP_FUNCTION(0x04, "ssp", "txd"),
0688         MPP_FUNCTION(0x05, "sdio0", "buspwr"),
0689         MPP_FUNCTION(0x06, "spi1", "mosi")),
0690     MPP_MODE(23,
0691         MPP_FUNCTION(0x00, "gpio", NULL),
0692         MPP_FUNCTION(0x02, "lcd-spi", "sck"),
0693         MPP_FUNCTION(0x03, "sdio1", "ledctrl"),
0694         MPP_FUNCTION(0x04, "ssp", "sclk"),
0695         MPP_FUNCTION(0x05, "sdio0", "ledctrl"),
0696         MPP_FUNCTION(0x06, "spi1", "sck")),
0697     MPP_MODE(24,
0698         MPP_FUNCTION(0x00, "camera", NULL),
0699         MPP_FUNCTION(0x01, "gpio", NULL)),
0700     MPP_MODE(40,
0701         MPP_FUNCTION(0x00, "sdio0", NULL),
0702         MPP_FUNCTION(0x01, "gpio", NULL)),
0703     MPP_MODE(46,
0704         MPP_FUNCTION(0x00, "sdio1", NULL),
0705         MPP_FUNCTION(0x01, "gpio", NULL)),
0706     MPP_MODE(52,
0707         MPP_FUNCTION(0x00, "i2s1/spdifo", NULL),
0708         MPP_FUNCTION(0x02, "i2s1", NULL),
0709         MPP_FUNCTION(0x08, "spdifo", NULL),
0710         MPP_FUNCTION(0x0a, "gpio", NULL),
0711         MPP_FUNCTION(0x0b, "twsi", NULL),
0712         MPP_FUNCTION(0x0c, "ssp/spdifo", NULL),
0713         MPP_FUNCTION(0x0e, "ssp", NULL),
0714         MPP_FUNCTION(0x0f, "ssp/twsi", NULL)),
0715     MPP_MODE(58,
0716         MPP_FUNCTION(0x00, "spi0", NULL),
0717         MPP_FUNCTION(0x01, "gpio", NULL)),
0718     MPP_MODE(62,
0719         MPP_FUNCTION(0x00, "uart1", NULL),
0720         MPP_FUNCTION(0x01, "gpio", NULL)),
0721     MPP_MODE(64,
0722         MPP_FUNCTION(0x00, "nand", NULL),
0723         MPP_FUNCTION(0x01, "gpo", NULL)),
0724     MPP_MODE(72,
0725         MPP_FUNCTION(0x00, "i2s", NULL),
0726         MPP_FUNCTION(0x01, "ac97", NULL)),
0727     MPP_MODE(73,
0728         MPP_FUNCTION(0x00, "twsi-none", NULL),
0729         MPP_FUNCTION(0x01, "twsi-opt1", NULL),
0730         MPP_FUNCTION(0x02, "twsi-opt2", NULL),
0731         MPP_FUNCTION(0x03, "twsi-opt3", NULL)),
0732 };
0733 
0734 static struct pinctrl_gpio_range dove_mpp_gpio_ranges[] = {
0735     MPP_GPIO_RANGE(0,  0,  0, 32),
0736     MPP_GPIO_RANGE(1, 32, 32, 32),
0737     MPP_GPIO_RANGE(2, 64, 64,  8),
0738 };
0739 
0740 static struct mvebu_pinctrl_soc_info dove_pinctrl_info = {
0741     .controls = dove_mpp_controls,
0742     .ncontrols = ARRAY_SIZE(dove_mpp_controls),
0743     .modes = dove_mpp_modes,
0744     .nmodes = ARRAY_SIZE(dove_mpp_modes),
0745     .gpioranges = dove_mpp_gpio_ranges,
0746     .ngpioranges = ARRAY_SIZE(dove_mpp_gpio_ranges),
0747     .variant = 0,
0748 };
0749 
0750 static struct clk *clk;
0751 
0752 static const struct of_device_id dove_pinctrl_of_match[] = {
0753     { .compatible = "marvell,dove-pinctrl", .data = &dove_pinctrl_info },
0754     { }
0755 };
0756 
0757 static const struct regmap_config gc_regmap_config = {
0758     .reg_bits = 32,
0759     .val_bits = 32,
0760     .reg_stride = 4,
0761     .max_register = 5,
0762 };
0763 
0764 static int dove_pinctrl_probe(struct platform_device *pdev)
0765 {
0766     struct resource *res, *mpp_res;
0767     struct resource fb_res;
0768     const struct of_device_id *match =
0769         of_match_device(dove_pinctrl_of_match, &pdev->dev);
0770     struct mvebu_mpp_ctrl_data *mpp_data;
0771     void __iomem *base;
0772     int i;
0773 
0774     pdev->dev.platform_data = (void *)match->data;
0775 
0776     /*
0777      * General MPP Configuration Register is part of pdma registers.
0778      * grab clk to make sure it is ticking.
0779      */
0780     clk = devm_clk_get(&pdev->dev, NULL);
0781     if (IS_ERR(clk)) {
0782         dev_err(&pdev->dev, "Unable to get pdma clock");
0783         return PTR_ERR(clk);
0784     }
0785     clk_prepare_enable(clk);
0786 
0787     mpp_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0788     base = devm_ioremap_resource(&pdev->dev, mpp_res);
0789     if (IS_ERR(base))
0790         return PTR_ERR(base);
0791 
0792     mpp_data = devm_kcalloc(&pdev->dev, dove_pinctrl_info.ncontrols,
0793                 sizeof(*mpp_data), GFP_KERNEL);
0794     if (!mpp_data)
0795         return -ENOMEM;
0796 
0797     dove_pinctrl_info.control_data = mpp_data;
0798     for (i = 0; i < ARRAY_SIZE(dove_mpp_controls); i++)
0799         mpp_data[i].base = base;
0800 
0801     /* prepare fallback resource */
0802     memcpy(&fb_res, mpp_res, sizeof(struct resource));
0803     fb_res.start = 0;
0804 
0805     res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
0806     if (!res) {
0807         dev_warn(&pdev->dev, "falling back to hardcoded MPP4 resource\n");
0808         adjust_resource(&fb_res,
0809             (mpp_res->start & INT_REGS_MASK) + MPP4_REGS_OFFS, 0x4);
0810         res = &fb_res;
0811     }
0812 
0813     mpp4_base = devm_ioremap_resource(&pdev->dev, res);
0814     if (IS_ERR(mpp4_base))
0815         return PTR_ERR(mpp4_base);
0816 
0817     res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
0818     if (!res) {
0819         dev_warn(&pdev->dev, "falling back to hardcoded PMU resource\n");
0820         adjust_resource(&fb_res,
0821             (mpp_res->start & INT_REGS_MASK) + PMU_REGS_OFFS, 0x8);
0822         res = &fb_res;
0823     }
0824 
0825     pmu_base = devm_ioremap_resource(&pdev->dev, res);
0826     if (IS_ERR(pmu_base))
0827         return PTR_ERR(pmu_base);
0828 
0829     gconfmap = syscon_regmap_lookup_by_compatible("marvell,dove-global-config");
0830     if (IS_ERR(gconfmap)) {
0831         void __iomem *gc_base;
0832 
0833         dev_warn(&pdev->dev, "falling back to hardcoded global registers\n");
0834         adjust_resource(&fb_res,
0835             (mpp_res->start & INT_REGS_MASK) + GC_REGS_OFFS, 0x14);
0836         gc_base = devm_ioremap_resource(&pdev->dev, &fb_res);
0837         if (IS_ERR(gc_base))
0838             return PTR_ERR(gc_base);
0839         gconfmap = devm_regmap_init_mmio(&pdev->dev,
0840                          gc_base, &gc_regmap_config);
0841         if (IS_ERR(gconfmap))
0842             return PTR_ERR(gconfmap);
0843     }
0844 
0845     /* Warn on any missing DT resource */
0846     if (fb_res.start)
0847         dev_warn(&pdev->dev, FW_BUG "Missing pinctrl regs in DTB. Please update your firmware.\n");
0848 
0849     return mvebu_pinctrl_probe(pdev);
0850 }
0851 
0852 static struct platform_driver dove_pinctrl_driver = {
0853     .driver = {
0854         .name = "dove-pinctrl",
0855         .suppress_bind_attrs = true,
0856         .of_match_table = dove_pinctrl_of_match,
0857     },
0858     .probe = dove_pinctrl_probe,
0859 };
0860 builtin_platform_driver(dove_pinctrl_driver);
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