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0001 /*
0002  * Marvell 37xx SoC pinctrl driver
0003  *
0004  * Copyright (C) 2017 Marvell
0005  *
0006  * Gregory CLEMENT <gregory.clement@free-electrons.com>
0007  *
0008  * This file is licensed under the terms of the GNU General Public
0009  * License version 2 or later. This program is licensed "as is"
0010  * without any warranty of any kind, whether express or implied.
0011  */
0012 
0013 #include <linux/gpio/driver.h>
0014 #include <linux/mfd/syscon.h>
0015 #include <linux/of.h>
0016 #include <linux/of_address.h>
0017 #include <linux/of_device.h>
0018 #include <linux/of_irq.h>
0019 #include <linux/pinctrl/pinconf-generic.h>
0020 #include <linux/pinctrl/pinconf.h>
0021 #include <linux/pinctrl/pinctrl.h>
0022 #include <linux/pinctrl/pinmux.h>
0023 #include <linux/platform_device.h>
0024 #include <linux/property.h>
0025 #include <linux/regmap.h>
0026 #include <linux/slab.h>
0027 #include <linux/string_helpers.h>
0028 
0029 #include "../pinctrl-utils.h"
0030 
0031 #define OUTPUT_EN   0x0
0032 #define INPUT_VAL   0x10
0033 #define OUTPUT_VAL  0x18
0034 #define OUTPUT_CTL  0x20
0035 #define SELECTION   0x30
0036 
0037 #define IRQ_EN      0x0
0038 #define IRQ_POL     0x08
0039 #define IRQ_STATUS  0x10
0040 #define IRQ_WKUP    0x18
0041 
0042 #define NB_FUNCS 3
0043 #define GPIO_PER_REG    32
0044 
0045 /**
0046  * struct armada_37xx_pin_group: represents group of pins of a pinmux function.
0047  * The pins of a pinmux groups are composed of one or two groups of contiguous
0048  * pins.
0049  * @name:   Name of the pin group, used to lookup the group.
0050  * @start_pin:  Index of the first pin of the main range of pins belonging to
0051  *      the group
0052  * @npins:  Number of pins included in the first range
0053  * @reg_mask:   Bit mask matching the group in the selection register
0054  * @val:    Value to write to the registers for a given function
0055  * @extra_pin:  Index of the first pin of the optional second range of pins
0056  *      belonging to the group
0057  * @extra_npins:Number of pins included in the second optional range
0058  * @funcs:  A list of pinmux functions that can be selected for this group.
0059  * @pins:   List of the pins included in the group
0060  */
0061 struct armada_37xx_pin_group {
0062     const char  *name;
0063     unsigned int    start_pin;
0064     unsigned int    npins;
0065     u32     reg_mask;
0066     u32     val[NB_FUNCS];
0067     unsigned int    extra_pin;
0068     unsigned int    extra_npins;
0069     const char  *funcs[NB_FUNCS];
0070     unsigned int    *pins;
0071 };
0072 
0073 struct armada_37xx_pin_data {
0074     u8              nr_pins;
0075     char                *name;
0076     struct armada_37xx_pin_group    *groups;
0077     int             ngroups;
0078 };
0079 
0080 struct armada_37xx_pmx_func {
0081     const char      *name;
0082     const char      **groups;
0083     unsigned int        ngroups;
0084 };
0085 
0086 struct armada_37xx_pm_state {
0087     u32 out_en_l;
0088     u32 out_en_h;
0089     u32 out_val_l;
0090     u32 out_val_h;
0091     u32 irq_en_l;
0092     u32 irq_en_h;
0093     u32 irq_pol_l;
0094     u32 irq_pol_h;
0095     u32 selection;
0096 };
0097 
0098 struct armada_37xx_pinctrl {
0099     struct regmap           *regmap;
0100     void __iomem            *base;
0101     const struct armada_37xx_pin_data   *data;
0102     struct device           *dev;
0103     struct gpio_chip        gpio_chip;
0104     struct irq_chip         irq_chip;
0105     raw_spinlock_t          irq_lock;
0106     struct pinctrl_desc     pctl;
0107     struct pinctrl_dev      *pctl_dev;
0108     struct armada_37xx_pin_group    *groups;
0109     unsigned int            ngroups;
0110     struct armada_37xx_pmx_func *funcs;
0111     unsigned int            nfuncs;
0112     struct armada_37xx_pm_state pm;
0113 };
0114 
0115 #define PIN_GRP(_name, _start, _nr, _mask, _func1, _func2)  \
0116     {                   \
0117         .name = _name,          \
0118         .start_pin = _start,        \
0119         .npins = _nr,           \
0120         .reg_mask = _mask,      \
0121         .val = {0, _mask},      \
0122         .funcs = {_func1, _func2}   \
0123     }
0124 
0125 #define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \
0126     {                   \
0127         .name = _name,          \
0128         .start_pin = _start,        \
0129         .npins = _nr,           \
0130         .reg_mask = _mask,      \
0131         .val = {0, _mask},      \
0132         .funcs = {_func1, "gpio"}   \
0133     }
0134 
0135 #define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1)   \
0136     {                   \
0137         .name = _name,          \
0138         .start_pin = _start,        \
0139         .npins = _nr,           \
0140         .reg_mask = _mask,      \
0141         .val = {_val1, _val2},      \
0142         .funcs = {_func1, "gpio"}   \
0143     }
0144 
0145 #define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \
0146     {                   \
0147         .name = _name,          \
0148         .start_pin = _start,        \
0149         .npins = _nr,           \
0150         .reg_mask = _mask,      \
0151         .val = {_v1, _v2, _v3}, \
0152         .funcs = {_f1, _f2, "gpio"} \
0153     }
0154 
0155 #define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \
0156               _f1, _f2)             \
0157     {                       \
0158         .name = _name,              \
0159         .start_pin = _start,            \
0160         .npins = _nr,               \
0161         .reg_mask = _mask,          \
0162         .val = {_v1, _v2},          \
0163         .extra_pin = _start2,           \
0164         .extra_npins = _nr2,            \
0165         .funcs = {_f1, _f2}         \
0166     }
0167 
0168 static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
0169     PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"),
0170     PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"),
0171     PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"),
0172     PIN_GRP_GPIO_3("pwm0", 11, 1, BIT(3) | BIT(20), 0, BIT(20), BIT(3),
0173                "pwm", "led"),
0174     PIN_GRP_GPIO_3("pwm1", 12, 1, BIT(4) | BIT(21), 0, BIT(21), BIT(4),
0175                "pwm", "led"),
0176     PIN_GRP_GPIO_3("pwm2", 13, 1, BIT(5) | BIT(22), 0, BIT(22), BIT(5),
0177                "pwm", "led"),
0178     PIN_GRP_GPIO_3("pwm3", 14, 1, BIT(6) | BIT(23), 0, BIT(23), BIT(6),
0179                "pwm", "led"),
0180     PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"),
0181     PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"),
0182     PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
0183     PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"),
0184     PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"),
0185     PIN_GRP_GPIO_2("spi_cs2", 18, 1, BIT(13) | BIT(19), 0, BIT(13), "spi"),
0186     PIN_GRP_GPIO_2("spi_cs3", 19, 1, BIT(14) | BIT(19), 0, BIT(14), "spi"),
0187     PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"),
0188     PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"),
0189     PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"),
0190     PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19),
0191               BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19),
0192               18, 2, "gpio", "uart"),
0193 };
0194 
0195 static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
0196     PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"),
0197     PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
0198     PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
0199     PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"),
0200     PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"),
0201     PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"), /* this actually controls "pcie1_reset" */
0202     PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"),
0203     PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"),
0204     PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"),
0205     PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"),
0206     PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"),
0207     PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14),
0208                "mii", "mii_err"),
0209 };
0210 
0211 static const struct armada_37xx_pin_data armada_37xx_pin_nb = {
0212     .nr_pins = 36,
0213     .name = "GPIO1",
0214     .groups = armada_37xx_nb_groups,
0215     .ngroups = ARRAY_SIZE(armada_37xx_nb_groups),
0216 };
0217 
0218 static const struct armada_37xx_pin_data armada_37xx_pin_sb = {
0219     .nr_pins = 30,
0220     .name = "GPIO2",
0221     .groups = armada_37xx_sb_groups,
0222     .ngroups = ARRAY_SIZE(armada_37xx_sb_groups),
0223 };
0224 
0225 static inline void armada_37xx_update_reg(unsigned int *reg,
0226                       unsigned int *offset)
0227 {
0228     /* We never have more than 2 registers */
0229     if (*offset >= GPIO_PER_REG) {
0230         *offset -= GPIO_PER_REG;
0231         *reg += sizeof(u32);
0232     }
0233 }
0234 
0235 static struct armada_37xx_pin_group *armada_37xx_find_next_grp_by_pin(
0236     struct armada_37xx_pinctrl *info, int pin, int *grp)
0237 {
0238     while (*grp < info->ngroups) {
0239         struct armada_37xx_pin_group *group = &info->groups[*grp];
0240         int j;
0241 
0242         *grp = *grp + 1;
0243         for (j = 0; j < (group->npins + group->extra_npins); j++)
0244             if (group->pins[j] == pin)
0245                 return group;
0246     }
0247     return NULL;
0248 }
0249 
0250 static int armada_37xx_pin_config_group_get(struct pinctrl_dev *pctldev,
0251                 unsigned int selector, unsigned long *config)
0252 {
0253     return -ENOTSUPP;
0254 }
0255 
0256 static int armada_37xx_pin_config_group_set(struct pinctrl_dev *pctldev,
0257                 unsigned int selector, unsigned long *configs,
0258                 unsigned int num_configs)
0259 {
0260     return -ENOTSUPP;
0261 }
0262 
0263 static const struct pinconf_ops armada_37xx_pinconf_ops = {
0264     .is_generic = true,
0265     .pin_config_group_get = armada_37xx_pin_config_group_get,
0266     .pin_config_group_set = armada_37xx_pin_config_group_set,
0267 };
0268 
0269 static int armada_37xx_get_groups_count(struct pinctrl_dev *pctldev)
0270 {
0271     struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
0272 
0273     return info->ngroups;
0274 }
0275 
0276 static const char *armada_37xx_get_group_name(struct pinctrl_dev *pctldev,
0277                           unsigned int group)
0278 {
0279     struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
0280 
0281     return info->groups[group].name;
0282 }
0283 
0284 static int armada_37xx_get_group_pins(struct pinctrl_dev *pctldev,
0285                       unsigned int selector,
0286                       const unsigned int **pins,
0287                       unsigned int *npins)
0288 {
0289     struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
0290 
0291     if (selector >= info->ngroups)
0292         return -EINVAL;
0293 
0294     *pins = info->groups[selector].pins;
0295     *npins = info->groups[selector].npins +
0296         info->groups[selector].extra_npins;
0297 
0298     return 0;
0299 }
0300 
0301 static const struct pinctrl_ops armada_37xx_pctrl_ops = {
0302     .get_groups_count   = armada_37xx_get_groups_count,
0303     .get_group_name     = armada_37xx_get_group_name,
0304     .get_group_pins     = armada_37xx_get_group_pins,
0305     .dt_node_to_map     = pinconf_generic_dt_node_to_map_group,
0306     .dt_free_map        = pinctrl_utils_free_map,
0307 };
0308 
0309 /*
0310  * Pinmux_ops handling
0311  */
0312 
0313 static int armada_37xx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
0314 {
0315     struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
0316 
0317     return info->nfuncs;
0318 }
0319 
0320 static const char *armada_37xx_pmx_get_func_name(struct pinctrl_dev *pctldev,
0321                          unsigned int selector)
0322 {
0323     struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
0324 
0325     return info->funcs[selector].name;
0326 }
0327 
0328 static int armada_37xx_pmx_get_groups(struct pinctrl_dev *pctldev,
0329                       unsigned int selector,
0330                       const char * const **groups,
0331                       unsigned int * const num_groups)
0332 {
0333     struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
0334 
0335     *groups = info->funcs[selector].groups;
0336     *num_groups = info->funcs[selector].ngroups;
0337 
0338     return 0;
0339 }
0340 
0341 static int armada_37xx_pmx_set_by_name(struct pinctrl_dev *pctldev,
0342                        const char *name,
0343                        struct armada_37xx_pin_group *grp)
0344 {
0345     struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
0346     struct device *dev = info->dev;
0347     unsigned int reg = SELECTION;
0348     unsigned int mask = grp->reg_mask;
0349     int func, val;
0350 
0351     dev_dbg(dev, "enable function %s group %s\n", name, grp->name);
0352 
0353     func = match_string(grp->funcs, NB_FUNCS, name);
0354     if (func < 0)
0355         return -ENOTSUPP;
0356 
0357     val = grp->val[func];
0358 
0359     regmap_update_bits(info->regmap, reg, mask, val);
0360 
0361     return 0;
0362 }
0363 
0364 static int armada_37xx_pmx_set(struct pinctrl_dev *pctldev,
0365                    unsigned int selector,
0366                    unsigned int group)
0367 {
0368 
0369     struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
0370     struct armada_37xx_pin_group *grp = &info->groups[group];
0371     const char *name = info->funcs[selector].name;
0372 
0373     return armada_37xx_pmx_set_by_name(pctldev, name, grp);
0374 }
0375 
0376 static inline void armada_37xx_irq_update_reg(unsigned int *reg,
0377                       struct irq_data *d)
0378 {
0379     int offset = irqd_to_hwirq(d);
0380 
0381     armada_37xx_update_reg(reg, &offset);
0382 }
0383 
0384 static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
0385                         unsigned int offset)
0386 {
0387     struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
0388     unsigned int reg = OUTPUT_EN;
0389     unsigned int mask;
0390 
0391     armada_37xx_update_reg(&reg, &offset);
0392     mask = BIT(offset);
0393 
0394     return regmap_update_bits(info->regmap, reg, mask, 0);
0395 }
0396 
0397 static int armada_37xx_gpio_get_direction(struct gpio_chip *chip,
0398                       unsigned int offset)
0399 {
0400     struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
0401     unsigned int reg = OUTPUT_EN;
0402     unsigned int val, mask;
0403 
0404     armada_37xx_update_reg(&reg, &offset);
0405     mask = BIT(offset);
0406     regmap_read(info->regmap, reg, &val);
0407 
0408     if (val & mask)
0409         return GPIO_LINE_DIRECTION_OUT;
0410 
0411     return GPIO_LINE_DIRECTION_IN;
0412 }
0413 
0414 static int armada_37xx_gpio_direction_output(struct gpio_chip *chip,
0415                          unsigned int offset, int value)
0416 {
0417     struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
0418     unsigned int reg = OUTPUT_EN;
0419     unsigned int mask, val, ret;
0420 
0421     armada_37xx_update_reg(&reg, &offset);
0422     mask = BIT(offset);
0423 
0424     ret = regmap_update_bits(info->regmap, reg, mask, mask);
0425 
0426     if (ret)
0427         return ret;
0428 
0429     reg = OUTPUT_VAL;
0430     val = value ? mask : 0;
0431     regmap_update_bits(info->regmap, reg, mask, val);
0432 
0433     return 0;
0434 }
0435 
0436 static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset)
0437 {
0438     struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
0439     unsigned int reg = INPUT_VAL;
0440     unsigned int val, mask;
0441 
0442     armada_37xx_update_reg(&reg, &offset);
0443     mask = BIT(offset);
0444 
0445     regmap_read(info->regmap, reg, &val);
0446 
0447     return (val & mask) != 0;
0448 }
0449 
0450 static void armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset,
0451                  int value)
0452 {
0453     struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
0454     unsigned int reg = OUTPUT_VAL;
0455     unsigned int mask, val;
0456 
0457     armada_37xx_update_reg(&reg, &offset);
0458     mask = BIT(offset);
0459     val = value ? mask : 0;
0460 
0461     regmap_update_bits(info->regmap, reg, mask, val);
0462 }
0463 
0464 static int armada_37xx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
0465                           struct pinctrl_gpio_range *range,
0466                           unsigned int offset, bool input)
0467 {
0468     struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
0469     struct gpio_chip *chip = range->gc;
0470 
0471     dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
0472         offset, range->name, offset, input ? "input" : "output");
0473 
0474     if (input)
0475         armada_37xx_gpio_direction_input(chip, offset);
0476     else
0477         armada_37xx_gpio_direction_output(chip, offset, 0);
0478 
0479     return 0;
0480 }
0481 
0482 static int armada_37xx_gpio_request_enable(struct pinctrl_dev *pctldev,
0483                        struct pinctrl_gpio_range *range,
0484                        unsigned int offset)
0485 {
0486     struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
0487     struct armada_37xx_pin_group *group;
0488     int grp = 0;
0489 
0490     dev_dbg(info->dev, "requesting gpio %d\n", offset);
0491 
0492     while ((group = armada_37xx_find_next_grp_by_pin(info, offset, &grp)))
0493         armada_37xx_pmx_set_by_name(pctldev, "gpio", group);
0494 
0495     return 0;
0496 }
0497 
0498 static const struct pinmux_ops armada_37xx_pmx_ops = {
0499     .get_functions_count    = armada_37xx_pmx_get_funcs_count,
0500     .get_function_name  = armada_37xx_pmx_get_func_name,
0501     .get_function_groups    = armada_37xx_pmx_get_groups,
0502     .set_mux        = armada_37xx_pmx_set,
0503     .gpio_request_enable    = armada_37xx_gpio_request_enable,
0504     .gpio_set_direction = armada_37xx_pmx_gpio_set_direction,
0505 };
0506 
0507 static const struct gpio_chip armada_37xx_gpiolib_chip = {
0508     .request = gpiochip_generic_request,
0509     .free = gpiochip_generic_free,
0510     .set = armada_37xx_gpio_set,
0511     .get = armada_37xx_gpio_get,
0512     .get_direction  = armada_37xx_gpio_get_direction,
0513     .direction_input = armada_37xx_gpio_direction_input,
0514     .direction_output = armada_37xx_gpio_direction_output,
0515     .owner = THIS_MODULE,
0516 };
0517 
0518 static void armada_37xx_irq_ack(struct irq_data *d)
0519 {
0520     struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
0521     struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
0522     u32 reg = IRQ_STATUS;
0523     unsigned long flags;
0524 
0525     armada_37xx_irq_update_reg(&reg, d);
0526     raw_spin_lock_irqsave(&info->irq_lock, flags);
0527     writel(d->mask, info->base + reg);
0528     raw_spin_unlock_irqrestore(&info->irq_lock, flags);
0529 }
0530 
0531 static void armada_37xx_irq_mask(struct irq_data *d)
0532 {
0533     struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
0534     struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
0535     u32 val, reg = IRQ_EN;
0536     unsigned long flags;
0537 
0538     armada_37xx_irq_update_reg(&reg, d);
0539     raw_spin_lock_irqsave(&info->irq_lock, flags);
0540     val = readl(info->base + reg);
0541     writel(val & ~d->mask, info->base + reg);
0542     raw_spin_unlock_irqrestore(&info->irq_lock, flags);
0543 }
0544 
0545 static void armada_37xx_irq_unmask(struct irq_data *d)
0546 {
0547     struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
0548     struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
0549     u32 val, reg = IRQ_EN;
0550     unsigned long flags;
0551 
0552     armada_37xx_irq_update_reg(&reg, d);
0553     raw_spin_lock_irqsave(&info->irq_lock, flags);
0554     val = readl(info->base + reg);
0555     writel(val | d->mask, info->base + reg);
0556     raw_spin_unlock_irqrestore(&info->irq_lock, flags);
0557 }
0558 
0559 static int armada_37xx_irq_set_wake(struct irq_data *d, unsigned int on)
0560 {
0561     struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
0562     struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
0563     u32 val, reg = IRQ_WKUP;
0564     unsigned long flags;
0565 
0566     armada_37xx_irq_update_reg(&reg, d);
0567     raw_spin_lock_irqsave(&info->irq_lock, flags);
0568     val = readl(info->base + reg);
0569     if (on)
0570         val |= (BIT(d->hwirq % GPIO_PER_REG));
0571     else
0572         val &= ~(BIT(d->hwirq % GPIO_PER_REG));
0573     writel(val, info->base + reg);
0574     raw_spin_unlock_irqrestore(&info->irq_lock, flags);
0575 
0576     return 0;
0577 }
0578 
0579 static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type)
0580 {
0581     struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
0582     struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
0583     u32 val, reg = IRQ_POL;
0584     unsigned long flags;
0585 
0586     raw_spin_lock_irqsave(&info->irq_lock, flags);
0587     armada_37xx_irq_update_reg(&reg, d);
0588     val = readl(info->base + reg);
0589     switch (type) {
0590     case IRQ_TYPE_EDGE_RISING:
0591         val &= ~(BIT(d->hwirq % GPIO_PER_REG));
0592         break;
0593     case IRQ_TYPE_EDGE_FALLING:
0594         val |= (BIT(d->hwirq % GPIO_PER_REG));
0595         break;
0596     case IRQ_TYPE_EDGE_BOTH: {
0597         u32 in_val, in_reg = INPUT_VAL;
0598 
0599         armada_37xx_irq_update_reg(&in_reg, d);
0600         regmap_read(info->regmap, in_reg, &in_val);
0601 
0602         /* Set initial polarity based on current input level. */
0603         if (in_val & BIT(d->hwirq % GPIO_PER_REG))
0604             val |= BIT(d->hwirq % GPIO_PER_REG);    /* falling */
0605         else
0606             val &= ~(BIT(d->hwirq % GPIO_PER_REG)); /* rising */
0607         break;
0608     }
0609     default:
0610         raw_spin_unlock_irqrestore(&info->irq_lock, flags);
0611         return -EINVAL;
0612     }
0613     writel(val, info->base + reg);
0614     raw_spin_unlock_irqrestore(&info->irq_lock, flags);
0615 
0616     return 0;
0617 }
0618 
0619 static int armada_37xx_edge_both_irq_swap_pol(struct armada_37xx_pinctrl *info,
0620                          u32 pin_idx)
0621 {
0622     u32 reg_idx = pin_idx / GPIO_PER_REG;
0623     u32 bit_num = pin_idx % GPIO_PER_REG;
0624     u32 p, l, ret;
0625     unsigned long flags;
0626 
0627     regmap_read(info->regmap, INPUT_VAL + 4*reg_idx, &l);
0628 
0629     raw_spin_lock_irqsave(&info->irq_lock, flags);
0630     p = readl(info->base + IRQ_POL + 4 * reg_idx);
0631     if ((p ^ l) & (1 << bit_num)) {
0632         /*
0633          * For the gpios which are used for both-edge irqs, when their
0634          * interrupts happen, their input levels are changed,
0635          * yet their interrupt polarities are kept in old values, we
0636          * should synchronize their interrupt polarities; for example,
0637          * at first a gpio's input level is low and its interrupt
0638          * polarity control is "Detect rising edge", then the gpio has
0639          * a interrupt , its level turns to high, we should change its
0640          * polarity control to "Detect falling edge" correspondingly.
0641          */
0642         p ^= 1 << bit_num;
0643         writel(p, info->base + IRQ_POL + 4 * reg_idx);
0644         ret = 0;
0645     } else {
0646         /* Spurious irq */
0647         ret = -1;
0648     }
0649 
0650     raw_spin_unlock_irqrestore(&info->irq_lock, flags);
0651     return ret;
0652 }
0653 
0654 static void armada_37xx_irq_handler(struct irq_desc *desc)
0655 {
0656     struct gpio_chip *gc = irq_desc_get_handler_data(desc);
0657     struct irq_chip *chip = irq_desc_get_chip(desc);
0658     struct armada_37xx_pinctrl *info = gpiochip_get_data(gc);
0659     struct irq_domain *d = gc->irq.domain;
0660     int i;
0661 
0662     chained_irq_enter(chip, desc);
0663     for (i = 0; i <= d->revmap_size / GPIO_PER_REG; i++) {
0664         u32 status;
0665         unsigned long flags;
0666 
0667         raw_spin_lock_irqsave(&info->irq_lock, flags);
0668         status = readl_relaxed(info->base + IRQ_STATUS + 4 * i);
0669         /* Manage only the interrupt that was enabled */
0670         status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
0671         raw_spin_unlock_irqrestore(&info->irq_lock, flags);
0672         while (status) {
0673             u32 hwirq = ffs(status) - 1;
0674             u32 virq = irq_find_mapping(d, hwirq +
0675                              i * GPIO_PER_REG);
0676             u32 t = irq_get_trigger_type(virq);
0677 
0678             if ((t & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
0679                 /* Swap polarity (race with GPIO line) */
0680                 if (armada_37xx_edge_both_irq_swap_pol(info,
0681                     hwirq + i * GPIO_PER_REG)) {
0682                     /*
0683                      * For spurious irq, which gpio level
0684                      * is not as expected after incoming
0685                      * edge, just ack the gpio irq.
0686                      */
0687                     writel(1 << hwirq,
0688                            info->base +
0689                            IRQ_STATUS + 4 * i);
0690                     goto update_status;
0691                 }
0692             }
0693 
0694             generic_handle_irq(virq);
0695 
0696 update_status:
0697             /* Update status in case a new IRQ appears */
0698             raw_spin_lock_irqsave(&info->irq_lock, flags);
0699             status = readl_relaxed(info->base +
0700                            IRQ_STATUS + 4 * i);
0701             /* Manage only the interrupt that was enabled */
0702             status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
0703             raw_spin_unlock_irqrestore(&info->irq_lock, flags);
0704         }
0705     }
0706     chained_irq_exit(chip, desc);
0707 }
0708 
0709 static unsigned int armada_37xx_irq_startup(struct irq_data *d)
0710 {
0711     /*
0712      * The mask field is a "precomputed bitmask for accessing the
0713      * chip registers" which was introduced for the generic
0714      * irqchip framework. As we don't use this framework, we can
0715      * reuse this field for our own usage.
0716      */
0717     d->mask = BIT(d->hwirq % GPIO_PER_REG);
0718 
0719     armada_37xx_irq_unmask(d);
0720 
0721     return 0;
0722 }
0723 
0724 static int armada_37xx_irqchip_register(struct platform_device *pdev,
0725                     struct armada_37xx_pinctrl *info)
0726 {
0727     struct gpio_chip *gc = &info->gpio_chip;
0728     struct irq_chip *irqchip = &info->irq_chip;
0729     struct gpio_irq_chip *girq = &gc->irq;
0730     struct device_node *np = to_of_node(gc->fwnode);
0731     struct device *dev = &pdev->dev;
0732     unsigned int i, nr_irq_parent;
0733 
0734     raw_spin_lock_init(&info->irq_lock);
0735 
0736     nr_irq_parent = of_irq_count(np);
0737     if (!nr_irq_parent) {
0738         dev_err(dev, "invalid or no IRQ\n");
0739         return 0;
0740     }
0741 
0742     info->base = devm_platform_ioremap_resource(pdev, 1);
0743     if (IS_ERR(info->base))
0744         return PTR_ERR(info->base);
0745 
0746     irqchip->irq_ack = armada_37xx_irq_ack;
0747     irqchip->irq_mask = armada_37xx_irq_mask;
0748     irqchip->irq_unmask = armada_37xx_irq_unmask;
0749     irqchip->irq_set_wake = armada_37xx_irq_set_wake;
0750     irqchip->irq_set_type = armada_37xx_irq_set_type;
0751     irqchip->irq_startup = armada_37xx_irq_startup;
0752     irqchip->name = info->data->name;
0753     girq->chip = irqchip;
0754     girq->parent_handler = armada_37xx_irq_handler;
0755     /*
0756      * Many interrupts are connected to the parent interrupt
0757      * controller. But we do not take advantage of this and use
0758      * the chained irq with all of them.
0759      */
0760     girq->num_parents = nr_irq_parent;
0761     girq->parents = devm_kcalloc(dev, nr_irq_parent, sizeof(*girq->parents), GFP_KERNEL);
0762     if (!girq->parents)
0763         return -ENOMEM;
0764     for (i = 0; i < nr_irq_parent; i++) {
0765         int irq = irq_of_parse_and_map(np, i);
0766 
0767         if (!irq)
0768             continue;
0769         girq->parents[i] = irq;
0770     }
0771     girq->default_type = IRQ_TYPE_NONE;
0772     girq->handler = handle_edge_irq;
0773 
0774     return 0;
0775 }
0776 
0777 static int armada_37xx_gpiochip_register(struct platform_device *pdev,
0778                     struct armada_37xx_pinctrl *info)
0779 {
0780     struct device *dev = &pdev->dev;
0781     struct fwnode_handle *fwnode;
0782     struct gpio_chip *gc;
0783     int ret;
0784 
0785     fwnode = gpiochip_node_get_first(dev);
0786     if (!fwnode)
0787         return -ENODEV;
0788 
0789     info->gpio_chip = armada_37xx_gpiolib_chip;
0790 
0791     gc = &info->gpio_chip;
0792     gc->ngpio = info->data->nr_pins;
0793     gc->parent = dev;
0794     gc->base = -1;
0795     gc->fwnode = fwnode;
0796     gc->label = info->data->name;
0797 
0798     ret = armada_37xx_irqchip_register(pdev, info);
0799     if (ret)
0800         return ret;
0801 
0802     return devm_gpiochip_add_data(dev, gc, info);
0803 }
0804 
0805 /**
0806  * armada_37xx_add_function() - Add a new function to the list
0807  * @funcs: array of function to add the new one
0808  * @funcsize: size of the remaining space for the function
0809  * @name: name of the function to add
0810  *
0811  * If it is a new function then create it by adding its name else
0812  * increment the number of group associated to this function.
0813  */
0814 static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs,
0815                     int *funcsize, const char *name)
0816 {
0817     int i = 0;
0818 
0819     if (*funcsize <= 0)
0820         return -EOVERFLOW;
0821 
0822     while (funcs->ngroups) {
0823         /* function already there */
0824         if (strcmp(funcs->name, name) == 0) {
0825             funcs->ngroups++;
0826 
0827             return -EEXIST;
0828         }
0829         funcs++;
0830         i++;
0831     }
0832 
0833     /* append new unique function */
0834     funcs->name = name;
0835     funcs->ngroups = 1;
0836     (*funcsize)--;
0837 
0838     return 0;
0839 }
0840 
0841 /**
0842  * armada_37xx_fill_group() - complete the group array
0843  * @info: info driver instance
0844  *
0845  * Based on the data available from the armada_37xx_pin_group array
0846  * completes the last member of the struct for each function: the list
0847  * of the groups associated to this function.
0848  *
0849  */
0850 static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info)
0851 {
0852     int n, num = 0, funcsize = info->data->nr_pins;
0853     struct device *dev = info->dev;
0854 
0855     for (n = 0; n < info->ngroups; n++) {
0856         struct armada_37xx_pin_group *grp = &info->groups[n];
0857         int i, j, f;
0858 
0859         grp->pins = devm_kcalloc(dev, grp->npins + grp->extra_npins,
0860                      sizeof(*grp->pins),
0861                      GFP_KERNEL);
0862         if (!grp->pins)
0863             return -ENOMEM;
0864 
0865         for (i = 0; i < grp->npins; i++)
0866             grp->pins[i] = grp->start_pin + i;
0867 
0868         for (j = 0; j < grp->extra_npins; j++)
0869             grp->pins[i+j] = grp->extra_pin + j;
0870 
0871         for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) {
0872             int ret;
0873             /* check for unique functions and count groups */
0874             ret = armada_37xx_add_function(info->funcs, &funcsize,
0875                         grp->funcs[f]);
0876             if (ret == -EOVERFLOW)
0877                 dev_err(dev, "More functions than pins(%d)\n",
0878                     info->data->nr_pins);
0879             if (ret < 0)
0880                 continue;
0881             num++;
0882         }
0883     }
0884 
0885     info->nfuncs = num;
0886 
0887     return 0;
0888 }
0889 
0890 /**
0891  * armada_37xx_fill_func() - complete the funcs array
0892  * @info: info driver instance
0893  *
0894  * Based on the data available from the armada_37xx_pin_group array
0895  * completes the last two member of the struct for each group:
0896  * - the list of the pins included in the group
0897  * - the list of pinmux functions that can be selected for this group
0898  *
0899  */
0900 static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info)
0901 {
0902     struct armada_37xx_pmx_func *funcs = info->funcs;
0903     struct device *dev = info->dev;
0904     int n;
0905 
0906     for (n = 0; n < info->nfuncs; n++) {
0907         const char *name = funcs[n].name;
0908         const char **groups;
0909         int g;
0910 
0911         funcs[n].groups = devm_kcalloc(dev, funcs[n].ngroups,
0912                            sizeof(*(funcs[n].groups)),
0913                            GFP_KERNEL);
0914         if (!funcs[n].groups)
0915             return -ENOMEM;
0916 
0917         groups = funcs[n].groups;
0918 
0919         for (g = 0; g < info->ngroups; g++) {
0920             struct armada_37xx_pin_group *gp = &info->groups[g];
0921             int f;
0922 
0923             f = match_string(gp->funcs, NB_FUNCS, name);
0924             if (f < 0)
0925                 continue;
0926 
0927             *groups = gp->name;
0928             groups++;
0929         }
0930     }
0931     return 0;
0932 }
0933 
0934 static int armada_37xx_pinctrl_register(struct platform_device *pdev,
0935                     struct armada_37xx_pinctrl *info)
0936 {
0937     const struct armada_37xx_pin_data *pin_data = info->data;
0938     struct pinctrl_desc *ctrldesc = &info->pctl;
0939     struct pinctrl_pin_desc *pindesc, *pdesc;
0940     struct device *dev = &pdev->dev;
0941     char **pin_names;
0942     int pin, ret;
0943 
0944     info->groups = pin_data->groups;
0945     info->ngroups = pin_data->ngroups;
0946 
0947     ctrldesc->name = "armada_37xx-pinctrl";
0948     ctrldesc->owner = THIS_MODULE;
0949     ctrldesc->pctlops = &armada_37xx_pctrl_ops;
0950     ctrldesc->pmxops = &armada_37xx_pmx_ops;
0951     ctrldesc->confops = &armada_37xx_pinconf_ops;
0952 
0953     pindesc = devm_kcalloc(dev, pin_data->nr_pins, sizeof(*pindesc), GFP_KERNEL);
0954     if (!pindesc)
0955         return -ENOMEM;
0956 
0957     ctrldesc->pins = pindesc;
0958     ctrldesc->npins = pin_data->nr_pins;
0959 
0960     pin_names = devm_kasprintf_strarray(dev, pin_data->name, pin_data->nr_pins);
0961     if (IS_ERR(pin_names))
0962         return PTR_ERR(pin_names);
0963 
0964     pdesc = pindesc;
0965     for (pin = 0; pin < pin_data->nr_pins; pin++) {
0966         pdesc->number = pin;
0967         pdesc->name = pin_names[pin];
0968         pdesc++;
0969     }
0970 
0971     /*
0972      * we allocate functions for number of pins and hope there are
0973      * fewer unique functions than pins available
0974      */
0975     info->funcs = devm_kcalloc(dev, pin_data->nr_pins, sizeof(*info->funcs), GFP_KERNEL);
0976     if (!info->funcs)
0977         return -ENOMEM;
0978 
0979     ret = armada_37xx_fill_group(info);
0980     if (ret)
0981         return ret;
0982 
0983     ret = armada_37xx_fill_func(info);
0984     if (ret)
0985         return ret;
0986 
0987     info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info);
0988     if (IS_ERR(info->pctl_dev))
0989         return dev_err_probe(dev, PTR_ERR(info->pctl_dev), "could not register pinctrl driver\n");
0990 
0991     return 0;
0992 }
0993 
0994 #if defined(CONFIG_PM)
0995 static int armada_3700_pinctrl_suspend(struct device *dev)
0996 {
0997     struct armada_37xx_pinctrl *info = dev_get_drvdata(dev);
0998 
0999     /* Save GPIO state */
1000     regmap_read(info->regmap, OUTPUT_EN, &info->pm.out_en_l);
1001     regmap_read(info->regmap, OUTPUT_EN + sizeof(u32), &info->pm.out_en_h);
1002     regmap_read(info->regmap, OUTPUT_VAL, &info->pm.out_val_l);
1003     regmap_read(info->regmap, OUTPUT_VAL + sizeof(u32),
1004             &info->pm.out_val_h);
1005 
1006     info->pm.irq_en_l = readl(info->base + IRQ_EN);
1007     info->pm.irq_en_h = readl(info->base + IRQ_EN + sizeof(u32));
1008     info->pm.irq_pol_l = readl(info->base + IRQ_POL);
1009     info->pm.irq_pol_h = readl(info->base + IRQ_POL + sizeof(u32));
1010 
1011     /* Save pinctrl state */
1012     regmap_read(info->regmap, SELECTION, &info->pm.selection);
1013 
1014     return 0;
1015 }
1016 
1017 static int armada_3700_pinctrl_resume(struct device *dev)
1018 {
1019     struct armada_37xx_pinctrl *info = dev_get_drvdata(dev);
1020     struct gpio_chip *gc;
1021     struct irq_domain *d;
1022     int i;
1023 
1024     /* Restore GPIO state */
1025     regmap_write(info->regmap, OUTPUT_EN, info->pm.out_en_l);
1026     regmap_write(info->regmap, OUTPUT_EN + sizeof(u32),
1027              info->pm.out_en_h);
1028     regmap_write(info->regmap, OUTPUT_VAL, info->pm.out_val_l);
1029     regmap_write(info->regmap, OUTPUT_VAL + sizeof(u32),
1030              info->pm.out_val_h);
1031 
1032     /*
1033      * Input levels may change during suspend, which is not monitored at
1034      * that time. GPIOs used for both-edge IRQs may not be synchronized
1035      * anymore with their polarities (rising/falling edge) and must be
1036      * re-configured manually.
1037      */
1038     gc = &info->gpio_chip;
1039     d = gc->irq.domain;
1040     for (i = 0; i < gc->ngpio; i++) {
1041         u32 irq_bit = BIT(i % GPIO_PER_REG);
1042         u32 mask, *irq_pol, input_reg, virq, type, level;
1043 
1044         if (i < GPIO_PER_REG) {
1045             mask = info->pm.irq_en_l;
1046             irq_pol = &info->pm.irq_pol_l;
1047             input_reg = INPUT_VAL;
1048         } else {
1049             mask = info->pm.irq_en_h;
1050             irq_pol = &info->pm.irq_pol_h;
1051             input_reg = INPUT_VAL + sizeof(u32);
1052         }
1053 
1054         if (!(mask & irq_bit))
1055             continue;
1056 
1057         virq = irq_find_mapping(d, i);
1058         type = irq_get_trigger_type(virq);
1059 
1060         /*
1061          * Synchronize level and polarity for both-edge irqs:
1062          *     - a high input level expects a falling edge,
1063          *     - a low input level exepects a rising edge.
1064          */
1065         if ((type & IRQ_TYPE_SENSE_MASK) ==
1066             IRQ_TYPE_EDGE_BOTH) {
1067             regmap_read(info->regmap, input_reg, &level);
1068             if ((*irq_pol ^ level) & irq_bit)
1069                 *irq_pol ^= irq_bit;
1070         }
1071     }
1072 
1073     writel(info->pm.irq_en_l, info->base + IRQ_EN);
1074     writel(info->pm.irq_en_h, info->base + IRQ_EN + sizeof(u32));
1075     writel(info->pm.irq_pol_l, info->base + IRQ_POL);
1076     writel(info->pm.irq_pol_h, info->base + IRQ_POL + sizeof(u32));
1077 
1078     /* Restore pinctrl state */
1079     regmap_write(info->regmap, SELECTION, info->pm.selection);
1080 
1081     return 0;
1082 }
1083 
1084 /*
1085  * Since pinctrl is an infrastructure module, its resume should be issued prior
1086  * to other IO drivers.
1087  */
1088 static const struct dev_pm_ops armada_3700_pinctrl_pm_ops = {
1089     .suspend_noirq = armada_3700_pinctrl_suspend,
1090     .resume_noirq = armada_3700_pinctrl_resume,
1091 };
1092 
1093 #define PINCTRL_ARMADA_37XX_DEV_PM_OPS (&armada_3700_pinctrl_pm_ops)
1094 #else
1095 #define PINCTRL_ARMADA_37XX_DEV_PM_OPS NULL
1096 #endif /* CONFIG_PM */
1097 
1098 static const struct of_device_id armada_37xx_pinctrl_of_match[] = {
1099     {
1100         .compatible = "marvell,armada3710-sb-pinctrl",
1101         .data = &armada_37xx_pin_sb,
1102     },
1103     {
1104         .compatible = "marvell,armada3710-nb-pinctrl",
1105         .data = &armada_37xx_pin_nb,
1106     },
1107     { },
1108 };
1109 
1110 static const struct regmap_config armada_37xx_pinctrl_regmap_config = {
1111     .reg_bits = 32,
1112     .val_bits = 32,
1113     .reg_stride = 4,
1114     .use_raw_spinlock = true,
1115 };
1116 
1117 static int __init armada_37xx_pinctrl_probe(struct platform_device *pdev)
1118 {
1119     struct armada_37xx_pinctrl *info;
1120     struct device *dev = &pdev->dev;
1121     struct regmap *regmap;
1122     void __iomem *base;
1123     int ret;
1124 
1125     base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
1126     if (IS_ERR(base)) {
1127         dev_err(dev, "failed to ioremap base address: %pe\n", base);
1128         return PTR_ERR(base);
1129     }
1130 
1131     regmap = devm_regmap_init_mmio(dev, base,
1132                        &armada_37xx_pinctrl_regmap_config);
1133     if (IS_ERR(regmap)) {
1134         dev_err(dev, "failed to create regmap: %pe\n", regmap);
1135         return PTR_ERR(regmap);
1136     }
1137 
1138     info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
1139     if (!info)
1140         return -ENOMEM;
1141 
1142     info->dev = dev;
1143     info->regmap = regmap;
1144     info->data = of_device_get_match_data(dev);
1145 
1146     ret = armada_37xx_pinctrl_register(pdev, info);
1147     if (ret)
1148         return ret;
1149 
1150     ret = armada_37xx_gpiochip_register(pdev, info);
1151     if (ret)
1152         return ret;
1153 
1154     platform_set_drvdata(pdev, info);
1155 
1156     return 0;
1157 }
1158 
1159 static struct platform_driver armada_37xx_pinctrl_driver = {
1160     .driver = {
1161         .name = "armada-37xx-pinctrl",
1162         .of_match_table = armada_37xx_pinctrl_of_match,
1163         .pm = PINCTRL_ARMADA_37XX_DEV_PM_OPS,
1164     },
1165 };
1166 
1167 builtin_platform_driver_probe(armada_37xx_pinctrl_driver,
1168                   armada_37xx_pinctrl_probe);
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