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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Pin controller and GPIO driver for Amlogic Meson SoCs
0004  *
0005  * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
0006  */
0007 
0008 /*
0009  * The available pins are organized in banks (A,B,C,D,E,X,Y,Z,AO,
0010  * BOOT,CARD for meson6, X,Y,DV,H,Z,AO,BOOT,CARD for meson8 and
0011  * X,Y,DV,H,AO,BOOT,CARD,DIF for meson8b) and each bank has a
0012  * variable number of pins.
0013  *
0014  * The AO bank is special because it belongs to the Always-On power
0015  * domain which can't be powered off; the bank also uses a set of
0016  * registers different from the other banks.
0017  *
0018  * For each pin controller there are 4 different register ranges that
0019  * control the following properties of the pins:
0020  *  1) pin muxing
0021  *  2) pull enable/disable
0022  *  3) pull up/down
0023  *  4) GPIO direction, output value, input value
0024  *
0025  * In some cases the register ranges for pull enable and pull
0026  * direction are the same and thus there are only 3 register ranges.
0027  *
0028  * Since Meson G12A SoC, the ao register ranges for gpio, pull enable
0029  * and pull direction are the same, so there are only 2 register ranges.
0030  *
0031  * For the pull and GPIO configuration every bank uses a contiguous
0032  * set of bits in the register sets described above; the same register
0033  * can be shared by more banks with different offsets.
0034  *
0035  * In addition to this there are some registers shared between all
0036  * banks that control the IRQ functionality. This feature is not
0037  * supported at the moment by the driver.
0038  */
0039 
0040 #include <linux/device.h>
0041 #include <linux/gpio/driver.h>
0042 #include <linux/init.h>
0043 #include <linux/io.h>
0044 #include <linux/of.h>
0045 #include <linux/of_address.h>
0046 #include <linux/of_device.h>
0047 #include <linux/pinctrl/pinconf-generic.h>
0048 #include <linux/pinctrl/pinconf.h>
0049 #include <linux/pinctrl/pinctrl.h>
0050 #include <linux/pinctrl/pinmux.h>
0051 #include <linux/platform_device.h>
0052 #include <linux/property.h>
0053 #include <linux/regmap.h>
0054 #include <linux/seq_file.h>
0055 
0056 #include "../core.h"
0057 #include "../pinctrl-utils.h"
0058 #include "pinctrl-meson.h"
0059 
0060 static const unsigned int meson_bit_strides[] = {
0061     1, 1, 1, 1, 1, 2, 1
0062 };
0063 
0064 /**
0065  * meson_get_bank() - find the bank containing a given pin
0066  *
0067  * @pc:     the pinctrl instance
0068  * @pin:    the pin number
0069  * @bank:   the found bank
0070  *
0071  * Return:  0 on success, a negative value on error
0072  */
0073 static int meson_get_bank(struct meson_pinctrl *pc, unsigned int pin,
0074               struct meson_bank **bank)
0075 {
0076     int i;
0077 
0078     for (i = 0; i < pc->data->num_banks; i++) {
0079         if (pin >= pc->data->banks[i].first &&
0080             pin <= pc->data->banks[i].last) {
0081             *bank = &pc->data->banks[i];
0082             return 0;
0083         }
0084     }
0085 
0086     return -EINVAL;
0087 }
0088 
0089 /**
0090  * meson_calc_reg_and_bit() - calculate register and bit for a pin
0091  *
0092  * @bank:   the bank containing the pin
0093  * @pin:    the pin number
0094  * @reg_type:   the type of register needed (pull-enable, pull, etc...)
0095  * @reg:    the computed register offset
0096  * @bit:    the computed bit
0097  */
0098 static void meson_calc_reg_and_bit(struct meson_bank *bank, unsigned int pin,
0099                    enum meson_reg_type reg_type,
0100                    unsigned int *reg, unsigned int *bit)
0101 {
0102     struct meson_reg_desc *desc = &bank->regs[reg_type];
0103 
0104     *bit = (desc->bit + pin - bank->first) * meson_bit_strides[reg_type];
0105     *reg = (desc->reg + (*bit / 32)) * 4;
0106     *bit &= 0x1f;
0107 }
0108 
0109 static int meson_get_groups_count(struct pinctrl_dev *pcdev)
0110 {
0111     struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
0112 
0113     return pc->data->num_groups;
0114 }
0115 
0116 static const char *meson_get_group_name(struct pinctrl_dev *pcdev,
0117                     unsigned selector)
0118 {
0119     struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
0120 
0121     return pc->data->groups[selector].name;
0122 }
0123 
0124 static int meson_get_group_pins(struct pinctrl_dev *pcdev, unsigned selector,
0125                 const unsigned **pins, unsigned *num_pins)
0126 {
0127     struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
0128 
0129     *pins = pc->data->groups[selector].pins;
0130     *num_pins = pc->data->groups[selector].num_pins;
0131 
0132     return 0;
0133 }
0134 
0135 static void meson_pin_dbg_show(struct pinctrl_dev *pcdev, struct seq_file *s,
0136                    unsigned offset)
0137 {
0138     seq_printf(s, " %s", dev_name(pcdev->dev));
0139 }
0140 
0141 static const struct pinctrl_ops meson_pctrl_ops = {
0142     .get_groups_count   = meson_get_groups_count,
0143     .get_group_name     = meson_get_group_name,
0144     .get_group_pins     = meson_get_group_pins,
0145     .dt_node_to_map     = pinconf_generic_dt_node_to_map_all,
0146     .dt_free_map        = pinctrl_utils_free_map,
0147     .pin_dbg_show       = meson_pin_dbg_show,
0148 };
0149 
0150 int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev)
0151 {
0152     struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
0153 
0154     return pc->data->num_funcs;
0155 }
0156 EXPORT_SYMBOL_GPL(meson_pmx_get_funcs_count);
0157 
0158 const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev,
0159                     unsigned selector)
0160 {
0161     struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
0162 
0163     return pc->data->funcs[selector].name;
0164 }
0165 EXPORT_SYMBOL_GPL(meson_pmx_get_func_name);
0166 
0167 int meson_pmx_get_groups(struct pinctrl_dev *pcdev, unsigned selector,
0168              const char * const **groups,
0169              unsigned * const num_groups)
0170 {
0171     struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
0172 
0173     *groups = pc->data->funcs[selector].groups;
0174     *num_groups = pc->data->funcs[selector].num_groups;
0175 
0176     return 0;
0177 }
0178 EXPORT_SYMBOL_GPL(meson_pmx_get_groups);
0179 
0180 static int meson_pinconf_set_gpio_bit(struct meson_pinctrl *pc,
0181                       unsigned int pin,
0182                       unsigned int reg_type,
0183                       bool arg)
0184 {
0185     struct meson_bank *bank;
0186     unsigned int reg, bit;
0187     int ret;
0188 
0189     ret = meson_get_bank(pc, pin, &bank);
0190     if (ret)
0191         return ret;
0192 
0193     meson_calc_reg_and_bit(bank, pin, reg_type, &reg, &bit);
0194     return regmap_update_bits(pc->reg_gpio, reg, BIT(bit),
0195                   arg ? BIT(bit) : 0);
0196 }
0197 
0198 static int meson_pinconf_get_gpio_bit(struct meson_pinctrl *pc,
0199                       unsigned int pin,
0200                       unsigned int reg_type)
0201 {
0202     struct meson_bank *bank;
0203     unsigned int reg, bit, val;
0204     int ret;
0205 
0206     ret = meson_get_bank(pc, pin, &bank);
0207     if (ret)
0208         return ret;
0209 
0210     meson_calc_reg_and_bit(bank, pin, reg_type, &reg, &bit);
0211     ret = regmap_read(pc->reg_gpio, reg, &val);
0212     if (ret)
0213         return ret;
0214 
0215     return BIT(bit) & val ? 1 : 0;
0216 }
0217 
0218 static int meson_pinconf_set_output(struct meson_pinctrl *pc,
0219                     unsigned int pin,
0220                     bool out)
0221 {
0222     return meson_pinconf_set_gpio_bit(pc, pin, MESON_REG_DIR, !out);
0223 }
0224 
0225 static int meson_pinconf_get_output(struct meson_pinctrl *pc,
0226                     unsigned int pin)
0227 {
0228     int ret = meson_pinconf_get_gpio_bit(pc, pin, MESON_REG_DIR);
0229 
0230     if (ret < 0)
0231         return ret;
0232 
0233     return !ret;
0234 }
0235 
0236 static int meson_pinconf_set_drive(struct meson_pinctrl *pc,
0237                    unsigned int pin,
0238                    bool high)
0239 {
0240     return meson_pinconf_set_gpio_bit(pc, pin, MESON_REG_OUT, high);
0241 }
0242 
0243 static int meson_pinconf_get_drive(struct meson_pinctrl *pc,
0244                    unsigned int pin)
0245 {
0246     return meson_pinconf_get_gpio_bit(pc, pin, MESON_REG_OUT);
0247 }
0248 
0249 static int meson_pinconf_set_output_drive(struct meson_pinctrl *pc,
0250                       unsigned int pin,
0251                       bool high)
0252 {
0253     int ret;
0254 
0255     ret = meson_pinconf_set_output(pc, pin, true);
0256     if (ret)
0257         return ret;
0258 
0259     return meson_pinconf_set_drive(pc, pin, high);
0260 }
0261 
0262 static int meson_pinconf_disable_bias(struct meson_pinctrl *pc,
0263                       unsigned int pin)
0264 {
0265     struct meson_bank *bank;
0266     unsigned int reg, bit = 0;
0267     int ret;
0268 
0269     ret = meson_get_bank(pc, pin, &bank);
0270     if (ret)
0271         return ret;
0272 
0273     meson_calc_reg_and_bit(bank, pin, MESON_REG_PULLEN, &reg, &bit);
0274     ret = regmap_update_bits(pc->reg_pullen, reg, BIT(bit), 0);
0275     if (ret)
0276         return ret;
0277 
0278     return 0;
0279 }
0280 
0281 static int meson_pinconf_enable_bias(struct meson_pinctrl *pc, unsigned int pin,
0282                      bool pull_up)
0283 {
0284     struct meson_bank *bank;
0285     unsigned int reg, bit, val = 0;
0286     int ret;
0287 
0288     ret = meson_get_bank(pc, pin, &bank);
0289     if (ret)
0290         return ret;
0291 
0292     meson_calc_reg_and_bit(bank, pin, MESON_REG_PULL, &reg, &bit);
0293     if (pull_up)
0294         val = BIT(bit);
0295 
0296     ret = regmap_update_bits(pc->reg_pull, reg, BIT(bit), val);
0297     if (ret)
0298         return ret;
0299 
0300     meson_calc_reg_and_bit(bank, pin, MESON_REG_PULLEN, &reg, &bit);
0301     ret = regmap_update_bits(pc->reg_pullen, reg, BIT(bit), BIT(bit));
0302     if (ret)
0303         return ret;
0304 
0305     return 0;
0306 }
0307 
0308 static int meson_pinconf_set_drive_strength(struct meson_pinctrl *pc,
0309                         unsigned int pin,
0310                         u16 drive_strength_ua)
0311 {
0312     struct meson_bank *bank;
0313     unsigned int reg, bit, ds_val;
0314     int ret;
0315 
0316     if (!pc->reg_ds) {
0317         dev_err(pc->dev, "drive-strength not supported\n");
0318         return -ENOTSUPP;
0319     }
0320 
0321     ret = meson_get_bank(pc, pin, &bank);
0322     if (ret)
0323         return ret;
0324 
0325     meson_calc_reg_and_bit(bank, pin, MESON_REG_DS, &reg, &bit);
0326 
0327     if (drive_strength_ua <= 500) {
0328         ds_val = MESON_PINCONF_DRV_500UA;
0329     } else if (drive_strength_ua <= 2500) {
0330         ds_val = MESON_PINCONF_DRV_2500UA;
0331     } else if (drive_strength_ua <= 3000) {
0332         ds_val = MESON_PINCONF_DRV_3000UA;
0333     } else if (drive_strength_ua <= 4000) {
0334         ds_val = MESON_PINCONF_DRV_4000UA;
0335     } else {
0336         dev_warn_once(pc->dev,
0337                   "pin %u: invalid drive-strength : %d , default to 4mA\n",
0338                   pin, drive_strength_ua);
0339         ds_val = MESON_PINCONF_DRV_4000UA;
0340     }
0341 
0342     ret = regmap_update_bits(pc->reg_ds, reg, 0x3 << bit, ds_val << bit);
0343     if (ret)
0344         return ret;
0345 
0346     return 0;
0347 }
0348 
0349 static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin,
0350                  unsigned long *configs, unsigned num_configs)
0351 {
0352     struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
0353     enum pin_config_param param;
0354     unsigned int arg = 0;
0355     int i, ret;
0356 
0357     for (i = 0; i < num_configs; i++) {
0358         param = pinconf_to_config_param(configs[i]);
0359 
0360         switch (param) {
0361         case PIN_CONFIG_DRIVE_STRENGTH_UA:
0362         case PIN_CONFIG_OUTPUT_ENABLE:
0363         case PIN_CONFIG_OUTPUT:
0364             arg = pinconf_to_config_argument(configs[i]);
0365             break;
0366 
0367         default:
0368             break;
0369         }
0370 
0371         switch (param) {
0372         case PIN_CONFIG_BIAS_DISABLE:
0373             ret = meson_pinconf_disable_bias(pc, pin);
0374             break;
0375         case PIN_CONFIG_BIAS_PULL_UP:
0376             ret = meson_pinconf_enable_bias(pc, pin, true);
0377             break;
0378         case PIN_CONFIG_BIAS_PULL_DOWN:
0379             ret = meson_pinconf_enable_bias(pc, pin, false);
0380             break;
0381         case PIN_CONFIG_DRIVE_STRENGTH_UA:
0382             ret = meson_pinconf_set_drive_strength(pc, pin, arg);
0383             break;
0384         case PIN_CONFIG_OUTPUT_ENABLE:
0385             ret = meson_pinconf_set_output(pc, pin, arg);
0386             break;
0387         case PIN_CONFIG_OUTPUT:
0388             ret = meson_pinconf_set_output_drive(pc, pin, arg);
0389             break;
0390         default:
0391             ret = -ENOTSUPP;
0392         }
0393 
0394         if (ret)
0395             return ret;
0396     }
0397 
0398     return 0;
0399 }
0400 
0401 static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin)
0402 {
0403     struct meson_bank *bank;
0404     unsigned int reg, bit, val;
0405     int ret, conf;
0406 
0407     ret = meson_get_bank(pc, pin, &bank);
0408     if (ret)
0409         return ret;
0410 
0411     meson_calc_reg_and_bit(bank, pin, MESON_REG_PULLEN, &reg, &bit);
0412 
0413     ret = regmap_read(pc->reg_pullen, reg, &val);
0414     if (ret)
0415         return ret;
0416 
0417     if (!(val & BIT(bit))) {
0418         conf = PIN_CONFIG_BIAS_DISABLE;
0419     } else {
0420         meson_calc_reg_and_bit(bank, pin, MESON_REG_PULL, &reg, &bit);
0421 
0422         ret = regmap_read(pc->reg_pull, reg, &val);
0423         if (ret)
0424             return ret;
0425 
0426         if (val & BIT(bit))
0427             conf = PIN_CONFIG_BIAS_PULL_UP;
0428         else
0429             conf = PIN_CONFIG_BIAS_PULL_DOWN;
0430     }
0431 
0432     return conf;
0433 }
0434 
0435 static int meson_pinconf_get_drive_strength(struct meson_pinctrl *pc,
0436                         unsigned int pin,
0437                         u16 *drive_strength_ua)
0438 {
0439     struct meson_bank *bank;
0440     unsigned int reg, bit;
0441     unsigned int val;
0442     int ret;
0443 
0444     if (!pc->reg_ds)
0445         return -ENOTSUPP;
0446 
0447     ret = meson_get_bank(pc, pin, &bank);
0448     if (ret)
0449         return ret;
0450 
0451     meson_calc_reg_and_bit(bank, pin, MESON_REG_DS, &reg, &bit);
0452 
0453     ret = regmap_read(pc->reg_ds, reg, &val);
0454     if (ret)
0455         return ret;
0456 
0457     switch ((val >> bit) & 0x3) {
0458     case MESON_PINCONF_DRV_500UA:
0459         *drive_strength_ua = 500;
0460         break;
0461     case MESON_PINCONF_DRV_2500UA:
0462         *drive_strength_ua = 2500;
0463         break;
0464     case MESON_PINCONF_DRV_3000UA:
0465         *drive_strength_ua = 3000;
0466         break;
0467     case MESON_PINCONF_DRV_4000UA:
0468         *drive_strength_ua = 4000;
0469         break;
0470     default:
0471         return -EINVAL;
0472     }
0473 
0474     return 0;
0475 }
0476 
0477 static int meson_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin,
0478                  unsigned long *config)
0479 {
0480     struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
0481     enum pin_config_param param = pinconf_to_config_param(*config);
0482     u16 arg;
0483     int ret;
0484 
0485     switch (param) {
0486     case PIN_CONFIG_BIAS_DISABLE:
0487     case PIN_CONFIG_BIAS_PULL_DOWN:
0488     case PIN_CONFIG_BIAS_PULL_UP:
0489         if (meson_pinconf_get_pull(pc, pin) == param)
0490             arg = 1;
0491         else
0492             return -EINVAL;
0493         break;
0494     case PIN_CONFIG_DRIVE_STRENGTH_UA:
0495         ret = meson_pinconf_get_drive_strength(pc, pin, &arg);
0496         if (ret)
0497             return ret;
0498         break;
0499     case PIN_CONFIG_OUTPUT_ENABLE:
0500         ret = meson_pinconf_get_output(pc, pin);
0501         if (ret <= 0)
0502             return -EINVAL;
0503         arg = 1;
0504         break;
0505     case PIN_CONFIG_OUTPUT:
0506         ret = meson_pinconf_get_output(pc, pin);
0507         if (ret <= 0)
0508             return -EINVAL;
0509 
0510         ret = meson_pinconf_get_drive(pc, pin);
0511         if (ret < 0)
0512             return -EINVAL;
0513 
0514         arg = ret;
0515         break;
0516 
0517     default:
0518         return -ENOTSUPP;
0519     }
0520 
0521     *config = pinconf_to_config_packed(param, arg);
0522     dev_dbg(pc->dev, "pinconf for pin %u is %lu\n", pin, *config);
0523 
0524     return 0;
0525 }
0526 
0527 static int meson_pinconf_group_set(struct pinctrl_dev *pcdev,
0528                    unsigned int num_group,
0529                    unsigned long *configs, unsigned num_configs)
0530 {
0531     struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
0532     struct meson_pmx_group *group = &pc->data->groups[num_group];
0533     int i;
0534 
0535     dev_dbg(pc->dev, "set pinconf for group %s\n", group->name);
0536 
0537     for (i = 0; i < group->num_pins; i++) {
0538         meson_pinconf_set(pcdev, group->pins[i], configs,
0539                   num_configs);
0540     }
0541 
0542     return 0;
0543 }
0544 
0545 static int meson_pinconf_group_get(struct pinctrl_dev *pcdev,
0546                    unsigned int group, unsigned long *config)
0547 {
0548     return -ENOTSUPP;
0549 }
0550 
0551 static const struct pinconf_ops meson_pinconf_ops = {
0552     .pin_config_get     = meson_pinconf_get,
0553     .pin_config_set     = meson_pinconf_set,
0554     .pin_config_group_get   = meson_pinconf_group_get,
0555     .pin_config_group_set   = meson_pinconf_group_set,
0556     .is_generic     = true,
0557 };
0558 
0559 static int meson_gpio_get_direction(struct gpio_chip *chip, unsigned gpio)
0560 {
0561     struct meson_pinctrl *pc = gpiochip_get_data(chip);
0562     int ret;
0563 
0564     ret = meson_pinconf_get_output(pc, gpio);
0565     if (ret < 0)
0566         return ret;
0567 
0568     return ret ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
0569 }
0570 
0571 static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
0572 {
0573     return meson_pinconf_set_output(gpiochip_get_data(chip), gpio, false);
0574 }
0575 
0576 static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
0577                        int value)
0578 {
0579     return meson_pinconf_set_output_drive(gpiochip_get_data(chip),
0580                           gpio, value);
0581 }
0582 
0583 static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
0584 {
0585     meson_pinconf_set_drive(gpiochip_get_data(chip), gpio, value);
0586 }
0587 
0588 static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio)
0589 {
0590     struct meson_pinctrl *pc = gpiochip_get_data(chip);
0591     unsigned int reg, bit, val;
0592     struct meson_bank *bank;
0593     int ret;
0594 
0595     ret = meson_get_bank(pc, gpio, &bank);
0596     if (ret)
0597         return ret;
0598 
0599     meson_calc_reg_and_bit(bank, gpio, MESON_REG_IN, &reg, &bit);
0600     regmap_read(pc->reg_gpio, reg, &val);
0601 
0602     return !!(val & BIT(bit));
0603 }
0604 
0605 static int meson_gpiolib_register(struct meson_pinctrl *pc)
0606 {
0607     int ret;
0608 
0609     pc->chip.label = pc->data->name;
0610     pc->chip.parent = pc->dev;
0611     pc->chip.request = gpiochip_generic_request;
0612     pc->chip.free = gpiochip_generic_free;
0613     pc->chip.set_config = gpiochip_generic_config;
0614     pc->chip.get_direction = meson_gpio_get_direction;
0615     pc->chip.direction_input = meson_gpio_direction_input;
0616     pc->chip.direction_output = meson_gpio_direction_output;
0617     pc->chip.get = meson_gpio_get;
0618     pc->chip.set = meson_gpio_set;
0619     pc->chip.base = -1;
0620     pc->chip.ngpio = pc->data->num_pins;
0621     pc->chip.can_sleep = false;
0622     pc->chip.of_node = pc->of_node;
0623     pc->chip.of_gpio_n_cells = 2;
0624 
0625     ret = gpiochip_add_data(&pc->chip, pc);
0626     if (ret) {
0627         dev_err(pc->dev, "can't add gpio chip %s\n",
0628             pc->data->name);
0629         return ret;
0630     }
0631 
0632     return 0;
0633 }
0634 
0635 static struct regmap_config meson_regmap_config = {
0636     .reg_bits = 32,
0637     .val_bits = 32,
0638     .reg_stride = 4,
0639 };
0640 
0641 static struct regmap *meson_map_resource(struct meson_pinctrl *pc,
0642                      struct device_node *node, char *name)
0643 {
0644     struct resource res;
0645     void __iomem *base;
0646     int i;
0647 
0648     i = of_property_match_string(node, "reg-names", name);
0649     if (of_address_to_resource(node, i, &res))
0650         return NULL;
0651 
0652     base = devm_ioremap_resource(pc->dev, &res);
0653     if (IS_ERR(base))
0654         return ERR_CAST(base);
0655 
0656     meson_regmap_config.max_register = resource_size(&res) - 4;
0657     meson_regmap_config.name = devm_kasprintf(pc->dev, GFP_KERNEL,
0658                           "%pOFn-%s", node,
0659                           name);
0660     if (!meson_regmap_config.name)
0661         return ERR_PTR(-ENOMEM);
0662 
0663     return devm_regmap_init_mmio(pc->dev, base, &meson_regmap_config);
0664 }
0665 
0666 static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc)
0667 {
0668     struct device_node *gpio_np;
0669     unsigned int chips;
0670 
0671     chips = gpiochip_node_count(pc->dev);
0672     if (!chips) {
0673         dev_err(pc->dev, "no gpio node found\n");
0674         return -EINVAL;
0675     }
0676     if (chips > 1) {
0677         dev_err(pc->dev, "multiple gpio nodes\n");
0678         return -EINVAL;
0679     }
0680 
0681     gpio_np = to_of_node(gpiochip_node_get_first(pc->dev));
0682     pc->of_node = gpio_np;
0683 
0684     pc->reg_mux = meson_map_resource(pc, gpio_np, "mux");
0685     if (IS_ERR_OR_NULL(pc->reg_mux)) {
0686         dev_err(pc->dev, "mux registers not found\n");
0687         return pc->reg_mux ? PTR_ERR(pc->reg_mux) : -ENOENT;
0688     }
0689 
0690     pc->reg_gpio = meson_map_resource(pc, gpio_np, "gpio");
0691     if (IS_ERR_OR_NULL(pc->reg_gpio)) {
0692         dev_err(pc->dev, "gpio registers not found\n");
0693         return pc->reg_gpio ? PTR_ERR(pc->reg_gpio) : -ENOENT;
0694     }
0695 
0696     pc->reg_pull = meson_map_resource(pc, gpio_np, "pull");
0697     if (IS_ERR(pc->reg_pull))
0698         pc->reg_pull = NULL;
0699 
0700     pc->reg_pullen = meson_map_resource(pc, gpio_np, "pull-enable");
0701     if (IS_ERR(pc->reg_pullen))
0702         pc->reg_pullen = NULL;
0703 
0704     pc->reg_ds = meson_map_resource(pc, gpio_np, "ds");
0705     if (IS_ERR(pc->reg_ds)) {
0706         dev_dbg(pc->dev, "ds registers not found - skipping\n");
0707         pc->reg_ds = NULL;
0708     }
0709 
0710     if (pc->data->parse_dt)
0711         return pc->data->parse_dt(pc);
0712 
0713     return 0;
0714 }
0715 
0716 int meson8_aobus_parse_dt_extra(struct meson_pinctrl *pc)
0717 {
0718     if (!pc->reg_pull)
0719         return -EINVAL;
0720 
0721     pc->reg_pullen = pc->reg_pull;
0722 
0723     return 0;
0724 }
0725 EXPORT_SYMBOL_GPL(meson8_aobus_parse_dt_extra);
0726 
0727 int meson_a1_parse_dt_extra(struct meson_pinctrl *pc)
0728 {
0729     pc->reg_pull = pc->reg_gpio;
0730     pc->reg_pullen = pc->reg_gpio;
0731     pc->reg_ds = pc->reg_gpio;
0732 
0733     return 0;
0734 }
0735 EXPORT_SYMBOL_GPL(meson_a1_parse_dt_extra);
0736 
0737 int meson_pinctrl_probe(struct platform_device *pdev)
0738 {
0739     struct device *dev = &pdev->dev;
0740     struct meson_pinctrl *pc;
0741     int ret;
0742 
0743     pc = devm_kzalloc(dev, sizeof(struct meson_pinctrl), GFP_KERNEL);
0744     if (!pc)
0745         return -ENOMEM;
0746 
0747     pc->dev = dev;
0748     pc->data = (struct meson_pinctrl_data *) of_device_get_match_data(dev);
0749 
0750     ret = meson_pinctrl_parse_dt(pc);
0751     if (ret)
0752         return ret;
0753 
0754     pc->desc.name       = "pinctrl-meson";
0755     pc->desc.owner      = THIS_MODULE;
0756     pc->desc.pctlops    = &meson_pctrl_ops;
0757     pc->desc.pmxops     = pc->data->pmx_ops;
0758     pc->desc.confops    = &meson_pinconf_ops;
0759     pc->desc.pins       = pc->data->pins;
0760     pc->desc.npins      = pc->data->num_pins;
0761 
0762     pc->pcdev = devm_pinctrl_register(pc->dev, &pc->desc, pc);
0763     if (IS_ERR(pc->pcdev)) {
0764         dev_err(pc->dev, "can't register pinctrl device");
0765         return PTR_ERR(pc->pcdev);
0766     }
0767 
0768     return meson_gpiolib_register(pc);
0769 }
0770 EXPORT_SYMBOL_GPL(meson_pinctrl_probe);
0771 
0772 MODULE_LICENSE("GPL v2");
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