pinctrl/mediatek/pinctrl-mtk-common.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2014 MediaTek Inc.
0004  * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
0005  */
0006
0007 #ifndef __PINCTRL_MTK_COMMON_H
0008 #define __PINCTRL_MTK_COMMON_H
0009
0010 #include <linux/pinctrl/pinctrl.h>
0011 #include <linux/regmap.h>
0012 #include <linux/pinctrl/pinconf-generic.h>
0013
0014 #include "mtk-eint.h"
0015
0016 #define NO_EINT_SUPPORT    255
0017 #define MT_EDGE_SENSITIVE           0
0018 #define MT_LEVEL_SENSITIVE          1
0019 #define EINT_DBNC_SET_DBNC_BITS     4
0020 #define EINT_DBNC_RST_BIT           (0x1 << 1)
0021 #define EINT_DBNC_SET_EN            (0x1 << 0)
0022
0023 #define MTK_PINCTRL_NOT_SUPPORT (0xffff)
0024
0025 struct mtk_desc_function {
0026     const char *name;
0027     unsigned char muxval;
0028 };
0029
0030 struct mtk_desc_eint {
0031     unsigned char eintmux;
0032     unsigned char eintnum;
0033 };
0034
0035 struct mtk_desc_pin {
0036     struct pinctrl_pin_desc pin;
0037     const struct mtk_desc_eint eint;
0038     const struct mtk_desc_function  *functions;
0039 };
0040
0041 #define MTK_PIN(_pin, _pad, _chip, _eint, ...)      \
0042     {                           \
0043         .pin = _pin,                    \
0044         .eint = _eint,                  \
0045         .functions = (struct mtk_desc_function[]){  \
0046             __VA_ARGS__, { } },         \
0047     }
0048
0049 #define MTK_EINT_FUNCTION(_eintmux, _eintnum)               \
0050     {                           \
0051         .eintmux = _eintmux,                    \
0052         .eintnum = _eintnum,                    \
0053     }
0054
0055 #define MTK_FUNCTION(_val, _name)               \
0056     {                           \
0057         .muxval = _val,                 \
0058         .name = _name,                  \
0059     }
0060
0061 #define SET_ADDR(x, y)  (x + (y->devdata->port_align))
0062 #define CLR_ADDR(x, y)  (x + (y->devdata->port_align << 1))
0063
0064 struct mtk_pinctrl_group {
0065     const char  *name;
0066     unsigned long   config;
0067     unsigned    pin;
0068 };
0069
0070 /**
0071  * struct mtk_drv_group_desc - Provide driving group data.
0072  * @max_drv: The maximum current of this group.
0073  * @min_drv: The minimum current of this group.
0074  * @low_bit: The lowest bit of this group.
0075  * @high_bit: The highest bit of this group.
0076  * @step: The step current of this group.
0077  */
0078 struct mtk_drv_group_desc {
0079     unsigned char min_drv;
0080     unsigned char max_drv;
0081     unsigned char low_bit;
0082     unsigned char high_bit;
0083     unsigned char step;
0084 };
0085
0086 #define MTK_DRV_GRP(_min, _max, _low, _high, _step) \
0087     {   \
0088         .min_drv = _min,    \
0089         .max_drv = _max,    \
0090         .low_bit = _low,    \
0091         .high_bit = _high,  \
0092         .step = _step,      \
0093     }
0094
0095 /**
0096  * struct mtk_pin_drv_grp - Provide each pin driving info.
0097  * @pin: The pin number.
0098  * @offset: The offset of driving register for this pin.
0099  * @bit: The bit of driving register for this pin.
0100  * @grp: The group for this pin belongs to.
0101  */
0102 struct mtk_pin_drv_grp {
0103     unsigned short pin;
0104     unsigned short offset;
0105     unsigned char bit;
0106     unsigned char grp;
0107 };
0108
0109 #define MTK_PIN_DRV_GRP(_pin, _offset, _bit, _grp)  \
0110     {   \
0111         .pin = _pin,    \
0112         .offset = _offset,  \
0113         .bit = _bit,    \
0114         .grp = _grp,    \
0115     }
0116
0117 /**
0118  * struct mtk_pin_spec_pupd_set_samereg
0119  * - For special pins' pull up/down setting which resides in same register
0120  * @pin: The pin number.
0121  * @offset: The offset of special pull up/down setting register.
0122  * @pupd_bit: The pull up/down bit in this register.
0123  * @r0_bit: The r0 bit of pull resistor.
0124  * @r1_bit: The r1 bit of pull resistor.
0125  */
0126 struct mtk_pin_spec_pupd_set_samereg {
0127     unsigned short pin;
0128     unsigned short offset;
0129     unsigned char pupd_bit;
0130     unsigned char r1_bit;
0131     unsigned char r0_bit;
0132 };
0133
0134 #define MTK_PIN_PUPD_SPEC_SR(_pin, _offset, _pupd, _r1, _r0)    \
0135     {   \
0136         .pin = _pin,    \
0137         .offset = _offset,  \
0138         .pupd_bit = _pupd,  \
0139         .r1_bit = _r1,      \
0140         .r0_bit = _r0,      \
0141     }
0142
0143 /**
0144  * struct mtk_pin_ies_set - For special pins' ies and smt setting.
0145  * @start: The start pin number of those special pins.
0146  * @end: The end pin number of those special pins.
0147  * @offset: The offset of special setting register.
0148  * @bit: The bit of special setting register.
0149  */
0150 struct mtk_pin_ies_smt_set {
0151     unsigned short start;
0152     unsigned short end;
0153     unsigned short offset;
0154     unsigned char bit;
0155 };
0156
0157 #define MTK_PIN_IES_SMT_SPEC(_start, _end, _offset, _bit)   \
0158     {   \
0159         .start = _start,    \
0160         .end = _end,    \
0161         .bit = _bit,    \
0162         .offset = _offset,  \
0163     }
0164
0165 struct mtk_eint_offsets {
0166     const char *name;
0167     unsigned int  stat;
0168     unsigned int  ack;
0169     unsigned int  mask;
0170     unsigned int  mask_set;
0171     unsigned int  mask_clr;
0172     unsigned int  sens;
0173     unsigned int  sens_set;
0174     unsigned int  sens_clr;
0175     unsigned int  soft;
0176     unsigned int  soft_set;
0177     unsigned int  soft_clr;
0178     unsigned int  pol;
0179     unsigned int  pol_set;
0180     unsigned int  pol_clr;
0181     unsigned int  dom_en;
0182     unsigned int  dbnc_ctrl;
0183     unsigned int  dbnc_set;
0184     unsigned int  dbnc_clr;
0185     u8  port_mask;
0186     u8  ports;
0187 };
0188
0189 /**
0190  * struct mtk_pinctrl_devdata - Provide HW GPIO related data.
0191  * @pins: An array describing all pins the pin controller affects.
0192  * @npins: The number of entries in @pins.
0193  *
0194  * @grp_desc: The driving group info.
0195  * @pin_drv_grp: The driving group for all pins.
0196  * @spec_ies: Special pin setting for input enable
0197  * @n_spec_ies: Number of entries in spec_ies
0198  * @spec_pupd: Special pull up/down setting
0199  * @n_spec_pupd: Number of entries in spec_pupd
0200  * @spec_smt: Special pin setting for schmitt
0201  * @n_spec_smt: Number of entries in spec_smt
0202  * @spec_pull_set: Each SoC may have special pins for pull up/down setting,
0203  *  these pins' pull setting are very different, they have separate pull
0204  *  up/down bit, R0 and R1 resistor bit, so they need special pull setting.
0205  *  If special setting is success, this should return 0, otherwise it should
0206  *  return non-zero value.
0207  * @spec_ies_smt_set: Some pins are irregular, their input enable and smt
0208  * control register are discontinuous, but they are mapping together. That
0209  * means when user set smt, input enable is set at the same time. So they
0210  * also need special control. If special control is success, this should
0211  * return 0, otherwise return non-zero value.
0212  * @spec_pinmux_set: In some cases, there are two pinmux functions share
0213  * the same value in the same segment of pinmux control register. If user
0214  * want to use one of the two functions, they need an extra bit setting to
0215  * select the right one.
0216  * @spec_dir_set: In very few SoCs, direction control registers are not
0217  * arranged continuously, they may be cut to parts. So they need special
0218  * dir setting.
0219
0220  * @dir_offset: The direction register offset.
0221  * @pullen_offset: The pull-up/pull-down enable register offset.
0222  * @pinmux_offset: The pinmux register offset.
0223  *
0224  * @type1_start: Some chips have two base addresses for pull select register,
0225  *  that means some pins use the first address and others use the second. This
0226  *  member record the start of pin number to use the second address.
0227  * @type1_end: The end of pin number to use the second address.
0228  *
0229  * @port_shf: The shift between two registers.
0230  * @port_mask: The mask of register.
0231  * @port_align: Provide clear register and set register step.
0232  */
0233 struct mtk_pinctrl_devdata {
0234     const struct mtk_desc_pin   *pins;
0235     unsigned int                npins;
0236     const struct mtk_drv_group_desc *grp_desc;
0237     unsigned int    n_grp_cls;
0238     const struct mtk_pin_drv_grp    *pin_drv_grp;
0239     unsigned int    n_pin_drv_grps;
0240     const struct mtk_pin_ies_smt_set *spec_ies;
0241     unsigned int n_spec_ies;
0242     const struct mtk_pin_spec_pupd_set_samereg *spec_pupd;
0243     unsigned int n_spec_pupd;
0244     const struct mtk_pin_ies_smt_set *spec_smt;
0245     unsigned int n_spec_smt;
0246     int (*spec_pull_set)(struct regmap *regmap,
0247             const struct mtk_pinctrl_devdata *devdata,
0248             unsigned int pin, bool isup, unsigned int r1r0);
0249     int (*spec_ies_smt_set)(struct regmap *reg,
0250             const struct mtk_pinctrl_devdata *devdata,
0251             unsigned int pin, int value, enum pin_config_param arg);
0252     void (*spec_pinmux_set)(struct regmap *reg, unsigned int pin,
0253             unsigned int mode);
0254     void (*spec_dir_set)(unsigned int *reg_addr, unsigned int pin);
0255     unsigned int dir_offset;
0256     unsigned int ies_offset;
0257     unsigned int smt_offset;
0258     unsigned int pullen_offset;
0259     unsigned int pullsel_offset;
0260     unsigned int drv_offset;
0261     unsigned int dout_offset;
0262     unsigned int din_offset;
0263     unsigned int pinmux_offset;
0264     unsigned short type1_start;
0265     unsigned short type1_end;
0266     unsigned char  port_shf;
0267     unsigned char  port_mask;
0268     unsigned char  port_align;
0269     struct mtk_eint_hw eint_hw;
0270     struct mtk_eint_regs *eint_regs;
0271     unsigned int mode_mask;
0272     unsigned int mode_per_reg;
0273     unsigned int mode_shf;
0274 };
0275
0276 struct mtk_pinctrl {
0277     struct regmap   *regmap1;
0278     struct regmap   *regmap2;
0279     struct pinctrl_desc pctl_desc;
0280     struct device           *dev;
0281     struct gpio_chip    *chip;
0282     struct mtk_pinctrl_group    *groups;
0283     unsigned            ngroups;
0284     const char          **grp_names;
0285     struct pinctrl_dev      *pctl_dev;
0286     const struct mtk_pinctrl_devdata  *devdata;
0287     struct mtk_eint *eint;
0288 };
0289
0290 int mtk_pctrl_init(struct platform_device *pdev,
0291         const struct mtk_pinctrl_devdata *data,
0292         struct regmap *regmap);
0293
0294 int mtk_pctrl_common_probe(struct platform_device *pdev);
0295
0296 int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap,
0297         const struct mtk_pinctrl_devdata *devdata,
0298         unsigned int pin, bool isup, unsigned int r1r0);
0299
0300 int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap,
0301         const struct mtk_pinctrl_devdata *devdata,
0302         unsigned int pin, int value, enum pin_config_param arg);
0303
0304 extern const struct dev_pm_ops mtk_eint_pm_ops;
0305
0306 #endif /* __PINCTRL_MTK_COMMON_H */