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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2014-2015 MediaTek Inc.
0004  * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
0005  */
0006 
0007 #include <linux/init.h>
0008 #include <linux/platform_device.h>
0009 #include <linux/of.h>
0010 #include <linux/of_device.h>
0011 #include <linux/pinctrl/pinctrl.h>
0012 #include <linux/regmap.h>
0013 #include <linux/pinctrl/pinconf-generic.h>
0014 #include <dt-bindings/pinctrl/mt65xx.h>
0015 
0016 #include "pinctrl-mtk-common.h"
0017 #include "pinctrl-mtk-mt8173.h"
0018 
0019 #define DRV_BASE                0xb00
0020 
0021 static const struct mtk_pin_spec_pupd_set_samereg mt8173_spec_pupd[] = {
0022     MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 2, 1, 0),  /* KROW0 */
0023     MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 6, 5, 4),  /* KROW1 */
0024     MTK_PIN_PUPD_SPEC_SR(121, 0xe00, 10, 9, 8), /* KROW2 */
0025     MTK_PIN_PUPD_SPEC_SR(122, 0xe10, 2, 1, 0),  /* KCOL0 */
0026     MTK_PIN_PUPD_SPEC_SR(123, 0xe10, 6, 5, 4),  /* KCOL1 */
0027     MTK_PIN_PUPD_SPEC_SR(124, 0xe10, 10, 9, 8), /* KCOL2 */
0028 
0029     MTK_PIN_PUPD_SPEC_SR(67, 0xd10, 2, 1, 0),   /* ms0 DS */
0030     MTK_PIN_PUPD_SPEC_SR(68, 0xd00, 2, 1, 0),   /* ms0 RST */
0031     MTK_PIN_PUPD_SPEC_SR(66, 0xc10, 2, 1, 0),   /* ms0 cmd */
0032     MTK_PIN_PUPD_SPEC_SR(65, 0xc00, 2, 1, 0),   /* ms0 clk */
0033     MTK_PIN_PUPD_SPEC_SR(57, 0xc20, 2, 1, 0),   /* ms0 data0 */
0034     MTK_PIN_PUPD_SPEC_SR(58, 0xc20, 2, 1, 0),   /* ms0 data1 */
0035     MTK_PIN_PUPD_SPEC_SR(59, 0xc20, 2, 1, 0),   /* ms0 data2 */
0036     MTK_PIN_PUPD_SPEC_SR(60, 0xc20, 2, 1, 0),   /* ms0 data3 */
0037     MTK_PIN_PUPD_SPEC_SR(61, 0xc20, 2, 1, 0),   /* ms0 data4 */
0038     MTK_PIN_PUPD_SPEC_SR(62, 0xc20, 2, 1, 0),   /* ms0 data5 */
0039     MTK_PIN_PUPD_SPEC_SR(63, 0xc20, 2, 1, 0),   /* ms0 data6 */
0040     MTK_PIN_PUPD_SPEC_SR(64, 0xc20, 2, 1, 0),   /* ms0 data7 */
0041 
0042     MTK_PIN_PUPD_SPEC_SR(78, 0xc50, 2, 1, 0),    /* ms1 cmd */
0043     MTK_PIN_PUPD_SPEC_SR(73, 0xd20, 2, 1, 0),    /* ms1 dat0 */
0044     MTK_PIN_PUPD_SPEC_SR(74, 0xd20, 6, 5, 4),    /* ms1 dat1 */
0045     MTK_PIN_PUPD_SPEC_SR(75, 0xd20, 10, 9, 8),   /* ms1 dat2 */
0046     MTK_PIN_PUPD_SPEC_SR(76, 0xd20, 14, 13, 12), /* ms1 dat3 */
0047     MTK_PIN_PUPD_SPEC_SR(77, 0xc40, 2, 1, 0),    /* ms1 clk */
0048 
0049     MTK_PIN_PUPD_SPEC_SR(100, 0xd40, 2, 1, 0),    /* ms2 dat0 */
0050     MTK_PIN_PUPD_SPEC_SR(101, 0xd40, 6, 5, 4),    /* ms2 dat1 */
0051     MTK_PIN_PUPD_SPEC_SR(102, 0xd40, 10, 9, 8),   /* ms2 dat2 */
0052     MTK_PIN_PUPD_SPEC_SR(103, 0xd40, 14, 13, 12), /* ms2 dat3 */
0053     MTK_PIN_PUPD_SPEC_SR(104, 0xc80, 2, 1, 0),    /* ms2 clk */
0054     MTK_PIN_PUPD_SPEC_SR(105, 0xc90, 2, 1, 0),    /* ms2 cmd */
0055 
0056     MTK_PIN_PUPD_SPEC_SR(22, 0xd60, 2, 1, 0),    /* ms3 dat0 */
0057     MTK_PIN_PUPD_SPEC_SR(23, 0xd60, 6, 5, 4),    /* ms3 dat1 */
0058     MTK_PIN_PUPD_SPEC_SR(24, 0xd60, 10, 9, 8),   /* ms3 dat2 */
0059     MTK_PIN_PUPD_SPEC_SR(25, 0xd60, 14, 13, 12), /* ms3 dat3 */
0060     MTK_PIN_PUPD_SPEC_SR(26, 0xcc0, 2, 1, 0),    /* ms3 clk */
0061     MTK_PIN_PUPD_SPEC_SR(27, 0xcd0, 2, 1, 0)     /* ms3 cmd */
0062 };
0063 
0064 static const struct mtk_pin_ies_smt_set mt8173_smt_set[] = {
0065     MTK_PIN_IES_SMT_SPEC(0, 4, 0x930, 1),
0066     MTK_PIN_IES_SMT_SPEC(5, 9, 0x930, 2),
0067     MTK_PIN_IES_SMT_SPEC(10, 13, 0x930, 10),
0068     MTK_PIN_IES_SMT_SPEC(14, 15, 0x940, 10),
0069     MTK_PIN_IES_SMT_SPEC(16, 16, 0x930, 0),
0070     MTK_PIN_IES_SMT_SPEC(17, 17, 0x950, 2),
0071     MTK_PIN_IES_SMT_SPEC(18, 21, 0x940, 3),
0072     MTK_PIN_IES_SMT_SPEC(22, 25, 0xce0, 13),
0073     MTK_PIN_IES_SMT_SPEC(26, 26, 0xcc0, 13),
0074     MTK_PIN_IES_SMT_SPEC(27, 27, 0xcd0, 13),
0075     MTK_PIN_IES_SMT_SPEC(28, 28, 0xd70, 13),
0076     MTK_PIN_IES_SMT_SPEC(29, 32, 0x930, 3),
0077     MTK_PIN_IES_SMT_SPEC(33, 33, 0x930, 4),
0078     MTK_PIN_IES_SMT_SPEC(34, 36, 0x930, 5),
0079     MTK_PIN_IES_SMT_SPEC(37, 38, 0x930, 6),
0080     MTK_PIN_IES_SMT_SPEC(39, 39, 0x930, 7),
0081     MTK_PIN_IES_SMT_SPEC(40, 41, 0x930, 9),
0082     MTK_PIN_IES_SMT_SPEC(42, 42, 0x940, 0),
0083     MTK_PIN_IES_SMT_SPEC(43, 44, 0x930, 11),
0084     MTK_PIN_IES_SMT_SPEC(45, 46, 0x930, 12),
0085     MTK_PIN_IES_SMT_SPEC(57, 64, 0xc20, 13),
0086     MTK_PIN_IES_SMT_SPEC(65, 65, 0xc10, 13),
0087     MTK_PIN_IES_SMT_SPEC(66, 66, 0xc00, 13),
0088     MTK_PIN_IES_SMT_SPEC(67, 67, 0xd10, 13),
0089     MTK_PIN_IES_SMT_SPEC(68, 68, 0xd00, 13),
0090     MTK_PIN_IES_SMT_SPEC(69, 72, 0x940, 14),
0091     MTK_PIN_IES_SMT_SPEC(73, 76, 0xc60, 13),
0092     MTK_PIN_IES_SMT_SPEC(77, 77, 0xc40, 13),
0093     MTK_PIN_IES_SMT_SPEC(78, 78, 0xc50, 13),
0094     MTK_PIN_IES_SMT_SPEC(79, 82, 0x940, 15),
0095     MTK_PIN_IES_SMT_SPEC(83, 83, 0x950, 0),
0096     MTK_PIN_IES_SMT_SPEC(84, 85, 0x950, 1),
0097     MTK_PIN_IES_SMT_SPEC(86, 91, 0x950, 2),
0098     MTK_PIN_IES_SMT_SPEC(92, 92, 0x930, 13),
0099     MTK_PIN_IES_SMT_SPEC(93, 95, 0x930, 14),
0100     MTK_PIN_IES_SMT_SPEC(96, 99, 0x930, 15),
0101     MTK_PIN_IES_SMT_SPEC(100, 103, 0xca0, 13),
0102     MTK_PIN_IES_SMT_SPEC(104, 104, 0xc80, 13),
0103     MTK_PIN_IES_SMT_SPEC(105, 105, 0xc90, 13),
0104     MTK_PIN_IES_SMT_SPEC(106, 107, 0x940, 4),
0105     MTK_PIN_IES_SMT_SPEC(108, 112, 0x940, 1),
0106     MTK_PIN_IES_SMT_SPEC(113, 116, 0x940, 2),
0107     MTK_PIN_IES_SMT_SPEC(117, 118, 0x940, 5),
0108     MTK_PIN_IES_SMT_SPEC(119, 124, 0x940, 6),
0109     MTK_PIN_IES_SMT_SPEC(125, 126, 0x940, 7),
0110     MTK_PIN_IES_SMT_SPEC(127, 127, 0x940, 0),
0111     MTK_PIN_IES_SMT_SPEC(128, 128, 0x950, 8),
0112     MTK_PIN_IES_SMT_SPEC(129, 130, 0x950, 9),
0113     MTK_PIN_IES_SMT_SPEC(131, 132, 0x950, 8),
0114     MTK_PIN_IES_SMT_SPEC(133, 134, 0x910, 8)
0115 };
0116 
0117 static const struct mtk_pin_ies_smt_set mt8173_ies_set[] = {
0118     MTK_PIN_IES_SMT_SPEC(0, 4, 0x900, 1),
0119     MTK_PIN_IES_SMT_SPEC(5, 9, 0x900, 2),
0120     MTK_PIN_IES_SMT_SPEC(10, 13, 0x900, 10),
0121     MTK_PIN_IES_SMT_SPEC(14, 15, 0x910, 10),
0122     MTK_PIN_IES_SMT_SPEC(16, 16, 0x900, 0),
0123     MTK_PIN_IES_SMT_SPEC(17, 17, 0x920, 2),
0124     MTK_PIN_IES_SMT_SPEC(18, 21, 0x910, 3),
0125     MTK_PIN_IES_SMT_SPEC(22, 25, 0xce0, 14),
0126     MTK_PIN_IES_SMT_SPEC(26, 26, 0xcc0, 14),
0127     MTK_PIN_IES_SMT_SPEC(27, 27, 0xcd0, 14),
0128     MTK_PIN_IES_SMT_SPEC(28, 28, 0xd70, 14),
0129     MTK_PIN_IES_SMT_SPEC(29, 32, 0x900, 3),
0130     MTK_PIN_IES_SMT_SPEC(33, 33, 0x900, 4),
0131     MTK_PIN_IES_SMT_SPEC(34, 36, 0x900, 5),
0132     MTK_PIN_IES_SMT_SPEC(37, 38, 0x900, 6),
0133     MTK_PIN_IES_SMT_SPEC(39, 39, 0x900, 7),
0134     MTK_PIN_IES_SMT_SPEC(40, 41, 0x900, 9),
0135     MTK_PIN_IES_SMT_SPEC(42, 42, 0x910, 0),
0136     MTK_PIN_IES_SMT_SPEC(43, 44, 0x900, 11),
0137     MTK_PIN_IES_SMT_SPEC(45, 46, 0x900, 12),
0138     MTK_PIN_IES_SMT_SPEC(57, 64, 0xc20, 14),
0139     MTK_PIN_IES_SMT_SPEC(65, 65, 0xc10, 14),
0140     MTK_PIN_IES_SMT_SPEC(66, 66, 0xc00, 14),
0141     MTK_PIN_IES_SMT_SPEC(67, 67, 0xd10, 14),
0142     MTK_PIN_IES_SMT_SPEC(68, 68, 0xd00, 14),
0143     MTK_PIN_IES_SMT_SPEC(69, 72, 0x910, 14),
0144     MTK_PIN_IES_SMT_SPEC(73, 76, 0xc60, 14),
0145     MTK_PIN_IES_SMT_SPEC(77, 77, 0xc40, 14),
0146     MTK_PIN_IES_SMT_SPEC(78, 78, 0xc50, 14),
0147     MTK_PIN_IES_SMT_SPEC(79, 82, 0x910, 15),
0148     MTK_PIN_IES_SMT_SPEC(83, 83, 0x920, 0),
0149     MTK_PIN_IES_SMT_SPEC(84, 85, 0x920, 1),
0150     MTK_PIN_IES_SMT_SPEC(86, 91, 0x920, 2),
0151     MTK_PIN_IES_SMT_SPEC(92, 92, 0x900, 13),
0152     MTK_PIN_IES_SMT_SPEC(93, 95, 0x900, 14),
0153     MTK_PIN_IES_SMT_SPEC(96, 99, 0x900, 15),
0154     MTK_PIN_IES_SMT_SPEC(100, 103, 0xca0, 14),
0155     MTK_PIN_IES_SMT_SPEC(104, 104, 0xc80, 14),
0156     MTK_PIN_IES_SMT_SPEC(105, 105, 0xc90, 14),
0157     MTK_PIN_IES_SMT_SPEC(106, 107, 0x910, 4),
0158     MTK_PIN_IES_SMT_SPEC(108, 112, 0x910, 1),
0159     MTK_PIN_IES_SMT_SPEC(113, 116, 0x910, 2),
0160     MTK_PIN_IES_SMT_SPEC(117, 118, 0x910, 5),
0161     MTK_PIN_IES_SMT_SPEC(119, 124, 0x910, 6),
0162     MTK_PIN_IES_SMT_SPEC(125, 126, 0x910, 7),
0163     MTK_PIN_IES_SMT_SPEC(127, 127, 0x910, 0),
0164     MTK_PIN_IES_SMT_SPEC(128, 128, 0x920, 8),
0165     MTK_PIN_IES_SMT_SPEC(129, 130, 0x920, 9),
0166     MTK_PIN_IES_SMT_SPEC(131, 132, 0x920, 8),
0167     MTK_PIN_IES_SMT_SPEC(133, 134, 0x910, 8)
0168 };
0169 
0170 static const struct mtk_drv_group_desc mt8173_drv_grp[] =  {
0171     /* 0E4E8SR 4/8/12/16 */
0172     MTK_DRV_GRP(4, 16, 1, 2, 4),
0173     /* 0E2E4SR  2/4/6/8 */
0174     MTK_DRV_GRP(2, 8, 1, 2, 2),
0175     /* E8E4E2  2/4/6/8/10/12/14/16 */
0176     MTK_DRV_GRP(2, 16, 0, 2, 2)
0177 };
0178 
0179 static const struct mtk_pin_drv_grp mt8173_pin_drv[] = {
0180     MTK_PIN_DRV_GRP(0, DRV_BASE+0x20, 12, 0),
0181     MTK_PIN_DRV_GRP(1, DRV_BASE+0x20, 12, 0),
0182     MTK_PIN_DRV_GRP(2, DRV_BASE+0x20, 12, 0),
0183     MTK_PIN_DRV_GRP(3, DRV_BASE+0x20, 12, 0),
0184     MTK_PIN_DRV_GRP(4, DRV_BASE+0x20, 12, 0),
0185     MTK_PIN_DRV_GRP(5, DRV_BASE+0x30, 0, 0),
0186     MTK_PIN_DRV_GRP(6, DRV_BASE+0x30, 0, 0),
0187     MTK_PIN_DRV_GRP(7, DRV_BASE+0x30, 0, 0),
0188     MTK_PIN_DRV_GRP(8, DRV_BASE+0x30, 0, 0),
0189     MTK_PIN_DRV_GRP(9, DRV_BASE+0x30, 0, 0),
0190     MTK_PIN_DRV_GRP(10, DRV_BASE+0x30, 4, 1),
0191     MTK_PIN_DRV_GRP(11, DRV_BASE+0x30, 4, 1),
0192     MTK_PIN_DRV_GRP(12, DRV_BASE+0x30, 4, 1),
0193     MTK_PIN_DRV_GRP(13, DRV_BASE+0x30, 4, 1),
0194     MTK_PIN_DRV_GRP(14, DRV_BASE+0x40, 8, 1),
0195     MTK_PIN_DRV_GRP(15, DRV_BASE+0x40, 8, 1),
0196     MTK_PIN_DRV_GRP(16, DRV_BASE, 8, 1),
0197     MTK_PIN_DRV_GRP(17, 0xce0, 8, 2),
0198     MTK_PIN_DRV_GRP(22, 0xce0, 8, 2),
0199     MTK_PIN_DRV_GRP(23, 0xce0, 8, 2),
0200     MTK_PIN_DRV_GRP(24, 0xce0, 8, 2),
0201     MTK_PIN_DRV_GRP(25, 0xce0, 8, 2),
0202     MTK_PIN_DRV_GRP(26, 0xcc0, 8, 2),
0203     MTK_PIN_DRV_GRP(27, 0xcd0, 8, 2),
0204     MTK_PIN_DRV_GRP(28, 0xd70, 8, 2),
0205     MTK_PIN_DRV_GRP(29, DRV_BASE+0x80, 12, 1),
0206     MTK_PIN_DRV_GRP(30, DRV_BASE+0x80, 12, 1),
0207     MTK_PIN_DRV_GRP(31, DRV_BASE+0x80, 12, 1),
0208     MTK_PIN_DRV_GRP(32, DRV_BASE+0x80, 12, 1),
0209     MTK_PIN_DRV_GRP(33, DRV_BASE+0x10, 12, 1),
0210     MTK_PIN_DRV_GRP(34, DRV_BASE+0x10, 8, 1),
0211     MTK_PIN_DRV_GRP(35, DRV_BASE+0x10, 8, 1),
0212     MTK_PIN_DRV_GRP(36, DRV_BASE+0x10, 8, 1),
0213     MTK_PIN_DRV_GRP(37, DRV_BASE+0x10, 4, 1),
0214     MTK_PIN_DRV_GRP(38, DRV_BASE+0x10, 4, 1),
0215     MTK_PIN_DRV_GRP(39, DRV_BASE+0x20, 0, 0),
0216     MTK_PIN_DRV_GRP(40, DRV_BASE+0x20, 8, 0),
0217     MTK_PIN_DRV_GRP(41, DRV_BASE+0x20, 8, 0),
0218     MTK_PIN_DRV_GRP(42, DRV_BASE+0x50, 8, 1),
0219     MTK_PIN_DRV_GRP(57, 0xc20, 8, 2),
0220     MTK_PIN_DRV_GRP(58, 0xc20, 8, 2),
0221     MTK_PIN_DRV_GRP(59, 0xc20, 8, 2),
0222     MTK_PIN_DRV_GRP(60, 0xc20, 8, 2),
0223     MTK_PIN_DRV_GRP(61, 0xc20, 8, 2),
0224     MTK_PIN_DRV_GRP(62, 0xc20, 8, 2),
0225     MTK_PIN_DRV_GRP(63, 0xc20, 8, 2),
0226     MTK_PIN_DRV_GRP(64, 0xc20, 8, 2),
0227     MTK_PIN_DRV_GRP(65, 0xc00, 8, 2),
0228     MTK_PIN_DRV_GRP(66, 0xc10, 8, 2),
0229     MTK_PIN_DRV_GRP(67, 0xd10, 8, 2),
0230     MTK_PIN_DRV_GRP(68, 0xd00, 8, 2),
0231     MTK_PIN_DRV_GRP(69, DRV_BASE+0x80, 0, 1),
0232     MTK_PIN_DRV_GRP(70, DRV_BASE+0x80, 0, 1),
0233     MTK_PIN_DRV_GRP(71, DRV_BASE+0x80, 0, 1),
0234     MTK_PIN_DRV_GRP(72, DRV_BASE+0x80, 0, 1),
0235     MTK_PIN_DRV_GRP(73, 0xc60, 8, 2),
0236     MTK_PIN_DRV_GRP(74, 0xc60, 8, 2),
0237     MTK_PIN_DRV_GRP(75, 0xc60, 8, 2),
0238     MTK_PIN_DRV_GRP(76, 0xc60, 8, 2),
0239     MTK_PIN_DRV_GRP(77, 0xc40, 8, 2),
0240     MTK_PIN_DRV_GRP(78, 0xc50, 8, 2),
0241     MTK_PIN_DRV_GRP(79, DRV_BASE+0x70, 12, 1),
0242     MTK_PIN_DRV_GRP(80, DRV_BASE+0x70, 12, 1),
0243     MTK_PIN_DRV_GRP(81, DRV_BASE+0x70, 12, 1),
0244     MTK_PIN_DRV_GRP(82, DRV_BASE+0x70, 12, 1),
0245     MTK_PIN_DRV_GRP(83, DRV_BASE, 4, 1),
0246     MTK_PIN_DRV_GRP(84, DRV_BASE, 0, 1),
0247     MTK_PIN_DRV_GRP(85, DRV_BASE, 0, 1),
0248     MTK_PIN_DRV_GRP(85, DRV_BASE+0x60, 8, 1),
0249     MTK_PIN_DRV_GRP(86, DRV_BASE+0x60, 8, 1),
0250     MTK_PIN_DRV_GRP(87, DRV_BASE+0x60, 8, 1),
0251     MTK_PIN_DRV_GRP(88, DRV_BASE+0x60, 8, 1),
0252     MTK_PIN_DRV_GRP(89, DRV_BASE+0x60, 8, 1),
0253     MTK_PIN_DRV_GRP(90, DRV_BASE+0x60, 8, 1),
0254     MTK_PIN_DRV_GRP(91, DRV_BASE+0x60, 8, 1),
0255     MTK_PIN_DRV_GRP(92, DRV_BASE+0x60, 4, 0),
0256     MTK_PIN_DRV_GRP(93, DRV_BASE+0x60, 0, 0),
0257     MTK_PIN_DRV_GRP(94, DRV_BASE+0x60, 0, 0),
0258     MTK_PIN_DRV_GRP(95, DRV_BASE+0x60, 0, 0),
0259     MTK_PIN_DRV_GRP(96, DRV_BASE+0x80, 8, 1),
0260     MTK_PIN_DRV_GRP(97, DRV_BASE+0x80, 8, 1),
0261     MTK_PIN_DRV_GRP(98, DRV_BASE+0x80, 8, 1),
0262     MTK_PIN_DRV_GRP(99, DRV_BASE+0x80, 8, 1),
0263     MTK_PIN_DRV_GRP(100, 0xca0, 8, 2),
0264     MTK_PIN_DRV_GRP(101, 0xca0, 8, 2),
0265     MTK_PIN_DRV_GRP(102, 0xca0, 8, 2),
0266     MTK_PIN_DRV_GRP(103, 0xca0, 8, 2),
0267     MTK_PIN_DRV_GRP(104, 0xc80, 8, 2),
0268     MTK_PIN_DRV_GRP(105, 0xc90, 8, 2),
0269     MTK_PIN_DRV_GRP(108, DRV_BASE+0x50, 0, 1),
0270     MTK_PIN_DRV_GRP(109, DRV_BASE+0x50, 0, 1),
0271     MTK_PIN_DRV_GRP(110, DRV_BASE+0x50, 0, 1),
0272     MTK_PIN_DRV_GRP(111, DRV_BASE+0x50, 0, 1),
0273     MTK_PIN_DRV_GRP(112, DRV_BASE+0x50, 0, 1),
0274     MTK_PIN_DRV_GRP(113, DRV_BASE+0x80, 4, 1),
0275     MTK_PIN_DRV_GRP(114, DRV_BASE+0x80, 4, 1),
0276     MTK_PIN_DRV_GRP(115, DRV_BASE+0x80, 4, 1),
0277     MTK_PIN_DRV_GRP(116, DRV_BASE+0x80, 4, 1),
0278     MTK_PIN_DRV_GRP(117, DRV_BASE+0x90, 0, 1),
0279     MTK_PIN_DRV_GRP(118, DRV_BASE+0x90, 0, 1),
0280     MTK_PIN_DRV_GRP(119, DRV_BASE+0x50, 4, 1),
0281     MTK_PIN_DRV_GRP(120, DRV_BASE+0x50, 4, 1),
0282     MTK_PIN_DRV_GRP(121, DRV_BASE+0x50, 4, 1),
0283     MTK_PIN_DRV_GRP(122, DRV_BASE+0x50, 4, 1),
0284     MTK_PIN_DRV_GRP(123, DRV_BASE+0x50, 4, 1),
0285     MTK_PIN_DRV_GRP(124, DRV_BASE+0x50, 4, 1),
0286     MTK_PIN_DRV_GRP(125, DRV_BASE+0x30, 12, 1),
0287     MTK_PIN_DRV_GRP(126, DRV_BASE+0x30, 12, 1),
0288     MTK_PIN_DRV_GRP(127, DRV_BASE+0x50, 8, 1),
0289     MTK_PIN_DRV_GRP(128, DRV_BASE+0x40, 0, 1),
0290     MTK_PIN_DRV_GRP(129, DRV_BASE+0x40, 0, 1),
0291     MTK_PIN_DRV_GRP(130, DRV_BASE+0x40, 0, 1),
0292     MTK_PIN_DRV_GRP(131, DRV_BASE+0x40, 0, 1),
0293     MTK_PIN_DRV_GRP(132, DRV_BASE+0x40, 0, 1)
0294 };
0295 
0296 static const struct mtk_pinctrl_devdata mt8173_pinctrl_data = {
0297     .pins = mtk_pins_mt8173,
0298     .npins = ARRAY_SIZE(mtk_pins_mt8173),
0299     .grp_desc = mt8173_drv_grp,
0300     .n_grp_cls = ARRAY_SIZE(mt8173_drv_grp),
0301     .pin_drv_grp = mt8173_pin_drv,
0302     .n_pin_drv_grps = ARRAY_SIZE(mt8173_pin_drv),
0303     .spec_ies = mt8173_ies_set,
0304     .n_spec_ies = ARRAY_SIZE(mt8173_ies_set),
0305     .spec_pupd = mt8173_spec_pupd,
0306     .n_spec_pupd = ARRAY_SIZE(mt8173_spec_pupd),
0307     .spec_smt = mt8173_smt_set,
0308     .n_spec_smt = ARRAY_SIZE(mt8173_smt_set),
0309     .spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
0310     .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
0311     .dir_offset = 0x0000,
0312     .pullen_offset = 0x0100,
0313     .pullsel_offset = 0x0200,
0314     .dout_offset = 0x0400,
0315     .din_offset = 0x0500,
0316     .pinmux_offset = 0x0600,
0317     .type1_start = 135,
0318     .type1_end = 135,
0319     .port_shf = 4,
0320     .port_mask = 0xf,
0321     .port_align = 4,
0322     .mode_mask = 0xf,
0323     .mode_per_reg = 5,
0324     .mode_shf = 4,
0325     .eint_hw = {
0326         .port_mask = 7,
0327         .ports     = 6,
0328         .ap_num    = 224,
0329         .db_cnt    = 16,
0330     },
0331 };
0332 
0333 static int mt8173_pinctrl_probe(struct platform_device *pdev)
0334 {
0335     return mtk_pctrl_init(pdev, &mt8173_pinctrl_data, NULL);
0336 }
0337 
0338 static const struct of_device_id mt8173_pctrl_match[] = {
0339     {
0340         .compatible = "mediatek,mt8173-pinctrl",
0341     },
0342     { }
0343 };
0344 
0345 static struct platform_driver mtk_pinctrl_driver = {
0346     .probe = mt8173_pinctrl_probe,
0347     .driver = {
0348         .name = "mediatek-mt8173-pinctrl",
0349         .of_match_table = mt8173_pctrl_match,
0350         .pm = &mtk_eint_pm_ops,
0351     },
0352 };
0353 
0354 static int __init mtk_pinctrl_init(void)
0355 {
0356     return platform_driver_register(&mtk_pinctrl_driver);
0357 }
0358 arch_initcall(mtk_pinctrl_init);
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