pinctrl/mediatek/pinctrl-mt8167.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2020 MediaTek Inc.
0004  * Author: Min.Guo <min.guo@mediatek.com>
0005  */
0006
0007 #include <dt-bindings/pinctrl/mt65xx.h>
0008 #include <linux/of.h>
0009 #include <linux/of_device.h>
0010 #include <linux/module.h>
0011 #include <linux/pinctrl/pinctrl.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/regmap.h>
0014
0015 #include "pinctrl-mtk-common.h"
0016 #include "pinctrl-mtk-mt8167.h"
0017
0018 static const struct mtk_drv_group_desc mt8167_drv_grp[] = {
0019     /* 0E4E8SR 4/8/12/16 */
0020     MTK_DRV_GRP(4, 16, 1, 2, 4),
0021     /* 0E2E4SR  2/4/6/8 */
0022     MTK_DRV_GRP(2, 8, 1, 2, 2),
0023     /* E8E4E2  2/4/6/8/10/12/14/16 */
0024     MTK_DRV_GRP(2, 16, 0, 2, 2)
0025 };
0026
0027 static const struct mtk_pin_drv_grp mt8167_pin_drv[] = {
0028     MTK_PIN_DRV_GRP(0, 0xd00, 0, 0),
0029     MTK_PIN_DRV_GRP(1, 0xd00, 0, 0),
0030     MTK_PIN_DRV_GRP(2, 0xd00, 0, 0),
0031     MTK_PIN_DRV_GRP(3, 0xd00, 0, 0),
0032     MTK_PIN_DRV_GRP(4, 0xd00, 0, 0),
0033
0034     MTK_PIN_DRV_GRP(5, 0xd00, 4, 0),
0035     MTK_PIN_DRV_GRP(6, 0xd00, 4, 0),
0036     MTK_PIN_DRV_GRP(7, 0xd00, 4, 0),
0037     MTK_PIN_DRV_GRP(8, 0xd00, 4, 0),
0038     MTK_PIN_DRV_GRP(9, 0xd00, 4, 0),
0039     MTK_PIN_DRV_GRP(10, 0xd00, 4, 0),
0040
0041     MTK_PIN_DRV_GRP(11, 0xd00, 8, 0),
0042     MTK_PIN_DRV_GRP(12, 0xd00, 8, 0),
0043     MTK_PIN_DRV_GRP(13, 0xd00, 8, 0),
0044
0045     MTK_PIN_DRV_GRP(14, 0xd00, 12, 2),
0046     MTK_PIN_DRV_GRP(15, 0xd00, 12, 2),
0047     MTK_PIN_DRV_GRP(16, 0xd00, 12, 2),
0048     MTK_PIN_DRV_GRP(17, 0xd00, 12, 2),
0049
0050     MTK_PIN_DRV_GRP(18, 0xd10, 0, 0),
0051     MTK_PIN_DRV_GRP(19, 0xd10, 0, 0),
0052     MTK_PIN_DRV_GRP(20, 0xd10, 0, 0),
0053
0054     MTK_PIN_DRV_GRP(21, 0xd00, 12, 2),
0055     MTK_PIN_DRV_GRP(22, 0xd00, 12, 2),
0056     MTK_PIN_DRV_GRP(23, 0xd00, 12, 2),
0057
0058     MTK_PIN_DRV_GRP(24, 0xd00, 8, 0),
0059     MTK_PIN_DRV_GRP(25, 0xd00, 8, 0),
0060
0061     MTK_PIN_DRV_GRP(26, 0xd10, 4, 1),
0062     MTK_PIN_DRV_GRP(27, 0xd10, 4, 1),
0063     MTK_PIN_DRV_GRP(28, 0xd10, 4, 1),
0064     MTK_PIN_DRV_GRP(29, 0xd10, 4, 1),
0065     MTK_PIN_DRV_GRP(30, 0xd10, 4, 1),
0066
0067     MTK_PIN_DRV_GRP(31, 0xd10, 8, 1),
0068     MTK_PIN_DRV_GRP(32, 0xd10, 8, 1),
0069     MTK_PIN_DRV_GRP(33, 0xd10, 8, 1),
0070
0071     MTK_PIN_DRV_GRP(34, 0xd10, 12, 0),
0072     MTK_PIN_DRV_GRP(35, 0xd10, 12, 0),
0073
0074     MTK_PIN_DRV_GRP(36, 0xd20, 0, 0),
0075     MTK_PIN_DRV_GRP(37, 0xd20, 0, 0),
0076     MTK_PIN_DRV_GRP(38, 0xd20, 0, 0),
0077     MTK_PIN_DRV_GRP(39, 0xd20, 0, 0),
0078
0079     MTK_PIN_DRV_GRP(40, 0xd20, 4, 1),
0080
0081     MTK_PIN_DRV_GRP(41, 0xd20, 8, 1),
0082     MTK_PIN_DRV_GRP(42, 0xd20, 8, 1),
0083     MTK_PIN_DRV_GRP(43, 0xd20, 8, 1),
0084
0085     MTK_PIN_DRV_GRP(44, 0xd20, 12, 1),
0086     MTK_PIN_DRV_GRP(45, 0xd20, 12, 1),
0087     MTK_PIN_DRV_GRP(46, 0xd20, 12, 1),
0088     MTK_PIN_DRV_GRP(47, 0xd20, 12, 1),
0089
0090     MTK_PIN_DRV_GRP(48, 0xd30, 0, 1),
0091     MTK_PIN_DRV_GRP(49, 0xd30, 0, 1),
0092     MTK_PIN_DRV_GRP(50, 0xd30, 0, 1),
0093     MTK_PIN_DRV_GRP(51, 0xd30, 0, 1),
0094
0095     MTK_PIN_DRV_GRP(54, 0xd30, 8, 1),
0096
0097     MTK_PIN_DRV_GRP(55, 0xd30, 12, 1),
0098     MTK_PIN_DRV_GRP(56, 0xd30, 12, 1),
0099     MTK_PIN_DRV_GRP(57, 0xd30, 12, 1),
0100
0101     MTK_PIN_DRV_GRP(62, 0xd40, 8, 1),
0102     MTK_PIN_DRV_GRP(63, 0xd40, 8, 1),
0103     MTK_PIN_DRV_GRP(64, 0xd40, 8, 1),
0104     MTK_PIN_DRV_GRP(65, 0xd40, 8, 1),
0105     MTK_PIN_DRV_GRP(66, 0xd40, 8, 1),
0106     MTK_PIN_DRV_GRP(67, 0xd40, 8, 1),
0107
0108     MTK_PIN_DRV_GRP(68, 0xd40, 12, 2),
0109
0110     MTK_PIN_DRV_GRP(69, 0xd50, 0, 2),
0111
0112     MTK_PIN_DRV_GRP(70, 0xd50, 4, 2),
0113     MTK_PIN_DRV_GRP(71, 0xd50, 4, 2),
0114     MTK_PIN_DRV_GRP(72, 0xd50, 4, 2),
0115     MTK_PIN_DRV_GRP(73, 0xd50, 4, 2),
0116
0117     MTK_PIN_DRV_GRP(100, 0xd50, 8, 1),
0118     MTK_PIN_DRV_GRP(101, 0xd50, 8, 1),
0119     MTK_PIN_DRV_GRP(102, 0xd50, 8, 1),
0120     MTK_PIN_DRV_GRP(103, 0xd50, 8, 1),
0121
0122     MTK_PIN_DRV_GRP(104, 0xd50, 12, 2),
0123
0124     MTK_PIN_DRV_GRP(105, 0xd60, 0, 2),
0125
0126     MTK_PIN_DRV_GRP(106, 0xd60, 4, 2),
0127     MTK_PIN_DRV_GRP(107, 0xd60, 4, 2),
0128     MTK_PIN_DRV_GRP(108, 0xd60, 4, 2),
0129     MTK_PIN_DRV_GRP(109, 0xd60, 4, 2),
0130
0131     MTK_PIN_DRV_GRP(110, 0xd70, 0, 2),
0132     MTK_PIN_DRV_GRP(111, 0xd70, 0, 2),
0133     MTK_PIN_DRV_GRP(112, 0xd70, 0, 2),
0134     MTK_PIN_DRV_GRP(113, 0xd70, 0, 2),
0135
0136     MTK_PIN_DRV_GRP(114, 0xd70, 4, 2),
0137
0138     MTK_PIN_DRV_GRP(115, 0xd60, 12, 2),
0139
0140     MTK_PIN_DRV_GRP(116, 0xd60, 8, 2),
0141
0142     MTK_PIN_DRV_GRP(117, 0xd70, 0, 2),
0143     MTK_PIN_DRV_GRP(118, 0xd70, 0, 2),
0144     MTK_PIN_DRV_GRP(119, 0xd70, 0, 2),
0145     MTK_PIN_DRV_GRP(120, 0xd70, 0, 2),
0146 };
0147
0148 static const struct mtk_pin_spec_pupd_set_samereg mt8167_spec_pupd[] = {
0149     MTK_PIN_PUPD_SPEC_SR(14, 0xe50, 14, 13, 12),
0150     MTK_PIN_PUPD_SPEC_SR(15, 0xe60, 2, 1, 0),
0151     MTK_PIN_PUPD_SPEC_SR(16, 0xe60, 6, 5, 4),
0152     MTK_PIN_PUPD_SPEC_SR(17, 0xe60, 10, 9, 8),
0153
0154     MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 14, 13, 12),
0155     MTK_PIN_PUPD_SPEC_SR(22, 0xe70, 2, 1, 0),
0156     MTK_PIN_PUPD_SPEC_SR(23, 0xe70, 6, 5, 4),
0157
0158     MTK_PIN_PUPD_SPEC_SR(40, 0xe80, 2, 1, 0),
0159     MTK_PIN_PUPD_SPEC_SR(41, 0xe80, 6, 5, 4),
0160     MTK_PIN_PUPD_SPEC_SR(42, 0xe90, 2, 1, 0),
0161     MTK_PIN_PUPD_SPEC_SR(43, 0xe90, 6, 5, 4),
0162
0163     MTK_PIN_PUPD_SPEC_SR(68, 0xe50, 10, 9, 8),
0164     MTK_PIN_PUPD_SPEC_SR(69, 0xe50, 6, 5, 4),
0165     MTK_PIN_PUPD_SPEC_SR(70, 0xe40, 6, 5, 4),
0166     MTK_PIN_PUPD_SPEC_SR(71, 0xe40, 10, 9, 8),
0167     MTK_PIN_PUPD_SPEC_SR(72, 0xe40, 14, 13, 12),
0168     MTK_PIN_PUPD_SPEC_SR(73, 0xe50, 2, 1, 0),
0169
0170     MTK_PIN_PUPD_SPEC_SR(104, 0xe40, 2, 1, 0),
0171     MTK_PIN_PUPD_SPEC_SR(105, 0xe30, 14, 13, 12),
0172     MTK_PIN_PUPD_SPEC_SR(106, 0xe20, 14, 13, 12),
0173     MTK_PIN_PUPD_SPEC_SR(107, 0xe30, 2, 1, 0),
0174     MTK_PIN_PUPD_SPEC_SR(108, 0xe30, 6, 5, 4),
0175     MTK_PIN_PUPD_SPEC_SR(109, 0xe30, 10, 9, 8),
0176     MTK_PIN_PUPD_SPEC_SR(110, 0xe10, 14, 13, 12),
0177     MTK_PIN_PUPD_SPEC_SR(111, 0xe10, 10, 9, 8),
0178     MTK_PIN_PUPD_SPEC_SR(112, 0xe10, 6, 5, 4),
0179     MTK_PIN_PUPD_SPEC_SR(113, 0xe10, 2, 1, 0),
0180     MTK_PIN_PUPD_SPEC_SR(114, 0xe20, 10, 9, 8),
0181     MTK_PIN_PUPD_SPEC_SR(115, 0xe20, 2, 1, 0),
0182     MTK_PIN_PUPD_SPEC_SR(116, 0xe20, 6, 5, 4),
0183     MTK_PIN_PUPD_SPEC_SR(117, 0xe00, 14, 13, 12),
0184     MTK_PIN_PUPD_SPEC_SR(118, 0xe00, 10, 9, 8),
0185     MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 6, 5, 4),
0186     MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 2, 1, 0),
0187 };
0188
0189 static const struct mtk_pin_ies_smt_set mt8167_ies_set[] = {
0190     MTK_PIN_IES_SMT_SPEC(0, 6, 0x900, 2),
0191     MTK_PIN_IES_SMT_SPEC(7, 10, 0x900, 3),
0192     MTK_PIN_IES_SMT_SPEC(11, 13, 0x900, 12),
0193     MTK_PIN_IES_SMT_SPEC(14, 17, 0x900, 13),
0194     MTK_PIN_IES_SMT_SPEC(18, 20, 0x910, 10),
0195     MTK_PIN_IES_SMT_SPEC(21, 23, 0x900, 13),
0196     MTK_PIN_IES_SMT_SPEC(24, 25, 0x900, 12),
0197     MTK_PIN_IES_SMT_SPEC(26, 30, 0x900, 0),
0198     MTK_PIN_IES_SMT_SPEC(31, 33, 0x900, 1),
0199     MTK_PIN_IES_SMT_SPEC(34, 39, 0x900, 2),
0200     MTK_PIN_IES_SMT_SPEC(40, 40, 0x910, 11),
0201     MTK_PIN_IES_SMT_SPEC(41, 43, 0x900, 10),
0202     MTK_PIN_IES_SMT_SPEC(44, 47, 0x900, 11),
0203     MTK_PIN_IES_SMT_SPEC(48, 51, 0x900, 14),
0204     MTK_PIN_IES_SMT_SPEC(52, 53, 0x910, 0),
0205     MTK_PIN_IES_SMT_SPEC(54, 54, 0x910, 2),
0206     MTK_PIN_IES_SMT_SPEC(55, 57, 0x910, 4),
0207     MTK_PIN_IES_SMT_SPEC(58, 59, 0x900, 15),
0208     MTK_PIN_IES_SMT_SPEC(60, 61, 0x910, 1),
0209     MTK_PIN_IES_SMT_SPEC(62, 65, 0x910, 5),
0210     MTK_PIN_IES_SMT_SPEC(66, 67, 0x910, 6),
0211     MTK_PIN_IES_SMT_SPEC(68, 68, 0x930, 2),
0212     MTK_PIN_IES_SMT_SPEC(69, 69, 0x930, 1),
0213     MTK_PIN_IES_SMT_SPEC(70, 70, 0x930, 6),
0214     MTK_PIN_IES_SMT_SPEC(71, 71, 0x930, 5),
0215     MTK_PIN_IES_SMT_SPEC(72, 72, 0x930, 4),
0216     MTK_PIN_IES_SMT_SPEC(73, 73, 0x930, 3),
0217     MTK_PIN_IES_SMT_SPEC(100, 103, 0x910, 7),
0218     MTK_PIN_IES_SMT_SPEC(104, 104, 0x920, 12),
0219     MTK_PIN_IES_SMT_SPEC(105, 105, 0x920, 11),
0220     MTK_PIN_IES_SMT_SPEC(106, 106, 0x930, 0),
0221     MTK_PIN_IES_SMT_SPEC(107, 107, 0x920, 15),
0222     MTK_PIN_IES_SMT_SPEC(108, 108, 0x920, 14),
0223     MTK_PIN_IES_SMT_SPEC(109, 109, 0x920, 13),
0224     MTK_PIN_IES_SMT_SPEC(110, 110, 0x920, 9),
0225     MTK_PIN_IES_SMT_SPEC(111, 111, 0x920, 8),
0226     MTK_PIN_IES_SMT_SPEC(112, 112, 0x920, 7),
0227     MTK_PIN_IES_SMT_SPEC(113, 113, 0x920, 6),
0228     MTK_PIN_IES_SMT_SPEC(114, 114, 0x920, 10),
0229     MTK_PIN_IES_SMT_SPEC(115, 115, 0x920, 1),
0230     MTK_PIN_IES_SMT_SPEC(116, 116, 0x920, 0),
0231     MTK_PIN_IES_SMT_SPEC(117, 117, 0x920, 5),
0232     MTK_PIN_IES_SMT_SPEC(118, 118, 0x920, 4),
0233     MTK_PIN_IES_SMT_SPEC(119, 119, 0x920, 3),
0234     MTK_PIN_IES_SMT_SPEC(120, 120, 0x920, 2),
0235     MTK_PIN_IES_SMT_SPEC(121, 124, 0x910, 9),
0236 };
0237
0238 static const struct mtk_pin_ies_smt_set mt8167_smt_set[] = {
0239     MTK_PIN_IES_SMT_SPEC(0, 6, 0xA00, 2),
0240     MTK_PIN_IES_SMT_SPEC(7, 10, 0xA00, 3),
0241     MTK_PIN_IES_SMT_SPEC(11, 13, 0xA00, 12),
0242     MTK_PIN_IES_SMT_SPEC(14, 17, 0xA00, 13),
0243     MTK_PIN_IES_SMT_SPEC(18, 20, 0xA10, 10),
0244     MTK_PIN_IES_SMT_SPEC(21, 23, 0xA00, 13),
0245     MTK_PIN_IES_SMT_SPEC(24, 25, 0xA00, 12),
0246     MTK_PIN_IES_SMT_SPEC(26, 30, 0xA00, 0),
0247     MTK_PIN_IES_SMT_SPEC(31, 33, 0xA00, 1),
0248     MTK_PIN_IES_SMT_SPEC(34, 39, 0xA900, 2),
0249     MTK_PIN_IES_SMT_SPEC(40, 40, 0xA10, 11),
0250     MTK_PIN_IES_SMT_SPEC(41, 43, 0xA00, 10),
0251     MTK_PIN_IES_SMT_SPEC(44, 47, 0xA00, 11),
0252     MTK_PIN_IES_SMT_SPEC(48, 51, 0xA00, 14),
0253     MTK_PIN_IES_SMT_SPEC(52, 53, 0xA10, 0),
0254     MTK_PIN_IES_SMT_SPEC(54, 54, 0xA10, 2),
0255     MTK_PIN_IES_SMT_SPEC(55, 57, 0xA10, 4),
0256     MTK_PIN_IES_SMT_SPEC(58, 59, 0xA00, 15),
0257     MTK_PIN_IES_SMT_SPEC(60, 61, 0xA10, 1),
0258     MTK_PIN_IES_SMT_SPEC(62, 65, 0xA10, 5),
0259     MTK_PIN_IES_SMT_SPEC(66, 67, 0xA10, 6),
0260     MTK_PIN_IES_SMT_SPEC(68, 68, 0xA30, 2),
0261     MTK_PIN_IES_SMT_SPEC(69, 69, 0xA30, 1),
0262     MTK_PIN_IES_SMT_SPEC(70, 70, 0xA30, 3),
0263     MTK_PIN_IES_SMT_SPEC(71, 71, 0xA30, 4),
0264     MTK_PIN_IES_SMT_SPEC(72, 72, 0xA30, 5),
0265     MTK_PIN_IES_SMT_SPEC(73, 73, 0xA30, 6),
0266
0267     MTK_PIN_IES_SMT_SPEC(100, 103, 0xA10, 7),
0268     MTK_PIN_IES_SMT_SPEC(104, 104, 0xA20, 12),
0269     MTK_PIN_IES_SMT_SPEC(105, 105, 0xA20, 11),
0270     MTK_PIN_IES_SMT_SPEC(106, 106, 0xA30, 13),
0271     MTK_PIN_IES_SMT_SPEC(107, 107, 0xA20, 14),
0272     MTK_PIN_IES_SMT_SPEC(108, 108, 0xA20, 15),
0273     MTK_PIN_IES_SMT_SPEC(109, 109, 0xA30, 0),
0274     MTK_PIN_IES_SMT_SPEC(110, 110, 0xA20, 9),
0275     MTK_PIN_IES_SMT_SPEC(111, 111, 0xA20, 8),
0276     MTK_PIN_IES_SMT_SPEC(112, 112, 0xA20, 7),
0277     MTK_PIN_IES_SMT_SPEC(113, 113, 0xA20, 6),
0278     MTK_PIN_IES_SMT_SPEC(114, 114, 0xA20, 10),
0279     MTK_PIN_IES_SMT_SPEC(115, 115, 0xA20, 1),
0280     MTK_PIN_IES_SMT_SPEC(116, 116, 0xA20, 0),
0281     MTK_PIN_IES_SMT_SPEC(117, 117, 0xA20, 5),
0282     MTK_PIN_IES_SMT_SPEC(118, 118, 0xA20, 4),
0283     MTK_PIN_IES_SMT_SPEC(119, 119, 0xA20, 3),
0284     MTK_PIN_IES_SMT_SPEC(120, 120, 0xA20, 2),
0285     MTK_PIN_IES_SMT_SPEC(121, 124, 0xA10, 9),
0286 };
0287
0288 static const struct mtk_pinctrl_devdata mt8167_pinctrl_data = {
0289     .pins = mtk_pins_mt8167,
0290     .npins = ARRAY_SIZE(mtk_pins_mt8167),
0291     .grp_desc = mt8167_drv_grp,
0292     .n_grp_cls = ARRAY_SIZE(mt8167_drv_grp),
0293     .pin_drv_grp = mt8167_pin_drv,
0294     .n_pin_drv_grps = ARRAY_SIZE(mt8167_pin_drv),
0295     .spec_ies = mt8167_ies_set,
0296     .n_spec_ies = ARRAY_SIZE(mt8167_ies_set),
0297     .spec_pupd = mt8167_spec_pupd,
0298     .n_spec_pupd = ARRAY_SIZE(mt8167_spec_pupd),
0299     .spec_smt = mt8167_smt_set,
0300     .n_spec_smt = ARRAY_SIZE(mt8167_smt_set),
0301     .spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
0302     .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
0303     .dir_offset = 0x0000,
0304     .pullen_offset = 0x0500,
0305     .pullsel_offset = 0x0600,
0306     .dout_offset = 0x0100,
0307     .din_offset = 0x0200,
0308     .pinmux_offset = 0x0300,
0309     .type1_start = 125,
0310     .type1_end = 125,
0311     .port_shf = 4,
0312     .port_mask = 0xf,
0313     .port_align = 4,
0314     .mode_mask = 0xf,
0315     .mode_per_reg = 5,
0316     .mode_shf = 4,
0317     .eint_hw = {
0318         .port_mask = 7,
0319         .ports     = 6,
0320         .ap_num    = 169,
0321         .db_cnt    = 64,
0322     },
0323 };
0324
0325 static const struct of_device_id mt8167_pctrl_match[] = {
0326     { .compatible = "mediatek,mt8167-pinctrl", .data = &mt8167_pinctrl_data },
0327     {}
0328 };
0329
0330 MODULE_DEVICE_TABLE(of, mt8167_pctrl_match);
0331
0332 static struct platform_driver mtk_pinctrl_driver = {
0333     .probe = mtk_pctrl_common_probe,
0334     .driver = {
0335         .name = "mediatek-mt8167-pinctrl",
0336         .of_match_table = mt8167_pctrl_match,
0337         .pm = &mtk_eint_pm_ops,
0338     },
0339 };
0340
0341 static int __init mtk_pinctrl_init(void)
0342 {
0343     return platform_driver_register(&mtk_pinctrl_driver);
0344 }
0345 arch_initcall(mtk_pinctrl_init);