pinctrl/mediatek/pinctrl-mt8135.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2014 MediaTek Inc.
0004  * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
0005  */
0006
0007 #include <linux/init.h>
0008 #include <linux/platform_device.h>
0009 #include <linux/of.h>
0010 #include <linux/of_device.h>
0011 #include <linux/pinctrl/pinctrl.h>
0012 #include <linux/regmap.h>
0013 #include <dt-bindings/pinctrl/mt65xx.h>
0014
0015 #include "pinctrl-mtk-common.h"
0016 #include "pinctrl-mtk-mt8135.h"
0017
0018 #define DRV_BASE1               0x500
0019 #define DRV_BASE2               0x510
0020 #define PUPD_BASE1              0x400
0021 #define PUPD_BASE2              0x450
0022 #define R0_BASE1                0x4d0
0023 #define R1_BASE1                0x200
0024 #define R1_BASE2                0x250
0025
0026 struct mtk_spec_pull_set {
0027     unsigned char pin;
0028     unsigned char pupd_bit;
0029     unsigned short pupd_offset;
0030     unsigned short r0_offset;
0031     unsigned short r1_offset;
0032     unsigned char r0_bit;
0033     unsigned char r1_bit;
0034 };
0035
0036 #define SPEC_PULL(_pin, _pupd_offset, _pupd_bit, _r0_offset, \
0037     _r0_bit, _r1_offset, _r1_bit)   \
0038     {   \
0039         .pin = _pin,    \
0040         .pupd_offset = _pupd_offset,    \
0041         .pupd_bit = _pupd_bit,  \
0042         .r0_offset = _r0_offset, \
0043         .r0_bit = _r0_bit, \
0044         .r1_offset = _r1_offset, \
0045         .r1_bit = _r1_bit, \
0046     }
0047
0048 static const struct mtk_drv_group_desc mt8135_drv_grp[] =  {
0049     /* E8E4E2 2/4/6/8/10/12/14/16 */
0050     MTK_DRV_GRP(2, 16, 0, 2, 2),
0051     /* E8E4  4/8/12/16 */
0052     MTK_DRV_GRP(4, 16, 1, 2, 4),
0053     /* E4E2  2/4/6/8 */
0054     MTK_DRV_GRP(2, 8, 0, 1, 2),
0055     /* E16E8E4 4/8/12/16/20/24/28/32 */
0056     MTK_DRV_GRP(4, 32, 0, 2, 4)
0057 };
0058
0059 static const struct mtk_pin_drv_grp mt8135_pin_drv[] = {
0060     MTK_PIN_DRV_GRP(0, DRV_BASE1, 0, 0),
0061     MTK_PIN_DRV_GRP(1, DRV_BASE1, 0, 0),
0062     MTK_PIN_DRV_GRP(2, DRV_BASE1, 0, 0),
0063     MTK_PIN_DRV_GRP(3, DRV_BASE1, 0, 0),
0064     MTK_PIN_DRV_GRP(4, DRV_BASE1, 4, 0),
0065     MTK_PIN_DRV_GRP(5, DRV_BASE1, 8, 0),
0066     MTK_PIN_DRV_GRP(6, DRV_BASE1, 0, 0),
0067     MTK_PIN_DRV_GRP(7, DRV_BASE1, 0, 0),
0068     MTK_PIN_DRV_GRP(8, DRV_BASE1, 0, 0),
0069     MTK_PIN_DRV_GRP(9, DRV_BASE1, 0, 0),
0070
0071     MTK_PIN_DRV_GRP(10, DRV_BASE1, 12, 1),
0072     MTK_PIN_DRV_GRP(11, DRV_BASE1, 12, 1),
0073     MTK_PIN_DRV_GRP(12, DRV_BASE1, 12, 1),
0074     MTK_PIN_DRV_GRP(13, DRV_BASE1, 12, 1),
0075     MTK_PIN_DRV_GRP(14, DRV_BASE1, 12, 1),
0076     MTK_PIN_DRV_GRP(15, DRV_BASE1, 12, 1),
0077     MTK_PIN_DRV_GRP(16, DRV_BASE1, 12, 1),
0078     MTK_PIN_DRV_GRP(17, DRV_BASE1, 16, 1),
0079     MTK_PIN_DRV_GRP(18, DRV_BASE1, 16, 1),
0080     MTK_PIN_DRV_GRP(19, DRV_BASE1, 16, 1),
0081     MTK_PIN_DRV_GRP(20, DRV_BASE1, 16, 1),
0082     MTK_PIN_DRV_GRP(21, DRV_BASE1, 16, 1),
0083     MTK_PIN_DRV_GRP(22, DRV_BASE1, 16, 1),
0084     MTK_PIN_DRV_GRP(23, DRV_BASE1, 16, 1),
0085     MTK_PIN_DRV_GRP(24, DRV_BASE1, 16, 1),
0086     MTK_PIN_DRV_GRP(33, DRV_BASE1, 24, 1),
0087     MTK_PIN_DRV_GRP(34, DRV_BASE2, 12, 2),
0088     MTK_PIN_DRV_GRP(37, DRV_BASE2, 20, 1),
0089     MTK_PIN_DRV_GRP(38, DRV_BASE2, 20, 1),
0090     MTK_PIN_DRV_GRP(39, DRV_BASE2, 20, 1),
0091     MTK_PIN_DRV_GRP(40, DRV_BASE2, 24, 1),
0092     MTK_PIN_DRV_GRP(41, DRV_BASE2, 24, 1),
0093     MTK_PIN_DRV_GRP(42, DRV_BASE2, 24, 1),
0094     MTK_PIN_DRV_GRP(43, DRV_BASE2, 28, 1),
0095     MTK_PIN_DRV_GRP(44, DRV_BASE2, 28, 1),
0096     MTK_PIN_DRV_GRP(45, DRV_BASE2, 28, 1),
0097     MTK_PIN_DRV_GRP(46, DRV_BASE2, 28, 1),
0098     MTK_PIN_DRV_GRP(47, DRV_BASE2, 28, 1),
0099
0100     MTK_PIN_DRV_GRP(49, DRV_BASE2+0x10, 0, 1),
0101     MTK_PIN_DRV_GRP(50, DRV_BASE2+0x10, 4, 1),
0102     MTK_PIN_DRV_GRP(51, DRV_BASE2+0x10, 8, 1),
0103     MTK_PIN_DRV_GRP(52, DRV_BASE2+0x10, 12, 2),
0104     MTK_PIN_DRV_GRP(53, DRV_BASE2+0x10, 16, 1),
0105     MTK_PIN_DRV_GRP(54, DRV_BASE2+0x10, 20, 1),
0106     MTK_PIN_DRV_GRP(55, DRV_BASE2+0x10, 24, 1),
0107     MTK_PIN_DRV_GRP(56, DRV_BASE2+0x10, 28, 1),
0108
0109     MTK_PIN_DRV_GRP(57, DRV_BASE2+0x20, 0, 1),
0110     MTK_PIN_DRV_GRP(58, DRV_BASE2+0x20, 0, 1),
0111     MTK_PIN_DRV_GRP(59, DRV_BASE2+0x20, 0, 1),
0112     MTK_PIN_DRV_GRP(60, DRV_BASE2+0x20, 0, 1),
0113     MTK_PIN_DRV_GRP(61, DRV_BASE2+0x20, 0, 1),
0114     MTK_PIN_DRV_GRP(62, DRV_BASE2+0x20, 0, 1),
0115     MTK_PIN_DRV_GRP(63, DRV_BASE2+0x20, 4, 1),
0116     MTK_PIN_DRV_GRP(64, DRV_BASE2+0x20, 8, 1),
0117     MTK_PIN_DRV_GRP(65, DRV_BASE2+0x20, 12, 1),
0118     MTK_PIN_DRV_GRP(66, DRV_BASE2+0x20, 16, 1),
0119     MTK_PIN_DRV_GRP(67, DRV_BASE2+0x20, 20, 1),
0120     MTK_PIN_DRV_GRP(68, DRV_BASE2+0x20, 24, 1),
0121     MTK_PIN_DRV_GRP(69, DRV_BASE2+0x20, 28, 1),
0122
0123     MTK_PIN_DRV_GRP(70, DRV_BASE2+0x30, 0, 1),
0124     MTK_PIN_DRV_GRP(71, DRV_BASE2+0x30, 4, 1),
0125     MTK_PIN_DRV_GRP(72, DRV_BASE2+0x30, 8, 1),
0126     MTK_PIN_DRV_GRP(73, DRV_BASE2+0x30, 12, 1),
0127     MTK_PIN_DRV_GRP(74, DRV_BASE2+0x30, 16, 1),
0128     MTK_PIN_DRV_GRP(75, DRV_BASE2+0x30, 20, 1),
0129     MTK_PIN_DRV_GRP(76, DRV_BASE2+0x30, 24, 1),
0130     MTK_PIN_DRV_GRP(77, DRV_BASE2+0x30, 28, 3),
0131     MTK_PIN_DRV_GRP(78, DRV_BASE2+0x30, 28, 3),
0132
0133     MTK_PIN_DRV_GRP(79, DRV_BASE2+0x40, 0, 3),
0134     MTK_PIN_DRV_GRP(80, DRV_BASE2+0x40, 4, 3),
0135
0136     MTK_PIN_DRV_GRP(81, DRV_BASE2+0x30, 28, 3),
0137     MTK_PIN_DRV_GRP(82, DRV_BASE2+0x30, 28, 3),
0138
0139     MTK_PIN_DRV_GRP(83, DRV_BASE2+0x40, 8, 3),
0140     MTK_PIN_DRV_GRP(84, DRV_BASE2+0x40, 8, 3),
0141     MTK_PIN_DRV_GRP(85, DRV_BASE2+0x40, 12, 3),
0142     MTK_PIN_DRV_GRP(86, DRV_BASE2+0x40, 16, 3),
0143     MTK_PIN_DRV_GRP(87, DRV_BASE2+0x40, 8, 3),
0144     MTK_PIN_DRV_GRP(88, DRV_BASE2+0x40, 8, 3),
0145
0146     MTK_PIN_DRV_GRP(89, DRV_BASE2+0x50, 12, 0),
0147     MTK_PIN_DRV_GRP(90, DRV_BASE2+0x50, 12, 0),
0148     MTK_PIN_DRV_GRP(91, DRV_BASE2+0x50, 12, 0),
0149     MTK_PIN_DRV_GRP(92, DRV_BASE2+0x50, 12, 0),
0150     MTK_PIN_DRV_GRP(93, DRV_BASE2+0x50, 12, 0),
0151     MTK_PIN_DRV_GRP(94, DRV_BASE2+0x50, 12, 0),
0152     MTK_PIN_DRV_GRP(95, DRV_BASE2+0x50, 12, 0),
0153
0154     MTK_PIN_DRV_GRP(96, DRV_BASE1+0xb0, 28, 0),
0155
0156     MTK_PIN_DRV_GRP(97, DRV_BASE2+0x50, 12, 0),
0157     MTK_PIN_DRV_GRP(98, DRV_BASE2+0x50, 16, 0),
0158     MTK_PIN_DRV_GRP(99, DRV_BASE2+0x50, 20, 1),
0159     MTK_PIN_DRV_GRP(102, DRV_BASE2+0x50, 24, 1),
0160     MTK_PIN_DRV_GRP(103, DRV_BASE2+0x50, 28, 1),
0161
0162
0163     MTK_PIN_DRV_GRP(104, DRV_BASE2+0x60, 0, 1),
0164     MTK_PIN_DRV_GRP(105, DRV_BASE2+0x60, 4, 1),
0165     MTK_PIN_DRV_GRP(106, DRV_BASE2+0x60, 4, 1),
0166     MTK_PIN_DRV_GRP(107, DRV_BASE2+0x60, 4, 1),
0167     MTK_PIN_DRV_GRP(108, DRV_BASE2+0x60, 4, 1),
0168     MTK_PIN_DRV_GRP(109, DRV_BASE2+0x60, 8, 2),
0169     MTK_PIN_DRV_GRP(110, DRV_BASE2+0x60, 12, 2),
0170     MTK_PIN_DRV_GRP(111, DRV_BASE2+0x60, 16, 2),
0171     MTK_PIN_DRV_GRP(112, DRV_BASE2+0x60, 20, 2),
0172     MTK_PIN_DRV_GRP(113, DRV_BASE2+0x60, 24, 2),
0173     MTK_PIN_DRV_GRP(114, DRV_BASE2+0x60, 28, 2),
0174
0175     MTK_PIN_DRV_GRP(115, DRV_BASE2+0x70, 0, 2),
0176     MTK_PIN_DRV_GRP(116, DRV_BASE2+0x70, 4, 2),
0177     MTK_PIN_DRV_GRP(117, DRV_BASE2+0x70, 8, 2),
0178     MTK_PIN_DRV_GRP(118, DRV_BASE2+0x70, 12, 2),
0179     MTK_PIN_DRV_GRP(119, DRV_BASE2+0x70, 16, 2),
0180     MTK_PIN_DRV_GRP(120, DRV_BASE2+0x70, 20, 2),
0181
0182     MTK_PIN_DRV_GRP(181, DRV_BASE1+0xa0, 12, 1),
0183     MTK_PIN_DRV_GRP(182, DRV_BASE1+0xa0, 16, 1),
0184     MTK_PIN_DRV_GRP(183, DRV_BASE1+0xa0, 20, 1),
0185     MTK_PIN_DRV_GRP(184, DRV_BASE1+0xa0, 24, 1),
0186     MTK_PIN_DRV_GRP(185, DRV_BASE1+0xa0, 28, 1),
0187
0188     MTK_PIN_DRV_GRP(186, DRV_BASE1+0xb0, 0, 2),
0189     MTK_PIN_DRV_GRP(187, DRV_BASE1+0xb0, 0, 2),
0190     MTK_PIN_DRV_GRP(188, DRV_BASE1+0xb0, 0, 2),
0191     MTK_PIN_DRV_GRP(189, DRV_BASE1+0xb0, 0, 2),
0192     MTK_PIN_DRV_GRP(190, DRV_BASE1+0xb0, 4, 1),
0193     MTK_PIN_DRV_GRP(191, DRV_BASE1+0xb0, 8, 1),
0194     MTK_PIN_DRV_GRP(192, DRV_BASE1+0xb0, 12, 1),
0195
0196     MTK_PIN_DRV_GRP(197, DRV_BASE1+0xb0, 16, 0),
0197     MTK_PIN_DRV_GRP(198, DRV_BASE1+0xb0, 16, 0),
0198     MTK_PIN_DRV_GRP(199, DRV_BASE1+0xb0, 20, 0),
0199     MTK_PIN_DRV_GRP(200, DRV_BASE1+0xb0, 24, 0),
0200     MTK_PIN_DRV_GRP(201, DRV_BASE1+0xb0, 16, 0),
0201     MTK_PIN_DRV_GRP(202, DRV_BASE1+0xb0, 16, 0)
0202 };
0203
0204 static const struct mtk_spec_pull_set spec_pupd[] = {
0205     SPEC_PULL(0, PUPD_BASE1, 0, R0_BASE1, 9, R1_BASE1, 0),
0206     SPEC_PULL(1, PUPD_BASE1, 1, R0_BASE1, 8, R1_BASE1, 1),
0207     SPEC_PULL(2, PUPD_BASE1, 2, R0_BASE1, 7, R1_BASE1, 2),
0208     SPEC_PULL(3, PUPD_BASE1, 3, R0_BASE1, 6, R1_BASE1, 3),
0209     SPEC_PULL(4, PUPD_BASE1, 4, R0_BASE1, 1, R1_BASE1, 4),
0210     SPEC_PULL(5, PUPD_BASE1, 5, R0_BASE1, 0, R1_BASE1, 5),
0211     SPEC_PULL(6, PUPD_BASE1, 6, R0_BASE1, 5, R1_BASE1, 6),
0212     SPEC_PULL(7, PUPD_BASE1, 7, R0_BASE1, 4, R1_BASE1, 7),
0213     SPEC_PULL(8, PUPD_BASE1, 8, R0_BASE1, 3, R1_BASE1, 8),
0214     SPEC_PULL(9, PUPD_BASE1, 9, R0_BASE1, 2, R1_BASE1, 9),
0215     SPEC_PULL(89, PUPD_BASE2, 9, R0_BASE1, 18, R1_BASE2, 9),
0216     SPEC_PULL(90, PUPD_BASE2, 10, R0_BASE1, 19, R1_BASE2, 10),
0217     SPEC_PULL(91, PUPD_BASE2, 11, R0_BASE1, 23, R1_BASE2, 11),
0218     SPEC_PULL(92, PUPD_BASE2, 12, R0_BASE1, 24, R1_BASE2, 12),
0219     SPEC_PULL(93, PUPD_BASE2, 13, R0_BASE1, 25, R1_BASE2, 13),
0220     SPEC_PULL(94, PUPD_BASE2, 14, R0_BASE1, 22, R1_BASE2, 14),
0221     SPEC_PULL(95, PUPD_BASE2, 15, R0_BASE1, 20, R1_BASE2, 15),
0222     SPEC_PULL(96, PUPD_BASE2+0x10, 0, R0_BASE1, 16, R1_BASE2+0x10, 0),
0223     SPEC_PULL(97, PUPD_BASE2+0x10, 1, R0_BASE1, 21, R1_BASE2+0x10, 1),
0224     SPEC_PULL(98, PUPD_BASE2+0x10, 2, R0_BASE1, 17, R1_BASE2+0x10, 2),
0225     SPEC_PULL(197, PUPD_BASE1+0xc0, 5, R0_BASE1, 13, R1_BASE2+0xc0, 5),
0226     SPEC_PULL(198, PUPD_BASE2+0xc0, 6, R0_BASE1, 14, R1_BASE2+0xc0, 6),
0227     SPEC_PULL(199, PUPD_BASE2+0xc0, 7, R0_BASE1, 11, R1_BASE2+0xc0, 7),
0228     SPEC_PULL(200, PUPD_BASE2+0xc0, 8, R0_BASE1, 10, R1_BASE2+0xc0, 8),
0229     SPEC_PULL(201, PUPD_BASE2+0xc0, 9, R0_BASE1, 13, R1_BASE2+0xc0, 9),
0230     SPEC_PULL(202, PUPD_BASE2+0xc0, 10, R0_BASE1, 12, R1_BASE2+0xc0, 10)
0231 };
0232
0233 static int spec_pull_set(struct regmap *regmap,
0234         const struct mtk_pinctrl_devdata *devdata,
0235         unsigned int pin, bool isup, unsigned int r1r0)
0236 {
0237     unsigned int i;
0238     unsigned int reg_pupd, reg_set_r0, reg_set_r1;
0239     unsigned int reg_rst_r0, reg_rst_r1;
0240     unsigned char align = devdata->port_align;
0241     bool find = false;
0242
0243     for (i = 0; i < ARRAY_SIZE(spec_pupd); i++) {
0244         if (pin == spec_pupd[i].pin) {
0245             find = true;
0246             break;
0247         }
0248     }
0249
0250     if (!find)
0251         return -EINVAL;
0252
0253     if (isup)
0254         reg_pupd = spec_pupd[i].pupd_offset + align;
0255     else
0256         reg_pupd = spec_pupd[i].pupd_offset + (align << 1);
0257
0258     regmap_write(regmap, reg_pupd, spec_pupd[i].pupd_bit);
0259
0260     reg_set_r0 = spec_pupd[i].r0_offset + align;
0261     reg_rst_r0 = spec_pupd[i].r0_offset + (align << 1);
0262     reg_set_r1 = spec_pupd[i].r1_offset + align;
0263     reg_rst_r1 = spec_pupd[i].r1_offset + (align << 1);
0264
0265     switch (r1r0) {
0266     case MTK_PUPD_SET_R1R0_00:
0267         regmap_write(regmap, reg_rst_r0, spec_pupd[i].r0_bit);
0268         regmap_write(regmap, reg_rst_r1, spec_pupd[i].r1_bit);
0269         break;
0270     case MTK_PUPD_SET_R1R0_01:
0271         regmap_write(regmap, reg_set_r0, spec_pupd[i].r0_bit);
0272         regmap_write(regmap, reg_rst_r1, spec_pupd[i].r1_bit);
0273         break;
0274     case MTK_PUPD_SET_R1R0_10:
0275         regmap_write(regmap, reg_rst_r0, spec_pupd[i].r0_bit);
0276         regmap_write(regmap, reg_set_r1, spec_pupd[i].r1_bit);
0277         break;
0278     case MTK_PUPD_SET_R1R0_11:
0279         regmap_write(regmap, reg_set_r0, spec_pupd[i].r0_bit);
0280         regmap_write(regmap, reg_set_r1, spec_pupd[i].r1_bit);
0281         break;
0282     default:
0283         return -EINVAL;
0284     }
0285
0286     return 0;
0287 }
0288
0289 static const struct mtk_pinctrl_devdata mt8135_pinctrl_data = {
0290     .pins = mtk_pins_mt8135,
0291     .npins = ARRAY_SIZE(mtk_pins_mt8135),
0292     .grp_desc = mt8135_drv_grp,
0293     .n_grp_cls = ARRAY_SIZE(mt8135_drv_grp),
0294     .pin_drv_grp = mt8135_pin_drv,
0295     .n_pin_drv_grps = ARRAY_SIZE(mt8135_pin_drv),
0296     .spec_pull_set = spec_pull_set,
0297     .dir_offset = 0x0000,
0298     .ies_offset = 0x0100,
0299     .pullen_offset = 0x0200,
0300     .smt_offset = 0x0300,
0301     .pullsel_offset = 0x0400,
0302     .dout_offset = 0x0800,
0303     .din_offset = 0x0A00,
0304     .pinmux_offset = 0x0C00,
0305     .type1_start = 34,
0306     .type1_end = 149,
0307     .port_shf = 4,
0308     .port_mask = 0xf,
0309     .port_align = 4,
0310     .mode_mask = 0xf,
0311     .mode_per_reg = 5,
0312     .mode_shf = 4,
0313     .eint_hw = {
0314         .port_mask = 7,
0315         .ports     = 6,
0316         .ap_num    = 192,
0317         .db_cnt    = 16,
0318     },
0319 };
0320
0321 static const struct of_device_id mt8135_pctrl_match[] = {
0322     { .compatible = "mediatek,mt8135-pinctrl", .data = &mt8135_pinctrl_data },
0323     { }
0324 };
0325
0326 static struct platform_driver mtk_pinctrl_driver = {
0327     .probe = mtk_pctrl_common_probe,
0328     .driver = {
0329         .name = "mediatek-mt8135-pinctrl",
0330         .of_match_table = mt8135_pctrl_match,
0331     },
0332 };
0333
0334 static int __init mtk_pinctrl_init(void)
0335 {
0336     return platform_driver_register(&mtk_pinctrl_driver);
0337 }
0338 arch_initcall(mtk_pinctrl_init);