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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2015 MediaTek Inc.
0004  * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
0005  *         Yingjoe Chen <yingjoe.chen@mediatek.com>
0006  */
0007 
0008 #include <linux/init.h>
0009 #include <linux/platform_device.h>
0010 #include <linux/of.h>
0011 #include <linux/of_device.h>
0012 #include <linux/pinctrl/pinctrl.h>
0013 #include <linux/regmap.h>
0014 #include <dt-bindings/pinctrl/mt65xx.h>
0015 
0016 #include "pinctrl-mtk-common.h"
0017 #include "pinctrl-mtk-mt8127.h"
0018 
0019 static const struct mtk_drv_group_desc mt8127_drv_grp[] =  {
0020     /* 0E4E8SR 4/8/12/16 */
0021     MTK_DRV_GRP(4, 16, 1, 2, 4),
0022     /* 0E2E4SR  2/4/6/8 */
0023     MTK_DRV_GRP(2, 8, 1, 2, 2),
0024     /* E8E4E2  2/4/6/8/10/12/14/16 */
0025     MTK_DRV_GRP(2, 16, 0, 2, 2)
0026 };
0027 
0028 static const struct mtk_pin_drv_grp mt8127_pin_drv[] = {
0029     MTK_PIN_DRV_GRP(0,   0xb00,  0, 1),
0030     MTK_PIN_DRV_GRP(1,   0xb00,  0, 1),
0031     MTK_PIN_DRV_GRP(2,   0xb00,  0, 1),
0032     MTK_PIN_DRV_GRP(3,   0xb00,  0, 1),
0033     MTK_PIN_DRV_GRP(4,   0xb00,  0, 1),
0034     MTK_PIN_DRV_GRP(5,   0xb00,  0, 1),
0035     MTK_PIN_DRV_GRP(6,   0xb00,  0, 1),
0036     MTK_PIN_DRV_GRP(7,   0xb00, 12, 1),
0037     MTK_PIN_DRV_GRP(8,   0xb00, 12, 1),
0038     MTK_PIN_DRV_GRP(9,   0xb00, 12, 1),
0039     MTK_PIN_DRV_GRP(10,  0xb00,  8, 1),
0040     MTK_PIN_DRV_GRP(11,  0xb00,  8, 1),
0041     MTK_PIN_DRV_GRP(12,  0xb00,  8, 1),
0042     MTK_PIN_DRV_GRP(13,  0xb00,  8, 1),
0043     MTK_PIN_DRV_GRP(14,  0xb10,  4, 0),
0044     MTK_PIN_DRV_GRP(15,  0xb10,  4, 0),
0045     MTK_PIN_DRV_GRP(16,  0xb10,  4, 0),
0046     MTK_PIN_DRV_GRP(17,  0xb10,  4, 0),
0047     MTK_PIN_DRV_GRP(18,  0xb10,  8, 0),
0048     MTK_PIN_DRV_GRP(19,  0xb10,  8, 0),
0049     MTK_PIN_DRV_GRP(20,  0xb10,  8, 0),
0050     MTK_PIN_DRV_GRP(21,  0xb10,  8, 0),
0051     MTK_PIN_DRV_GRP(22,  0xb20,  0, 0),
0052     MTK_PIN_DRV_GRP(23,  0xb20,  0, 0),
0053     MTK_PIN_DRV_GRP(24,  0xb20,  0, 0),
0054     MTK_PIN_DRV_GRP(25,  0xb20,  0, 0),
0055     MTK_PIN_DRV_GRP(26,  0xb20,  0, 0),
0056     MTK_PIN_DRV_GRP(27,  0xb20,  4, 0),
0057     MTK_PIN_DRV_GRP(28,  0xb20,  4, 0),
0058     MTK_PIN_DRV_GRP(29,  0xb20,  4, 0),
0059     MTK_PIN_DRV_GRP(30,  0xb20,  4, 0),
0060     MTK_PIN_DRV_GRP(31,  0xb20,  4, 0),
0061     MTK_PIN_DRV_GRP(32,  0xb20,  4, 0),
0062     MTK_PIN_DRV_GRP(33,  0xb30,  4, 1),
0063     MTK_PIN_DRV_GRP(34,  0xb30,  8, 1),
0064     MTK_PIN_DRV_GRP(35,  0xb30,  8, 1),
0065     MTK_PIN_DRV_GRP(36,  0xb30,  8, 1),
0066     MTK_PIN_DRV_GRP(37,  0xb30,  8, 1),
0067     MTK_PIN_DRV_GRP(38,  0xb30,  8, 1),
0068     MTK_PIN_DRV_GRP(39,  0xb30, 12, 1),
0069     MTK_PIN_DRV_GRP(40,  0xb30, 12, 1),
0070     MTK_PIN_DRV_GRP(41,  0xb30, 12, 1),
0071     MTK_PIN_DRV_GRP(42,  0xb30, 12, 1),
0072     MTK_PIN_DRV_GRP(43,  0xb40, 12, 0),
0073     MTK_PIN_DRV_GRP(44,  0xb40, 12, 0),
0074     MTK_PIN_DRV_GRP(45,  0xb40, 12, 0),
0075     MTK_PIN_DRV_GRP(46,  0xb50,  0, 2),
0076     MTK_PIN_DRV_GRP(47,  0xb50,  0, 2),
0077     MTK_PIN_DRV_GRP(48,  0xb50,  0, 2),
0078     MTK_PIN_DRV_GRP(49,  0xb50,  0, 2),
0079     MTK_PIN_DRV_GRP(50,  0xb70,  0, 1),
0080     MTK_PIN_DRV_GRP(51,  0xb70,  0, 1),
0081     MTK_PIN_DRV_GRP(52,  0xb70,  0, 1),
0082     MTK_PIN_DRV_GRP(53,  0xb50, 12, 1),
0083     MTK_PIN_DRV_GRP(54,  0xb50, 12, 1),
0084     MTK_PIN_DRV_GRP(55,  0xb50, 12, 1),
0085     MTK_PIN_DRV_GRP(56,  0xb50, 12, 1),
0086     MTK_PIN_DRV_GRP(59,  0xb40,  4, 1),
0087     MTK_PIN_DRV_GRP(60,  0xb40,  0, 1),
0088     MTK_PIN_DRV_GRP(61,  0xb40,  0, 1),
0089     MTK_PIN_DRV_GRP(62,  0xb40,  0, 1),
0090     MTK_PIN_DRV_GRP(63,  0xb40,  4, 1),
0091     MTK_PIN_DRV_GRP(64,  0xb40,  4, 1),
0092     MTK_PIN_DRV_GRP(65,  0xb40,  4, 1),
0093     MTK_PIN_DRV_GRP(66,  0xb40,  8, 1),
0094     MTK_PIN_DRV_GRP(67,  0xb40,  8, 1),
0095     MTK_PIN_DRV_GRP(68,  0xb40,  8, 1),
0096     MTK_PIN_DRV_GRP(69,  0xb40,  8, 1),
0097     MTK_PIN_DRV_GRP(70,  0xb40,  8, 1),
0098     MTK_PIN_DRV_GRP(71,  0xb40,  8, 1),
0099     MTK_PIN_DRV_GRP(72,  0xb50,  4, 1),
0100     MTK_PIN_DRV_GRP(73,  0xb50,  4, 1),
0101     MTK_PIN_DRV_GRP(74,  0xb50,  4, 1),
0102     MTK_PIN_DRV_GRP(79,  0xb50,  8, 1),
0103     MTK_PIN_DRV_GRP(80,  0xb50,  8, 1),
0104     MTK_PIN_DRV_GRP(81,  0xb50,  8, 1),
0105     MTK_PIN_DRV_GRP(82,  0xb50,  8, 1),
0106     MTK_PIN_DRV_GRP(83,  0xb50,  8, 1),
0107     MTK_PIN_DRV_GRP(84,  0xb50,  8, 1),
0108     MTK_PIN_DRV_GRP(85,  0xce0,  0, 2),
0109     MTK_PIN_DRV_GRP(86,  0xcd0,  0, 2),
0110     MTK_PIN_DRV_GRP(87,  0xcf0,  0, 2),
0111     MTK_PIN_DRV_GRP(88,  0xcf0,  0, 2),
0112     MTK_PIN_DRV_GRP(89,  0xcf0,  0, 2),
0113     MTK_PIN_DRV_GRP(90,  0xcf0,  0, 2),
0114     MTK_PIN_DRV_GRP(117, 0xb60, 12, 1),
0115     MTK_PIN_DRV_GRP(118, 0xb60, 12, 1),
0116     MTK_PIN_DRV_GRP(119, 0xb60, 12, 1),
0117     MTK_PIN_DRV_GRP(120, 0xb60, 12, 1),
0118     MTK_PIN_DRV_GRP(121, 0xc80,  0, 2),
0119     MTK_PIN_DRV_GRP(122, 0xc70,  0, 2),
0120     MTK_PIN_DRV_GRP(123, 0xc90,  0, 2),
0121     MTK_PIN_DRV_GRP(124, 0xc90,  0, 2),
0122     MTK_PIN_DRV_GRP(125, 0xc90,  0, 2),
0123     MTK_PIN_DRV_GRP(126, 0xc90,  0, 2),
0124     MTK_PIN_DRV_GRP(127, 0xc20,  0, 2),
0125     MTK_PIN_DRV_GRP(128, 0xc20,  0, 2),
0126     MTK_PIN_DRV_GRP(129, 0xc20,  0, 2),
0127     MTK_PIN_DRV_GRP(130, 0xc20,  0, 2),
0128     MTK_PIN_DRV_GRP(131, 0xc20,  0, 2),
0129     MTK_PIN_DRV_GRP(132, 0xc10,  0, 2),
0130     MTK_PIN_DRV_GRP(133, 0xc00,  0, 2),
0131     MTK_PIN_DRV_GRP(134, 0xc20,  0, 2),
0132     MTK_PIN_DRV_GRP(135, 0xc20,  0, 2),
0133     MTK_PIN_DRV_GRP(136, 0xc20,  0, 2),
0134     MTK_PIN_DRV_GRP(137, 0xc20,  0, 2),
0135     MTK_PIN_DRV_GRP(142, 0xb50,  0, 2),
0136 };
0137 
0138 static const struct mtk_pin_spec_pupd_set_samereg mt8127_spec_pupd[] = {
0139     MTK_PIN_PUPD_SPEC_SR(33,  0xd90, 2, 0, 1),  /* KPROW0 */
0140     MTK_PIN_PUPD_SPEC_SR(34,  0xd90, 6, 4, 5),  /* KPROW1 */
0141     MTK_PIN_PUPD_SPEC_SR(35,  0xd90, 10, 8, 9), /* KPROW2 */
0142     MTK_PIN_PUPD_SPEC_SR(36,  0xda0, 2, 0, 1),  /* KPCOL0 */
0143     MTK_PIN_PUPD_SPEC_SR(37,  0xda0, 6, 4, 5),  /* KPCOL1 */
0144     MTK_PIN_PUPD_SPEC_SR(38,  0xda0, 10, 8, 9), /* KPCOL2 */
0145     MTK_PIN_PUPD_SPEC_SR(46,  0xdb0, 2, 0, 1),  /* EINT14 */
0146     MTK_PIN_PUPD_SPEC_SR(47,  0xdb0, 6, 4, 5),  /* EINT15 */
0147     MTK_PIN_PUPD_SPEC_SR(48,  0xdb0, 10, 8, 9), /* EINT16 */
0148     MTK_PIN_PUPD_SPEC_SR(49,  0xdb0, 14, 12, 13),   /* EINT17 */
0149     MTK_PIN_PUPD_SPEC_SR(85,  0xce0, 8, 10, 9), /* MSDC2_CMD */
0150     MTK_PIN_PUPD_SPEC_SR(86,  0xcd0, 8, 10, 9), /* MSDC2_CLK */
0151     MTK_PIN_PUPD_SPEC_SR(87,  0xd00, 0, 2, 1),  /* MSDC2_DAT0 */
0152     MTK_PIN_PUPD_SPEC_SR(88,  0xd00, 4, 6, 5),  /* MSDC2_DAT1 */
0153     MTK_PIN_PUPD_SPEC_SR(89,  0xd00, 8, 10, 9), /* MSDC2_DAT2 */
0154     MTK_PIN_PUPD_SPEC_SR(90,  0xd00, 12, 14, 13),   /* MSDC2_DAT3 */
0155     MTK_PIN_PUPD_SPEC_SR(121, 0xc80, 8, 10, 9), /* MSDC1_CMD */
0156     MTK_PIN_PUPD_SPEC_SR(122, 0xc70, 8, 10, 9), /* MSDC1_CLK */
0157     MTK_PIN_PUPD_SPEC_SR(123, 0xca0, 0, 2, 1),  /* MSDC1_DAT0 */
0158     MTK_PIN_PUPD_SPEC_SR(124, 0xca0, 4, 6, 5),  /* MSDC1_DAT1 */
0159     MTK_PIN_PUPD_SPEC_SR(125, 0xca0, 8, 10, 9), /* MSDC1_DAT2 */
0160     MTK_PIN_PUPD_SPEC_SR(126, 0xca0, 12, 14, 13),   /* MSDC1_DAT3 */
0161     MTK_PIN_PUPD_SPEC_SR(127, 0xc40, 12, 14, 13),   /* MSDC0_DAT7 */
0162     MTK_PIN_PUPD_SPEC_SR(128, 0xc40, 8, 10, 9), /* MSDC0_DAT6 */
0163     MTK_PIN_PUPD_SPEC_SR(129, 0xc40, 4, 6, 5),  /* MSDC0_DAT5 */
0164     MTK_PIN_PUPD_SPEC_SR(130, 0xc40, 0, 2, 1),  /* MSDC0_DAT4 */
0165     MTK_PIN_PUPD_SPEC_SR(131, 0xc50, 0, 2, 1),  /* MSDC0_RSTB */
0166     MTK_PIN_PUPD_SPEC_SR(132, 0xc10, 8, 10, 9), /* MSDC0_CMD */
0167     MTK_PIN_PUPD_SPEC_SR(133, 0xc00, 8, 10, 9), /* MSDC0_CLK */
0168     MTK_PIN_PUPD_SPEC_SR(134, 0xc30, 12, 14, 13),   /* MSDC0_DAT3 */
0169     MTK_PIN_PUPD_SPEC_SR(135, 0xc30, 8, 10, 9), /* MSDC0_DAT2 */
0170     MTK_PIN_PUPD_SPEC_SR(136, 0xc30, 4, 6, 5),  /* MSDC0_DAT1 */
0171     MTK_PIN_PUPD_SPEC_SR(137, 0xc30, 0, 2, 1),  /* MSDC0_DAT0 */
0172     MTK_PIN_PUPD_SPEC_SR(142, 0xdc0, 2, 0, 1),  /* EINT21 */
0173 };
0174 
0175 static const struct mtk_pin_ies_smt_set mt8127_ies_set[] = {
0176     MTK_PIN_IES_SMT_SPEC(0, 9, 0x900, 0),
0177     MTK_PIN_IES_SMT_SPEC(10, 13, 0x900, 1),
0178     MTK_PIN_IES_SMT_SPEC(14, 28, 0x900, 2),
0179     MTK_PIN_IES_SMT_SPEC(29, 32, 0x900, 3),
0180     MTK_PIN_IES_SMT_SPEC(33, 33, 0x910, 11),
0181     MTK_PIN_IES_SMT_SPEC(34, 38, 0x900, 10),
0182     MTK_PIN_IES_SMT_SPEC(39, 42, 0x900, 11),
0183     MTK_PIN_IES_SMT_SPEC(43, 45, 0x900, 12),
0184     MTK_PIN_IES_SMT_SPEC(46, 49, 0x900, 13),
0185     MTK_PIN_IES_SMT_SPEC(50, 52, 0x910, 10),
0186     MTK_PIN_IES_SMT_SPEC(53, 56, 0x900, 14),
0187     MTK_PIN_IES_SMT_SPEC(57, 58, 0x910, 0),
0188     MTK_PIN_IES_SMT_SPEC(59, 65, 0x910, 2),
0189     MTK_PIN_IES_SMT_SPEC(66, 71, 0x910, 3),
0190     MTK_PIN_IES_SMT_SPEC(72, 74, 0x910, 4),
0191     MTK_PIN_IES_SMT_SPEC(75, 76, 0x900, 15),
0192     MTK_PIN_IES_SMT_SPEC(77, 78, 0x910, 1),
0193     MTK_PIN_IES_SMT_SPEC(79, 82, 0x910, 5),
0194     MTK_PIN_IES_SMT_SPEC(83, 84, 0x910, 6),
0195     MTK_PIN_IES_SMT_SPEC(117, 120, 0x910, 7),
0196     MTK_PIN_IES_SMT_SPEC(121, 121, 0xc80, 4),
0197     MTK_PIN_IES_SMT_SPEC(122, 122, 0xc70, 4),
0198     MTK_PIN_IES_SMT_SPEC(123, 126, 0xc90, 4),
0199     MTK_PIN_IES_SMT_SPEC(127, 131, 0xc20, 4),
0200     MTK_PIN_IES_SMT_SPEC(132, 132, 0xc10, 4),
0201     MTK_PIN_IES_SMT_SPEC(133, 133, 0xc00, 4),
0202     MTK_PIN_IES_SMT_SPEC(134, 137, 0xc20, 4),
0203     MTK_PIN_IES_SMT_SPEC(138, 141, 0x910, 9),
0204     MTK_PIN_IES_SMT_SPEC(142, 142, 0x900, 13),
0205 };
0206 
0207 static const struct mtk_pin_ies_smt_set mt8127_smt_set[] = {
0208     MTK_PIN_IES_SMT_SPEC(0, 9, 0x920, 0),
0209     MTK_PIN_IES_SMT_SPEC(10, 13, 0x920, 1),
0210     MTK_PIN_IES_SMT_SPEC(14, 28, 0x920, 2),
0211     MTK_PIN_IES_SMT_SPEC(29, 32, 0x920, 3),
0212     MTK_PIN_IES_SMT_SPEC(33, 33, 0x930, 11),
0213     MTK_PIN_IES_SMT_SPEC(34, 38, 0x920, 10),
0214     MTK_PIN_IES_SMT_SPEC(39, 42, 0x920, 11),
0215     MTK_PIN_IES_SMT_SPEC(43, 45, 0x920, 12),
0216     MTK_PIN_IES_SMT_SPEC(46, 49, 0x920, 13),
0217     MTK_PIN_IES_SMT_SPEC(50, 52, 0x930, 10),
0218     MTK_PIN_IES_SMT_SPEC(53, 56, 0x920, 14),
0219     MTK_PIN_IES_SMT_SPEC(57, 58, 0x930, 0),
0220     MTK_PIN_IES_SMT_SPEC(59, 65, 0x930, 2),
0221     MTK_PIN_IES_SMT_SPEC(66, 71, 0x930, 3),
0222     MTK_PIN_IES_SMT_SPEC(72, 74, 0x930, 4),
0223     MTK_PIN_IES_SMT_SPEC(75, 76, 0x920, 15),
0224     MTK_PIN_IES_SMT_SPEC(77, 78, 0x930, 1),
0225     MTK_PIN_IES_SMT_SPEC(79, 82, 0x930, 5),
0226     MTK_PIN_IES_SMT_SPEC(83, 84, 0x930, 6),
0227     MTK_PIN_IES_SMT_SPEC(85, 85, 0xce0, 11),
0228     MTK_PIN_IES_SMT_SPEC(86, 86, 0xcd0, 11),
0229     MTK_PIN_IES_SMT_SPEC(87, 87, 0xd00, 3),
0230     MTK_PIN_IES_SMT_SPEC(88, 88, 0xd00, 7),
0231     MTK_PIN_IES_SMT_SPEC(89, 89, 0xd00, 11),
0232     MTK_PIN_IES_SMT_SPEC(90, 90, 0xd00, 15),
0233     MTK_PIN_IES_SMT_SPEC(117, 120, 0x930, 7),
0234     MTK_PIN_IES_SMT_SPEC(121, 121, 0xc80, 11),
0235     MTK_PIN_IES_SMT_SPEC(122, 122, 0xc70, 11),
0236     MTK_PIN_IES_SMT_SPEC(123, 123, 0xca0, 3),
0237     MTK_PIN_IES_SMT_SPEC(124, 124, 0xca0, 7),
0238     MTK_PIN_IES_SMT_SPEC(125, 125, 0xca0, 11),
0239     MTK_PIN_IES_SMT_SPEC(126, 126, 0xca0, 15),
0240     MTK_PIN_IES_SMT_SPEC(127, 127, 0xc40, 15),
0241     MTK_PIN_IES_SMT_SPEC(128, 128, 0xc40, 11),
0242     MTK_PIN_IES_SMT_SPEC(129, 129, 0xc40, 7),
0243     MTK_PIN_IES_SMT_SPEC(130, 130, 0xc40, 3),
0244     MTK_PIN_IES_SMT_SPEC(131, 131, 0xc50, 3),
0245     MTK_PIN_IES_SMT_SPEC(132, 132, 0xc10, 11),
0246     MTK_PIN_IES_SMT_SPEC(133, 133, 0xc00, 11),
0247     MTK_PIN_IES_SMT_SPEC(134, 134, 0xc30, 15),
0248     MTK_PIN_IES_SMT_SPEC(135, 135, 0xc30, 11),
0249     MTK_PIN_IES_SMT_SPEC(136, 136, 0xc30, 7),
0250     MTK_PIN_IES_SMT_SPEC(137, 137, 0xc30, 3),
0251     MTK_PIN_IES_SMT_SPEC(138, 141, 0x930, 9),
0252     MTK_PIN_IES_SMT_SPEC(142, 142, 0x920, 13),
0253 };
0254 
0255 static const struct mtk_pinctrl_devdata mt8127_pinctrl_data = {
0256     .pins = mtk_pins_mt8127,
0257     .npins = ARRAY_SIZE(mtk_pins_mt8127),
0258     .grp_desc = mt8127_drv_grp,
0259     .n_grp_cls = ARRAY_SIZE(mt8127_drv_grp),
0260     .pin_drv_grp = mt8127_pin_drv,
0261     .n_pin_drv_grps = ARRAY_SIZE(mt8127_pin_drv),
0262     .spec_ies = mt8127_ies_set,
0263     .n_spec_ies = ARRAY_SIZE(mt8127_ies_set),
0264     .spec_pupd = mt8127_spec_pupd,
0265     .n_spec_pupd = ARRAY_SIZE(mt8127_spec_pupd),
0266     .spec_smt = mt8127_smt_set,
0267     .n_spec_smt = ARRAY_SIZE(mt8127_smt_set),
0268     .spec_pull_set = mtk_pctrl_spec_pull_set_samereg,
0269     .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range,
0270     .dir_offset = 0x0000,
0271     .pullen_offset = 0x0100,
0272     .pullsel_offset = 0x0200,
0273     .dout_offset = 0x0400,
0274     .din_offset = 0x0500,
0275     .pinmux_offset = 0x0600,
0276     .type1_start = 143,
0277     .type1_end = 143,
0278     .port_shf = 4,
0279     .port_mask = 0xf,
0280     .port_align = 4,
0281     .mode_mask = 0xf,
0282     .mode_per_reg = 5,
0283     .mode_shf = 4,
0284     .eint_hw = {
0285         .port_mask = 7,
0286         .ports     = 6,
0287         .ap_num    = 143,
0288         .db_cnt    = 16,
0289     },
0290 };
0291 
0292 static const struct of_device_id mt8127_pctrl_match[] = {
0293     { .compatible = "mediatek,mt8127-pinctrl", .data = &mt8127_pinctrl_data },
0294     { }
0295 };
0296 
0297 static struct platform_driver mtk_pinctrl_driver = {
0298     .probe = mtk_pctrl_common_probe,
0299     .driver = {
0300         .name = "mediatek-mt8127-pinctrl",
0301         .of_match_table = mt8127_pctrl_match,
0302     },
0303 };
0304 
0305 static int __init mtk_pinctrl_init(void)
0306 {
0307     return platform_driver_register(&mtk_pinctrl_driver);
0308 }
0309 arch_initcall(mtk_pinctrl_init);
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