pinctrl/mediatek/pinctrl-mt7986.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * The MT7986 driver based on Linux generic pinctrl binding.
0004  *
0005  * Copyright (C) 2021 MediaTek Inc.
0006  * Author: Sam Shih <sam.shih@mediatek.com>
0007  */
0008
0009 #include "pinctrl-moore.h"
0010
0011 #define MT7986_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4)
0012 #define MT7986_NOT_BALLOUT_PIN(_number) { .number = _number, .name = NULL }
0013
0014 #define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,  \
0015             _x_bits)    \
0016         PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,  \
0017             _x_bits, 32, 0)
0018
0019 /**
0020  * enum - Locking variants of the iocfg bases
0021  *
0022  * MT7986 have multiple bases to program pin configuration listed as the below:
0023  * iocfg_rt:0x11c30000, iocfg_rb:0x11c40000, iocfg_lt:0x11e20000,
0024  * iocfg_lb:0x11e30000, iocfg_tr:0x11f00000, iocfg_tl:0x11f10000,
0025  * _i_based could be used to indicate what base the pin should be mapped into.
0026  *
0027  * Each iocfg register base control different group of pads on the SoC
0028  *
0029  *
0030  *  chip carrier
0031  *
0032  *      A  B  C  D  E  F  G  H
0033  *    +------------------------+
0034  *  8 | o  o  o  o  o  o  o  o |
0035  *  7 | o  o  o  o  o  o  o  o |
0036  *  6 | o  o  o  o  o  o  o  o |
0037  *  5 | o  o  o  o  o  o  o  o |
0038  *  4 | o  o  o  o  o  o  o  o |
0039  *  3 | o  o  o  o  o  o  o  o |
0040  *  2 | o  o  o  o  o  o  o  o |
0041  *  1 | o  o  o  o  o  o  o  o |
0042  *    +------------------------+
0043  *
0044  *  inside Chip carrier
0045  *
0046  *      A  B  C  D  E  F  G  H
0047  *    +------------------------+
0048  *  8 |                        |
0049  *  7 |        TL  TR          |
0050  *  6 |      +---------+       |
0051  *  5 |   LT |         | RT    |
0052  *  4 |      |         |       |
0053  *  3 |   LB |         | RB    |
0054  *  2 |      +---------+       |
0055  *  1 |                        |
0056  *    +------------------------+
0057  *
0058  */
0059
0060 enum {
0061     GPIO_BASE,
0062     IOCFG_RT_BASE,
0063     IOCFG_RB_BASE,
0064     IOCFG_LT_BASE,
0065     IOCFG_LB_BASE,
0066     IOCFG_TR_BASE,
0067     IOCFG_TL_BASE,
0068 };
0069
0070 static const char *const mt7986_pinctrl_register_base_names[] = {
0071     "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt", "iocfg_lb", "iocfg_tr",
0072     "iocfg_tl",
0073 };
0074
0075 static const struct mtk_pin_field_calc mt7986_pin_mode_range[] = {
0076     PIN_FIELD(0, 100, 0x300, 0x10, 0, 4),
0077 };
0078
0079 static const struct mtk_pin_field_calc mt7986_pin_dir_range[] = {
0080     PIN_FIELD(0, 100, 0x0, 0x10, 0, 1),
0081 };
0082
0083 static const struct mtk_pin_field_calc mt7986_pin_di_range[] = {
0084     PIN_FIELD(0, 100, 0x200, 0x10, 0, 1),
0085 };
0086
0087 static const struct mtk_pin_field_calc mt7986_pin_do_range[] = {
0088     PIN_FIELD(0, 100, 0x100, 0x10, 0, 1),
0089 };
0090
0091 static const struct mtk_pin_field_calc mt7986_pin_ies_range[] = {
0092     PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x40, 0x10, 17, 1),
0093     PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x20, 0x10, 10, 1),
0094     PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x20, 0x10, 0, 1),
0095     PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x40, 0x10, 0, 1),
0096     PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x20, 0x10, 0, 1),
0097     PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x40, 0x10, 8, 1),
0098     PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x40, 0x10, 2, 1),
0099     PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x30, 0x10, 12, 1),
0100     PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x30, 0x10, 18, 1),
0101     PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x30, 0x10, 17, 1),
0102     PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x30, 0x10, 15, 1),
0103     PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x30, 0x10, 19, 1),
0104     PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x30, 0x10, 23, 1),
0105     PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x30, 0x10, 22, 1),
0106     PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x30, 0x10, 21, 1),
0107     PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x20, 0x10, 4, 1),
0108     PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x20, 0x10, 8, 1),
0109     PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x20, 0x10, 7, 1),
0110     PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x20, 0x10, 5, 1),
0111     PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x20, 0x10, 9, 1),
0112     PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x40, 0x10, 18, 1),
0113     PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x40, 0x10, 12, 1),
0114     PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x40, 0x10, 22, 1),
0115     PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x40, 0x10, 20, 1),
0116     PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x40, 0x10, 26, 1),
0117     PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x40, 0x10, 24, 1),
0118     PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x30, 0x10, 2, 1),
0119     PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x30, 0x10, 1, 1),
0120     PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x30, 0x10, 0, 1),
0121     PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x30, 0x10, 10, 1),
0122     PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x40, 0x10, 15, 1),
0123     PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x40, 0x10, 14, 1),
0124     PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x40, 0x10, 13, 1),
0125     PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x40, 0x10, 16, 1),
0126     PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x20, 0x10, 2, 1),
0127     PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x30, 0x10, 1, 1),
0128     PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x30, 0x10, 0, 1),
0129     PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x30, 0x10, 16, 1),
0130     PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x30, 0x10, 14, 1),
0131     PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x30, 0x10, 4, 1),
0132     PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x30, 0x10, 6, 1),
0133     PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x30, 0x10, 2, 1),
0134     PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x30, 0x10, 9, 1),
0135     PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x30, 0x10, 5, 1),
0136     PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x30, 0x10, 1, 1),
0137     PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x30, 0x10, 0, 1),
0138     PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x30, 0x10, 14, 1),
0139     PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x30, 0x10, 12, 1),
0140     PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x30, 0x10, 4, 1),
0141     PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x30, 0x10, 2, 1),
0142     PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x30, 0x10, 8, 1),
0143 };
0144
0145 static const struct mtk_pin_field_calc mt7986_pin_smt_range[] = {
0146     PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0xf0, 0x10, 17, 1),
0147     PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x90, 0x10, 10, 1),
0148     PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x90, 0x10, 0, 1),
0149     PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0xf0, 0x10, 0, 1),
0150     PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x90, 0x10, 0, 1),
0151     PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0xf0, 0x10, 8, 1),
0152     PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0xf0, 0x10, 2, 1),
0153     PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0xc0, 0x10, 12, 1),
0154     PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0xc0, 0x10, 18, 1),
0155     PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0xc0, 0x10, 17, 1),
0156     PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0xc0, 0x10, 15, 1),
0157     PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0xc0, 0x10, 19, 1),
0158     PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0xc0, 0x10, 23, 1),
0159     PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0xc0, 0x10, 22, 1),
0160     PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0xc0, 0x10, 21, 1),
0161     PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x90, 0x10, 4, 1),
0162     PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x90, 0x10, 8, 1),
0163     PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x90, 0x10, 7, 1),
0164     PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x90, 0x10, 5, 1),
0165     PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x90, 0x10, 9, 1),
0166     PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0xf0, 0x10, 18, 1),
0167     PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0xf0, 0x10, 12, 1),
0168     PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0xf0, 0x10, 22, 1),
0169     PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0xf0, 0x10, 20, 1),
0170     PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0xf0, 0x10, 26, 1),
0171     PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0xf0, 0x10, 24, 1),
0172     PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0xc0, 0x10, 2, 1),
0173     PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0xc0, 0x10, 1, 1),
0174     PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0xc0, 0x10, 0, 1),
0175     PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0xc0, 0x10, 10, 1),
0176     PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0xf0, 0x10, 15, 1),
0177     PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0xf0, 0x10, 14, 1),
0178     PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0xf0, 0x10, 13, 1),
0179     PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0xf0, 0x10, 16, 1),
0180     PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x90, 0x10, 2, 1),
0181     PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x80, 0x10, 1, 1),
0182     PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x80, 0x10, 0, 1),
0183     PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x80, 0x10, 16, 1),
0184     PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x80, 0x10, 14, 1),
0185     PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x80, 0x10, 4, 1),
0186     PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x80, 0x10, 6, 1),
0187     PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x80, 0x10, 2, 1),
0188     PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x80, 0x10, 9, 1),
0189     PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x80, 0x10, 5, 1),
0190     PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x70, 0x10, 1, 1),
0191     PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x70, 0x10, 0, 1),
0192     PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x70, 0x10, 14, 1),
0193     PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x70, 0x10, 12, 1),
0194     PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x70, 0x10, 4, 1),
0195     PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x70, 0x10, 2, 1),
0196     PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x70, 0x10, 8, 1),
0197 };
0198
0199 static const struct mtk_pin_field_calc mt7986_pin_pu_range[] = {
0200     PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x50, 0x10, 1, 1),
0201     PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x50, 0x10, 0, 1),
0202     PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x50, 0x10, 16, 1),
0203     PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x50, 0x10, 14, 1),
0204     PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x50, 0x10, 4, 1),
0205     PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x50, 0x10, 6, 1),
0206     PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x50, 0x10, 2, 1),
0207     PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x50, 0x10, 9, 1),
0208     PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x50, 0x10, 5, 1),
0209     PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x50, 0x10, 1, 1),
0210     PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x50, 0x10, 0, 1),
0211     PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x50, 0x10, 14, 1),
0212     PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x50, 0x10, 12, 1),
0213     PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x50, 0x10, 4, 1),
0214     PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x50, 0x10, 2, 1),
0215     PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x50, 0x10, 8, 1),
0216 };
0217
0218 static const struct mtk_pin_field_calc mt7986_pin_pd_range[] = {
0219     PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x40, 0x10, 1, 1),
0220     PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x40, 0x10, 0, 1),
0221     PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x40, 0x10, 16, 1),
0222     PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x40, 0x10, 14, 1),
0223     PIN_FIELD_BASE(74, 74, IOCFG_TR_BASE, 0x40, 0x10, 4, 1),
0224     PIN_FIELD_BASE(75, 77, IOCFG_TR_BASE, 0x40, 0x10, 6, 1),
0225     PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x40, 0x10, 2, 1),
0226     PIN_FIELD_BASE(80, 84, IOCFG_TR_BASE, 0x40, 0x10, 9, 1),
0227     PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x40, 0x10, 5, 1),
0228     PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x40, 0x10, 1, 1),
0229     PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x40, 0x10, 0, 1),
0230     PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x40, 0x10, 14, 1),
0231     PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x40, 0x10, 12, 1),
0232     PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x40, 0x10, 4, 1),
0233     PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x40, 0x10, 2, 1),
0234     PIN_FIELD_BASE(97, 100, IOCFG_TL_BASE, 0x40, 0x10, 8, 1),
0235 };
0236
0237 static const struct mtk_pin_field_calc mt7986_pin_drv_range[] = {
0238     PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x10, 0x10, 21, 3),
0239     PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x10, 0x10, 0, 3),
0240     PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x00, 0x10, 0, 1),
0241     PIN_FIELD_BASE(5, 5, IOCFG_RB_BASE, 0x00, 0x10, 0, 3),
0242     PIN_FIELD_BASE(6, 6, IOCFG_RB_BASE, 0x00, 0x10, 21, 3),
0243     PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x00, 0x10, 0, 3),
0244     PIN_FIELD_BASE(11, 12, IOCFG_RB_BASE, 0x00, 0x10, 24, 3),
0245     PIN_FIELD_BASE(13, 14, IOCFG_RB_BASE, 0x10, 0x10, 0, 3),
0246     PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x00, 0x10, 3, 3),
0247     PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x10, 0x10, 6, 3),
0248     PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x10, 0x10, 24, 3),
0249     PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x10, 0x10, 21, 3),
0250     PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x10, 0x10, 15, 3),
0251     PIN_FIELD_BASE(28, 28, IOCFG_RT_BASE, 0x10, 0x10, 27, 3),
0252     PIN_FIELD_BASE(29, 29, IOCFG_RT_BASE, 0x20, 0x10, 0, 3),
0253     PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x20, 0x10, 9, 3),
0254     PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x20, 0x10, 6, 3),
0255     PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x20, 0x10, 3, 3),
0256     PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x00, 0x10, 12, 3),
0257     PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x00, 0x10, 24, 3),
0258     PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x00, 0x10, 21, 3),
0259     PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x00, 0x10, 15, 3),
0260     PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x00, 0x10, 27, 3),
0261     PIN_FIELD_BASE(39, 39, IOCFG_RB_BASE, 0x10, 0x10, 27, 3),
0262     PIN_FIELD_BASE(40, 40, IOCFG_RB_BASE, 0x20, 0x10, 0, 3),
0263     PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x10, 0x10, 6, 3),
0264     PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x20, 0x10, 9, 3),
0265     PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x20, 0x10, 3, 3),
0266     PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x20, 0x10, 21, 3),
0267     PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x20, 0x10, 15, 3),
0268     PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x00, 0x10, 6, 3),
0269     PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x00, 0x10, 3, 3),
0270     PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x00, 0x10, 0, 3),
0271     PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x10, 0x10, 0, 3),
0272     PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x10, 0x10, 15, 3),
0273     PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x10, 0x10, 12, 3),
0274     PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x10, 0x10, 9, 3),
0275     PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x10, 0x10, 18, 3),
0276     PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x00, 0x10, 2, 3),
0277     PIN_FIELD_BASE(69, 69, IOCFG_TR_BASE, 0x00, 0x10, 3, 3),
0278     PIN_FIELD_BASE(70, 70, IOCFG_TR_BASE, 0x00, 0x10, 0, 3),
0279     PIN_FIELD_BASE(71, 71, IOCFG_TR_BASE, 0x10, 0x10, 18, 3),
0280     PIN_FIELD_BASE(72, 73, IOCFG_TR_BASE, 0x10, 0x10, 12, 3),
0281     PIN_FIELD_BASE(74, 77, IOCFG_TR_BASE, 0x00, 0x10, 15, 3),
0282     PIN_FIELD_BASE(78, 79, IOCFG_TR_BASE, 0x00, 0x10, 6, 3),
0283     PIN_FIELD_BASE(80, 80, IOCFG_TR_BASE, 0x00, 0x10, 27, 3),
0284     PIN_FIELD_BASE(81, 84, IOCFG_TR_BASE, 0x10, 0x10, 0, 3),
0285     PIN_FIELD_BASE(85, 85, IOCFG_TR_BASE, 0x00, 0x10, 12, 3),
0286     PIN_FIELD_BASE(86, 86, IOCFG_TL_BASE, 0x00, 0x10, 3, 3),
0287     PIN_FIELD_BASE(87, 87, IOCFG_TL_BASE, 0x00, 0x10, 0, 3),
0288     PIN_FIELD_BASE(88, 88, IOCFG_TL_BASE, 0x10, 0x10, 12, 3),
0289     PIN_FIELD_BASE(89, 90, IOCFG_TL_BASE, 0x10, 0x10, 6, 3),
0290     PIN_FIELD_BASE(91, 94, IOCFG_TL_BASE, 0x00, 0x10, 12, 3),
0291     PIN_FIELD_BASE(95, 96, IOCFG_TL_BASE, 0x00, 0x10, 6, 3),
0292     PIN_FIELD_BASE(97, 98, IOCFG_TL_BASE, 0x00, 0x10, 24, 3),
0293     PIN_FIELD_BASE(99, 100, IOCFG_TL_BASE, 0x10, 0x10, 2, 3),
0294 };
0295
0296 static const struct mtk_pin_field_calc mt7986_pin_pupd_range[] = {
0297     PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x60, 0x10, 17, 1),
0298     PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x30, 0x10, 10, 1),
0299     PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x40, 0x10, 0, 1),
0300     PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x60, 0x10, 0, 1),
0301     PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x30, 0x10, 0, 1),
0302     PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x60, 0x10, 8, 1),
0303     PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x60, 0x10, 2, 1),
0304     PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x40, 0x10, 12, 1),
0305     PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x40, 0x10, 18, 1),
0306     PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x40, 0x10, 17, 1),
0307     PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x40, 0x10, 15, 1),
0308     PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x40, 0x10, 19, 1),
0309     PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x40, 0x10, 23, 1),
0310     PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x40, 0x10, 22, 1),
0311     PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x40, 0x10, 21, 1),
0312     PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x30, 0x10, 4, 1),
0313     PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x30, 0x10, 8, 1),
0314     PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x30, 0x10, 7, 1),
0315     PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x30, 0x10, 5, 1),
0316     PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x30, 0x10, 9, 1),
0317     PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x60, 0x10, 18, 1),
0318     PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x60, 0x10, 12, 1),
0319     PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x60, 0x10, 22, 1),
0320     PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x60, 0x10, 20, 1),
0321     PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x60, 0x10, 26, 1),
0322     PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x60, 0x10, 24, 1),
0323     PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x40, 0x10, 2, 1),
0324     PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x40, 0x10, 1, 1),
0325     PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x40, 0x10, 0, 1),
0326     PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x40, 0x10, 10, 1),
0327     PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x60, 0x10, 15, 1),
0328     PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x60, 0x10, 14, 1),
0329     PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x60, 0x10, 13, 1),
0330     PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x60, 0x10, 16, 1),
0331     PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x40, 0x10, 2, 1),
0332 };
0333
0334 static const struct mtk_pin_field_calc mt7986_pin_r0_range[] = {
0335     PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x70, 0x10, 17, 1),
0336     PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x40, 0x10, 10, 1),
0337     PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x50, 0x10, 0, 1),
0338     PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x70, 0x10, 0, 1),
0339     PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x40, 0x10, 0, 1),
0340     PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x70, 0x10, 8, 1),
0341     PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x70, 0x10, 2, 1),
0342     PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x50, 0x10, 12, 1),
0343     PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x50, 0x10, 18, 1),
0344     PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x50, 0x10, 17, 1),
0345     PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x50, 0x10, 15, 1),
0346     PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x50, 0x10, 19, 1),
0347     PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x50, 0x10, 23, 1),
0348     PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x50, 0x10, 22, 1),
0349     PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x50, 0x10, 21, 1),
0350     PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x40, 0x10, 4, 1),
0351     PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x40, 0x10, 8, 1),
0352     PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x40, 0x10, 7, 1),
0353     PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x40, 0x10, 5, 1),
0354     PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x40, 0x10, 9, 1),
0355     PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x70, 0x10, 18, 1),
0356     PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x70, 0x10, 12, 1),
0357     PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x70, 0x10, 22, 1),
0358     PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x70, 0x10, 20, 1),
0359     PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x70, 0x10, 26, 1),
0360     PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x70, 0x10, 24, 1),
0361     PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x50, 0x10, 2, 1),
0362     PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x50, 0x10, 1, 1),
0363     PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x50, 0x10, 0, 1),
0364     PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x50, 0x10, 10, 1),
0365     PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x70, 0x10, 15, 1),
0366     PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x70, 0x10, 14, 1),
0367     PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x70, 0x10, 13, 1),
0368     PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x70, 0x10, 16, 1),
0369     PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x50, 0x10, 2, 1),
0370 };
0371
0372 static const struct mtk_pin_field_calc mt7986_pin_r1_range[] = {
0373     PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x80, 0x10, 17, 1),
0374     PIN_FIELD_BASE(1, 2, IOCFG_LT_BASE, 0x50, 0x10, 10, 1),
0375     PIN_FIELD_BASE(3, 4, IOCFG_LB_BASE, 0x60, 0x10, 0, 1),
0376     PIN_FIELD_BASE(5, 6, IOCFG_RB_BASE, 0x80, 0x10, 0, 1),
0377     PIN_FIELD_BASE(7, 10, IOCFG_LT_BASE, 0x50, 0x10, 0, 1),
0378     PIN_FIELD_BASE(11, 14, IOCFG_RB_BASE, 0x80, 0x10, 8, 1),
0379     PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x80, 0x10, 2, 1),
0380     PIN_FIELD_BASE(21, 23, IOCFG_RT_BASE, 0x60, 0x10, 12, 1),
0381     PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x60, 0x10, 18, 1),
0382     PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x60, 0x10, 17, 1),
0383     PIN_FIELD_BASE(26, 27, IOCFG_RT_BASE, 0x60, 0x10, 15, 1),
0384     PIN_FIELD_BASE(28, 29, IOCFG_RT_BASE, 0x60, 0x10, 19, 1),
0385     PIN_FIELD_BASE(30, 30, IOCFG_RT_BASE, 0x60, 0x10, 23, 1),
0386     PIN_FIELD_BASE(31, 31, IOCFG_RT_BASE, 0x60, 0x10, 22, 1),
0387     PIN_FIELD_BASE(32, 32, IOCFG_RT_BASE, 0x60, 0x10, 21, 1),
0388     PIN_FIELD_BASE(33, 33, IOCFG_LT_BASE, 0x50, 0x10, 4, 1),
0389     PIN_FIELD_BASE(34, 34, IOCFG_LT_BASE, 0x50, 0x10, 8, 1),
0390     PIN_FIELD_BASE(35, 35, IOCFG_LT_BASE, 0x50, 0x10, 7, 1),
0391     PIN_FIELD_BASE(36, 37, IOCFG_LT_BASE, 0x50, 0x10, 5, 1),
0392     PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x50, 0x10, 9, 1),
0393     PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x80, 0x10, 18, 1),
0394     PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x80, 0x10, 12, 1),
0395     PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x80, 0x10, 22, 1),
0396     PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x80, 0x10, 20, 1),
0397     PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x80, 0x10, 26, 1),
0398     PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x80, 0x10, 24, 1),
0399     PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x60, 0x10, 2, 1),
0400     PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x60, 0x10, 1, 1),
0401     PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x60, 0x10, 0, 1),
0402     PIN_FIELD_BASE(60, 61, IOCFG_RT_BASE, 0x60, 0x10, 10, 1),
0403     PIN_FIELD_BASE(62, 62, IOCFG_RB_BASE, 0x80, 0x10, 15, 1),
0404     PIN_FIELD_BASE(63, 63, IOCFG_RB_BASE, 0x80, 0x10, 14, 1),
0405     PIN_FIELD_BASE(64, 64, IOCFG_RB_BASE, 0x80, 0x10, 13, 1),
0406     PIN_FIELD_BASE(65, 65, IOCFG_RB_BASE, 0x80, 0x10, 16, 1),
0407     PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x60, 0x10, 2, 1),
0408 };
0409
0410 static const struct mtk_pin_reg_calc mt7986_reg_cals[] = {
0411     [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7986_pin_mode_range),
0412     [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7986_pin_dir_range),
0413     [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7986_pin_di_range),
0414     [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7986_pin_do_range),
0415     [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7986_pin_smt_range),
0416     [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7986_pin_ies_range),
0417     [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7986_pin_drv_range),
0418     [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7986_pin_pu_range),
0419     [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7986_pin_pd_range),
0420     [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7986_pin_pupd_range),
0421     [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7986_pin_r0_range),
0422     [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7986_pin_r1_range),
0423 };
0424
0425 static const struct mtk_pin_desc mt7986a_pins[] = {
0426     MT7986_PIN(0, "SYS_WATCHDOG"),
0427     MT7986_PIN(1, "WF2G_LED"),
0428     MT7986_PIN(2, "WF5G_LED"),
0429     MT7986_PIN(3, "I2C_SCL"),
0430     MT7986_PIN(4, "I2C_SDA"),
0431     MT7986_PIN(5, "GPIO_0"),
0432     MT7986_PIN(6, "GPIO_1"),
0433     MT7986_PIN(7, "GPIO_2"),
0434     MT7986_PIN(8, "GPIO_3"),
0435     MT7986_PIN(9, "GPIO_4"),
0436     MT7986_PIN(10, "GPIO_5"),
0437     MT7986_PIN(11, "GPIO_6"),
0438     MT7986_PIN(12, "GPIO_7"),
0439     MT7986_PIN(13, "GPIO_8"),
0440     MT7986_PIN(14, "GPIO_9"),
0441     MT7986_PIN(15, "GPIO_10"),
0442     MT7986_PIN(16, "GPIO_11"),
0443     MT7986_PIN(17, "GPIO_12"),
0444     MT7986_PIN(18, "GPIO_13"),
0445     MT7986_PIN(19, "GPIO_14"),
0446     MT7986_PIN(20, "GPIO_15"),
0447     MT7986_PIN(21, "PWM0"),
0448     MT7986_PIN(22, "PWM1"),
0449     MT7986_PIN(23, "SPI0_CLK"),
0450     MT7986_PIN(24, "SPI0_MOSI"),
0451     MT7986_PIN(25, "SPI0_MISO"),
0452     MT7986_PIN(26, "SPI0_CS"),
0453     MT7986_PIN(27, "SPI0_HOLD"),
0454     MT7986_PIN(28, "SPI0_WP"),
0455     MT7986_PIN(29, "SPI1_CLK"),
0456     MT7986_PIN(30, "SPI1_MOSI"),
0457     MT7986_PIN(31, "SPI1_MISO"),
0458     MT7986_PIN(32, "SPI1_CS"),
0459     MT7986_PIN(33, "SPI2_CLK"),
0460     MT7986_PIN(34, "SPI2_MOSI"),
0461     MT7986_PIN(35, "SPI2_MISO"),
0462     MT7986_PIN(36, "SPI2_CS"),
0463     MT7986_PIN(37, "SPI2_HOLD"),
0464     MT7986_PIN(38, "SPI2_WP"),
0465     MT7986_PIN(39, "UART0_RXD"),
0466     MT7986_PIN(40, "UART0_TXD"),
0467     MT7986_PIN(41, "PCIE_PERESET_N"),
0468     MT7986_PIN(42, "UART1_RXD"),
0469     MT7986_PIN(43, "UART1_TXD"),
0470     MT7986_PIN(44, "UART1_CTS"),
0471     MT7986_PIN(45, "UART1_RTS"),
0472     MT7986_PIN(46, "UART2_RXD"),
0473     MT7986_PIN(47, "UART2_TXD"),
0474     MT7986_PIN(48, "UART2_CTS"),
0475     MT7986_PIN(49, "UART2_RTS"),
0476     MT7986_PIN(50, "EMMC_DATA_0"),
0477     MT7986_PIN(51, "EMMC_DATA_1"),
0478     MT7986_PIN(52, "EMMC_DATA_2"),
0479     MT7986_PIN(53, "EMMC_DATA_3"),
0480     MT7986_PIN(54, "EMMC_DATA_4"),
0481     MT7986_PIN(55, "EMMC_DATA_5"),
0482     MT7986_PIN(56, "EMMC_DATA_6"),
0483     MT7986_PIN(57, "EMMC_DATA_7"),
0484     MT7986_PIN(58, "EMMC_CMD"),
0485     MT7986_PIN(59, "EMMC_CK"),
0486     MT7986_PIN(60, "EMMC_DSL"),
0487     MT7986_PIN(61, "EMMC_RSTB"),
0488     MT7986_PIN(62, "PCM_DTX"),
0489     MT7986_PIN(63, "PCM_DRX"),
0490     MT7986_PIN(64, "PCM_CLK"),
0491     MT7986_PIN(65, "PCM_FS"),
0492     MT7986_PIN(66, "MT7531_INT"),
0493     MT7986_PIN(67, "SMI_MDC"),
0494     MT7986_PIN(68, "SMI_MDIO"),
0495     MT7986_PIN(69, "WF0_DIG_RESETB"),
0496     MT7986_PIN(70, "WF0_CBA_RESETB"),
0497     MT7986_PIN(71, "WF0_XO_REQ"),
0498     MT7986_PIN(72, "WF0_TOP_CLK"),
0499     MT7986_PIN(73, "WF0_TOP_DATA"),
0500     MT7986_PIN(74, "WF0_HB1"),
0501     MT7986_PIN(75, "WF0_HB2"),
0502     MT7986_PIN(76, "WF0_HB3"),
0503     MT7986_PIN(77, "WF0_HB4"),
0504     MT7986_PIN(78, "WF0_HB0"),
0505     MT7986_PIN(79, "WF0_HB0_B"),
0506     MT7986_PIN(80, "WF0_HB5"),
0507     MT7986_PIN(81, "WF0_HB6"),
0508     MT7986_PIN(82, "WF0_HB7"),
0509     MT7986_PIN(83, "WF0_HB8"),
0510     MT7986_PIN(84, "WF0_HB9"),
0511     MT7986_PIN(85, "WF0_HB10"),
0512     MT7986_PIN(86, "WF1_DIG_RESETB"),
0513     MT7986_PIN(87, "WF1_CBA_RESETB"),
0514     MT7986_PIN(88, "WF1_XO_REQ"),
0515     MT7986_PIN(89, "WF1_TOP_CLK"),
0516     MT7986_PIN(90, "WF1_TOP_DATA"),
0517     MT7986_PIN(91, "WF1_HB1"),
0518     MT7986_PIN(92, "WF1_HB2"),
0519     MT7986_PIN(93, "WF1_HB3"),
0520     MT7986_PIN(94, "WF1_HB4"),
0521     MT7986_PIN(95, "WF1_HB0"),
0522     MT7986_PIN(96, "WF1_HB0_B"),
0523     MT7986_PIN(97, "WF1_HB5"),
0524     MT7986_PIN(98, "WF1_HB6"),
0525     MT7986_PIN(99, "WF1_HB7"),
0526     MT7986_PIN(100, "WF1_HB8"),
0527 };
0528
0529 static const struct mtk_pin_desc mt7986b_pins[] = {
0530     MT7986_PIN(0, "SYS_WATCHDOG"),
0531     MT7986_PIN(1, "WF2G_LED"),
0532     MT7986_PIN(2, "WF5G_LED"),
0533     MT7986_PIN(3, "I2C_SCL"),
0534     MT7986_PIN(4, "I2C_SDA"),
0535     MT7986_PIN(5, "GPIO_0"),
0536     MT7986_PIN(6, "GPIO_1"),
0537     MT7986_PIN(7, "GPIO_2"),
0538     MT7986_PIN(8, "GPIO_3"),
0539     MT7986_PIN(9, "GPIO_4"),
0540     MT7986_PIN(10, "GPIO_5"),
0541     MT7986_PIN(11, "GPIO_6"),
0542     MT7986_PIN(12, "GPIO_7"),
0543     MT7986_PIN(13, "GPIO_8"),
0544     MT7986_PIN(14, "GPIO_9"),
0545     MT7986_PIN(15, "GPIO_10"),
0546     MT7986_PIN(16, "GPIO_11"),
0547     MT7986_PIN(17, "GPIO_12"),
0548     MT7986_PIN(18, "GPIO_13"),
0549     MT7986_PIN(19, "GPIO_14"),
0550     MT7986_PIN(20, "GPIO_15"),
0551     MT7986_PIN(21, "PWM0"),
0552     MT7986_PIN(22, "PWM1"),
0553     MT7986_PIN(23, "SPI0_CLK"),
0554     MT7986_PIN(24, "SPI0_MOSI"),
0555     MT7986_PIN(25, "SPI0_MISO"),
0556     MT7986_PIN(26, "SPI0_CS"),
0557     MT7986_PIN(27, "SPI0_HOLD"),
0558     MT7986_PIN(28, "SPI0_WP"),
0559     MT7986_PIN(29, "SPI1_CLK"),
0560     MT7986_PIN(30, "SPI1_MOSI"),
0561     MT7986_PIN(31, "SPI1_MISO"),
0562     MT7986_PIN(32, "SPI1_CS"),
0563     MT7986_PIN(33, "SPI2_CLK"),
0564     MT7986_PIN(34, "SPI2_MOSI"),
0565     MT7986_PIN(35, "SPI2_MISO"),
0566     MT7986_PIN(36, "SPI2_CS"),
0567     MT7986_PIN(37, "SPI2_HOLD"),
0568     MT7986_PIN(38, "SPI2_WP"),
0569     MT7986_PIN(39, "UART0_RXD"),
0570     MT7986_PIN(40, "UART0_TXD"),
0571     MT7986_NOT_BALLOUT_PIN(41),
0572     MT7986_NOT_BALLOUT_PIN(42),
0573     MT7986_NOT_BALLOUT_PIN(43),
0574     MT7986_NOT_BALLOUT_PIN(44),
0575     MT7986_NOT_BALLOUT_PIN(45),
0576     MT7986_NOT_BALLOUT_PIN(46),
0577     MT7986_NOT_BALLOUT_PIN(47),
0578     MT7986_NOT_BALLOUT_PIN(48),
0579     MT7986_NOT_BALLOUT_PIN(49),
0580     MT7986_NOT_BALLOUT_PIN(50),
0581     MT7986_NOT_BALLOUT_PIN(51),
0582     MT7986_NOT_BALLOUT_PIN(52),
0583     MT7986_NOT_BALLOUT_PIN(53),
0584     MT7986_NOT_BALLOUT_PIN(54),
0585     MT7986_NOT_BALLOUT_PIN(55),
0586     MT7986_NOT_BALLOUT_PIN(56),
0587     MT7986_NOT_BALLOUT_PIN(57),
0588     MT7986_NOT_BALLOUT_PIN(58),
0589     MT7986_NOT_BALLOUT_PIN(59),
0590     MT7986_NOT_BALLOUT_PIN(60),
0591     MT7986_NOT_BALLOUT_PIN(61),
0592     MT7986_NOT_BALLOUT_PIN(62),
0593     MT7986_NOT_BALLOUT_PIN(63),
0594     MT7986_NOT_BALLOUT_PIN(64),
0595     MT7986_NOT_BALLOUT_PIN(65),
0596     MT7986_PIN(66, "MT7531_INT"),
0597     MT7986_PIN(67, "SMI_MDC"),
0598     MT7986_PIN(68, "SMI_MDIO"),
0599     MT7986_PIN(69, "WF0_DIG_RESETB"),
0600     MT7986_PIN(70, "WF0_CBA_RESETB"),
0601     MT7986_PIN(71, "WF0_XO_REQ"),
0602     MT7986_PIN(72, "WF0_TOP_CLK"),
0603     MT7986_PIN(73, "WF0_TOP_DATA"),
0604     MT7986_PIN(74, "WF0_HB1"),
0605     MT7986_PIN(75, "WF0_HB2"),
0606     MT7986_PIN(76, "WF0_HB3"),
0607     MT7986_PIN(77, "WF0_HB4"),
0608     MT7986_PIN(78, "WF0_HB0"),
0609     MT7986_PIN(79, "WF0_HB0_B"),
0610     MT7986_PIN(80, "WF0_HB5"),
0611     MT7986_PIN(81, "WF0_HB6"),
0612     MT7986_PIN(82, "WF0_HB7"),
0613     MT7986_PIN(83, "WF0_HB8"),
0614     MT7986_PIN(84, "WF0_HB9"),
0615     MT7986_PIN(85, "WF0_HB10"),
0616     MT7986_PIN(86, "WF1_DIG_RESETB"),
0617     MT7986_PIN(87, "WF1_CBA_RESETB"),
0618     MT7986_PIN(88, "WF1_XO_REQ"),
0619     MT7986_PIN(89, "WF1_TOP_CLK"),
0620     MT7986_PIN(90, "WF1_TOP_DATA"),
0621     MT7986_PIN(91, "WF1_HB1"),
0622     MT7986_PIN(92, "WF1_HB2"),
0623     MT7986_PIN(93, "WF1_HB3"),
0624     MT7986_PIN(94, "WF1_HB4"),
0625     MT7986_PIN(95, "WF1_HB0"),
0626     MT7986_PIN(96, "WF1_HB0_B"),
0627     MT7986_PIN(97, "WF1_HB5"),
0628     MT7986_PIN(98, "WF1_HB6"),
0629     MT7986_PIN(99, "WF1_HB7"),
0630     MT7986_PIN(100, "WF1_HB8"),
0631 };
0632
0633 /* List all groups consisting of these pins dedicated to the enablement of
0634  * certain hardware block and the corresponding mode for all of the pins.
0635  * The hardware probably has multiple combinations of these pinouts.
0636  */
0637
0638 static int mt7986_watchdog_pins[] = { 0, };
0639 static int mt7986_watchdog_funcs[] = { 1, };
0640
0641 static int mt7986_wifi_led_pins[] = { 1, 2, };
0642 static int mt7986_wifi_led_funcs[] = { 1, 1, };
0643
0644 static int mt7986_i2c_pins[] = { 3, 4, };
0645 static int mt7986_i2c_funcs[] = { 1, 1, };
0646
0647 static int mt7986_uart1_0_pins[] = { 7, 8, 9, 10, };
0648 static int mt7986_uart1_0_funcs[] = { 3, 3, 3, 3, };
0649
0650 static int mt7986_spi1_0_pins[] = { 11, 12, 13, 14, };
0651 static int mt7986_spi1_0_funcs[] = { 3, 3, 3, 3, };
0652
0653 static int mt7986_pwm1_1_pins[] = { 20, };
0654 static int mt7986_pwm1_1_funcs[] = { 2, };
0655
0656 static int mt7986_pwm0_pins[] = { 21, };
0657 static int mt7986_pwm0_funcs[] = { 1, };
0658
0659 static int mt7986_pwm1_0_pins[] = { 22, };
0660 static int mt7986_pwm1_0_funcs[] = { 1, };
0661
0662 static int mt7986_emmc_45_pins[] = {
0663     22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, };
0664 static int mt7986_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
0665
0666 static int mt7986_snfi_pins[] = { 23, 24, 25, 26, 27, 28, };
0667 static int mt7986_snfi_funcs[] = { 1, 1, 1, 1, 1, 1, };
0668
0669 static int mt7986_spi1_1_pins[] = { 23, 24, 25, 26, };
0670 static int mt7986_spi1_1_funcs[] = { 3, 3, 3, 3, };
0671
0672 static int mt7986_uart1_1_pins[] = { 23, 24, 25, 26, };
0673 static int mt7986_uart1_1_funcs[] = { 4, 4, 4, 4, };
0674
0675 static int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, };
0676 static int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, };
0677
0678 static int mt7986_uart1_2_pins[] = { 29, 30, 31, 32, };
0679 static int mt7986_uart1_2_funcs[] = { 3, 3, 3, 3, };
0680
0681 static int mt7986_uart2_0_pins[] = { 29, 30, 31, 32, };
0682 static int mt7986_uart2_0_funcs[] = { 4, 4, 4, 4, };
0683
0684 static int mt7986_spi0_pins[] = { 33, 34, 35, 36, };
0685 static int mt7986_spi0_funcs[] = { 1, 1, 1, 1, };
0686
0687 static int mt7986_spi0_wp_hold_pins[] = { 37, 38, };
0688 static int mt7986_spi0_wp_hold_funcs[] = { 1, 1, };
0689
0690 static int mt7986_uart2_1_pins[] = { 33, 34, 35, 36, };
0691 static int mt7986_uart2_1_funcs[] = { 3, 3, 3, 3, };
0692
0693 static int mt7986_uart1_3_rx_tx_pins[] = { 35, 36, };
0694 static int mt7986_uart1_3_rx_tx_funcs[] = { 2, 2, };
0695
0696 static int mt7986_uart1_3_cts_rts_pins[] = { 37, 38, };
0697 static int mt7986_uart1_3_cts_rts_funcs[] = { 2, 2, };
0698
0699 static int mt7986_spi1_3_pins[] = { 33, 34, 35, 36, };
0700 static int mt7986_spi1_3_funcs[] = { 4, 4, 4, 4, };
0701
0702 static int mt7986_uart0_pins[] = { 39, 40, };
0703 static int mt7986_uart0_funcs[] = { 1, 1, };
0704
0705 static int mt7986_pcie_reset_pins[] = { 41, };
0706 static int mt7986_pcie_reset_funcs[] = { 1, };
0707
0708 static int mt7986_uart1_pins[] = { 42, 43, 44, 45, };
0709 static int mt7986_uart1_funcs[] = { 1, 1, 1, 1, };
0710
0711 static int mt7986_uart2_pins[] = { 46, 47, 48, 49, };
0712 static int mt7986_uart2_funcs[] = { 1, 1, 1, 1, };
0713
0714 static int mt7986_emmc_51_pins[] = {
0715     50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, };
0716 static int mt7986_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
0717
0718 static int mt7986_pcm_pins[] = { 62, 63, 64, 65, };
0719 static int mt7986_pcm_funcs[] = { 1, 1, 1, 1, };
0720
0721 static int mt7986_i2s_pins[] = { 62, 63, 64, 65, };
0722 static int mt7986_i2s_funcs[] = { 1, 1, 1, 1, };
0723
0724 static int mt7986_switch_int_pins[] = { 66, };
0725 static int mt7986_switch_int_funcs[] = { 1, };
0726
0727 static int mt7986_mdc_mdio_pins[] = { 67, 68, };
0728 static int mt7986_mdc_mdio_funcs[] = { 1, 1, };
0729
0730 static int mt7986_wf_2g_pins[] = {74, 75, 76, 77, 78, 79, 80, 81, 82, 83, };
0731 static int mt7986_wf_2g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
0732
0733 static int mt7986_wf_5g_pins[] = {91, 92, 93, 94, 95, 96, 97, 98, 99, 100, };
0734 static int mt7986_wf_5g_funcs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
0735
0736 static int mt7986_wf_dbdc_pins[] = {
0737     74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, };
0738 static int mt7986_wf_dbdc_funcs[] = {
0739     2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
0740
0741 static int mt7986_pcie_clk_pins[] = { 9, };
0742 static int mt7986_pcie_clk_funcs[] = { 1, };
0743
0744 static int mt7986_pcie_wake_pins[] = { 10, };
0745 static int mt7986_pcie_wake_funcs[] = { 1, };
0746
0747 static const struct group_desc mt7986_groups[] = {
0748     PINCTRL_PIN_GROUP("watchdog", mt7986_watchdog),
0749     PINCTRL_PIN_GROUP("wifi_led", mt7986_wifi_led),
0750     PINCTRL_PIN_GROUP("i2c", mt7986_i2c),
0751     PINCTRL_PIN_GROUP("uart1_0", mt7986_uart1_0),
0752     PINCTRL_PIN_GROUP("pcie_clk", mt7986_pcie_clk),
0753     PINCTRL_PIN_GROUP("pcie_wake", mt7986_pcie_wake),
0754     PINCTRL_PIN_GROUP("spi1_0", mt7986_spi1_0),
0755     PINCTRL_PIN_GROUP("pwm1_1", mt7986_pwm1_1),
0756     PINCTRL_PIN_GROUP("pwm0", mt7986_pwm0),
0757     PINCTRL_PIN_GROUP("pwm1_0", mt7986_pwm1_0),
0758     PINCTRL_PIN_GROUP("emmc_45", mt7986_emmc_45),
0759     PINCTRL_PIN_GROUP("snfi", mt7986_snfi),
0760     PINCTRL_PIN_GROUP("spi1_1", mt7986_spi1_1),
0761     PINCTRL_PIN_GROUP("uart1_1", mt7986_uart1_1),
0762     PINCTRL_PIN_GROUP("spi1_2", mt7986_spi1_2),
0763     PINCTRL_PIN_GROUP("uart1_2", mt7986_uart1_2),
0764     PINCTRL_PIN_GROUP("uart2_0", mt7986_uart2_0),
0765     PINCTRL_PIN_GROUP("spi0", mt7986_spi0),
0766     PINCTRL_PIN_GROUP("spi0_wp_hold", mt7986_spi0_wp_hold),
0767     PINCTRL_PIN_GROUP("uart2_1", mt7986_uart2_1),
0768     PINCTRL_PIN_GROUP("uart1_3_rx_tx", mt7986_uart1_3_rx_tx),
0769     PINCTRL_PIN_GROUP("uart1_3_cts_rts", mt7986_uart1_3_cts_rts),
0770     PINCTRL_PIN_GROUP("spi1_3", mt7986_spi1_3),
0771     PINCTRL_PIN_GROUP("uart0", mt7986_uart0),
0772     PINCTRL_PIN_GROUP("switch_int", mt7986_switch_int),
0773     PINCTRL_PIN_GROUP("mdc_mdio", mt7986_mdc_mdio),
0774     PINCTRL_PIN_GROUP("pcie_pereset", mt7986_pcie_reset),
0775     PINCTRL_PIN_GROUP("uart1", mt7986_uart1),
0776     PINCTRL_PIN_GROUP("uart2", mt7986_uart2),
0777     PINCTRL_PIN_GROUP("emmc_51", mt7986_emmc_51),
0778     PINCTRL_PIN_GROUP("pcm", mt7986_pcm),
0779     PINCTRL_PIN_GROUP("i2s", mt7986_i2s),
0780     PINCTRL_PIN_GROUP("wf_2g", mt7986_wf_2g),
0781     PINCTRL_PIN_GROUP("wf_5g", mt7986_wf_5g),
0782     PINCTRL_PIN_GROUP("wf_dbdc", mt7986_wf_dbdc),
0783 };
0784
0785 /* Joint those groups owning the same capability in user point of view which
0786  * allows that people tend to use through the device tree.
0787  */
0788
0789 static const char *mt7986_audio_groups[] = { "pcm", "i2s" };
0790 static const char *mt7986_emmc_groups[] = {
0791     "emmc_45", "emmc_51", };
0792 static const char *mt7986_ethernet_groups[] = {
0793     "switch_int", "mdc_mdio", };
0794 static const char *mt7986_i2c_groups[] = { "i2c", };
0795 static const char *mt7986_led_groups[] = { "wifi_led", };
0796 static const char *mt7986_flash_groups[] = { "snfi", };
0797 static const char *mt7986_pcie_groups[] = {
0798     "pcie_clk", "pcie_wake", "pcie_pereset" };
0799 static const char *mt7986_pwm_groups[] = { "pwm0", "pwm1_0", "pwm1_1", };
0800 static const char *mt7986_spi_groups[] = {
0801     "spi0", "spi0_wp_hold", "spi1_0", "spi1_1", "spi1_2", "spi1_3", };
0802 static const char *mt7986_uart_groups[] = {
0803     "uart1_0", "uart1_1", "uart1_2", "uart1_3_rx_tx", "uart1_3_cts_rts",
0804     "uart2_0", "uart2_1", "uart0", "uart1", "uart2",
0805 };
0806 static const char *mt7986_wdt_groups[] = { "watchdog", };
0807 static const char *mt7986_wf_groups[] = { "wf_2g", "wf_5g", "wf_dbdc", };
0808
0809 static const struct function_desc mt7986_functions[] = {
0810     {"audio", mt7986_audio_groups, ARRAY_SIZE(mt7986_audio_groups)},
0811     {"emmc", mt7986_emmc_groups, ARRAY_SIZE(mt7986_emmc_groups)},
0812     {"eth", mt7986_ethernet_groups, ARRAY_SIZE(mt7986_ethernet_groups)},
0813     {"i2c", mt7986_i2c_groups, ARRAY_SIZE(mt7986_i2c_groups)},
0814     {"led", mt7986_led_groups, ARRAY_SIZE(mt7986_led_groups)},
0815     {"flash", mt7986_flash_groups, ARRAY_SIZE(mt7986_flash_groups)},
0816     {"pcie", mt7986_pcie_groups, ARRAY_SIZE(mt7986_pcie_groups)},
0817     {"pwm", mt7986_pwm_groups, ARRAY_SIZE(mt7986_pwm_groups)},
0818     {"spi", mt7986_spi_groups, ARRAY_SIZE(mt7986_spi_groups)},
0819     {"uart", mt7986_uart_groups, ARRAY_SIZE(mt7986_uart_groups)},
0820     {"watchdog", mt7986_wdt_groups, ARRAY_SIZE(mt7986_wdt_groups)},
0821     {"wifi", mt7986_wf_groups, ARRAY_SIZE(mt7986_wf_groups)},
0822 };
0823
0824 static const struct mtk_eint_hw mt7986a_eint_hw = {
0825     .port_mask = 7,
0826     .ports = 7,
0827     .ap_num = ARRAY_SIZE(mt7986a_pins),
0828     .db_cnt = 16,
0829 };
0830
0831 static const struct mtk_eint_hw mt7986b_eint_hw = {
0832     .port_mask = 7,
0833     .ports = 7,
0834     .ap_num = ARRAY_SIZE(mt7986b_pins),
0835     .db_cnt = 16,
0836 };
0837
0838 static struct mtk_pin_soc mt7986a_data = {
0839     .reg_cal = mt7986_reg_cals,
0840     .pins = mt7986a_pins,
0841     .npins = ARRAY_SIZE(mt7986a_pins),
0842     .grps = mt7986_groups,
0843     .ngrps = ARRAY_SIZE(mt7986_groups),
0844     .funcs = mt7986_functions,
0845     .nfuncs = ARRAY_SIZE(mt7986_functions),
0846     .eint_hw = &mt7986a_eint_hw,
0847     .gpio_m = 0,
0848     .ies_present = false,
0849     .base_names = mt7986_pinctrl_register_base_names,
0850     .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
0851     .bias_set_combo = mtk_pinconf_bias_set_combo,
0852     .bias_get_combo = mtk_pinconf_bias_get_combo,
0853     .drive_set = mtk_pinconf_drive_set_rev1,
0854     .drive_get = mtk_pinconf_drive_get_rev1,
0855     .adv_pull_get = mtk_pinconf_adv_pull_get,
0856     .adv_pull_set = mtk_pinconf_adv_pull_set,
0857 };
0858
0859 static struct mtk_pin_soc mt7986b_data = {
0860     .reg_cal = mt7986_reg_cals,
0861     .pins = mt7986b_pins,
0862     .npins = ARRAY_SIZE(mt7986b_pins),
0863     .grps = mt7986_groups,
0864     .ngrps = ARRAY_SIZE(mt7986_groups),
0865     .funcs = mt7986_functions,
0866     .nfuncs = ARRAY_SIZE(mt7986_functions),
0867     .eint_hw = &mt7986b_eint_hw,
0868     .gpio_m = 0,
0869     .ies_present = false,
0870     .base_names = mt7986_pinctrl_register_base_names,
0871     .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names),
0872     .bias_set_combo = mtk_pinconf_bias_set_combo,
0873     .bias_get_combo = mtk_pinconf_bias_get_combo,
0874     .drive_set = mtk_pinconf_drive_set_rev1,
0875     .drive_get = mtk_pinconf_drive_get_rev1,
0876     .adv_pull_get = mtk_pinconf_adv_pull_get,
0877     .adv_pull_set = mtk_pinconf_adv_pull_set,
0878 };
0879
0880 static const struct of_device_id mt7986a_pinctrl_of_match[] = {
0881     {.compatible = "mediatek,mt7986a-pinctrl",},
0882     {}
0883 };
0884
0885 static const struct of_device_id mt7986b_pinctrl_of_match[] = {
0886     {.compatible = "mediatek,mt7986b-pinctrl",},
0887     {}
0888 };
0889
0890 static int mt7986a_pinctrl_probe(struct platform_device *pdev)
0891 {
0892     return mtk_moore_pinctrl_probe(pdev, &mt7986a_data);
0893 }
0894
0895 static int mt7986b_pinctrl_probe(struct platform_device *pdev)
0896 {
0897     return mtk_moore_pinctrl_probe(pdev, &mt7986b_data);
0898 }
0899
0900 static struct platform_driver mt7986a_pinctrl_driver = {
0901     .driver = {
0902         .name = "mt7986a-pinctrl",
0903         .of_match_table = mt7986a_pinctrl_of_match,
0904     },
0905     .probe = mt7986a_pinctrl_probe,
0906 };
0907
0908 static struct platform_driver mt7986b_pinctrl_driver = {
0909     .driver = {
0910         .name = "mt7986b-pinctrl",
0911         .of_match_table = mt7986b_pinctrl_of_match,
0912     },
0913     .probe = mt7986b_pinctrl_probe,
0914 };
0915
0916 static int __init mt7986a_pinctrl_init(void)
0917 {
0918     return platform_driver_register(&mt7986a_pinctrl_driver);
0919 }
0920
0921 static int __init mt7986b_pinctrl_init(void)
0922 {
0923     return platform_driver_register(&mt7986b_pinctrl_driver);
0924 }
0925
0926 arch_initcall(mt7986a_pinctrl_init);
0927 arch_initcall(mt7986b_pinctrl_init);