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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * The MT7629 driver based on Linux generic pinctrl binding.
0004  *
0005  * Copyright (C) 2018 MediaTek Inc.
0006  * Author: Ryder Lee <ryder.lee@mediatek.com>
0007  */
0008 
0009 #include "pinctrl-moore.h"
0010 
0011 #define MT7629_PIN(_number, _name, _eint_n)             \
0012     MTK_PIN(_number, _name, 0, _eint_n, DRV_GRP1)
0013 
0014 static const struct mtk_pin_field_calc mt7629_pin_mode_range[] = {
0015     PIN_FIELD(0, 78, 0x300, 0x10, 0, 4),
0016 };
0017 
0018 static const struct mtk_pin_field_calc mt7629_pin_dir_range[] = {
0019     PIN_FIELD(0, 78, 0x0, 0x10, 0, 1),
0020 };
0021 
0022 static const struct mtk_pin_field_calc mt7629_pin_di_range[] = {
0023     PIN_FIELD(0, 78, 0x200, 0x10, 0, 1),
0024 };
0025 
0026 static const struct mtk_pin_field_calc mt7629_pin_do_range[] = {
0027     PIN_FIELD(0, 78, 0x100, 0x10, 0, 1),
0028 };
0029 
0030 static const struct mtk_pin_field_calc mt7629_pin_ies_range[] = {
0031     PIN_FIELD(0, 10, 0x1000, 0x10, 0, 1),
0032     PIN_FIELD(11, 18, 0x2000, 0x10, 0, 1),
0033     PIN_FIELD(19, 32, 0x3000, 0x10, 0, 1),
0034     PIN_FIELD(33, 48, 0x4000, 0x10, 0, 1),
0035     PIN_FIELD(49, 50, 0x5000, 0x10, 0, 1),
0036     PIN_FIELD(51, 69, 0x6000, 0x10, 0, 1),
0037     PIN_FIELD(70, 78, 0x7000, 0x10, 0, 1),
0038 };
0039 
0040 static const struct mtk_pin_field_calc mt7629_pin_smt_range[] = {
0041     PIN_FIELD(0, 10, 0x1100, 0x10, 0, 1),
0042     PIN_FIELD(11, 18, 0x2100, 0x10, 0, 1),
0043     PIN_FIELD(19, 32, 0x3100, 0x10, 0, 1),
0044     PIN_FIELD(33, 48, 0x4100, 0x10, 0, 1),
0045     PIN_FIELD(49, 50, 0x5100, 0x10, 0, 1),
0046     PIN_FIELD(51, 69, 0x6100, 0x10, 0, 1),
0047     PIN_FIELD(70, 78, 0x7100, 0x10, 0, 1),
0048 };
0049 
0050 static const struct mtk_pin_field_calc mt7629_pin_pullen_range[] = {
0051     PIN_FIELD(0, 10, 0x1400, 0x10, 0, 1),
0052     PIN_FIELD(11, 18, 0x2400, 0x10, 0, 1),
0053     PIN_FIELD(19, 32, 0x3400, 0x10, 0, 1),
0054     PIN_FIELD(33, 48, 0x4400, 0x10, 0, 1),
0055     PIN_FIELD(49, 50, 0x5400, 0x10, 0, 1),
0056     PIN_FIELD(51, 69, 0x6400, 0x10, 0, 1),
0057     PIN_FIELD(70, 78, 0x7400, 0x10, 0, 1),
0058 };
0059 
0060 static const struct mtk_pin_field_calc mt7629_pin_pullsel_range[] = {
0061     PIN_FIELD(0, 10, 0x1500, 0x10, 0, 1),
0062     PIN_FIELD(11, 18, 0x2500, 0x10, 0, 1),
0063     PIN_FIELD(19, 32, 0x3500, 0x10, 0, 1),
0064     PIN_FIELD(33, 48, 0x4500, 0x10, 0, 1),
0065     PIN_FIELD(49, 50, 0x5500, 0x10, 0, 1),
0066     PIN_FIELD(51, 69, 0x6500, 0x10, 0, 1),
0067     PIN_FIELD(70, 78, 0x7500, 0x10, 0, 1),
0068 };
0069 
0070 static const struct mtk_pin_field_calc mt7629_pin_drv_range[] = {
0071     PIN_FIELD(0, 10, 0x1600, 0x10, 0, 4),
0072     PIN_FIELD(11, 18, 0x2600, 0x10, 0, 4),
0073     PIN_FIELD(19, 32, 0x3600, 0x10, 0, 4),
0074     PIN_FIELD(33, 48, 0x4600, 0x10, 0, 4),
0075     PIN_FIELD(49, 50, 0x5600, 0x10, 0, 4),
0076     PIN_FIELD(51, 69, 0x6600, 0x10, 0, 4),
0077     PIN_FIELD(70, 78, 0x7600, 0x10, 0, 4),
0078 };
0079 
0080 static const struct mtk_pin_field_calc mt7629_pin_tdsel_range[] = {
0081     PIN_FIELD(0, 10, 0x1200, 0x10, 0, 4),
0082     PIN_FIELD(11, 18, 0x2200, 0x10, 0, 4),
0083     PIN_FIELD(19, 32, 0x3200, 0x10, 0, 4),
0084     PIN_FIELD(33, 48, 0x4200, 0x10, 0, 4),
0085     PIN_FIELD(49, 50, 0x5200, 0x10, 0, 4),
0086     PIN_FIELD(51, 69, 0x6200, 0x10, 0, 4),
0087     PIN_FIELD(70, 78, 0x7200, 0x10, 0, 4),
0088 };
0089 
0090 static const struct mtk_pin_field_calc mt7629_pin_rdsel_range[] = {
0091     PIN_FIELD(0, 10, 0x1300, 0x10, 0, 4),
0092     PIN_FIELD(11, 18, 0x2300, 0x10, 0, 4),
0093     PIN_FIELD(19, 32, 0x3300, 0x10, 0, 4),
0094     PIN_FIELD(33, 48, 0x4300, 0x10, 0, 4),
0095     PIN_FIELD(49, 50, 0x5300, 0x10, 0, 4),
0096     PIN_FIELD(51, 69, 0x6300, 0x10, 0, 4),
0097     PIN_FIELD(70, 78, 0x7300, 0x10, 0, 4),
0098 };
0099 
0100 static const struct mtk_pin_reg_calc mt7629_reg_cals[] = {
0101     [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7629_pin_mode_range),
0102     [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7629_pin_dir_range),
0103     [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7629_pin_di_range),
0104     [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7629_pin_do_range),
0105     [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7629_pin_ies_range),
0106     [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7629_pin_smt_range),
0107     [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt7629_pin_pullsel_range),
0108     [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt7629_pin_pullen_range),
0109     [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7629_pin_drv_range),
0110     [PINCTRL_PIN_REG_TDSEL] = MTK_RANGE(mt7629_pin_tdsel_range),
0111     [PINCTRL_PIN_REG_RDSEL] = MTK_RANGE(mt7629_pin_rdsel_range),
0112 };
0113 
0114 static const struct mtk_pin_desc mt7629_pins[] = {
0115     MT7629_PIN(0, "TOP_5G_CLK", 53),
0116     MT7629_PIN(1, "TOP_5G_DATA", 54),
0117     MT7629_PIN(2, "WF0_5G_HB0", 55),
0118     MT7629_PIN(3, "WF0_5G_HB1", 56),
0119     MT7629_PIN(4, "WF0_5G_HB2", 57),
0120     MT7629_PIN(5, "WF0_5G_HB3", 58),
0121     MT7629_PIN(6, "WF0_5G_HB4", 59),
0122     MT7629_PIN(7, "WF0_5G_HB5", 60),
0123     MT7629_PIN(8, "WF0_5G_HB6", 61),
0124     MT7629_PIN(9, "XO_REQ", 9),
0125     MT7629_PIN(10, "TOP_RST_N", 10),
0126     MT7629_PIN(11, "SYS_WATCHDOG", 11),
0127     MT7629_PIN(12, "EPHY_LED0_N_JTDO", 12),
0128     MT7629_PIN(13, "EPHY_LED1_N_JTDI", 13),
0129     MT7629_PIN(14, "EPHY_LED2_N_JTMS", 14),
0130     MT7629_PIN(15, "EPHY_LED3_N_JTCLK", 15),
0131     MT7629_PIN(16, "EPHY_LED4_N_JTRST_N", 16),
0132     MT7629_PIN(17, "WF2G_LED_N", 17),
0133     MT7629_PIN(18, "WF5G_LED_N", 18),
0134     MT7629_PIN(19, "I2C_SDA", 19),
0135     MT7629_PIN(20, "I2C_SCL", 20),
0136     MT7629_PIN(21, "GPIO_9", 21),
0137     MT7629_PIN(22, "GPIO_10", 22),
0138     MT7629_PIN(23, "GPIO_11", 23),
0139     MT7629_PIN(24, "GPIO_12", 24),
0140     MT7629_PIN(25, "UART1_TXD", 25),
0141     MT7629_PIN(26, "UART1_RXD", 26),
0142     MT7629_PIN(27, "UART1_CTS", 27),
0143     MT7629_PIN(28, "UART1_RTS", 28),
0144     MT7629_PIN(29, "UART2_TXD", 29),
0145     MT7629_PIN(30, "UART2_RXD", 30),
0146     MT7629_PIN(31, "UART2_CTS", 31),
0147     MT7629_PIN(32, "UART2_RTS", 32),
0148     MT7629_PIN(33, "MDI_TP_P1", 33),
0149     MT7629_PIN(34, "MDI_TN_P1", 34),
0150     MT7629_PIN(35, "MDI_RP_P1", 35),
0151     MT7629_PIN(36, "MDI_RN_P1", 36),
0152     MT7629_PIN(37, "MDI_RP_P2", 37),
0153     MT7629_PIN(38, "MDI_RN_P2", 38),
0154     MT7629_PIN(39, "MDI_TP_P2", 39),
0155     MT7629_PIN(40, "MDI_TN_P2", 40),
0156     MT7629_PIN(41, "MDI_TP_P3", 41),
0157     MT7629_PIN(42, "MDI_TN_P3", 42),
0158     MT7629_PIN(43, "MDI_RP_P3", 43),
0159     MT7629_PIN(44, "MDI_RN_P3", 44),
0160     MT7629_PIN(45, "MDI_RP_P4", 45),
0161     MT7629_PIN(46, "MDI_RN_P4", 46),
0162     MT7629_PIN(47, "MDI_TP_P4", 47),
0163     MT7629_PIN(48, "MDI_TN_P4", 48),
0164     MT7629_PIN(49, "SMI_MDC", 49),
0165     MT7629_PIN(50, "SMI_MDIO", 50),
0166     MT7629_PIN(51, "PCIE_PERESET_N", 51),
0167     MT7629_PIN(52, "PWM_0", 52),
0168     MT7629_PIN(53, "GPIO_0", 0),
0169     MT7629_PIN(54, "GPIO_1", 1),
0170     MT7629_PIN(55, "GPIO_2", 2),
0171     MT7629_PIN(56, "GPIO_3", 3),
0172     MT7629_PIN(57, "GPIO_4", 4),
0173     MT7629_PIN(58, "GPIO_5", 5),
0174     MT7629_PIN(59, "GPIO_6", 6),
0175     MT7629_PIN(60, "GPIO_7", 7),
0176     MT7629_PIN(61, "GPIO_8", 8),
0177     MT7629_PIN(62, "SPI_CLK", 62),
0178     MT7629_PIN(63, "SPI_CS", 63),
0179     MT7629_PIN(64, "SPI_MOSI", 64),
0180     MT7629_PIN(65, "SPI_MISO", 65),
0181     MT7629_PIN(66, "SPI_WP", 66),
0182     MT7629_PIN(67, "SPI_HOLD", 67),
0183     MT7629_PIN(68, "UART0_TXD", 68),
0184     MT7629_PIN(69, "UART0_RXD", 69),
0185     MT7629_PIN(70, "TOP_2G_CLK", 70),
0186     MT7629_PIN(71, "TOP_2G_DATA", 71),
0187     MT7629_PIN(72, "WF0_2G_HB0", 72),
0188     MT7629_PIN(73, "WF0_2G_HB1", 73),
0189     MT7629_PIN(74, "WF0_2G_HB2", 74),
0190     MT7629_PIN(75, "WF0_2G_HB3", 75),
0191     MT7629_PIN(76, "WF0_2G_HB4", 76),
0192     MT7629_PIN(77, "WF0_2G_HB5", 77),
0193     MT7629_PIN(78, "WF0_2G_HB6", 78),
0194 };
0195 
0196 /* List all groups consisting of these pins dedicated to the enablement of
0197  * certain hardware block and the corresponding mode for all of the pins.
0198  * The hardware probably has multiple combinations of these pinouts.
0199  */
0200 
0201 /* LED for EPHY */
0202 static int mt7629_ephy_leds_pins[] = { 12, 13, 14, 15, 16, 17, 18, };
0203 static int mt7629_ephy_leds_funcs[] = { 1, 1, 1, 1, 1, 1, 1, };
0204 static int mt7629_ephy_led0_pins[] = { 12, };
0205 static int mt7629_ephy_led0_funcs[] = { 1, };
0206 static int mt7629_ephy_led1_pins[] = { 13, };
0207 static int mt7629_ephy_led1_funcs[] = { 1, };
0208 static int mt7629_ephy_led2_pins[] = { 14, };
0209 static int mt7629_ephy_led2_funcs[] = { 1, };
0210 static int mt7629_ephy_led3_pins[] = { 15, };
0211 static int mt7629_ephy_led3_funcs[] = { 1, };
0212 static int mt7629_ephy_led4_pins[] = { 16, };
0213 static int mt7629_ephy_led4_funcs[] = { 1, };
0214 static int mt7629_wf2g_led_pins[] = { 17, };
0215 static int mt7629_wf2g_led_funcs[] = { 1, };
0216 static int mt7629_wf5g_led_pins[] = { 18, };
0217 static int mt7629_wf5g_led_funcs[] = { 1, };
0218 
0219 /* Watchdog */
0220 static int mt7629_watchdog_pins[] = { 11, };
0221 static int mt7629_watchdog_funcs[] = { 1, };
0222 
0223 /* LED for GPHY */
0224 static int mt7629_gphy_leds_0_pins[] = { 21, 22, 23, };
0225 static int mt7629_gphy_leds_0_funcs[] = { 2, 2, 2, };
0226 static int mt7629_gphy_led1_0_pins[] = { 21, };
0227 static int mt7629_gphy_led1_0_funcs[] = { 2, };
0228 static int mt7629_gphy_led2_0_pins[] = { 22, };
0229 static int mt7629_gphy_led2_0_funcs[] = { 2, };
0230 static int mt7629_gphy_led3_0_pins[] = { 23, };
0231 static int mt7629_gphy_led3_0_funcs[] = { 2, };
0232 static int mt7629_gphy_leds_1_pins[] = { 57, 58, 59, };
0233 static int mt7629_gphy_leds_1_funcs[] = { 1, 1, 1, };
0234 static int mt7629_gphy_led1_1_pins[] = { 57, };
0235 static int mt7629_gphy_led1_1_funcs[] = { 1, };
0236 static int mt7629_gphy_led2_1_pins[] = { 58, };
0237 static int mt7629_gphy_led2_1_funcs[] = { 1, };
0238 static int mt7629_gphy_led3_1_pins[] = { 59, };
0239 static int mt7629_gphy_led3_1_funcs[] = { 1, };
0240 
0241 /* I2C */
0242 static int mt7629_i2c_0_pins[] = { 19, 20, };
0243 static int mt7629_i2c_0_funcs[] = { 1, 1, };
0244 static int mt7629_i2c_1_pins[] = { 53, 54, };
0245 static int mt7629_i2c_1_funcs[] = { 1, 1, };
0246 
0247 /* SPI */
0248 static int mt7629_spi_0_pins[] = { 21, 22, 23, 24, };
0249 static int mt7629_spi_0_funcs[] = { 1, 1, 1, 1, };
0250 static int mt7629_spi_1_pins[] = { 62, 63, 64, 65, };
0251 static int mt7629_spi_1_funcs[] = { 1, 1, 1, 1, };
0252 static int mt7629_spi_wp_pins[] = { 66, };
0253 static int mt7629_spi_wp_funcs[] = { 1, };
0254 static int mt7629_spi_hold_pins[] = { 67, };
0255 static int mt7629_spi_hold_funcs[] = { 1, };
0256 
0257 /* UART */
0258 static int mt7629_uart1_0_txd_rxd_pins[] = { 25, 26, };
0259 static int mt7629_uart1_0_txd_rxd_funcs[] = { 1, 1, };
0260 static int mt7629_uart1_1_txd_rxd_pins[] = { 53, 54, };
0261 static int mt7629_uart1_1_txd_rxd_funcs[] = { 2, 2, };
0262 static int mt7629_uart2_0_txd_rxd_pins[] = { 29, 30, };
0263 static int mt7629_uart2_0_txd_rxd_funcs[] = { 1, 1, };
0264 static int mt7629_uart2_1_txd_rxd_pins[] = { 57, 58, };
0265 static int mt7629_uart2_1_txd_rxd_funcs[] = { 2, 2, };
0266 static int mt7629_uart1_0_cts_rts_pins[] = { 27, 28, };
0267 static int mt7629_uart1_0_cts_rts_funcs[] = { 1, 1, };
0268 static int mt7629_uart1_1_cts_rts_pins[] = { 55, 56, };
0269 static int mt7629_uart1_1_cts_rts_funcs[] = { 2, 2, };
0270 static int mt7629_uart2_0_cts_rts_pins[] = { 31, 32, };
0271 static int mt7629_uart2_0_cts_rts_funcs[] = { 1, 1, };
0272 static int mt7629_uart2_1_cts_rts_pins[] = { 59, 60, };
0273 static int mt7629_uart2_1_cts_rts_funcs[] = { 2, 2, };
0274 static int mt7629_uart0_txd_rxd_pins[] = { 68, 69, };
0275 static int mt7629_uart0_txd_rxd_funcs[] = { 1, 1, };
0276 
0277 /* MDC/MDIO */
0278 static int mt7629_mdc_mdio_pins[] = { 49, 50, };
0279 static int mt7629_mdc_mdio_funcs[] = { 1, 1, };
0280 
0281 /* PCIE */
0282 static int mt7629_pcie_pereset_pins[] = { 51, };
0283 static int mt7629_pcie_pereset_funcs[] = { 1, };
0284 static int mt7629_pcie_wake_pins[] = { 55, };
0285 static int mt7629_pcie_wake_funcs[] = { 1, };
0286 static int mt7629_pcie_clkreq_pins[] = { 56, };
0287 static int mt7629_pcie_clkreq_funcs[] = { 1, };
0288 
0289 /* PWM */
0290 static int mt7629_pwm_0_pins[] = { 52, };
0291 static int mt7629_pwm_0_funcs[] = { 1, };
0292 static int mt7629_pwm_1_pins[] = { 61, };
0293 static int mt7629_pwm_1_funcs[] = { 2, };
0294 
0295 /* WF 2G */
0296 static int mt7629_wf0_2g_pins[] = { 70, 71, 72, 73, 74, 75, 76, 77, 78, };
0297 static int mt7629_wf0_2g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, };
0298 
0299 /* WF 5G */
0300 static int mt7629_wf0_5g_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, };
0301 static int mt7629_wf0_5g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
0302 
0303 /* SNFI */
0304 static int mt7629_snfi_pins[] = { 62, 63, 64, 65, 66, 67 };
0305 static int mt7629_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 };
0306 
0307 /* SPI NOR */
0308 static int mt7629_snor_pins[] = { 62, 63, 64, 65, 66, 67 };
0309 static int mt7629_snor_funcs[] = { 1, 1, 1, 1, 1, 1 };
0310 
0311 static const struct group_desc mt7629_groups[] = {
0312     PINCTRL_PIN_GROUP("ephy_leds", mt7629_ephy_leds),
0313     PINCTRL_PIN_GROUP("ephy_led0", mt7629_ephy_led0),
0314     PINCTRL_PIN_GROUP("ephy_led1", mt7629_ephy_led1),
0315     PINCTRL_PIN_GROUP("ephy_led2", mt7629_ephy_led2),
0316     PINCTRL_PIN_GROUP("ephy_led3", mt7629_ephy_led3),
0317     PINCTRL_PIN_GROUP("ephy_led4", mt7629_ephy_led4),
0318     PINCTRL_PIN_GROUP("wf2g_led", mt7629_wf2g_led),
0319     PINCTRL_PIN_GROUP("wf5g_led", mt7629_wf5g_led),
0320     PINCTRL_PIN_GROUP("watchdog", mt7629_watchdog),
0321     PINCTRL_PIN_GROUP("gphy_leds_0", mt7629_gphy_leds_0),
0322     PINCTRL_PIN_GROUP("gphy_led1_0", mt7629_gphy_led1_0),
0323     PINCTRL_PIN_GROUP("gphy_led2_0", mt7629_gphy_led2_0),
0324     PINCTRL_PIN_GROUP("gphy_led3_0", mt7629_gphy_led3_0),
0325     PINCTRL_PIN_GROUP("gphy_leds_1", mt7629_gphy_leds_1),
0326     PINCTRL_PIN_GROUP("gphy_led1_1", mt7629_gphy_led1_1),
0327     PINCTRL_PIN_GROUP("gphy_led2_1", mt7629_gphy_led2_1),
0328     PINCTRL_PIN_GROUP("gphy_led3_1", mt7629_gphy_led3_1),
0329     PINCTRL_PIN_GROUP("i2c_0", mt7629_i2c_0),
0330     PINCTRL_PIN_GROUP("i2c_1", mt7629_i2c_1),
0331     PINCTRL_PIN_GROUP("spi_0", mt7629_spi_0),
0332     PINCTRL_PIN_GROUP("spi_1", mt7629_spi_1),
0333     PINCTRL_PIN_GROUP("spi_wp", mt7629_spi_wp),
0334     PINCTRL_PIN_GROUP("spi_hold", mt7629_spi_hold),
0335     PINCTRL_PIN_GROUP("uart1_0_txd_rxd", mt7629_uart1_0_txd_rxd),
0336     PINCTRL_PIN_GROUP("uart1_1_txd_rxd", mt7629_uart1_1_txd_rxd),
0337     PINCTRL_PIN_GROUP("uart2_0_txd_rxd", mt7629_uart2_0_txd_rxd),
0338     PINCTRL_PIN_GROUP("uart2_1_txd_rxd", mt7629_uart2_1_txd_rxd),
0339     PINCTRL_PIN_GROUP("uart1_0_cts_rts", mt7629_uart1_0_cts_rts),
0340     PINCTRL_PIN_GROUP("uart1_1_cts_rts", mt7629_uart1_1_cts_rts),
0341     PINCTRL_PIN_GROUP("uart2_0_cts_rts", mt7629_uart2_0_cts_rts),
0342     PINCTRL_PIN_GROUP("uart2_1_cts_rts", mt7629_uart2_1_cts_rts),
0343     PINCTRL_PIN_GROUP("uart0_txd_rxd", mt7629_uart0_txd_rxd),
0344     PINCTRL_PIN_GROUP("mdc_mdio", mt7629_mdc_mdio),
0345     PINCTRL_PIN_GROUP("pcie_pereset", mt7629_pcie_pereset),
0346     PINCTRL_PIN_GROUP("pcie_wake", mt7629_pcie_wake),
0347     PINCTRL_PIN_GROUP("pcie_clkreq", mt7629_pcie_clkreq),
0348     PINCTRL_PIN_GROUP("pwm_0", mt7629_pwm_0),
0349     PINCTRL_PIN_GROUP("pwm_1", mt7629_pwm_1),
0350     PINCTRL_PIN_GROUP("wf0_5g", mt7629_wf0_5g),
0351     PINCTRL_PIN_GROUP("wf0_2g", mt7629_wf0_2g),
0352     PINCTRL_PIN_GROUP("snfi", mt7629_snfi),
0353     PINCTRL_PIN_GROUP("spi_nor", mt7629_snor),
0354 };
0355 
0356 /* Joint those groups owning the same capability in user point of view which
0357  * allows that people tend to use through the device tree.
0358  */
0359 static const char *mt7629_ethernet_groups[] = { "mdc_mdio", };
0360 static const char *mt7629_i2c_groups[] = { "i2c_0", "i2c_1", };
0361 static const char *mt7629_led_groups[] = { "ephy_leds", "ephy_led0",
0362                        "ephy_led1", "ephy_led2",
0363                        "ephy_led3", "ephy_led4",
0364                        "wf2g_led", "wf5g_led",
0365                        "gphy_leds_0", "gphy_led1_0",
0366                        "gphy_led2_0", "gphy_led3_0",
0367                        "gphy_leds_1", "gphy_led1_1",
0368                        "gphy_led2_1", "gphy_led3_1",};
0369 static const char *mt7629_pcie_groups[] = { "pcie_pereset", "pcie_wake",
0370                         "pcie_clkreq", };
0371 static const char *mt7629_pwm_groups[] = { "pwm_0", "pwm_1", };
0372 static const char *mt7629_spi_groups[] = { "spi_0", "spi_1", "spi_wp",
0373                        "spi_hold", };
0374 static const char *mt7629_uart_groups[] = { "uart1_0_txd_rxd",
0375                         "uart1_1_txd_rxd",
0376                         "uart2_0_txd_rxd",
0377                         "uart2_1_txd_rxd",
0378                         "uart1_0_cts_rts",
0379                         "uart1_1_cts_rts",
0380                         "uart2_0_cts_rts",
0381                         "uart2_1_cts_rts",
0382                         "uart0_txd_rxd", };
0383 static const char *mt7629_wdt_groups[] = { "watchdog", };
0384 static const char *mt7629_wifi_groups[] = { "wf0_5g", "wf0_2g", };
0385 static const char *mt7629_flash_groups[] = { "snfi", "spi_nor" };
0386 
0387 static const struct function_desc mt7629_functions[] = {
0388     {"eth", mt7629_ethernet_groups, ARRAY_SIZE(mt7629_ethernet_groups)},
0389     {"i2c", mt7629_i2c_groups, ARRAY_SIZE(mt7629_i2c_groups)},
0390     {"led", mt7629_led_groups, ARRAY_SIZE(mt7629_led_groups)},
0391     {"pcie", mt7629_pcie_groups, ARRAY_SIZE(mt7629_pcie_groups)},
0392     {"pwm", mt7629_pwm_groups, ARRAY_SIZE(mt7629_pwm_groups)},
0393     {"spi", mt7629_spi_groups, ARRAY_SIZE(mt7629_spi_groups)},
0394     {"uart", mt7629_uart_groups, ARRAY_SIZE(mt7629_uart_groups)},
0395     {"watchdog", mt7629_wdt_groups, ARRAY_SIZE(mt7629_wdt_groups)},
0396     {"wifi", mt7629_wifi_groups, ARRAY_SIZE(mt7629_wifi_groups)},
0397     {"flash", mt7629_flash_groups, ARRAY_SIZE(mt7629_flash_groups)},
0398 };
0399 
0400 static const struct mtk_eint_hw mt7629_eint_hw = {
0401     .port_mask = 7,
0402     .ports     = 7,
0403     .ap_num    = ARRAY_SIZE(mt7629_pins),
0404     .db_cnt    = 16,
0405 };
0406 
0407 static struct mtk_pin_soc mt7629_data = {
0408     .reg_cal = mt7629_reg_cals,
0409     .pins = mt7629_pins,
0410     .npins = ARRAY_SIZE(mt7629_pins),
0411     .grps = mt7629_groups,
0412     .ngrps = ARRAY_SIZE(mt7629_groups),
0413     .funcs = mt7629_functions,
0414     .nfuncs = ARRAY_SIZE(mt7629_functions),
0415     .eint_hw = &mt7629_eint_hw,
0416     .gpio_m = 0,
0417     .ies_present = true,
0418     .base_names = mtk_default_register_base_names,
0419     .nbase_names = ARRAY_SIZE(mtk_default_register_base_names),
0420     .bias_disable_set = mtk_pinconf_bias_disable_set_rev1,
0421     .bias_disable_get = mtk_pinconf_bias_disable_get_rev1,
0422     .bias_set = mtk_pinconf_bias_set_rev1,
0423     .bias_get = mtk_pinconf_bias_get_rev1,
0424     .drive_set = mtk_pinconf_drive_set_rev1,
0425     .drive_get = mtk_pinconf_drive_get_rev1,
0426 };
0427 
0428 static const struct of_device_id mt7629_pinctrl_of_match[] = {
0429     { .compatible = "mediatek,mt7629-pinctrl", },
0430     {}
0431 };
0432 
0433 static int mt7629_pinctrl_probe(struct platform_device *pdev)
0434 {
0435     return mtk_moore_pinctrl_probe(pdev, &mt7629_data);
0436 }
0437 
0438 static struct platform_driver mt7629_pinctrl_driver = {
0439     .driver = {
0440         .name = "mt7629-pinctrl",
0441         .of_match_table = mt7629_pinctrl_of_match,
0442     },
0443     .probe = mt7629_pinctrl_probe,
0444 };
0445 
0446 static int __init mt7629_pinctrl_init(void)
0447 {
0448     return platform_driver_register(&mt7629_pinctrl_driver);
0449 }
0450 arch_initcall(mt7629_pinctrl_init);
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