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0010 #include <linux/mod_devicetable.h>
0011 #include <linux/module.h>
0012 #include <linux/platform_device.h>
0013
0014 #include <linux/pinctrl/pinctrl.h>
0015
0016 #include "pinctrl-intel.h"
0017
0018 #define SPT_PAD_OWN 0x020
0019 #define SPT_H_PADCFGLOCK 0x090
0020 #define SPT_LP_PADCFGLOCK 0x0a0
0021 #define SPT_HOSTSW_OWN 0x0d0
0022 #define SPT_GPI_IS 0x100
0023 #define SPT_GPI_IE 0x120
0024
0025 #define SPT_COMMUNITY(b, s, e, pl, gs, gn, g, n) \
0026 { \
0027 .barno = (b), \
0028 .padown_offset = SPT_PAD_OWN, \
0029 .padcfglock_offset = (pl), \
0030 .hostown_offset = SPT_HOSTSW_OWN, \
0031 .is_offset = SPT_GPI_IS, \
0032 .ie_offset = SPT_GPI_IE, \
0033 .gpp_size = (gs), \
0034 .gpp_num_padown_regs = (gn), \
0035 .pin_base = (s), \
0036 .npins = ((e) - (s) + 1), \
0037 .gpps = (g), \
0038 .ngpps = (n), \
0039 }
0040
0041 #define SPT_LP_COMMUNITY(b, s, e) \
0042 SPT_COMMUNITY(b, s, e, SPT_LP_PADCFGLOCK, 24, 4, NULL, 0)
0043
0044 #define SPT_H_GPP(r, s, e, g) \
0045 { \
0046 .reg_num = (r), \
0047 .base = (s), \
0048 .size = ((e) - (s) + 1), \
0049 .gpio_base = (g), \
0050 }
0051
0052 #define SPT_H_COMMUNITY(b, s, e, g) \
0053 SPT_COMMUNITY(b, s, e, SPT_H_PADCFGLOCK, 0, 0, g, ARRAY_SIZE(g))
0054
0055
0056 static const struct pinctrl_pin_desc sptlp_pins[] = {
0057
0058 PINCTRL_PIN(0, "RCINB"),
0059 PINCTRL_PIN(1, "LAD_0"),
0060 PINCTRL_PIN(2, "LAD_1"),
0061 PINCTRL_PIN(3, "LAD_2"),
0062 PINCTRL_PIN(4, "LAD_3"),
0063 PINCTRL_PIN(5, "LFRAMEB"),
0064 PINCTRL_PIN(6, "SERIQ"),
0065 PINCTRL_PIN(7, "PIRQAB"),
0066 PINCTRL_PIN(8, "CLKRUNB"),
0067 PINCTRL_PIN(9, "CLKOUT_LPC_0"),
0068 PINCTRL_PIN(10, "CLKOUT_LPC_1"),
0069 PINCTRL_PIN(11, "PMEB"),
0070 PINCTRL_PIN(12, "BM_BUSYB"),
0071 PINCTRL_PIN(13, "SUSWARNB_SUS_PWRDNACK"),
0072 PINCTRL_PIN(14, "SUS_STATB"),
0073 PINCTRL_PIN(15, "SUSACKB"),
0074 PINCTRL_PIN(16, "SD_1P8_SEL"),
0075 PINCTRL_PIN(17, "SD_PWR_EN_B"),
0076 PINCTRL_PIN(18, "ISH_GP_0"),
0077 PINCTRL_PIN(19, "ISH_GP_1"),
0078 PINCTRL_PIN(20, "ISH_GP_2"),
0079 PINCTRL_PIN(21, "ISH_GP_3"),
0080 PINCTRL_PIN(22, "ISH_GP_4"),
0081 PINCTRL_PIN(23, "ISH_GP_5"),
0082
0083 PINCTRL_PIN(24, "CORE_VID_0"),
0084 PINCTRL_PIN(25, "CORE_VID_1"),
0085 PINCTRL_PIN(26, "VRALERTB"),
0086 PINCTRL_PIN(27, "CPU_GP_2"),
0087 PINCTRL_PIN(28, "CPU_GP_3"),
0088 PINCTRL_PIN(29, "SRCCLKREQB_0"),
0089 PINCTRL_PIN(30, "SRCCLKREQB_1"),
0090 PINCTRL_PIN(31, "SRCCLKREQB_2"),
0091 PINCTRL_PIN(32, "SRCCLKREQB_3"),
0092 PINCTRL_PIN(33, "SRCCLKREQB_4"),
0093 PINCTRL_PIN(34, "SRCCLKREQB_5"),
0094 PINCTRL_PIN(35, "EXT_PWR_GATEB"),
0095 PINCTRL_PIN(36, "SLP_S0B"),
0096 PINCTRL_PIN(37, "PLTRSTB"),
0097 PINCTRL_PIN(38, "SPKR"),
0098 PINCTRL_PIN(39, "GSPI0_CSB"),
0099 PINCTRL_PIN(40, "GSPI0_CLK"),
0100 PINCTRL_PIN(41, "GSPI0_MISO"),
0101 PINCTRL_PIN(42, "GSPI0_MOSI"),
0102 PINCTRL_PIN(43, "GSPI1_CSB"),
0103 PINCTRL_PIN(44, "GSPI1_CLK"),
0104 PINCTRL_PIN(45, "GSPI1_MISO"),
0105 PINCTRL_PIN(46, "GSPI1_MOSI"),
0106 PINCTRL_PIN(47, "SML1ALERTB"),
0107
0108 PINCTRL_PIN(48, "SMBCLK"),
0109 PINCTRL_PIN(49, "SMBDATA"),
0110 PINCTRL_PIN(50, "SMBALERTB"),
0111 PINCTRL_PIN(51, "SML0CLK"),
0112 PINCTRL_PIN(52, "SML0DATA"),
0113 PINCTRL_PIN(53, "SML0ALERTB"),
0114 PINCTRL_PIN(54, "SML1CLK"),
0115 PINCTRL_PIN(55, "SML1DATA"),
0116 PINCTRL_PIN(56, "UART0_RXD"),
0117 PINCTRL_PIN(57, "UART0_TXD"),
0118 PINCTRL_PIN(58, "UART0_RTSB"),
0119 PINCTRL_PIN(59, "UART0_CTSB"),
0120 PINCTRL_PIN(60, "UART1_RXD"),
0121 PINCTRL_PIN(61, "UART1_TXD"),
0122 PINCTRL_PIN(62, "UART1_RTSB"),
0123 PINCTRL_PIN(63, "UART1_CTSB"),
0124 PINCTRL_PIN(64, "I2C0_SDA"),
0125 PINCTRL_PIN(65, "I2C0_SCL"),
0126 PINCTRL_PIN(66, "I2C1_SDA"),
0127 PINCTRL_PIN(67, "I2C1_SCL"),
0128 PINCTRL_PIN(68, "UART2_RXD"),
0129 PINCTRL_PIN(69, "UART2_TXD"),
0130 PINCTRL_PIN(70, "UART2_RTSB"),
0131 PINCTRL_PIN(71, "UART2_CTSB"),
0132
0133 PINCTRL_PIN(72, "SPI1_CSB"),
0134 PINCTRL_PIN(73, "SPI1_CLK"),
0135 PINCTRL_PIN(74, "SPI1_MISO_IO_1"),
0136 PINCTRL_PIN(75, "SPI1_MOSI_IO_0"),
0137 PINCTRL_PIN(76, "FLASHTRIG"),
0138 PINCTRL_PIN(77, "ISH_I2C0_SDA"),
0139 PINCTRL_PIN(78, "ISH_I2C0_SCL"),
0140 PINCTRL_PIN(79, "ISH_I2C1_SDA"),
0141 PINCTRL_PIN(80, "ISH_I2C1_SCL"),
0142 PINCTRL_PIN(81, "ISH_SPI_CSB"),
0143 PINCTRL_PIN(82, "ISH_SPI_CLK"),
0144 PINCTRL_PIN(83, "ISH_SPI_MISO"),
0145 PINCTRL_PIN(84, "ISH_SPI_MOSI"),
0146 PINCTRL_PIN(85, "ISH_UART0_RXD"),
0147 PINCTRL_PIN(86, "ISH_UART0_TXD"),
0148 PINCTRL_PIN(87, "ISH_UART0_RTSB"),
0149 PINCTRL_PIN(88, "ISH_UART0_CTSB"),
0150 PINCTRL_PIN(89, "DMIC_CLK_1"),
0151 PINCTRL_PIN(90, "DMIC_DATA_1"),
0152 PINCTRL_PIN(91, "DMIC_CLK_0"),
0153 PINCTRL_PIN(92, "DMIC_DATA_0"),
0154 PINCTRL_PIN(93, "SPI1_IO_2"),
0155 PINCTRL_PIN(94, "SPI1_IO_3"),
0156 PINCTRL_PIN(95, "SSP_MCLK"),
0157
0158 PINCTRL_PIN(96, "SATAXPCIE_0"),
0159 PINCTRL_PIN(97, "SATAXPCIE_1"),
0160 PINCTRL_PIN(98, "SATAXPCIE_2"),
0161 PINCTRL_PIN(99, "CPU_GP_0"),
0162 PINCTRL_PIN(100, "SATA_DEVSLP_0"),
0163 PINCTRL_PIN(101, "SATA_DEVSLP_1"),
0164 PINCTRL_PIN(102, "SATA_DEVSLP_2"),
0165 PINCTRL_PIN(103, "CPU_GP_1"),
0166 PINCTRL_PIN(104, "SATA_LEDB"),
0167 PINCTRL_PIN(105, "USB2_OCB_0"),
0168 PINCTRL_PIN(106, "USB2_OCB_1"),
0169 PINCTRL_PIN(107, "USB2_OCB_2"),
0170 PINCTRL_PIN(108, "USB2_OCB_3"),
0171 PINCTRL_PIN(109, "DDSP_HPD_0"),
0172 PINCTRL_PIN(110, "DDSP_HPD_1"),
0173 PINCTRL_PIN(111, "DDSP_HPD_2"),
0174 PINCTRL_PIN(112, "DDSP_HPD_3"),
0175 PINCTRL_PIN(113, "EDP_HPD"),
0176 PINCTRL_PIN(114, "DDPB_CTRLCLK"),
0177 PINCTRL_PIN(115, "DDPB_CTRLDATA"),
0178 PINCTRL_PIN(116, "DDPC_CTRLCLK"),
0179 PINCTRL_PIN(117, "DDPC_CTRLDATA"),
0180 PINCTRL_PIN(118, "DDPD_CTRLCLK"),
0181 PINCTRL_PIN(119, "DDPD_CTRLDATA"),
0182
0183 PINCTRL_PIN(120, "SSP2_SCLK"),
0184 PINCTRL_PIN(121, "SSP2_SFRM"),
0185 PINCTRL_PIN(122, "SSP2_TXD"),
0186 PINCTRL_PIN(123, "SSP2_RXD"),
0187 PINCTRL_PIN(124, "I2C2_SDA"),
0188 PINCTRL_PIN(125, "I2C2_SCL"),
0189 PINCTRL_PIN(126, "I2C3_SDA"),
0190 PINCTRL_PIN(127, "I2C3_SCL"),
0191 PINCTRL_PIN(128, "I2C4_SDA"),
0192 PINCTRL_PIN(129, "I2C4_SCL"),
0193 PINCTRL_PIN(130, "I2C5_SDA"),
0194 PINCTRL_PIN(131, "I2C5_SCL"),
0195 PINCTRL_PIN(132, "EMMC_CMD"),
0196 PINCTRL_PIN(133, "EMMC_DATA_0"),
0197 PINCTRL_PIN(134, "EMMC_DATA_1"),
0198 PINCTRL_PIN(135, "EMMC_DATA_2"),
0199 PINCTRL_PIN(136, "EMMC_DATA_3"),
0200 PINCTRL_PIN(137, "EMMC_DATA_4"),
0201 PINCTRL_PIN(138, "EMMC_DATA_5"),
0202 PINCTRL_PIN(139, "EMMC_DATA_6"),
0203 PINCTRL_PIN(140, "EMMC_DATA_7"),
0204 PINCTRL_PIN(141, "EMMC_RCLK"),
0205 PINCTRL_PIN(142, "EMMC_CLK"),
0206 PINCTRL_PIN(143, "GPP_F_23"),
0207
0208 PINCTRL_PIN(144, "SD_CMD"),
0209 PINCTRL_PIN(145, "SD_DATA_0"),
0210 PINCTRL_PIN(146, "SD_DATA_1"),
0211 PINCTRL_PIN(147, "SD_DATA_2"),
0212 PINCTRL_PIN(148, "SD_DATA_3"),
0213 PINCTRL_PIN(149, "SD_CDB"),
0214 PINCTRL_PIN(150, "SD_CLK"),
0215 PINCTRL_PIN(151, "SD_WP"),
0216 };
0217
0218 static const unsigned sptlp_spi0_pins[] = { 39, 40, 41, 42 };
0219 static const unsigned sptlp_spi1_pins[] = { 43, 44, 45, 46 };
0220 static const unsigned sptlp_uart0_pins[] = { 56, 57, 58, 59 };
0221 static const unsigned sptlp_uart1_pins[] = { 60, 61, 62, 63 };
0222 static const unsigned sptlp_uart2_pins[] = { 68, 69, 71, 71 };
0223 static const unsigned sptlp_i2c0_pins[] = { 64, 65 };
0224 static const unsigned sptlp_i2c1_pins[] = { 66, 67 };
0225 static const unsigned sptlp_i2c2_pins[] = { 124, 125 };
0226 static const unsigned sptlp_i2c3_pins[] = { 126, 127 };
0227 static const unsigned sptlp_i2c4_pins[] = { 128, 129 };
0228 static const unsigned sptlp_i2c4b_pins[] = { 85, 86 };
0229 static const unsigned sptlp_i2c5_pins[] = { 130, 131 };
0230 static const unsigned sptlp_ssp2_pins[] = { 120, 121, 122, 123 };
0231 static const unsigned sptlp_emmc_pins[] = {
0232 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142,
0233 };
0234 static const unsigned sptlp_sd_pins[] = {
0235 144, 145, 146, 147, 148, 149, 150, 151,
0236 };
0237
0238 static const struct intel_pingroup sptlp_groups[] = {
0239 PIN_GROUP("spi0_grp", sptlp_spi0_pins, 1),
0240 PIN_GROUP("spi1_grp", sptlp_spi1_pins, 1),
0241 PIN_GROUP("uart0_grp", sptlp_uart0_pins, 1),
0242 PIN_GROUP("uart1_grp", sptlp_uart1_pins, 1),
0243 PIN_GROUP("uart2_grp", sptlp_uart2_pins, 1),
0244 PIN_GROUP("i2c0_grp", sptlp_i2c0_pins, 1),
0245 PIN_GROUP("i2c1_grp", sptlp_i2c1_pins, 1),
0246 PIN_GROUP("i2c2_grp", sptlp_i2c2_pins, 1),
0247 PIN_GROUP("i2c3_grp", sptlp_i2c3_pins, 1),
0248 PIN_GROUP("i2c4_grp", sptlp_i2c4_pins, 1),
0249 PIN_GROUP("i2c4b_grp", sptlp_i2c4b_pins, 3),
0250 PIN_GROUP("i2c5_grp", sptlp_i2c5_pins, 1),
0251 PIN_GROUP("ssp2_grp", sptlp_ssp2_pins, 1),
0252 PIN_GROUP("emmc_grp", sptlp_emmc_pins, 1),
0253 PIN_GROUP("sd_grp", sptlp_sd_pins, 1),
0254 };
0255
0256 static const char * const sptlp_spi0_groups[] = { "spi0_grp" };
0257 static const char * const sptlp_spi1_groups[] = { "spi0_grp" };
0258 static const char * const sptlp_uart0_groups[] = { "uart0_grp" };
0259 static const char * const sptlp_uart1_groups[] = { "uart1_grp" };
0260 static const char * const sptlp_uart2_groups[] = { "uart2_grp" };
0261 static const char * const sptlp_i2c0_groups[] = { "i2c0_grp" };
0262 static const char * const sptlp_i2c1_groups[] = { "i2c1_grp" };
0263 static const char * const sptlp_i2c2_groups[] = { "i2c2_grp" };
0264 static const char * const sptlp_i2c3_groups[] = { "i2c3_grp" };
0265 static const char * const sptlp_i2c4_groups[] = { "i2c4_grp", "i2c4b_grp" };
0266 static const char * const sptlp_i2c5_groups[] = { "i2c5_grp" };
0267 static const char * const sptlp_ssp2_groups[] = { "ssp2_grp" };
0268 static const char * const sptlp_emmc_groups[] = { "emmc_grp" };
0269 static const char * const sptlp_sd_groups[] = { "sd_grp" };
0270
0271 static const struct intel_function sptlp_functions[] = {
0272 FUNCTION("spi0", sptlp_spi0_groups),
0273 FUNCTION("spi1", sptlp_spi1_groups),
0274 FUNCTION("uart0", sptlp_uart0_groups),
0275 FUNCTION("uart1", sptlp_uart1_groups),
0276 FUNCTION("uart2", sptlp_uart2_groups),
0277 FUNCTION("i2c0", sptlp_i2c0_groups),
0278 FUNCTION("i2c1", sptlp_i2c1_groups),
0279 FUNCTION("i2c2", sptlp_i2c2_groups),
0280 FUNCTION("i2c3", sptlp_i2c3_groups),
0281 FUNCTION("i2c4", sptlp_i2c4_groups),
0282 FUNCTION("i2c5", sptlp_i2c5_groups),
0283 FUNCTION("ssp2", sptlp_ssp2_groups),
0284 FUNCTION("emmc", sptlp_emmc_groups),
0285 FUNCTION("sd", sptlp_sd_groups),
0286 };
0287
0288 static const struct intel_community sptlp_communities[] = {
0289 SPT_LP_COMMUNITY(0, 0, 47),
0290 SPT_LP_COMMUNITY(1, 48, 119),
0291 SPT_LP_COMMUNITY(2, 120, 151),
0292 };
0293
0294 static const struct intel_pinctrl_soc_data sptlp_soc_data = {
0295 .pins = sptlp_pins,
0296 .npins = ARRAY_SIZE(sptlp_pins),
0297 .groups = sptlp_groups,
0298 .ngroups = ARRAY_SIZE(sptlp_groups),
0299 .functions = sptlp_functions,
0300 .nfunctions = ARRAY_SIZE(sptlp_functions),
0301 .communities = sptlp_communities,
0302 .ncommunities = ARRAY_SIZE(sptlp_communities),
0303 };
0304
0305
0306 static const struct pinctrl_pin_desc spth_pins[] = {
0307
0308 PINCTRL_PIN(0, "RCINB"),
0309 PINCTRL_PIN(1, "LAD_0"),
0310 PINCTRL_PIN(2, "LAD_1"),
0311 PINCTRL_PIN(3, "LAD_2"),
0312 PINCTRL_PIN(4, "LAD_3"),
0313 PINCTRL_PIN(5, "LFRAMEB"),
0314 PINCTRL_PIN(6, "SERIQ"),
0315 PINCTRL_PIN(7, "PIRQAB"),
0316 PINCTRL_PIN(8, "CLKRUNB"),
0317 PINCTRL_PIN(9, "CLKOUT_LPC_0"),
0318 PINCTRL_PIN(10, "CLKOUT_LPC_1"),
0319 PINCTRL_PIN(11, "PMEB"),
0320 PINCTRL_PIN(12, "BM_BUSYB"),
0321 PINCTRL_PIN(13, "SUSWARNB_SUS_PWRDNACK"),
0322 PINCTRL_PIN(14, "SUS_STATB"),
0323 PINCTRL_PIN(15, "SUSACKB"),
0324 PINCTRL_PIN(16, "CLKOUT_48"),
0325 PINCTRL_PIN(17, "ISH_GP_7"),
0326 PINCTRL_PIN(18, "ISH_GP_0"),
0327 PINCTRL_PIN(19, "ISH_GP_1"),
0328 PINCTRL_PIN(20, "ISH_GP_2"),
0329 PINCTRL_PIN(21, "ISH_GP_3"),
0330 PINCTRL_PIN(22, "ISH_GP_4"),
0331 PINCTRL_PIN(23, "ISH_GP_5"),
0332
0333 PINCTRL_PIN(24, "CORE_VID_0"),
0334 PINCTRL_PIN(25, "CORE_VID_1"),
0335 PINCTRL_PIN(26, "VRALERTB"),
0336 PINCTRL_PIN(27, "CPU_GP_2"),
0337 PINCTRL_PIN(28, "CPU_GP_3"),
0338 PINCTRL_PIN(29, "SRCCLKREQB_0"),
0339 PINCTRL_PIN(30, "SRCCLKREQB_1"),
0340 PINCTRL_PIN(31, "SRCCLKREQB_2"),
0341 PINCTRL_PIN(32, "SRCCLKREQB_3"),
0342 PINCTRL_PIN(33, "SRCCLKREQB_4"),
0343 PINCTRL_PIN(34, "SRCCLKREQB_5"),
0344 PINCTRL_PIN(35, "EXT_PWR_GATEB"),
0345 PINCTRL_PIN(36, "SLP_S0B"),
0346 PINCTRL_PIN(37, "PLTRSTB"),
0347 PINCTRL_PIN(38, "SPKR"),
0348 PINCTRL_PIN(39, "GSPI0_CSB"),
0349 PINCTRL_PIN(40, "GSPI0_CLK"),
0350 PINCTRL_PIN(41, "GSPI0_MISO"),
0351 PINCTRL_PIN(42, "GSPI0_MOSI"),
0352 PINCTRL_PIN(43, "GSPI1_CSB"),
0353 PINCTRL_PIN(44, "GSPI1_CLK"),
0354 PINCTRL_PIN(45, "GSPI1_MISO"),
0355 PINCTRL_PIN(46, "GSPI1_MOSI"),
0356 PINCTRL_PIN(47, "SML1ALERTB"),
0357
0358 PINCTRL_PIN(48, "SMBCLK"),
0359 PINCTRL_PIN(49, "SMBDATA"),
0360 PINCTRL_PIN(50, "SMBALERTB"),
0361 PINCTRL_PIN(51, "SML0CLK"),
0362 PINCTRL_PIN(52, "SML0DATA"),
0363 PINCTRL_PIN(53, "SML0ALERTB"),
0364 PINCTRL_PIN(54, "SML1CLK"),
0365 PINCTRL_PIN(55, "SML1DATA"),
0366 PINCTRL_PIN(56, "UART0_RXD"),
0367 PINCTRL_PIN(57, "UART0_TXD"),
0368 PINCTRL_PIN(58, "UART0_RTSB"),
0369 PINCTRL_PIN(59, "UART0_CTSB"),
0370 PINCTRL_PIN(60, "UART1_RXD"),
0371 PINCTRL_PIN(61, "UART1_TXD"),
0372 PINCTRL_PIN(62, "UART1_RTSB"),
0373 PINCTRL_PIN(63, "UART1_CTSB"),
0374 PINCTRL_PIN(64, "I2C0_SDA"),
0375 PINCTRL_PIN(65, "I2C0_SCL"),
0376 PINCTRL_PIN(66, "I2C1_SDA"),
0377 PINCTRL_PIN(67, "I2C1_SCL"),
0378 PINCTRL_PIN(68, "UART2_RXD"),
0379 PINCTRL_PIN(69, "UART2_TXD"),
0380 PINCTRL_PIN(70, "UART2_RTSB"),
0381 PINCTRL_PIN(71, "UART2_CTSB"),
0382
0383 PINCTRL_PIN(72, "SPI1_CSB"),
0384 PINCTRL_PIN(73, "SPI1_CLK"),
0385 PINCTRL_PIN(74, "SPI1_MISO_IO_1"),
0386 PINCTRL_PIN(75, "SPI1_MOSI_IO_0"),
0387 PINCTRL_PIN(76, "ISH_I2C2_SDA"),
0388 PINCTRL_PIN(77, "SSP0_SFRM"),
0389 PINCTRL_PIN(78, "SSP0_TXD"),
0390 PINCTRL_PIN(79, "SSP0_RXD"),
0391 PINCTRL_PIN(80, "SSP0_SCLK"),
0392 PINCTRL_PIN(81, "ISH_SPI_CSB"),
0393 PINCTRL_PIN(82, "ISH_SPI_CLK"),
0394 PINCTRL_PIN(83, "ISH_SPI_MISO"),
0395 PINCTRL_PIN(84, "ISH_SPI_MOSI"),
0396 PINCTRL_PIN(85, "ISH_UART0_RXD"),
0397 PINCTRL_PIN(86, "ISH_UART0_TXD"),
0398 PINCTRL_PIN(87, "ISH_UART0_RTSB"),
0399 PINCTRL_PIN(88, "ISH_UART0_CTSB"),
0400 PINCTRL_PIN(89, "DMIC_CLK_1"),
0401 PINCTRL_PIN(90, "DMIC_DATA_1"),
0402 PINCTRL_PIN(91, "DMIC_CLK_0"),
0403 PINCTRL_PIN(92, "DMIC_DATA_0"),
0404 PINCTRL_PIN(93, "SPI1_IO_2"),
0405 PINCTRL_PIN(94, "SPI1_IO_3"),
0406 PINCTRL_PIN(95, "ISH_I2C2_SCL"),
0407
0408 PINCTRL_PIN(96, "SATAXPCIE_0"),
0409 PINCTRL_PIN(97, "SATAXPCIE_1"),
0410 PINCTRL_PIN(98, "SATAXPCIE_2"),
0411 PINCTRL_PIN(99, "CPU_GP_0"),
0412 PINCTRL_PIN(100, "SATA_DEVSLP_0"),
0413 PINCTRL_PIN(101, "SATA_DEVSLP_1"),
0414 PINCTRL_PIN(102, "SATA_DEVSLP_2"),
0415 PINCTRL_PIN(103, "CPU_GP_1"),
0416 PINCTRL_PIN(104, "SATA_LEDB"),
0417 PINCTRL_PIN(105, "USB2_OCB_0"),
0418 PINCTRL_PIN(106, "USB2_OCB_1"),
0419 PINCTRL_PIN(107, "USB2_OCB_2"),
0420 PINCTRL_PIN(108, "USB2_OCB_3"),
0421
0422 PINCTRL_PIN(109, "SATAXPCIE_3"),
0423 PINCTRL_PIN(110, "SATAXPCIE_4"),
0424 PINCTRL_PIN(111, "SATAXPCIE_5"),
0425 PINCTRL_PIN(112, "SATAXPCIE_6"),
0426 PINCTRL_PIN(113, "SATAXPCIE_7"),
0427 PINCTRL_PIN(114, "SATA_DEVSLP_3"),
0428 PINCTRL_PIN(115, "SATA_DEVSLP_4"),
0429 PINCTRL_PIN(116, "SATA_DEVSLP_5"),
0430 PINCTRL_PIN(117, "SATA_DEVSLP_6"),
0431 PINCTRL_PIN(118, "SATA_DEVSLP_7"),
0432 PINCTRL_PIN(119, "SATA_SCLOCK"),
0433 PINCTRL_PIN(120, "SATA_SLOAD"),
0434 PINCTRL_PIN(121, "SATA_SDATAOUT1"),
0435 PINCTRL_PIN(122, "SATA_SDATAOUT0"),
0436 PINCTRL_PIN(123, "GPP_F_14"),
0437 PINCTRL_PIN(124, "USB_OCB_4"),
0438 PINCTRL_PIN(125, "USB_OCB_5"),
0439 PINCTRL_PIN(126, "USB_OCB_6"),
0440 PINCTRL_PIN(127, "USB_OCB_7"),
0441 PINCTRL_PIN(128, "L_VDDEN"),
0442 PINCTRL_PIN(129, "L_BKLTEN"),
0443 PINCTRL_PIN(130, "L_BKLTCTL"),
0444 PINCTRL_PIN(131, "GPP_F_22"),
0445 PINCTRL_PIN(132, "GPP_F_23"),
0446
0447 PINCTRL_PIN(133, "FAN_TACH_0"),
0448 PINCTRL_PIN(134, "FAN_TACH_1"),
0449 PINCTRL_PIN(135, "FAN_TACH_2"),
0450 PINCTRL_PIN(136, "FAN_TACH_3"),
0451 PINCTRL_PIN(137, "FAN_TACH_4"),
0452 PINCTRL_PIN(138, "FAN_TACH_5"),
0453 PINCTRL_PIN(139, "FAN_TACH_6"),
0454 PINCTRL_PIN(140, "FAN_TACH_7"),
0455 PINCTRL_PIN(141, "FAN_PWM_0"),
0456 PINCTRL_PIN(142, "FAN_PWM_1"),
0457 PINCTRL_PIN(143, "FAN_PWM_2"),
0458 PINCTRL_PIN(144, "FAN_PWM_3"),
0459 PINCTRL_PIN(145, "GSXDOUT"),
0460 PINCTRL_PIN(146, "GSXSLOAD"),
0461 PINCTRL_PIN(147, "GSXDIN"),
0462 PINCTRL_PIN(148, "GSXRESETB"),
0463 PINCTRL_PIN(149, "GSXCLK"),
0464 PINCTRL_PIN(150, "ADR_COMPLETE"),
0465 PINCTRL_PIN(151, "NMIB"),
0466 PINCTRL_PIN(152, "SMIB"),
0467 PINCTRL_PIN(153, "GPP_G_20"),
0468 PINCTRL_PIN(154, "GPP_G_21"),
0469 PINCTRL_PIN(155, "GPP_G_22"),
0470 PINCTRL_PIN(156, "GPP_G_23"),
0471
0472 PINCTRL_PIN(157, "SRCCLKREQB_6"),
0473 PINCTRL_PIN(158, "SRCCLKREQB_7"),
0474 PINCTRL_PIN(159, "SRCCLKREQB_8"),
0475 PINCTRL_PIN(160, "SRCCLKREQB_9"),
0476 PINCTRL_PIN(161, "SRCCLKREQB_10"),
0477 PINCTRL_PIN(162, "SRCCLKREQB_11"),
0478 PINCTRL_PIN(163, "SRCCLKREQB_12"),
0479 PINCTRL_PIN(164, "SRCCLKREQB_13"),
0480 PINCTRL_PIN(165, "SRCCLKREQB_14"),
0481 PINCTRL_PIN(166, "SRCCLKREQB_15"),
0482 PINCTRL_PIN(167, "SML2CLK"),
0483 PINCTRL_PIN(168, "SML2DATA"),
0484 PINCTRL_PIN(169, "SML2ALERTB"),
0485 PINCTRL_PIN(170, "SML3CLK"),
0486 PINCTRL_PIN(171, "SML3DATA"),
0487 PINCTRL_PIN(172, "SML3ALERTB"),
0488 PINCTRL_PIN(173, "SML4CLK"),
0489 PINCTRL_PIN(174, "SML4DATA"),
0490 PINCTRL_PIN(175, "SML4ALERTB"),
0491 PINCTRL_PIN(176, "ISH_I2C0_SDA"),
0492 PINCTRL_PIN(177, "ISH_I2C0_SCL"),
0493 PINCTRL_PIN(178, "ISH_I2C1_SDA"),
0494 PINCTRL_PIN(179, "ISH_I2C1_SCL"),
0495 PINCTRL_PIN(180, "GPP_H_23"),
0496
0497 PINCTRL_PIN(181, "DDSP_HDP_0"),
0498 PINCTRL_PIN(182, "DDSP_HDP_1"),
0499 PINCTRL_PIN(183, "DDSP_HDP_2"),
0500 PINCTRL_PIN(184, "DDSP_HDP_3"),
0501 PINCTRL_PIN(185, "EDP_HPD"),
0502 PINCTRL_PIN(186, "DDPB_CTRLCLK"),
0503 PINCTRL_PIN(187, "DDPB_CTRLDATA"),
0504 PINCTRL_PIN(188, "DDPC_CTRLCLK"),
0505 PINCTRL_PIN(189, "DDPC_CTRLDATA"),
0506 PINCTRL_PIN(190, "DDPD_CTRLCLK"),
0507 PINCTRL_PIN(191, "DDPD_CTRLDATA"),
0508 };
0509
0510 static const unsigned spth_spi0_pins[] = { 39, 40, 41, 42 };
0511 static const unsigned spth_spi1_pins[] = { 43, 44, 45, 46 };
0512 static const unsigned spth_uart0_pins[] = { 56, 57, 58, 59 };
0513 static const unsigned spth_uart1_pins[] = { 60, 61, 62, 63 };
0514 static const unsigned spth_uart2_pins[] = { 68, 69, 71, 71 };
0515 static const unsigned spth_i2c0_pins[] = { 64, 65 };
0516 static const unsigned spth_i2c1_pins[] = { 66, 67 };
0517 static const unsigned spth_i2c2_pins[] = { 76, 95 };
0518
0519 static const struct intel_pingroup spth_groups[] = {
0520 PIN_GROUP("spi0_grp", spth_spi0_pins, 1),
0521 PIN_GROUP("spi1_grp", spth_spi1_pins, 1),
0522 PIN_GROUP("uart0_grp", spth_uart0_pins, 1),
0523 PIN_GROUP("uart1_grp", spth_uart1_pins, 1),
0524 PIN_GROUP("uart2_grp", spth_uart2_pins, 1),
0525 PIN_GROUP("i2c0_grp", spth_i2c0_pins, 1),
0526 PIN_GROUP("i2c1_grp", spth_i2c1_pins, 1),
0527 PIN_GROUP("i2c2_grp", spth_i2c2_pins, 2),
0528 };
0529
0530 static const char * const spth_spi0_groups[] = { "spi0_grp" };
0531 static const char * const spth_spi1_groups[] = { "spi0_grp" };
0532 static const char * const spth_uart0_groups[] = { "uart0_grp" };
0533 static const char * const spth_uart1_groups[] = { "uart1_grp" };
0534 static const char * const spth_uart2_groups[] = { "uart2_grp" };
0535 static const char * const spth_i2c0_groups[] = { "i2c0_grp" };
0536 static const char * const spth_i2c1_groups[] = { "i2c1_grp" };
0537 static const char * const spth_i2c2_groups[] = { "i2c2_grp" };
0538
0539 static const struct intel_function spth_functions[] = {
0540 FUNCTION("spi0", spth_spi0_groups),
0541 FUNCTION("spi1", spth_spi1_groups),
0542 FUNCTION("uart0", spth_uart0_groups),
0543 FUNCTION("uart1", spth_uart1_groups),
0544 FUNCTION("uart2", spth_uart2_groups),
0545 FUNCTION("i2c0", spth_i2c0_groups),
0546 FUNCTION("i2c1", spth_i2c1_groups),
0547 FUNCTION("i2c2", spth_i2c2_groups),
0548 };
0549
0550 static const struct intel_padgroup spth_community0_gpps[] = {
0551 SPT_H_GPP(0, 0, 23, 0),
0552 SPT_H_GPP(1, 24, 47, 24),
0553 };
0554
0555 static const struct intel_padgroup spth_community1_gpps[] = {
0556 SPT_H_GPP(0, 48, 71, 48),
0557 SPT_H_GPP(1, 72, 95, 72),
0558 SPT_H_GPP(2, 96, 108, 96),
0559 SPT_H_GPP(3, 109, 132, 120),
0560 SPT_H_GPP(4, 133, 156, 144),
0561 SPT_H_GPP(5, 157, 180, 168),
0562 };
0563
0564 static const struct intel_padgroup spth_community3_gpps[] = {
0565 SPT_H_GPP(0, 181, 191, 192),
0566 };
0567
0568 static const struct intel_community spth_communities[] = {
0569 SPT_H_COMMUNITY(0, 0, 47, spth_community0_gpps),
0570 SPT_H_COMMUNITY(1, 48, 180, spth_community1_gpps),
0571 SPT_H_COMMUNITY(2, 181, 191, spth_community3_gpps),
0572 };
0573
0574 static const struct intel_pinctrl_soc_data spth_soc_data = {
0575 .pins = spth_pins,
0576 .npins = ARRAY_SIZE(spth_pins),
0577 .groups = spth_groups,
0578 .ngroups = ARRAY_SIZE(spth_groups),
0579 .functions = spth_functions,
0580 .nfunctions = ARRAY_SIZE(spth_functions),
0581 .communities = spth_communities,
0582 .ncommunities = ARRAY_SIZE(spth_communities),
0583 };
0584
0585 static const struct acpi_device_id spt_pinctrl_acpi_match[] = {
0586 { "INT344B", (kernel_ulong_t)&sptlp_soc_data },
0587 { "INT3451", (kernel_ulong_t)&spth_soc_data },
0588 { "INT345D", (kernel_ulong_t)&spth_soc_data },
0589 { }
0590 };
0591 MODULE_DEVICE_TABLE(acpi, spt_pinctrl_acpi_match);
0592
0593 static INTEL_PINCTRL_PM_OPS(spt_pinctrl_pm_ops);
0594
0595 static struct platform_driver spt_pinctrl_driver = {
0596 .probe = intel_pinctrl_probe_by_hid,
0597 .driver = {
0598 .name = "sunrisepoint-pinctrl",
0599 .acpi_match_table = spt_pinctrl_acpi_match,
0600 .pm = &spt_pinctrl_pm_ops,
0601 },
0602 };
0603
0604 static int __init spt_pinctrl_init(void)
0605 {
0606 return platform_driver_register(&spt_pinctrl_driver);
0607 }
0608 subsys_initcall(spt_pinctrl_init);
0609
0610 static void __exit spt_pinctrl_exit(void)
0611 {
0612 platform_driver_unregister(&spt_pinctrl_driver);
0613 }
0614 module_exit(spt_pinctrl_exit);
0615
0616 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
0617 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
0618 MODULE_DESCRIPTION("Intel Sunrisepoint PCH pinctrl/GPIO driver");
0619 MODULE_LICENSE("GPL v2");
