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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Intel Merrifield SoC pinctrl driver
0004  *
0005  * Copyright (C) 2016, Intel Corporation
0006  * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
0007  */
0008 
0009 #include <linux/bits.h>
0010 #include <linux/err.h>
0011 #include <linux/io.h>
0012 #include <linux/module.h>
0013 #include <linux/mod_devicetable.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/pinctrl/pinconf.h>
0016 #include <linux/pinctrl/pinconf-generic.h>
0017 #include <linux/pinctrl/pinctrl.h>
0018 #include <linux/pinctrl/pinmux.h>
0019 
0020 #include "pinctrl-intel.h"
0021 
0022 #define MRFLD_FAMILY_NR         64
0023 #define MRFLD_FAMILY_LEN        0x400
0024 
0025 #define SLEW_OFFSET         0x000
0026 #define BUFCFG_OFFSET           0x100
0027 #define MISC_OFFSET         0x300
0028 
0029 #define BUFCFG_PINMODE_SHIFT        0
0030 #define BUFCFG_PINMODE_MASK     GENMASK(2, 0)
0031 #define BUFCFG_PINMODE_GPIO     0
0032 #define BUFCFG_PUPD_VAL_SHIFT       4
0033 #define BUFCFG_PUPD_VAL_MASK        GENMASK(5, 4)
0034 #define BUFCFG_PUPD_VAL_2K      0
0035 #define BUFCFG_PUPD_VAL_20K     1
0036 #define BUFCFG_PUPD_VAL_50K     2
0037 #define BUFCFG_PUPD_VAL_910     3
0038 #define BUFCFG_PU_EN            BIT(8)
0039 #define BUFCFG_PD_EN            BIT(9)
0040 #define BUFCFG_Px_EN_MASK       GENMASK(9, 8)
0041 #define BUFCFG_SLEWSEL          BIT(10)
0042 #define BUFCFG_OVINEN           BIT(12)
0043 #define BUFCFG_OVINEN_EN        BIT(13)
0044 #define BUFCFG_OVINEN_MASK      GENMASK(13, 12)
0045 #define BUFCFG_OVOUTEN          BIT(14)
0046 #define BUFCFG_OVOUTEN_EN       BIT(15)
0047 #define BUFCFG_OVOUTEN_MASK     GENMASK(15, 14)
0048 #define BUFCFG_INDATAOV_VAL     BIT(16)
0049 #define BUFCFG_INDATAOV_EN      BIT(17)
0050 #define BUFCFG_INDATAOV_MASK        GENMASK(17, 16)
0051 #define BUFCFG_OUTDATAOV_VAL        BIT(18)
0052 #define BUFCFG_OUTDATAOV_EN     BIT(19)
0053 #define BUFCFG_OUTDATAOV_MASK       GENMASK(19, 18)
0054 #define BUFCFG_OD_EN            BIT(21)
0055 
0056 /**
0057  * struct mrfld_family - Intel pin family description
0058  * @barno: MMIO BAR number where registers for this family reside
0059  * @pin_base: Starting pin of pins in this family
0060  * @npins: Number of pins in this family
0061  * @protected: True if family is protected by access
0062  * @regs: family specific common registers
0063  */
0064 struct mrfld_family {
0065     unsigned int barno;
0066     unsigned int pin_base;
0067     size_t npins;
0068     bool protected;
0069     void __iomem *regs;
0070 };
0071 
0072 #define MRFLD_FAMILY(b, s, e)               \
0073     {                       \
0074         .barno = (b),               \
0075         .pin_base = (s),            \
0076         .npins = (e) - (s) + 1,         \
0077     }
0078 
0079 #define MRFLD_FAMILY_PROTECTED(b, s, e)         \
0080     {                       \
0081         .barno = (b),               \
0082         .pin_base = (s),            \
0083         .npins = (e) - (s) + 1,         \
0084         .protected = true,          \
0085     }
0086 
0087 static const struct pinctrl_pin_desc mrfld_pins[] = {
0088     /* Family 0: OCP2SSC (0 pins) */
0089     /* Family 1: ULPI (13 pins) */
0090     PINCTRL_PIN(0, "ULPI_CLK"),
0091     PINCTRL_PIN(1, "ULPI_D0"),
0092     PINCTRL_PIN(2, "ULPI_D1"),
0093     PINCTRL_PIN(3, "ULPI_D2"),
0094     PINCTRL_PIN(4, "ULPI_D3"),
0095     PINCTRL_PIN(5, "ULPI_D4"),
0096     PINCTRL_PIN(6, "ULPI_D5"),
0097     PINCTRL_PIN(7, "ULPI_D6"),
0098     PINCTRL_PIN(8, "ULPI_D7"),
0099     PINCTRL_PIN(9, "ULPI_DIR"),
0100     PINCTRL_PIN(10, "ULPI_NXT"),
0101     PINCTRL_PIN(11, "ULPI_REFCLK"),
0102     PINCTRL_PIN(12, "ULPI_STP"),
0103     /* Family 2: eMMC (24 pins) */
0104     PINCTRL_PIN(13, "EMMC_CLK"),
0105     PINCTRL_PIN(14, "EMMC_CMD"),
0106     PINCTRL_PIN(15, "EMMC_D0"),
0107     PINCTRL_PIN(16, "EMMC_D1"),
0108     PINCTRL_PIN(17, "EMMC_D2"),
0109     PINCTRL_PIN(18, "EMMC_D3"),
0110     PINCTRL_PIN(19, "EMMC_D4"),
0111     PINCTRL_PIN(20, "EMMC_D5"),
0112     PINCTRL_PIN(21, "EMMC_D6"),
0113     PINCTRL_PIN(22, "EMMC_D7"),
0114     PINCTRL_PIN(23, "EMMC_RST_N"),
0115     PINCTRL_PIN(24, "GP154"),
0116     PINCTRL_PIN(25, "GP155"),
0117     PINCTRL_PIN(26, "GP156"),
0118     PINCTRL_PIN(27, "GP157"),
0119     PINCTRL_PIN(28, "GP158"),
0120     PINCTRL_PIN(29, "GP159"),
0121     PINCTRL_PIN(30, "GP160"),
0122     PINCTRL_PIN(31, "GP161"),
0123     PINCTRL_PIN(32, "GP162"),
0124     PINCTRL_PIN(33, "GP163"),
0125     PINCTRL_PIN(34, "GP97"),
0126     PINCTRL_PIN(35, "GP14"),
0127     PINCTRL_PIN(36, "GP15"),
0128     /* Family 3: SDIO (20 pins) */
0129     PINCTRL_PIN(37, "GP77_SD_CD"),
0130     PINCTRL_PIN(38, "GP78_SD_CLK"),
0131     PINCTRL_PIN(39, "GP79_SD_CMD"),
0132     PINCTRL_PIN(40, "GP80_SD_D0"),
0133     PINCTRL_PIN(41, "GP81_SD_D1"),
0134     PINCTRL_PIN(42, "GP82_SD_D2"),
0135     PINCTRL_PIN(43, "GP83_SD_D3"),
0136     PINCTRL_PIN(44, "GP84_SD_LS_CLK_FB"),
0137     PINCTRL_PIN(45, "GP85_SD_LS_CMD_DIR"),
0138     PINCTRL_PIN(46, "GP86_SD_LS_D_DIR"),
0139     PINCTRL_PIN(47, "GP88_SD_LS_SEL"),
0140     PINCTRL_PIN(48, "GP87_SD_PD"),
0141     PINCTRL_PIN(49, "GP89_SD_WP"),
0142     PINCTRL_PIN(50, "GP90_SDIO_CLK"),
0143     PINCTRL_PIN(51, "GP91_SDIO_CMD"),
0144     PINCTRL_PIN(52, "GP92_SDIO_D0"),
0145     PINCTRL_PIN(53, "GP93_SDIO_D1"),
0146     PINCTRL_PIN(54, "GP94_SDIO_D2"),
0147     PINCTRL_PIN(55, "GP95_SDIO_D3"),
0148     PINCTRL_PIN(56, "GP96_SDIO_PD"),
0149     /* Family 4: HSI (8 pins) */
0150     PINCTRL_PIN(57, "HSI_ACDATA"),
0151     PINCTRL_PIN(58, "HSI_ACFLAG"),
0152     PINCTRL_PIN(59, "HSI_ACREADY"),
0153     PINCTRL_PIN(60, "HSI_ACWAKE"),
0154     PINCTRL_PIN(61, "HSI_CADATA"),
0155     PINCTRL_PIN(62, "HSI_CAFLAG"),
0156     PINCTRL_PIN(63, "HSI_CAREADY"),
0157     PINCTRL_PIN(64, "HSI_CAWAKE"),
0158     /* Family 5: SSP Audio (14 pins) */
0159     PINCTRL_PIN(65, "GP70"),
0160     PINCTRL_PIN(66, "GP71"),
0161     PINCTRL_PIN(67, "GP32_I2S_0_CLK"),
0162     PINCTRL_PIN(68, "GP33_I2S_0_FS"),
0163     PINCTRL_PIN(69, "GP34_I2S_0_RXD"),
0164     PINCTRL_PIN(70, "GP35_I2S_0_TXD"),
0165     PINCTRL_PIN(71, "GP36_I2S_1_CLK"),
0166     PINCTRL_PIN(72, "GP37_I2S_1_FS"),
0167     PINCTRL_PIN(73, "GP38_I2S_1_RXD"),
0168     PINCTRL_PIN(74, "GP39_I2S_1_TXD"),
0169     PINCTRL_PIN(75, "GP40_I2S_2_CLK"),
0170     PINCTRL_PIN(76, "GP41_I2S_2_FS"),
0171     PINCTRL_PIN(77, "GP42_I2S_2_RXD"),
0172     PINCTRL_PIN(78, "GP43_I2S_2_TXD"),
0173     /* Family 6: GP SSP (22 pins) */
0174     PINCTRL_PIN(79, "GP120_SPI_0_CLK"),
0175     PINCTRL_PIN(80, "GP121_SPI_0_SS"),
0176     PINCTRL_PIN(81, "GP122_SPI_0_RXD"),
0177     PINCTRL_PIN(82, "GP123_SPI_0_TXD"),
0178     PINCTRL_PIN(83, "GP102_SPI_1_CLK"),
0179     PINCTRL_PIN(84, "GP103_SPI_1_SS0"),
0180     PINCTRL_PIN(85, "GP104_SPI_1_SS1"),
0181     PINCTRL_PIN(86, "GP105_SPI_1_SS2"),
0182     PINCTRL_PIN(87, "GP106_SPI_1_SS3"),
0183     PINCTRL_PIN(88, "GP107_SPI_1_RXD"),
0184     PINCTRL_PIN(89, "GP108_SPI_1_TXD"),
0185     PINCTRL_PIN(90, "GP109_SPI_2_CLK"),
0186     PINCTRL_PIN(91, "GP110_SPI_2_SS0"),
0187     PINCTRL_PIN(92, "GP111_SPI_2_SS1"),
0188     PINCTRL_PIN(93, "GP112_SPI_2_SS2"),
0189     PINCTRL_PIN(94, "GP113_SPI_2_SS3"),
0190     PINCTRL_PIN(95, "GP114_SPI_2_RXD"),
0191     PINCTRL_PIN(96, "GP115_SPI_2_TXD"),
0192     PINCTRL_PIN(97, "GP116_SPI_3_CLK"),
0193     PINCTRL_PIN(98, "GP117_SPI_3_SS"),
0194     PINCTRL_PIN(99, "GP118_SPI_3_RXD"),
0195     PINCTRL_PIN(100, "GP119_SPI_3_TXD"),
0196     /* Family 7: I2C (14 pins) */
0197     PINCTRL_PIN(101, "GP19_I2C_1_SCL"),
0198     PINCTRL_PIN(102, "GP20_I2C_1_SDA"),
0199     PINCTRL_PIN(103, "GP21_I2C_2_SCL"),
0200     PINCTRL_PIN(104, "GP22_I2C_2_SDA"),
0201     PINCTRL_PIN(105, "GP17_I2C_3_SCL_HDMI"),
0202     PINCTRL_PIN(106, "GP18_I2C_3_SDA_HDMI"),
0203     PINCTRL_PIN(107, "GP23_I2C_4_SCL"),
0204     PINCTRL_PIN(108, "GP24_I2C_4_SDA"),
0205     PINCTRL_PIN(109, "GP25_I2C_5_SCL"),
0206     PINCTRL_PIN(110, "GP26_I2C_5_SDA"),
0207     PINCTRL_PIN(111, "GP27_I2C_6_SCL"),
0208     PINCTRL_PIN(112, "GP28_I2C_6_SDA"),
0209     PINCTRL_PIN(113, "GP29_I2C_7_SCL"),
0210     PINCTRL_PIN(114, "GP30_I2C_7_SDA"),
0211     /* Family 8: UART (12 pins) */
0212     PINCTRL_PIN(115, "GP124_UART_0_CTS"),
0213     PINCTRL_PIN(116, "GP125_UART_0_RTS"),
0214     PINCTRL_PIN(117, "GP126_UART_0_RX"),
0215     PINCTRL_PIN(118, "GP127_UART_0_TX"),
0216     PINCTRL_PIN(119, "GP128_UART_1_CTS"),
0217     PINCTRL_PIN(120, "GP129_UART_1_RTS"),
0218     PINCTRL_PIN(121, "GP130_UART_1_RX"),
0219     PINCTRL_PIN(122, "GP131_UART_1_TX"),
0220     PINCTRL_PIN(123, "GP132_UART_2_CTS"),
0221     PINCTRL_PIN(124, "GP133_UART_2_RTS"),
0222     PINCTRL_PIN(125, "GP134_UART_2_RX"),
0223     PINCTRL_PIN(126, "GP135_UART_2_TX"),
0224     /* Family 9: GPIO South (19 pins) */
0225     PINCTRL_PIN(127, "GP177"),
0226     PINCTRL_PIN(128, "GP178"),
0227     PINCTRL_PIN(129, "GP179"),
0228     PINCTRL_PIN(130, "GP180"),
0229     PINCTRL_PIN(131, "GP181"),
0230     PINCTRL_PIN(132, "GP182_PWM2"),
0231     PINCTRL_PIN(133, "GP183_PWM3"),
0232     PINCTRL_PIN(134, "GP184"),
0233     PINCTRL_PIN(135, "GP185"),
0234     PINCTRL_PIN(136, "GP186"),
0235     PINCTRL_PIN(137, "GP187"),
0236     PINCTRL_PIN(138, "GP188"),
0237     PINCTRL_PIN(139, "GP189"),
0238     PINCTRL_PIN(140, "GP64_FAST_INT0"),
0239     PINCTRL_PIN(141, "GP65_FAST_INT1"),
0240     PINCTRL_PIN(142, "GP66_FAST_INT2"),
0241     PINCTRL_PIN(143, "GP67_FAST_INT3"),
0242     PINCTRL_PIN(144, "GP12_PWM0"),
0243     PINCTRL_PIN(145, "GP13_PWM1"),
0244     /* Family 10: Camera Sideband (12 pins) */
0245     PINCTRL_PIN(146, "GP0"),
0246     PINCTRL_PIN(147, "GP1"),
0247     PINCTRL_PIN(148, "GP2"),
0248     PINCTRL_PIN(149, "GP3"),
0249     PINCTRL_PIN(150, "GP4"),
0250     PINCTRL_PIN(151, "GP5"),
0251     PINCTRL_PIN(152, "GP6"),
0252     PINCTRL_PIN(153, "GP7"),
0253     PINCTRL_PIN(154, "GP8"),
0254     PINCTRL_PIN(155, "GP9"),
0255     PINCTRL_PIN(156, "GP10"),
0256     PINCTRL_PIN(157, "GP11"),
0257     /* Family 11: Clock (22 pins) */
0258     PINCTRL_PIN(158, "GP137"),
0259     PINCTRL_PIN(159, "GP138"),
0260     PINCTRL_PIN(160, "GP139"),
0261     PINCTRL_PIN(161, "GP140"),
0262     PINCTRL_PIN(162, "GP141"),
0263     PINCTRL_PIN(163, "GP142"),
0264     PINCTRL_PIN(164, "GP16_HDMI_HPD"),
0265     PINCTRL_PIN(165, "GP68_DSI_A_TE"),
0266     PINCTRL_PIN(166, "GP69_DSI_C_TE"),
0267     PINCTRL_PIN(167, "OSC_CLK_CTRL0"),
0268     PINCTRL_PIN(168, "OSC_CLK_CTRL1"),
0269     PINCTRL_PIN(169, "OSC_CLK0"),
0270     PINCTRL_PIN(170, "OSC_CLK1"),
0271     PINCTRL_PIN(171, "OSC_CLK2"),
0272     PINCTRL_PIN(172, "OSC_CLK3"),
0273     PINCTRL_PIN(173, "OSC_CLK4"),
0274     PINCTRL_PIN(174, "RESETOUT"),
0275     PINCTRL_PIN(175, "PMODE"),
0276     PINCTRL_PIN(176, "PRDY"),
0277     PINCTRL_PIN(177, "PREQ"),
0278     PINCTRL_PIN(178, "GP190"),
0279     PINCTRL_PIN(179, "GP191"),
0280     /* Family 12: MSIC (15 pins) */
0281     PINCTRL_PIN(180, "I2C_0_SCL"),
0282     PINCTRL_PIN(181, "I2C_0_SDA"),
0283     PINCTRL_PIN(182, "IERR"),
0284     PINCTRL_PIN(183, "JTAG_TCK"),
0285     PINCTRL_PIN(184, "JTAG_TDI"),
0286     PINCTRL_PIN(185, "JTAG_TDO"),
0287     PINCTRL_PIN(186, "JTAG_TMS"),
0288     PINCTRL_PIN(187, "JTAG_TRST"),
0289     PINCTRL_PIN(188, "PROCHOT"),
0290     PINCTRL_PIN(189, "RTC_CLK"),
0291     PINCTRL_PIN(190, "SVID_ALERT"),
0292     PINCTRL_PIN(191, "SVID_CLK"),
0293     PINCTRL_PIN(192, "SVID_D"),
0294     PINCTRL_PIN(193, "THERMTRIP"),
0295     PINCTRL_PIN(194, "STANDBY"),
0296     /* Family 13: Keyboard (20 pins) */
0297     PINCTRL_PIN(195, "GP44"),
0298     PINCTRL_PIN(196, "GP45"),
0299     PINCTRL_PIN(197, "GP46"),
0300     PINCTRL_PIN(198, "GP47"),
0301     PINCTRL_PIN(199, "GP48"),
0302     PINCTRL_PIN(200, "GP49"),
0303     PINCTRL_PIN(201, "GP50"),
0304     PINCTRL_PIN(202, "GP51"),
0305     PINCTRL_PIN(203, "GP52"),
0306     PINCTRL_PIN(204, "GP53"),
0307     PINCTRL_PIN(205, "GP54"),
0308     PINCTRL_PIN(206, "GP55"),
0309     PINCTRL_PIN(207, "GP56"),
0310     PINCTRL_PIN(208, "GP57"),
0311     PINCTRL_PIN(209, "GP58"),
0312     PINCTRL_PIN(210, "GP59"),
0313     PINCTRL_PIN(211, "GP60"),
0314     PINCTRL_PIN(212, "GP61"),
0315     PINCTRL_PIN(213, "GP62"),
0316     PINCTRL_PIN(214, "GP63"),
0317     /* Family 14: GPIO North (13 pins) */
0318     PINCTRL_PIN(215, "GP164"),
0319     PINCTRL_PIN(216, "GP165"),
0320     PINCTRL_PIN(217, "GP166"),
0321     PINCTRL_PIN(218, "GP167"),
0322     PINCTRL_PIN(219, "GP168_MJTAG_TCK"),
0323     PINCTRL_PIN(220, "GP169_MJTAG_TDI"),
0324     PINCTRL_PIN(221, "GP170_MJTAG_TDO"),
0325     PINCTRL_PIN(222, "GP171_MJTAG_TMS"),
0326     PINCTRL_PIN(223, "GP172_MJTAG_TRST"),
0327     PINCTRL_PIN(224, "GP173"),
0328     PINCTRL_PIN(225, "GP174"),
0329     PINCTRL_PIN(226, "GP175"),
0330     PINCTRL_PIN(227, "GP176"),
0331     /* Family 15: PTI (5 pins) */
0332     PINCTRL_PIN(228, "GP72_PTI_CLK"),
0333     PINCTRL_PIN(229, "GP73_PTI_D0"),
0334     PINCTRL_PIN(230, "GP74_PTI_D1"),
0335     PINCTRL_PIN(231, "GP75_PTI_D2"),
0336     PINCTRL_PIN(232, "GP76_PTI_D3"),
0337     /* Family 16: USB3 (0 pins) */
0338     /* Family 17: HSIC (0 pins) */
0339     /* Family 18: Broadcast (0 pins) */
0340 };
0341 
0342 static const unsigned int mrfld_sdio_pins[] = { 50, 51, 52, 53, 54, 55, 56 };
0343 static const unsigned int mrfld_i2s2_pins[] = { 75, 76, 77, 78 };
0344 static const unsigned int mrfld_spi5_pins[] = { 90, 91, 92, 93, 94, 95, 96 };
0345 static const unsigned int mrfld_uart0_pins[] = { 115, 116, 117, 118 };
0346 static const unsigned int mrfld_uart1_pins[] = { 119, 120, 121, 122 };
0347 static const unsigned int mrfld_uart2_pins[] = { 123, 124, 125, 126 };
0348 static const unsigned int mrfld_pwm0_pins[] = { 144 };
0349 static const unsigned int mrfld_pwm1_pins[] = { 145 };
0350 static const unsigned int mrfld_pwm2_pins[] = { 132 };
0351 static const unsigned int mrfld_pwm3_pins[] = { 133 };
0352 
0353 static const struct intel_pingroup mrfld_groups[] = {
0354     PIN_GROUP("sdio_grp", mrfld_sdio_pins, 1),
0355     PIN_GROUP("i2s2_grp", mrfld_i2s2_pins, 1),
0356     PIN_GROUP("spi5_grp", mrfld_spi5_pins, 1),
0357     PIN_GROUP("uart0_grp", mrfld_uart0_pins, 1),
0358     PIN_GROUP("uart1_grp", mrfld_uart1_pins, 1),
0359     PIN_GROUP("uart2_grp", mrfld_uart2_pins, 1),
0360     PIN_GROUP("pwm0_grp", mrfld_pwm0_pins, 1),
0361     PIN_GROUP("pwm1_grp", mrfld_pwm1_pins, 1),
0362     PIN_GROUP("pwm2_grp", mrfld_pwm2_pins, 1),
0363     PIN_GROUP("pwm3_grp", mrfld_pwm3_pins, 1),
0364 };
0365 
0366 static const char * const mrfld_sdio_groups[] = { "sdio_grp" };
0367 static const char * const mrfld_i2s2_groups[] = { "i2s2_grp" };
0368 static const char * const mrfld_spi5_groups[] = { "spi5_grp" };
0369 static const char * const mrfld_uart0_groups[] = { "uart0_grp" };
0370 static const char * const mrfld_uart1_groups[] = { "uart1_grp" };
0371 static const char * const mrfld_uart2_groups[] = { "uart2_grp" };
0372 static const char * const mrfld_pwm0_groups[] = { "pwm0_grp" };
0373 static const char * const mrfld_pwm1_groups[] = { "pwm1_grp" };
0374 static const char * const mrfld_pwm2_groups[] = { "pwm2_grp" };
0375 static const char * const mrfld_pwm3_groups[] = { "pwm3_grp" };
0376 
0377 static const struct intel_function mrfld_functions[] = {
0378     FUNCTION("sdio", mrfld_sdio_groups),
0379     FUNCTION("i2s2", mrfld_i2s2_groups),
0380     FUNCTION("spi5", mrfld_spi5_groups),
0381     FUNCTION("uart0", mrfld_uart0_groups),
0382     FUNCTION("uart1", mrfld_uart1_groups),
0383     FUNCTION("uart2", mrfld_uart2_groups),
0384     FUNCTION("pwm0", mrfld_pwm0_groups),
0385     FUNCTION("pwm1", mrfld_pwm1_groups),
0386     FUNCTION("pwm2", mrfld_pwm2_groups),
0387     FUNCTION("pwm3", mrfld_pwm3_groups),
0388 };
0389 
0390 static const struct mrfld_family mrfld_families[] = {
0391     MRFLD_FAMILY(1, 0, 12),
0392     MRFLD_FAMILY(2, 13, 36),
0393     MRFLD_FAMILY(3, 37, 56),
0394     MRFLD_FAMILY(4, 57, 64),
0395     MRFLD_FAMILY(5, 65, 78),
0396     MRFLD_FAMILY(6, 79, 100),
0397     MRFLD_FAMILY_PROTECTED(7, 101, 114),
0398     MRFLD_FAMILY(8, 115, 126),
0399     MRFLD_FAMILY(9, 127, 145),
0400     MRFLD_FAMILY(10, 146, 157),
0401     MRFLD_FAMILY(11, 158, 179),
0402     MRFLD_FAMILY_PROTECTED(12, 180, 194),
0403     MRFLD_FAMILY(13, 195, 214),
0404     MRFLD_FAMILY(14, 215, 227),
0405     MRFLD_FAMILY(15, 228, 232),
0406 };
0407 
0408 /**
0409  * struct mrfld_pinctrl - Intel Merrifield pinctrl private structure
0410  * @dev: Pointer to the device structure
0411  * @lock: Lock to serialize register access
0412  * @pctldesc: Pin controller description
0413  * @pctldev: Pointer to the pin controller device
0414  * @families: Array of families this pinctrl handles
0415  * @nfamilies: Number of families in the array
0416  * @functions: Array of functions
0417  * @nfunctions: Number of functions in the array
0418  * @groups: Array of pin groups
0419  * @ngroups: Number of groups in the array
0420  * @pins: Array of pins this pinctrl controls
0421  * @npins: Number of pins in the array
0422  */
0423 struct mrfld_pinctrl {
0424     struct device *dev;
0425     raw_spinlock_t lock;
0426     struct pinctrl_desc pctldesc;
0427     struct pinctrl_dev *pctldev;
0428 
0429     /* Pin controller configuration */
0430     const struct mrfld_family *families;
0431     size_t nfamilies;
0432     const struct intel_function *functions;
0433     size_t nfunctions;
0434     const struct intel_pingroup *groups;
0435     size_t ngroups;
0436     const struct pinctrl_pin_desc *pins;
0437     size_t npins;
0438 };
0439 
0440 #define pin_to_bufno(f, p)      ((p) - (f)->pin_base)
0441 
0442 static const struct mrfld_family *mrfld_get_family(struct mrfld_pinctrl *mp,
0443                            unsigned int pin)
0444 {
0445     const struct mrfld_family *family;
0446     unsigned int i;
0447 
0448     for (i = 0; i < mp->nfamilies; i++) {
0449         family = &mp->families[i];
0450         if (pin >= family->pin_base &&
0451             pin < family->pin_base + family->npins)
0452             return family;
0453     }
0454 
0455     dev_warn(mp->dev, "failed to find family for pin %u\n", pin);
0456     return NULL;
0457 }
0458 
0459 static bool mrfld_buf_available(struct mrfld_pinctrl *mp, unsigned int pin)
0460 {
0461     const struct mrfld_family *family;
0462 
0463     family = mrfld_get_family(mp, pin);
0464     if (!family)
0465         return false;
0466 
0467     return !family->protected;
0468 }
0469 
0470 static void __iomem *mrfld_get_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin)
0471 {
0472     const struct mrfld_family *family;
0473     unsigned int bufno;
0474 
0475     family = mrfld_get_family(mp, pin);
0476     if (!family)
0477         return NULL;
0478 
0479     bufno = pin_to_bufno(family, pin);
0480     return family->regs + BUFCFG_OFFSET + bufno * 4;
0481 }
0482 
0483 static int mrfld_read_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin, u32 *value)
0484 {
0485     void __iomem *bufcfg;
0486 
0487     if (!mrfld_buf_available(mp, pin))
0488         return -EBUSY;
0489 
0490     bufcfg = mrfld_get_bufcfg(mp, pin);
0491     *value = readl(bufcfg);
0492 
0493     return 0;
0494 }
0495 
0496 static void mrfld_update_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin,
0497                 u32 bits, u32 mask)
0498 {
0499     void __iomem *bufcfg;
0500     u32 value;
0501 
0502     bufcfg = mrfld_get_bufcfg(mp, pin);
0503     value = readl(bufcfg);
0504 
0505     value &= ~mask;
0506     value |= bits & mask;
0507 
0508     writel(value, bufcfg);
0509 }
0510 
0511 static int mrfld_get_groups_count(struct pinctrl_dev *pctldev)
0512 {
0513     struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
0514 
0515     return mp->ngroups;
0516 }
0517 
0518 static const char *mrfld_get_group_name(struct pinctrl_dev *pctldev,
0519                     unsigned int group)
0520 {
0521     struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
0522 
0523     return mp->groups[group].grp.name;
0524 }
0525 
0526 static int mrfld_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
0527                 const unsigned int **pins, unsigned int *npins)
0528 {
0529     struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
0530 
0531     *pins = mp->groups[group].grp.pins;
0532     *npins = mp->groups[group].grp.npins;
0533     return 0;
0534 }
0535 
0536 static void mrfld_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
0537                    unsigned int pin)
0538 {
0539     struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
0540     u32 value, mode;
0541     int ret;
0542 
0543     ret = mrfld_read_bufcfg(mp, pin, &value);
0544     if (ret) {
0545         seq_puts(s, "not available");
0546         return;
0547     }
0548 
0549     mode = (value & BUFCFG_PINMODE_MASK) >> BUFCFG_PINMODE_SHIFT;
0550     if (!mode)
0551         seq_puts(s, "GPIO ");
0552     else
0553         seq_printf(s, "mode %d ", mode);
0554 
0555     seq_printf(s, "0x%08x", value);
0556 }
0557 
0558 static const struct pinctrl_ops mrfld_pinctrl_ops = {
0559     .get_groups_count = mrfld_get_groups_count,
0560     .get_group_name = mrfld_get_group_name,
0561     .get_group_pins = mrfld_get_group_pins,
0562     .pin_dbg_show = mrfld_pin_dbg_show,
0563 };
0564 
0565 static int mrfld_get_functions_count(struct pinctrl_dev *pctldev)
0566 {
0567     struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
0568 
0569     return mp->nfunctions;
0570 }
0571 
0572 static const char *mrfld_get_function_name(struct pinctrl_dev *pctldev,
0573                        unsigned int function)
0574 {
0575     struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
0576 
0577     return mp->functions[function].name;
0578 }
0579 
0580 static int mrfld_get_function_groups(struct pinctrl_dev *pctldev,
0581                      unsigned int function,
0582                      const char * const **groups,
0583                      unsigned int * const ngroups)
0584 {
0585     struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
0586 
0587     *groups = mp->functions[function].groups;
0588     *ngroups = mp->functions[function].ngroups;
0589     return 0;
0590 }
0591 
0592 static int mrfld_pinmux_set_mux(struct pinctrl_dev *pctldev,
0593                 unsigned int function,
0594                 unsigned int group)
0595 {
0596     struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
0597     const struct intel_pingroup *grp = &mp->groups[group];
0598     u32 bits = grp->mode << BUFCFG_PINMODE_SHIFT;
0599     u32 mask = BUFCFG_PINMODE_MASK;
0600     unsigned long flags;
0601     unsigned int i;
0602 
0603     /*
0604      * All pins in the groups needs to be accessible and writable
0605      * before we can enable the mux for this group.
0606      */
0607     for (i = 0; i < grp->grp.npins; i++) {
0608         if (!mrfld_buf_available(mp, grp->grp.pins[i]))
0609             return -EBUSY;
0610     }
0611 
0612     /* Now enable the mux setting for each pin in the group */
0613     raw_spin_lock_irqsave(&mp->lock, flags);
0614     for (i = 0; i < grp->grp.npins; i++)
0615         mrfld_update_bufcfg(mp, grp->grp.pins[i], bits, mask);
0616     raw_spin_unlock_irqrestore(&mp->lock, flags);
0617 
0618     return 0;
0619 }
0620 
0621 static int mrfld_gpio_request_enable(struct pinctrl_dev *pctldev,
0622                      struct pinctrl_gpio_range *range,
0623                      unsigned int pin)
0624 {
0625     struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
0626     u32 bits = BUFCFG_PINMODE_GPIO << BUFCFG_PINMODE_SHIFT;
0627     u32 mask = BUFCFG_PINMODE_MASK;
0628     unsigned long flags;
0629 
0630     if (!mrfld_buf_available(mp, pin))
0631         return -EBUSY;
0632 
0633     raw_spin_lock_irqsave(&mp->lock, flags);
0634     mrfld_update_bufcfg(mp, pin, bits, mask);
0635     raw_spin_unlock_irqrestore(&mp->lock, flags);
0636 
0637     return 0;
0638 }
0639 
0640 static const struct pinmux_ops mrfld_pinmux_ops = {
0641     .get_functions_count = mrfld_get_functions_count,
0642     .get_function_name = mrfld_get_function_name,
0643     .get_function_groups = mrfld_get_function_groups,
0644     .set_mux = mrfld_pinmux_set_mux,
0645     .gpio_request_enable = mrfld_gpio_request_enable,
0646 };
0647 
0648 static int mrfld_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
0649                 unsigned long *config)
0650 {
0651     struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
0652     enum pin_config_param param = pinconf_to_config_param(*config);
0653     u32 value, term;
0654     u16 arg = 0;
0655     int ret;
0656 
0657     ret = mrfld_read_bufcfg(mp, pin, &value);
0658     if (ret)
0659         return -ENOTSUPP;
0660 
0661     term = (value & BUFCFG_PUPD_VAL_MASK) >> BUFCFG_PUPD_VAL_SHIFT;
0662 
0663     switch (param) {
0664     case PIN_CONFIG_BIAS_DISABLE:
0665         if (value & BUFCFG_Px_EN_MASK)
0666             return -EINVAL;
0667         break;
0668 
0669     case PIN_CONFIG_BIAS_PULL_UP:
0670         if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PU_EN)
0671             return -EINVAL;
0672 
0673         switch (term) {
0674         case BUFCFG_PUPD_VAL_910:
0675             arg = 910;
0676             break;
0677         case BUFCFG_PUPD_VAL_2K:
0678             arg = 2000;
0679             break;
0680         case BUFCFG_PUPD_VAL_20K:
0681             arg = 20000;
0682             break;
0683         case BUFCFG_PUPD_VAL_50K:
0684             arg = 50000;
0685             break;
0686         }
0687 
0688         break;
0689 
0690     case PIN_CONFIG_BIAS_PULL_DOWN:
0691         if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PD_EN)
0692             return -EINVAL;
0693 
0694         switch (term) {
0695         case BUFCFG_PUPD_VAL_910:
0696             arg = 910;
0697             break;
0698         case BUFCFG_PUPD_VAL_2K:
0699             arg = 2000;
0700             break;
0701         case BUFCFG_PUPD_VAL_20K:
0702             arg = 20000;
0703             break;
0704         case BUFCFG_PUPD_VAL_50K:
0705             arg = 50000;
0706             break;
0707         }
0708 
0709         break;
0710 
0711     case PIN_CONFIG_DRIVE_OPEN_DRAIN:
0712         if (!(value & BUFCFG_OD_EN))
0713             return -EINVAL;
0714         break;
0715 
0716     case PIN_CONFIG_SLEW_RATE:
0717         if (!(value & BUFCFG_SLEWSEL))
0718             arg = 0;
0719         else
0720             arg = 1;
0721         break;
0722 
0723     default:
0724         return -ENOTSUPP;
0725     }
0726 
0727     *config = pinconf_to_config_packed(param, arg);
0728     return 0;
0729 }
0730 
0731 static int mrfld_config_set_pin(struct mrfld_pinctrl *mp, unsigned int pin,
0732                 unsigned long config)
0733 {
0734     unsigned int param = pinconf_to_config_param(config);
0735     unsigned int arg = pinconf_to_config_argument(config);
0736     u32 bits = 0, mask = 0;
0737     unsigned long flags;
0738 
0739     switch (param) {
0740     case PIN_CONFIG_BIAS_DISABLE:
0741         mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
0742         break;
0743 
0744     case PIN_CONFIG_BIAS_PULL_UP:
0745         mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
0746         bits |= BUFCFG_PU_EN;
0747 
0748         /* Set default strength value in case none is given */
0749         if (arg == 1)
0750             arg = 20000;
0751 
0752         switch (arg) {
0753         case 50000:
0754             bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT;
0755             break;
0756         case 20000:
0757             bits |= BUFCFG_PUPD_VAL_20K << BUFCFG_PUPD_VAL_SHIFT;
0758             break;
0759         case 2000:
0760             bits |= BUFCFG_PUPD_VAL_2K << BUFCFG_PUPD_VAL_SHIFT;
0761             break;
0762         default:
0763             return -EINVAL;
0764         }
0765 
0766         break;
0767 
0768     case PIN_CONFIG_BIAS_PULL_DOWN:
0769         mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
0770         bits |= BUFCFG_PD_EN;
0771 
0772         /* Set default strength value in case none is given */
0773         if (arg == 1)
0774             arg = 20000;
0775 
0776         switch (arg) {
0777         case 50000:
0778             bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT;
0779             break;
0780         case 20000:
0781             bits |= BUFCFG_PUPD_VAL_20K << BUFCFG_PUPD_VAL_SHIFT;
0782             break;
0783         case 2000:
0784             bits |= BUFCFG_PUPD_VAL_2K << BUFCFG_PUPD_VAL_SHIFT;
0785             break;
0786         default:
0787             return -EINVAL;
0788         }
0789 
0790         break;
0791 
0792     case PIN_CONFIG_DRIVE_OPEN_DRAIN:
0793         mask |= BUFCFG_OD_EN;
0794         if (arg)
0795             bits |= BUFCFG_OD_EN;
0796         break;
0797 
0798     case PIN_CONFIG_SLEW_RATE:
0799         mask |= BUFCFG_SLEWSEL;
0800         if (arg)
0801             bits |= BUFCFG_SLEWSEL;
0802         break;
0803     }
0804 
0805     raw_spin_lock_irqsave(&mp->lock, flags);
0806     mrfld_update_bufcfg(mp, pin, bits, mask);
0807     raw_spin_unlock_irqrestore(&mp->lock, flags);
0808 
0809     return 0;
0810 }
0811 
0812 static int mrfld_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
0813                 unsigned long *configs, unsigned int nconfigs)
0814 {
0815     struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
0816     unsigned int i;
0817     int ret;
0818 
0819     if (!mrfld_buf_available(mp, pin))
0820         return -ENOTSUPP;
0821 
0822     for (i = 0; i < nconfigs; i++) {
0823         switch (pinconf_to_config_param(configs[i])) {
0824         case PIN_CONFIG_BIAS_DISABLE:
0825         case PIN_CONFIG_BIAS_PULL_UP:
0826         case PIN_CONFIG_BIAS_PULL_DOWN:
0827         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
0828         case PIN_CONFIG_SLEW_RATE:
0829             ret = mrfld_config_set_pin(mp, pin, configs[i]);
0830             if (ret)
0831                 return ret;
0832             break;
0833 
0834         default:
0835             return -ENOTSUPP;
0836         }
0837     }
0838 
0839     return 0;
0840 }
0841 
0842 static int mrfld_config_group_get(struct pinctrl_dev *pctldev,
0843                   unsigned int group, unsigned long *config)
0844 {
0845     const unsigned int *pins;
0846     unsigned int npins;
0847     int ret;
0848 
0849     ret = mrfld_get_group_pins(pctldev, group, &pins, &npins);
0850     if (ret)
0851         return ret;
0852 
0853     ret = mrfld_config_get(pctldev, pins[0], config);
0854     if (ret)
0855         return ret;
0856 
0857     return 0;
0858 }
0859 
0860 static int mrfld_config_group_set(struct pinctrl_dev *pctldev,
0861                   unsigned int group, unsigned long *configs,
0862                   unsigned int num_configs)
0863 {
0864     const unsigned int *pins;
0865     unsigned int npins;
0866     int i, ret;
0867 
0868     ret = mrfld_get_group_pins(pctldev, group, &pins, &npins);
0869     if (ret)
0870         return ret;
0871 
0872     for (i = 0; i < npins; i++) {
0873         ret = mrfld_config_set(pctldev, pins[i], configs, num_configs);
0874         if (ret)
0875             return ret;
0876     }
0877 
0878     return 0;
0879 }
0880 
0881 static const struct pinconf_ops mrfld_pinconf_ops = {
0882     .is_generic = true,
0883     .pin_config_get = mrfld_config_get,
0884     .pin_config_set = mrfld_config_set,
0885     .pin_config_group_get = mrfld_config_group_get,
0886     .pin_config_group_set = mrfld_config_group_set,
0887 };
0888 
0889 static const struct pinctrl_desc mrfld_pinctrl_desc = {
0890     .pctlops = &mrfld_pinctrl_ops,
0891     .pmxops = &mrfld_pinmux_ops,
0892     .confops = &mrfld_pinconf_ops,
0893     .owner = THIS_MODULE,
0894 };
0895 
0896 static int mrfld_pinctrl_probe(struct platform_device *pdev)
0897 {
0898     struct mrfld_family *families;
0899     struct mrfld_pinctrl *mp;
0900     void __iomem *regs;
0901     size_t nfamilies;
0902     unsigned int i;
0903 
0904     mp = devm_kzalloc(&pdev->dev, sizeof(*mp), GFP_KERNEL);
0905     if (!mp)
0906         return -ENOMEM;
0907 
0908     mp->dev = &pdev->dev;
0909     raw_spin_lock_init(&mp->lock);
0910 
0911     regs = devm_platform_ioremap_resource(pdev, 0);
0912     if (IS_ERR(regs))
0913         return PTR_ERR(regs);
0914 
0915     /*
0916      * Make a copy of the families which we can use to hold pointers
0917      * to the registers.
0918      */
0919     nfamilies = ARRAY_SIZE(mrfld_families),
0920     families = devm_kmemdup(&pdev->dev, mrfld_families,
0921                         sizeof(mrfld_families),
0922                         GFP_KERNEL);
0923     if (!families)
0924         return -ENOMEM;
0925 
0926     /* Splice memory resource by chunk per family */
0927     for (i = 0; i < nfamilies; i++) {
0928         struct mrfld_family *family = &families[i];
0929 
0930         family->regs = regs + family->barno * MRFLD_FAMILY_LEN;
0931     }
0932 
0933     mp->families = families;
0934     mp->nfamilies = nfamilies;
0935     mp->functions = mrfld_functions;
0936     mp->nfunctions = ARRAY_SIZE(mrfld_functions);
0937     mp->groups = mrfld_groups;
0938     mp->ngroups = ARRAY_SIZE(mrfld_groups);
0939     mp->pctldesc = mrfld_pinctrl_desc;
0940     mp->pctldesc.name = dev_name(&pdev->dev);
0941     mp->pctldesc.pins = mrfld_pins;
0942     mp->pctldesc.npins = ARRAY_SIZE(mrfld_pins);
0943 
0944     mp->pctldev = devm_pinctrl_register(&pdev->dev, &mp->pctldesc, mp);
0945     if (IS_ERR(mp->pctldev)) {
0946         dev_err(&pdev->dev, "failed to register pinctrl driver\n");
0947         return PTR_ERR(mp->pctldev);
0948     }
0949 
0950     platform_set_drvdata(pdev, mp);
0951     return 0;
0952 }
0953 
0954 static const struct acpi_device_id mrfld_acpi_table[] = {
0955     { "INTC1002" },
0956     { }
0957 };
0958 MODULE_DEVICE_TABLE(acpi, mrfld_acpi_table);
0959 
0960 static struct platform_driver mrfld_pinctrl_driver = {
0961     .probe = mrfld_pinctrl_probe,
0962     .driver = {
0963         .name = "pinctrl-merrifield",
0964         .acpi_match_table = mrfld_acpi_table,
0965     },
0966 };
0967 
0968 static int __init mrfld_pinctrl_init(void)
0969 {
0970     return platform_driver_register(&mrfld_pinctrl_driver);
0971 }
0972 subsys_initcall(mrfld_pinctrl_init);
0973 
0974 static void __exit mrfld_pinctrl_exit(void)
0975 {
0976     platform_driver_unregister(&mrfld_pinctrl_driver);
0977 }
0978 module_exit(mrfld_pinctrl_exit);
0979 
0980 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
0981 MODULE_DESCRIPTION("Intel Merrifield SoC pinctrl driver");
0982 MODULE_LICENSE("GPL v2");
0983 MODULE_ALIAS("platform:pinctrl-merrifield");
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