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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Intel Lynxpoint PCH pinctrl/GPIO driver
0004  *
0005  * Copyright (c) 2012, 2019, Intel Corporation
0006  * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
0007  *          Andy Shevchenko <andriy.shevchenko@linux.intel.com>
0008  */
0009 
0010 #include <linux/acpi.h>
0011 #include <linux/bitops.h>
0012 #include <linux/gpio/driver.h>
0013 #include <linux/interrupt.h>
0014 #include <linux/io.h>
0015 #include <linux/kernel.h>
0016 #include <linux/module.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/pm_runtime.h>
0019 #include <linux/slab.h>
0020 #include <linux/types.h>
0021 
0022 #include <linux/pinctrl/pinctrl.h>
0023 #include <linux/pinctrl/pinmux.h>
0024 #include <linux/pinctrl/pinconf.h>
0025 #include <linux/pinctrl/pinconf-generic.h>
0026 
0027 #include "pinctrl-intel.h"
0028 
0029 #define COMMUNITY(p, n)         \
0030     {               \
0031         .pin_base   = (p),  \
0032         .npins      = (n),  \
0033     }
0034 
0035 static const struct pinctrl_pin_desc lptlp_pins[] = {
0036     PINCTRL_PIN(0, "GP0_UART1_RXD"),
0037     PINCTRL_PIN(1, "GP1_UART1_TXD"),
0038     PINCTRL_PIN(2, "GP2_UART1_RTSB"),
0039     PINCTRL_PIN(3, "GP3_UART1_CTSB"),
0040     PINCTRL_PIN(4, "GP4_I2C0_SDA"),
0041     PINCTRL_PIN(5, "GP5_I2C0_SCL"),
0042     PINCTRL_PIN(6, "GP6_I2C1_SDA"),
0043     PINCTRL_PIN(7, "GP7_I2C1_SCL"),
0044     PINCTRL_PIN(8, "GP8"),
0045     PINCTRL_PIN(9, "GP9"),
0046     PINCTRL_PIN(10, "GP10"),
0047     PINCTRL_PIN(11, "GP11_SMBALERTB"),
0048     PINCTRL_PIN(12, "GP12_LANPHYPC"),
0049     PINCTRL_PIN(13, "GP13"),
0050     PINCTRL_PIN(14, "GP14"),
0051     PINCTRL_PIN(15, "GP15"),
0052     PINCTRL_PIN(16, "GP16_MGPIO9"),
0053     PINCTRL_PIN(17, "GP17_MGPIO10"),
0054     PINCTRL_PIN(18, "GP18_SRC0CLKRQB"),
0055     PINCTRL_PIN(19, "GP19_SRC1CLKRQB"),
0056     PINCTRL_PIN(20, "GP20_SRC2CLKRQB"),
0057     PINCTRL_PIN(21, "GP21_SRC3CLKRQB"),
0058     PINCTRL_PIN(22, "GP22_SRC4CLKRQB_TRST2"),
0059     PINCTRL_PIN(23, "GP23_SRC5CLKRQB_TDI2"),
0060     PINCTRL_PIN(24, "GP24_MGPIO0"),
0061     PINCTRL_PIN(25, "GP25_USBWAKEOUTB"),
0062     PINCTRL_PIN(26, "GP26_MGPIO5"),
0063     PINCTRL_PIN(27, "GP27_MGPIO6"),
0064     PINCTRL_PIN(28, "GP28_MGPIO7"),
0065     PINCTRL_PIN(29, "GP29_SLP_WLANB_MGPIO3"),
0066     PINCTRL_PIN(30, "GP30_SUSWARNB_SUSPWRDNACK_MGPIO1"),
0067     PINCTRL_PIN(31, "GP31_ACPRESENT_MGPIO2"),
0068     PINCTRL_PIN(32, "GP32_CLKRUNB"),
0069     PINCTRL_PIN(33, "GP33_DEVSLP0"),
0070     PINCTRL_PIN(34, "GP34_SATA0XPCIE6L3B_SATA0GP"),
0071     PINCTRL_PIN(35, "GP35_SATA1XPCIE6L2B_SATA1GP"),
0072     PINCTRL_PIN(36, "GP36_SATA2XPCIE6L1B_SATA2GP"),
0073     PINCTRL_PIN(37, "GP37_SATA3XPCIE6L0B_SATA3GP"),
0074     PINCTRL_PIN(38, "GP38_DEVSLP1"),
0075     PINCTRL_PIN(39, "GP39_DEVSLP2"),
0076     PINCTRL_PIN(40, "GP40_OC0B"),
0077     PINCTRL_PIN(41, "GP41_OC1B"),
0078     PINCTRL_PIN(42, "GP42_OC2B"),
0079     PINCTRL_PIN(43, "GP43_OC3B"),
0080     PINCTRL_PIN(44, "GP44"),
0081     PINCTRL_PIN(45, "GP45_TMS2"),
0082     PINCTRL_PIN(46, "GP46_TDO2"),
0083     PINCTRL_PIN(47, "GP47"),
0084     PINCTRL_PIN(48, "GP48"),
0085     PINCTRL_PIN(49, "GP49"),
0086     PINCTRL_PIN(50, "GP50"),
0087     PINCTRL_PIN(51, "GP51_GSXDOUT"),
0088     PINCTRL_PIN(52, "GP52_GSXSLOAD"),
0089     PINCTRL_PIN(53, "GP53_GSXDIN"),
0090     PINCTRL_PIN(54, "GP54_GSXSRESETB"),
0091     PINCTRL_PIN(55, "GP55_GSXCLK"),
0092     PINCTRL_PIN(56, "GP56"),
0093     PINCTRL_PIN(57, "GP57"),
0094     PINCTRL_PIN(58, "GP58"),
0095     PINCTRL_PIN(59, "GP59"),
0096     PINCTRL_PIN(60, "GP60_SML0ALERTB_MGPIO4"),
0097     PINCTRL_PIN(61, "GP61_SUS_STATB"),
0098     PINCTRL_PIN(62, "GP62_SUSCLK"),
0099     PINCTRL_PIN(63, "GP63_SLP_S5B"),
0100     PINCTRL_PIN(64, "GP64_SDIO_CLK"),
0101     PINCTRL_PIN(65, "GP65_SDIO_CMD"),
0102     PINCTRL_PIN(66, "GP66_SDIO_D0"),
0103     PINCTRL_PIN(67, "GP67_SDIO_D1"),
0104     PINCTRL_PIN(68, "GP68_SDIO_D2"),
0105     PINCTRL_PIN(69, "GP69_SDIO_D3"),
0106     PINCTRL_PIN(70, "GP70_SDIO_POWER_EN"),
0107     PINCTRL_PIN(71, "GP71_MPHYPC"),
0108     PINCTRL_PIN(72, "GP72_BATLOWB"),
0109     PINCTRL_PIN(73, "GP73_SML1ALERTB_PCHHOTB_MGPIO8"),
0110     PINCTRL_PIN(74, "GP74_SML1DATA_MGPIO12"),
0111     PINCTRL_PIN(75, "GP75_SML1CLK_MGPIO11"),
0112     PINCTRL_PIN(76, "GP76_BMBUSYB"),
0113     PINCTRL_PIN(77, "GP77_PIRQAB"),
0114     PINCTRL_PIN(78, "GP78_PIRQBB"),
0115     PINCTRL_PIN(79, "GP79_PIRQCB"),
0116     PINCTRL_PIN(80, "GP80_PIRQDB"),
0117     PINCTRL_PIN(81, "GP81_SPKR"),
0118     PINCTRL_PIN(82, "GP82_RCINB"),
0119     PINCTRL_PIN(83, "GP83_GSPI0_CSB"),
0120     PINCTRL_PIN(84, "GP84_GSPI0_CLK"),
0121     PINCTRL_PIN(85, "GP85_GSPI0_MISO"),
0122     PINCTRL_PIN(86, "GP86_GSPI0_MOSI"),
0123     PINCTRL_PIN(87, "GP87_GSPI1_CSB"),
0124     PINCTRL_PIN(88, "GP88_GSPI1_CLK"),
0125     PINCTRL_PIN(89, "GP89_GSPI1_MISO"),
0126     PINCTRL_PIN(90, "GP90_GSPI1_MOSI"),
0127     PINCTRL_PIN(91, "GP91_UART0_RXD"),
0128     PINCTRL_PIN(92, "GP92_UART0_TXD"),
0129     PINCTRL_PIN(93, "GP93_UART0_RTSB"),
0130     PINCTRL_PIN(94, "GP94_UART0_CTSB"),
0131 };
0132 
0133 static const struct intel_community lptlp_communities[] = {
0134     COMMUNITY(0, 95),
0135 };
0136 
0137 static const struct intel_pinctrl_soc_data lptlp_soc_data = {
0138     .pins       = lptlp_pins,
0139     .npins      = ARRAY_SIZE(lptlp_pins),
0140     .communities    = lptlp_communities,
0141     .ncommunities   = ARRAY_SIZE(lptlp_communities),
0142 };
0143 
0144 /* LynxPoint chipset has support for 95 GPIO pins */
0145 
0146 #define LP_NUM_GPIO 95
0147 
0148 /* Bitmapped register offsets */
0149 #define LP_ACPI_OWNED   0x00 /* Bitmap, set by bios, 0: pin reserved for ACPI */
0150 #define LP_IRQ2IOXAPIC  0x10 /* Bitmap, set by bios, 1: pin routed to IOxAPIC */
0151 #define LP_GC       0x7C /* set APIC IRQ to IRQ14 or IRQ15 for all pins */
0152 #define LP_INT_STAT 0x80
0153 #define LP_INT_ENABLE   0x90
0154 
0155 /* Each pin has two 32 bit config registers, starting at 0x100 */
0156 #define LP_CONFIG1  0x100
0157 #define LP_CONFIG2  0x104
0158 
0159 /* LP_CONFIG1 reg bits */
0160 #define OUT_LVL_BIT BIT(31)
0161 #define IN_LVL_BIT  BIT(30)
0162 #define TRIG_SEL_BIT    BIT(4) /* 0: Edge, 1: Level */
0163 #define INT_INV_BIT BIT(3) /* Invert interrupt triggering */
0164 #define DIR_BIT     BIT(2) /* 0: Output, 1: Input */
0165 #define USE_SEL_MASK    GENMASK(1, 0)   /* 0: Native, 1: GPIO, ... */
0166 #define USE_SEL_NATIVE  (0 << 0)
0167 #define USE_SEL_GPIO    (1 << 0)
0168 
0169 /* LP_CONFIG2 reg bits */
0170 #define GPINDIS_BIT BIT(2) /* disable input sensing */
0171 #define GPIWP_MASK  GENMASK(1, 0)   /* weak pull options */
0172 #define GPIWP_NONE  0       /* none */
0173 #define GPIWP_DOWN  1       /* weak pull down */
0174 #define GPIWP_UP    2       /* weak pull up */
0175 
0176 /*
0177  * Lynxpoint gpios are controlled through both bitmapped registers and
0178  * per gpio specific registers. The bitmapped registers are in chunks of
0179  * 3 x 32bit registers to cover all 95 GPIOs
0180  *
0181  * per gpio specific registers consist of two 32bit registers per gpio
0182  * (LP_CONFIG1 and LP_CONFIG2), with 95 GPIOs there's a total of
0183  * 190 config registers.
0184  *
0185  * A simplified view of the register layout look like this:
0186  *
0187  * LP_ACPI_OWNED[31:0] gpio ownerships for gpios 0-31  (bitmapped registers)
0188  * LP_ACPI_OWNED[63:32] gpio ownerships for gpios 32-63
0189  * LP_ACPI_OWNED[94:64] gpio ownerships for gpios 63-94
0190  * ...
0191  * LP_INT_ENABLE[31:0] ...
0192  * LP_INT_ENABLE[63:32] ...
0193  * LP_INT_ENABLE[94:64] ...
0194  * LP0_CONFIG1 (gpio 0) config1 reg for gpio 0 (per gpio registers)
0195  * LP0_CONFIG2 (gpio 0) config2 reg for gpio 0
0196  * LP1_CONFIG1 (gpio 1) config1 reg for gpio 1
0197  * LP1_CONFIG2 (gpio 1) config2 reg for gpio 1
0198  * LP2_CONFIG1 (gpio 2) ...
0199  * LP2_CONFIG2 (gpio 2) ...
0200  * ...
0201  * LP94_CONFIG1 (gpio 94) ...
0202  * LP94_CONFIG2 (gpio 94) ...
0203  *
0204  * IOxAPIC redirection map applies only for gpio 8-10, 13-14, 45-55.
0205  */
0206 
0207 static struct intel_community *lp_get_community(struct intel_pinctrl *lg,
0208                         unsigned int pin)
0209 {
0210     struct intel_community *comm;
0211     int i;
0212 
0213     for (i = 0; i < lg->ncommunities; i++) {
0214         comm = &lg->communities[i];
0215         if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base)
0216             return comm;
0217     }
0218 
0219     return NULL;
0220 }
0221 
0222 static void __iomem *lp_gpio_reg(struct gpio_chip *chip, unsigned int offset,
0223                  int reg)
0224 {
0225     struct intel_pinctrl *lg = gpiochip_get_data(chip);
0226     struct intel_community *comm;
0227     int reg_offset;
0228 
0229     comm = lp_get_community(lg, offset);
0230     if (!comm)
0231         return NULL;
0232 
0233     offset -= comm->pin_base;
0234 
0235     if (reg == LP_CONFIG1 || reg == LP_CONFIG2)
0236         /* per gpio specific config registers */
0237         reg_offset = offset * 8;
0238     else
0239         /* bitmapped registers */
0240         reg_offset = (offset / 32) * 4;
0241 
0242     return comm->regs + reg_offset + reg;
0243 }
0244 
0245 static bool lp_gpio_acpi_use(struct intel_pinctrl *lg, unsigned int pin)
0246 {
0247     void __iomem *acpi_use;
0248 
0249     acpi_use = lp_gpio_reg(&lg->chip, pin, LP_ACPI_OWNED);
0250     if (!acpi_use)
0251         return true;
0252 
0253     return !(ioread32(acpi_use) & BIT(pin % 32));
0254 }
0255 
0256 static bool lp_gpio_ioxapic_use(struct gpio_chip *chip, unsigned int offset)
0257 {
0258     void __iomem *ioxapic_use = lp_gpio_reg(chip, offset, LP_IRQ2IOXAPIC);
0259     u32 value;
0260 
0261     value = ioread32(ioxapic_use);
0262 
0263     if (offset >= 8 && offset <= 10)
0264         return !!(value & BIT(offset -  8 + 0));
0265     if (offset >= 13 && offset <= 14)
0266         return !!(value & BIT(offset - 13 + 3));
0267     if (offset >= 45 && offset <= 55)
0268         return !!(value & BIT(offset - 45 + 5));
0269 
0270     return false;
0271 }
0272 
0273 static int lp_get_groups_count(struct pinctrl_dev *pctldev)
0274 {
0275     struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
0276 
0277     return lg->soc->ngroups;
0278 }
0279 
0280 static const char *lp_get_group_name(struct pinctrl_dev *pctldev,
0281                      unsigned int selector)
0282 {
0283     struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
0284 
0285     return lg->soc->groups[selector].grp.name;
0286 }
0287 
0288 static int lp_get_group_pins(struct pinctrl_dev *pctldev,
0289                  unsigned int selector,
0290                  const unsigned int **pins,
0291                  unsigned int *num_pins)
0292 {
0293     struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
0294 
0295     *pins       = lg->soc->groups[selector].grp.pins;
0296     *num_pins   = lg->soc->groups[selector].grp.npins;
0297 
0298     return 0;
0299 }
0300 
0301 static void lp_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
0302                 unsigned int pin)
0303 {
0304     struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
0305     void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1);
0306     void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
0307     u32 value, mode;
0308 
0309     value = ioread32(reg);
0310 
0311     mode = value & USE_SEL_MASK;
0312     if (mode == USE_SEL_GPIO)
0313         seq_puts(s, "GPIO ");
0314     else
0315         seq_printf(s, "mode %d ", mode);
0316 
0317     seq_printf(s, "0x%08x 0x%08x", value, ioread32(conf2));
0318 
0319     if (lp_gpio_acpi_use(lg, pin))
0320         seq_puts(s, " [ACPI]");
0321 }
0322 
0323 static const struct pinctrl_ops lptlp_pinctrl_ops = {
0324     .get_groups_count   = lp_get_groups_count,
0325     .get_group_name     = lp_get_group_name,
0326     .get_group_pins     = lp_get_group_pins,
0327     .pin_dbg_show       = lp_pin_dbg_show,
0328 };
0329 
0330 static int lp_get_functions_count(struct pinctrl_dev *pctldev)
0331 {
0332     struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
0333 
0334     return lg->soc->nfunctions;
0335 }
0336 
0337 static const char *lp_get_function_name(struct pinctrl_dev *pctldev,
0338                     unsigned int selector)
0339 {
0340     struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
0341 
0342     return lg->soc->functions[selector].name;
0343 }
0344 
0345 static int lp_get_function_groups(struct pinctrl_dev *pctldev,
0346                   unsigned int selector,
0347                   const char * const **groups,
0348                   unsigned int *num_groups)
0349 {
0350     struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
0351 
0352     *groups     = lg->soc->functions[selector].groups;
0353     *num_groups = lg->soc->functions[selector].ngroups;
0354 
0355     return 0;
0356 }
0357 
0358 static int lp_pinmux_set_mux(struct pinctrl_dev *pctldev,
0359                  unsigned int function, unsigned int group)
0360 {
0361     struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
0362     const struct intel_pingroup *grp = &lg->soc->groups[group];
0363     unsigned long flags;
0364     int i;
0365 
0366     raw_spin_lock_irqsave(&lg->lock, flags);
0367 
0368     /* Now enable the mux setting for each pin in the group */
0369     for (i = 0; i < grp->grp.npins; i++) {
0370         void __iomem *reg = lp_gpio_reg(&lg->chip, grp->grp.pins[i], LP_CONFIG1);
0371         u32 value;
0372 
0373         value = ioread32(reg);
0374 
0375         value &= ~USE_SEL_MASK;
0376         if (grp->modes)
0377             value |= grp->modes[i];
0378         else
0379             value |= grp->mode;
0380 
0381         iowrite32(value, reg);
0382     }
0383 
0384     raw_spin_unlock_irqrestore(&lg->lock, flags);
0385 
0386     return 0;
0387 }
0388 
0389 static void lp_gpio_enable_input(void __iomem *reg)
0390 {
0391     iowrite32(ioread32(reg) & ~GPINDIS_BIT, reg);
0392 }
0393 
0394 static void lp_gpio_disable_input(void __iomem *reg)
0395 {
0396     iowrite32(ioread32(reg) | GPINDIS_BIT, reg);
0397 }
0398 
0399 static int lp_gpio_request_enable(struct pinctrl_dev *pctldev,
0400                   struct pinctrl_gpio_range *range,
0401                   unsigned int pin)
0402 {
0403     struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
0404     void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1);
0405     void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
0406     unsigned long flags;
0407     u32 value;
0408 
0409     pm_runtime_get(lg->dev);
0410 
0411     raw_spin_lock_irqsave(&lg->lock, flags);
0412 
0413     /*
0414      * Reconfigure pin to GPIO mode if needed and issue a warning,
0415      * since we expect firmware to configure it properly.
0416      */
0417     value = ioread32(reg);
0418     if ((value & USE_SEL_MASK) != USE_SEL_GPIO) {
0419         iowrite32((value & USE_SEL_MASK) | USE_SEL_GPIO, reg);
0420         dev_warn(lg->dev, FW_BUG "pin %u forcibly reconfigured as GPIO\n", pin);
0421     }
0422 
0423     /* Enable input sensing */
0424     lp_gpio_enable_input(conf2);
0425 
0426     raw_spin_unlock_irqrestore(&lg->lock, flags);
0427 
0428     return 0;
0429 }
0430 
0431 static void lp_gpio_disable_free(struct pinctrl_dev *pctldev,
0432                  struct pinctrl_gpio_range *range,
0433                  unsigned int pin)
0434 {
0435     struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
0436     void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
0437     unsigned long flags;
0438 
0439     raw_spin_lock_irqsave(&lg->lock, flags);
0440 
0441     /* Disable input sensing */
0442     lp_gpio_disable_input(conf2);
0443 
0444     raw_spin_unlock_irqrestore(&lg->lock, flags);
0445 
0446     pm_runtime_put(lg->dev);
0447 }
0448 
0449 static int lp_gpio_set_direction(struct pinctrl_dev *pctldev,
0450                  struct pinctrl_gpio_range *range,
0451                  unsigned int pin, bool input)
0452 {
0453     struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
0454     void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1);
0455     unsigned long flags;
0456     u32 value;
0457 
0458     raw_spin_lock_irqsave(&lg->lock, flags);
0459 
0460     value = ioread32(reg);
0461     value &= ~DIR_BIT;
0462     if (input) {
0463         value |= DIR_BIT;
0464     } else {
0465         /*
0466          * Before making any direction modifications, do a check if GPIO
0467          * is set for direct IRQ. On Lynxpoint, setting GPIO to output
0468          * does not make sense, so let's at least warn the caller before
0469          * they shoot themselves in the foot.
0470          */
0471         WARN(lp_gpio_ioxapic_use(&lg->chip, pin),
0472              "Potential Error: Setting GPIO to output with IOxAPIC redirection");
0473     }
0474     iowrite32(value, reg);
0475 
0476     raw_spin_unlock_irqrestore(&lg->lock, flags);
0477 
0478     return 0;
0479 }
0480 
0481 static const struct pinmux_ops lptlp_pinmux_ops = {
0482     .get_functions_count    = lp_get_functions_count,
0483     .get_function_name  = lp_get_function_name,
0484     .get_function_groups    = lp_get_function_groups,
0485     .set_mux        = lp_pinmux_set_mux,
0486     .gpio_request_enable    = lp_gpio_request_enable,
0487     .gpio_disable_free  = lp_gpio_disable_free,
0488     .gpio_set_direction = lp_gpio_set_direction,
0489 };
0490 
0491 static int lp_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
0492                  unsigned long *config)
0493 {
0494     struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
0495     void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
0496     enum pin_config_param param = pinconf_to_config_param(*config);
0497     unsigned long flags;
0498     u32 value, pull;
0499     u16 arg;
0500 
0501     raw_spin_lock_irqsave(&lg->lock, flags);
0502     value = ioread32(conf2);
0503     raw_spin_unlock_irqrestore(&lg->lock, flags);
0504 
0505     pull = value & GPIWP_MASK;
0506 
0507     switch (param) {
0508     case PIN_CONFIG_BIAS_DISABLE:
0509         if (pull != GPIWP_NONE)
0510             return -EINVAL;
0511         arg = 0;
0512         break;
0513     case PIN_CONFIG_BIAS_PULL_DOWN:
0514         if (pull != GPIWP_DOWN)
0515             return -EINVAL;
0516 
0517         arg = 1;
0518         break;
0519     case PIN_CONFIG_BIAS_PULL_UP:
0520         if (pull != GPIWP_UP)
0521             return -EINVAL;
0522 
0523         arg = 1;
0524         break;
0525     default:
0526         return -ENOTSUPP;
0527     }
0528 
0529     *config = pinconf_to_config_packed(param, arg);
0530 
0531     return 0;
0532 }
0533 
0534 static int lp_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
0535                  unsigned long *configs, unsigned int num_configs)
0536 {
0537     struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
0538     void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
0539     enum pin_config_param param;
0540     unsigned long flags;
0541     int i, ret = 0;
0542     u32 value;
0543 
0544     raw_spin_lock_irqsave(&lg->lock, flags);
0545 
0546     value = ioread32(conf2);
0547 
0548     for (i = 0; i < num_configs; i++) {
0549         param = pinconf_to_config_param(configs[i]);
0550 
0551         switch (param) {
0552         case PIN_CONFIG_BIAS_DISABLE:
0553             value &= ~GPIWP_MASK;
0554             value |= GPIWP_NONE;
0555             break;
0556         case PIN_CONFIG_BIAS_PULL_DOWN:
0557             value &= ~GPIWP_MASK;
0558             value |= GPIWP_DOWN;
0559             break;
0560         case PIN_CONFIG_BIAS_PULL_UP:
0561             value &= ~GPIWP_MASK;
0562             value |= GPIWP_UP;
0563             break;
0564         default:
0565             ret = -ENOTSUPP;
0566         }
0567 
0568         if (ret)
0569             break;
0570     }
0571 
0572     if (!ret)
0573         iowrite32(value, conf2);
0574 
0575     raw_spin_unlock_irqrestore(&lg->lock, flags);
0576 
0577     return ret;
0578 }
0579 
0580 static const struct pinconf_ops lptlp_pinconf_ops = {
0581     .is_generic = true,
0582     .pin_config_get = lp_pin_config_get,
0583     .pin_config_set = lp_pin_config_set,
0584 };
0585 
0586 static const struct pinctrl_desc lptlp_pinctrl_desc = {
0587     .pctlops    = &lptlp_pinctrl_ops,
0588     .pmxops     = &lptlp_pinmux_ops,
0589     .confops    = &lptlp_pinconf_ops,
0590     .owner      = THIS_MODULE,
0591 };
0592 
0593 static int lp_gpio_get(struct gpio_chip *chip, unsigned int offset)
0594 {
0595     void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
0596     return !!(ioread32(reg) & IN_LVL_BIT);
0597 }
0598 
0599 static void lp_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
0600 {
0601     struct intel_pinctrl *lg = gpiochip_get_data(chip);
0602     void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
0603     unsigned long flags;
0604 
0605     raw_spin_lock_irqsave(&lg->lock, flags);
0606 
0607     if (value)
0608         iowrite32(ioread32(reg) | OUT_LVL_BIT, reg);
0609     else
0610         iowrite32(ioread32(reg) & ~OUT_LVL_BIT, reg);
0611 
0612     raw_spin_unlock_irqrestore(&lg->lock, flags);
0613 }
0614 
0615 static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
0616 {
0617     return pinctrl_gpio_direction_input(chip->base + offset);
0618 }
0619 
0620 static int lp_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
0621                     int value)
0622 {
0623     lp_gpio_set(chip, offset, value);
0624 
0625     return pinctrl_gpio_direction_output(chip->base + offset);
0626 }
0627 
0628 static int lp_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
0629 {
0630     void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
0631 
0632     if (ioread32(reg) & DIR_BIT)
0633         return GPIO_LINE_DIRECTION_IN;
0634 
0635     return GPIO_LINE_DIRECTION_OUT;
0636 }
0637 
0638 static void lp_gpio_irq_handler(struct irq_desc *desc)
0639 {
0640     struct irq_data *data = irq_desc_get_irq_data(desc);
0641     struct gpio_chip *gc = irq_desc_get_handler_data(desc);
0642     struct intel_pinctrl *lg = gpiochip_get_data(gc);
0643     struct irq_chip *chip = irq_data_get_irq_chip(data);
0644     void __iomem *reg, *ena;
0645     unsigned long pending;
0646     u32 base, pin;
0647 
0648     /* check from GPIO controller which pin triggered the interrupt */
0649     for (base = 0; base < lg->chip.ngpio; base += 32) {
0650         reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT);
0651         ena = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE);
0652 
0653         /* Only interrupts that are enabled */
0654         pending = ioread32(reg) & ioread32(ena);
0655 
0656         for_each_set_bit(pin, &pending, 32)
0657             generic_handle_domain_irq(lg->chip.irq.domain, base + pin);
0658     }
0659     chip->irq_eoi(data);
0660 }
0661 
0662 static void lp_irq_ack(struct irq_data *d)
0663 {
0664     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0665     struct intel_pinctrl *lg = gpiochip_get_data(gc);
0666     irq_hw_number_t hwirq = irqd_to_hwirq(d);
0667     void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_STAT);
0668     unsigned long flags;
0669 
0670     raw_spin_lock_irqsave(&lg->lock, flags);
0671     iowrite32(BIT(hwirq % 32), reg);
0672     raw_spin_unlock_irqrestore(&lg->lock, flags);
0673 }
0674 
0675 static void lp_irq_unmask(struct irq_data *d)
0676 {
0677 }
0678 
0679 static void lp_irq_mask(struct irq_data *d)
0680 {
0681 }
0682 
0683 static void lp_irq_enable(struct irq_data *d)
0684 {
0685     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0686     struct intel_pinctrl *lg = gpiochip_get_data(gc);
0687     irq_hw_number_t hwirq = irqd_to_hwirq(d);
0688     void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
0689     unsigned long flags;
0690 
0691     gpiochip_enable_irq(gc, hwirq);
0692 
0693     raw_spin_lock_irqsave(&lg->lock, flags);
0694     iowrite32(ioread32(reg) | BIT(hwirq % 32), reg);
0695     raw_spin_unlock_irqrestore(&lg->lock, flags);
0696 }
0697 
0698 static void lp_irq_disable(struct irq_data *d)
0699 {
0700     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0701     struct intel_pinctrl *lg = gpiochip_get_data(gc);
0702     irq_hw_number_t hwirq = irqd_to_hwirq(d);
0703     void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
0704     unsigned long flags;
0705 
0706     raw_spin_lock_irqsave(&lg->lock, flags);
0707     iowrite32(ioread32(reg) & ~BIT(hwirq % 32), reg);
0708     raw_spin_unlock_irqrestore(&lg->lock, flags);
0709 
0710     gpiochip_disable_irq(gc, hwirq);
0711 }
0712 
0713 static int lp_irq_set_type(struct irq_data *d, unsigned int type)
0714 {
0715     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0716     struct intel_pinctrl *lg = gpiochip_get_data(gc);
0717     irq_hw_number_t hwirq = irqd_to_hwirq(d);
0718     unsigned long flags;
0719     void __iomem *reg;
0720     u32 value;
0721 
0722     reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1);
0723     if (!reg)
0724         return -EINVAL;
0725 
0726     /* Fail if BIOS reserved pin for ACPI use */
0727     if (lp_gpio_acpi_use(lg, hwirq)) {
0728         dev_err(lg->dev, "pin %lu can't be used as IRQ\n", hwirq);
0729         return -EBUSY;
0730     }
0731 
0732     raw_spin_lock_irqsave(&lg->lock, flags);
0733     value = ioread32(reg);
0734 
0735     /* set both TRIG_SEL and INV bits to 0 for rising edge */
0736     if (type & IRQ_TYPE_EDGE_RISING)
0737         value &= ~(TRIG_SEL_BIT | INT_INV_BIT);
0738 
0739     /* TRIG_SEL bit 0, INV bit 1 for falling edge */
0740     if (type & IRQ_TYPE_EDGE_FALLING)
0741         value = (value | INT_INV_BIT) & ~TRIG_SEL_BIT;
0742 
0743     /* TRIG_SEL bit 1, INV bit 0 for level low */
0744     if (type & IRQ_TYPE_LEVEL_LOW)
0745         value = (value | TRIG_SEL_BIT) & ~INT_INV_BIT;
0746 
0747     /* TRIG_SEL bit 1, INV bit 1 for level high */
0748     if (type & IRQ_TYPE_LEVEL_HIGH)
0749         value |= TRIG_SEL_BIT | INT_INV_BIT;
0750 
0751     iowrite32(value, reg);
0752 
0753     if (type & IRQ_TYPE_EDGE_BOTH)
0754         irq_set_handler_locked(d, handle_edge_irq);
0755     else if (type & IRQ_TYPE_LEVEL_MASK)
0756         irq_set_handler_locked(d, handle_level_irq);
0757 
0758     raw_spin_unlock_irqrestore(&lg->lock, flags);
0759 
0760     return 0;
0761 }
0762 
0763 static const struct irq_chip lp_irqchip = {
0764     .name = "LP-GPIO",
0765     .irq_ack = lp_irq_ack,
0766     .irq_mask = lp_irq_mask,
0767     .irq_unmask = lp_irq_unmask,
0768     .irq_enable = lp_irq_enable,
0769     .irq_disable = lp_irq_disable,
0770     .irq_set_type = lp_irq_set_type,
0771     .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE,
0772     GPIOCHIP_IRQ_RESOURCE_HELPERS,
0773 };
0774 
0775 static int lp_gpio_irq_init_hw(struct gpio_chip *chip)
0776 {
0777     struct intel_pinctrl *lg = gpiochip_get_data(chip);
0778     void __iomem *reg;
0779     unsigned int base;
0780 
0781     for (base = 0; base < lg->chip.ngpio; base += 32) {
0782         /* disable gpio pin interrupts */
0783         reg = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE);
0784         iowrite32(0, reg);
0785         /* Clear interrupt status register */
0786         reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT);
0787         iowrite32(0xffffffff, reg);
0788     }
0789 
0790     return 0;
0791 }
0792 
0793 static int lp_gpio_add_pin_ranges(struct gpio_chip *chip)
0794 {
0795     struct intel_pinctrl *lg = gpiochip_get_data(chip);
0796     struct device *dev = lg->dev;
0797     int ret;
0798 
0799     ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, lg->soc->npins);
0800     if (ret)
0801         dev_err(dev, "failed to add GPIO pin range\n");
0802 
0803     return ret;
0804 }
0805 
0806 static int lp_gpio_probe(struct platform_device *pdev)
0807 {
0808     const struct intel_pinctrl_soc_data *soc;
0809     struct intel_pinctrl *lg;
0810     struct gpio_chip *gc;
0811     struct device *dev = &pdev->dev;
0812     struct resource *io_rc;
0813     void __iomem *regs;
0814     unsigned int i;
0815     int irq, ret;
0816 
0817     soc = (const struct intel_pinctrl_soc_data *)device_get_match_data(dev);
0818     if (!soc)
0819         return -ENODEV;
0820 
0821     lg = devm_kzalloc(dev, sizeof(*lg), GFP_KERNEL);
0822     if (!lg)
0823         return -ENOMEM;
0824 
0825     lg->dev = dev;
0826     lg->soc = soc;
0827 
0828     lg->ncommunities = lg->soc->ncommunities;
0829     lg->communities = devm_kcalloc(dev, lg->ncommunities,
0830                        sizeof(*lg->communities), GFP_KERNEL);
0831     if (!lg->communities)
0832         return -ENOMEM;
0833 
0834     lg->pctldesc           = lptlp_pinctrl_desc;
0835     lg->pctldesc.name      = dev_name(dev);
0836     lg->pctldesc.pins      = lg->soc->pins;
0837     lg->pctldesc.npins     = lg->soc->npins;
0838 
0839     lg->pctldev = devm_pinctrl_register(dev, &lg->pctldesc, lg);
0840     if (IS_ERR(lg->pctldev)) {
0841         dev_err(dev, "failed to register pinctrl driver\n");
0842         return PTR_ERR(lg->pctldev);
0843     }
0844 
0845     platform_set_drvdata(pdev, lg);
0846 
0847     io_rc = platform_get_resource(pdev, IORESOURCE_IO, 0);
0848     if (!io_rc) {
0849         dev_err(dev, "missing IO resources\n");
0850         return -EINVAL;
0851     }
0852 
0853     regs = devm_ioport_map(dev, io_rc->start, resource_size(io_rc));
0854     if (!regs) {
0855         dev_err(dev, "failed mapping IO region %pR\n", &io_rc);
0856         return -EBUSY;
0857     }
0858 
0859     for (i = 0; i < lg->soc->ncommunities; i++) {
0860         struct intel_community *comm = &lg->communities[i];
0861 
0862         *comm = lg->soc->communities[i];
0863 
0864         comm->regs = regs;
0865         comm->pad_regs = regs + 0x100;
0866     }
0867 
0868     raw_spin_lock_init(&lg->lock);
0869 
0870     gc = &lg->chip;
0871     gc->label = dev_name(dev);
0872     gc->owner = THIS_MODULE;
0873     gc->request = gpiochip_generic_request;
0874     gc->free = gpiochip_generic_free;
0875     gc->direction_input = lp_gpio_direction_input;
0876     gc->direction_output = lp_gpio_direction_output;
0877     gc->get = lp_gpio_get;
0878     gc->set = lp_gpio_set;
0879     gc->set_config = gpiochip_generic_config;
0880     gc->get_direction = lp_gpio_get_direction;
0881     gc->base = -1;
0882     gc->ngpio = LP_NUM_GPIO;
0883     gc->can_sleep = false;
0884     gc->add_pin_ranges = lp_gpio_add_pin_ranges;
0885     gc->parent = dev;
0886 
0887     /* set up interrupts  */
0888     irq = platform_get_irq_optional(pdev, 0);
0889     if (irq > 0) {
0890         struct gpio_irq_chip *girq;
0891 
0892         girq = &gc->irq;
0893         gpio_irq_chip_set_chip(girq, &lp_irqchip);
0894         girq->init_hw = lp_gpio_irq_init_hw;
0895         girq->parent_handler = lp_gpio_irq_handler;
0896         girq->num_parents = 1;
0897         girq->parents = devm_kcalloc(dev, girq->num_parents,
0898                          sizeof(*girq->parents),
0899                          GFP_KERNEL);
0900         if (!girq->parents)
0901             return -ENOMEM;
0902         girq->parents[0] = irq;
0903         girq->default_type = IRQ_TYPE_NONE;
0904         girq->handler = handle_bad_irq;
0905     }
0906 
0907     ret = devm_gpiochip_add_data(dev, gc, lg);
0908     if (ret) {
0909         dev_err(dev, "failed adding lp-gpio chip\n");
0910         return ret;
0911     }
0912 
0913     pm_runtime_enable(dev);
0914 
0915     return 0;
0916 }
0917 
0918 static int lp_gpio_remove(struct platform_device *pdev)
0919 {
0920     pm_runtime_disable(&pdev->dev);
0921     return 0;
0922 }
0923 
0924 static int lp_gpio_runtime_suspend(struct device *dev)
0925 {
0926     return 0;
0927 }
0928 
0929 static int lp_gpio_runtime_resume(struct device *dev)
0930 {
0931     return 0;
0932 }
0933 
0934 static int lp_gpio_resume(struct device *dev)
0935 {
0936     struct intel_pinctrl *lg = dev_get_drvdata(dev);
0937     struct gpio_chip *chip = &lg->chip;
0938     const char *dummy;
0939     int i;
0940 
0941     /* on some hardware suspend clears input sensing, re-enable it here */
0942     for_each_requested_gpio(chip, i, dummy)
0943         lp_gpio_enable_input(lp_gpio_reg(chip, i, LP_CONFIG2));
0944 
0945     return 0;
0946 }
0947 
0948 static const struct dev_pm_ops lp_gpio_pm_ops = {
0949     .runtime_suspend = lp_gpio_runtime_suspend,
0950     .runtime_resume = lp_gpio_runtime_resume,
0951     .resume = lp_gpio_resume,
0952 };
0953 
0954 static const struct acpi_device_id lynxpoint_gpio_acpi_match[] = {
0955     { "INT33C7", (kernel_ulong_t)&lptlp_soc_data },
0956     { "INT3437", (kernel_ulong_t)&lptlp_soc_data },
0957     { }
0958 };
0959 MODULE_DEVICE_TABLE(acpi, lynxpoint_gpio_acpi_match);
0960 
0961 static struct platform_driver lp_gpio_driver = {
0962     .probe          = lp_gpio_probe,
0963     .remove         = lp_gpio_remove,
0964     .driver         = {
0965         .name   = "lp_gpio",
0966         .pm = &lp_gpio_pm_ops,
0967         .acpi_match_table = lynxpoint_gpio_acpi_match,
0968     },
0969 };
0970 
0971 static int __init lp_gpio_init(void)
0972 {
0973     return platform_driver_register(&lp_gpio_driver);
0974 }
0975 subsys_initcall(lp_gpio_init);
0976 
0977 static void __exit lp_gpio_exit(void)
0978 {
0979     platform_driver_unregister(&lp_gpio_driver);
0980 }
0981 module_exit(lp_gpio_exit);
0982 
0983 MODULE_AUTHOR("Mathias Nyman (Intel)");
0984 MODULE_AUTHOR("Andy Shevchenko (Intel)");
0985 MODULE_DESCRIPTION("Intel Lynxpoint pinctrl driver");
0986 MODULE_LICENSE("GPL v2");
0987 MODULE_ALIAS("platform:lp_gpio");
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