pinctrl/intel/pinctrl-intel.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Core pinctrl/GPIO driver for Intel GPIO controllers
0004  *
0005  * Copyright (C) 2015, Intel Corporation
0006  * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
0007  *          Mika Westerberg <mika.westerberg@linux.intel.com>
0008  */
0009
0010 #ifndef PINCTRL_INTEL_H
0011 #define PINCTRL_INTEL_H
0012
0013 #include <linux/bits.h>
0014 #include <linux/compiler_types.h>
0015 #include <linux/gpio/driver.h>
0016 #include <linux/irq.h>
0017 #include <linux/kernel.h>
0018 #include <linux/pm.h>
0019 #include <linux/pinctrl/pinctrl.h>
0020 #include <linux/spinlock_types.h>
0021
0022 struct platform_device;
0023 struct device;
0024
0025 /**
0026  * struct intel_pingroup - Description about group of pins
0027  * @grp: Generic data of the pin group (name and pins)
0028  * @mode: Native mode in which the group is muxed out @pins. Used if @modes is %NULL.
0029  * @modes: If not %NULL this will hold mode for each pin in @pins
0030  */
0031 struct intel_pingroup {
0032     struct pingroup grp;
0033     unsigned short mode;
0034     const unsigned int *modes;
0035 };
0036
0037 /**
0038  * struct intel_function - Description about a function
0039  * @name: Name of the function
0040  * @groups: An array of groups for this function
0041  * @ngroups: Number of groups in @groups
0042  */
0043 struct intel_function {
0044     const char *name;
0045     const char * const *groups;
0046     size_t ngroups;
0047 };
0048
0049 /**
0050  * struct intel_padgroup - Hardware pad group information
0051  * @reg_num: GPI_IS register number
0052  * @base: Starting pin of this group
0053  * @size: Size of this group (maximum is 32).
0054  * @gpio_base: Starting GPIO base of this group
0055  * @padown_num: PAD_OWN register number (assigned by the core driver)
0056  *
0057  * If pad groups of a community are not the same size, use this structure
0058  * to specify them.
0059  */
0060 struct intel_padgroup {
0061     unsigned int reg_num;
0062     unsigned int base;
0063     unsigned int size;
0064     int gpio_base;
0065     unsigned int padown_num;
0066 };
0067
0068 /**
0069  * enum - Special treatment for GPIO base in pad group
0070  *
0071  * @INTEL_GPIO_BASE_ZERO:   force GPIO base to be 0
0072  * @INTEL_GPIO_BASE_NOMAP:  no GPIO mapping should be created
0073  * @INTEL_GPIO_BASE_MATCH:  matches with starting pin number
0074  */
0075 enum {
0076     INTEL_GPIO_BASE_ZERO    = -2,
0077     INTEL_GPIO_BASE_NOMAP   = -1,
0078     INTEL_GPIO_BASE_MATCH   = 0,
0079 };
0080
0081 /**
0082  * struct intel_community - Intel pin community description
0083  * @barno: MMIO BAR number where registers for this community reside
0084  * @padown_offset: Register offset of PAD_OWN register from @regs. If %0
0085  *                 then there is no support for owner.
0086  * @padcfglock_offset: Register offset of PADCFGLOCK from @regs. If %0 then
0087  *                     locking is not supported.
0088  * @hostown_offset: Register offset of HOSTSW_OWN from @regs. If %0 then it
0089  *                  is assumed that the host owns the pin (rather than
0090  *                  ACPI).
0091  * @is_offset: Register offset of GPI_IS from @regs.
0092  * @ie_offset: Register offset of GPI_IE from @regs.
0093  * @features: Additional features supported by the hardware
0094  * @pin_base: Starting pin of pins in this community
0095  * @npins: Number of pins in this community
0096  * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK,
0097  *            HOSTSW_OWN, GPI_IS, GPI_IE. Used when @gpps is %NULL.
0098  * @gpp_num_padown_regs: Number of pad registers each pad group consumes at
0099  *           minimum. Use %0 if the number of registers can be
0100  *           determined by the size of the group.
0101  * @gpps: Pad groups if the controller has variable size pad groups
0102  * @ngpps: Number of pad groups in this community
0103  * @pad_map: Optional non-linear mapping of the pads
0104  * @nirqs: Optional total number of IRQs this community can generate
0105  * @acpi_space_id: Optional address space ID for ACPI OpRegion handler
0106  * @regs: Community specific common registers (reserved for core driver)
0107  * @pad_regs: Community specific pad registers (reserved for core driver)
0108  *
0109  * In some of Intel GPIO host controllers this driver supports each pad group
0110  * is of equal size (except the last one). In that case the driver can just
0111  * fill in @gpp_size field and let the core driver to handle the rest. If
0112  * the controller has pad groups of variable size the client driver can
0113  * pass custom @gpps and @ngpps instead.
0114  */
0115 struct intel_community {
0116     unsigned int barno;
0117     unsigned int padown_offset;
0118     unsigned int padcfglock_offset;
0119     unsigned int hostown_offset;
0120     unsigned int is_offset;
0121     unsigned int ie_offset;
0122     unsigned int features;
0123     unsigned int pin_base;
0124     size_t npins;
0125     unsigned int gpp_size;
0126     unsigned int gpp_num_padown_regs;
0127     const struct intel_padgroup *gpps;
0128     size_t ngpps;
0129     const unsigned int *pad_map;
0130     unsigned short nirqs;
0131     unsigned short acpi_space_id;
0132
0133     /* Reserved for the core driver */
0134     void __iomem *regs;
0135     void __iomem *pad_regs;
0136 };
0137
0138 /* Additional features supported by the hardware */
0139 #define PINCTRL_FEATURE_DEBOUNCE    BIT(0)
0140 #define PINCTRL_FEATURE_1K_PD       BIT(1)
0141 #define PINCTRL_FEATURE_GPIO_HW_INFO    BIT(2)
0142 #define PINCTRL_FEATURE_PWM     BIT(3)
0143 #define PINCTRL_FEATURE_BLINK       BIT(4)
0144 #define PINCTRL_FEATURE_EXP     BIT(5)
0145
0146 /**
0147  * PIN_GROUP - Declare a pin group
0148  * @n: Name of the group
0149  * @p: An array of pins this group consists
0150  * @m: Mode which the pins are put when this group is active. Can be either
0151  *     a single integer or an array of integers in which case mode is per
0152  *     pin.
0153  */
0154 #define PIN_GROUP(n, p, m)                              \
0155     {                                       \
0156         .grp = PINCTRL_PINGROUP((n), (p), ARRAY_SIZE((p))),         \
0157         .mode = __builtin_choose_expr(__builtin_constant_p((m)), (m), 0),   \
0158         .modes = __builtin_choose_expr(__builtin_constant_p((m)), NULL, (m)),   \
0159     }
0160
0161 #define FUNCTION(n, g)              \
0162     {                   \
0163         .name = (n),            \
0164         .groups = (g),          \
0165         .ngroups = ARRAY_SIZE((g)), \
0166     }
0167
0168 /**
0169  * struct intel_pinctrl_soc_data - Intel pin controller per-SoC configuration
0170  * @uid: ACPI _UID for the probe driver use if needed
0171  * @pins: Array if pins this pinctrl controls
0172  * @npins: Number of pins in the array
0173  * @groups: Array of pin groups
0174  * @ngroups: Number of groups in the array
0175  * @functions: Array of functions
0176  * @nfunctions: Number of functions in the array
0177  * @communities: Array of communities this pinctrl handles
0178  * @ncommunities: Number of communities in the array
0179  *
0180  * The @communities is used as a template by the core driver. It will make
0181  * copy of all communities and fill in rest of the information.
0182  */
0183 struct intel_pinctrl_soc_data {
0184     const char *uid;
0185     const struct pinctrl_pin_desc *pins;
0186     size_t npins;
0187     const struct intel_pingroup *groups;
0188     size_t ngroups;
0189     const struct intel_function *functions;
0190     size_t nfunctions;
0191     const struct intel_community *communities;
0192     size_t ncommunities;
0193 };
0194
0195 const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev);
0196
0197 struct intel_pad_context;
0198 struct intel_community_context;
0199
0200 /**
0201  * struct intel_pinctrl_context - context to be saved during suspend-resume
0202  * @pads: Opaque context per pad (driver dependent)
0203  * @communities: Opaque context per community (driver dependent)
0204  */
0205 struct intel_pinctrl_context {
0206     struct intel_pad_context *pads;
0207     struct intel_community_context *communities;
0208 };
0209
0210 /**
0211  * struct intel_pinctrl - Intel pinctrl private structure
0212  * @dev: Pointer to the device structure
0213  * @lock: Lock to serialize register access
0214  * @pctldesc: Pin controller description
0215  * @pctldev: Pointer to the pin controller device
0216  * @chip: GPIO chip in this pin controller
0217  * @soc: SoC/PCH specific pin configuration data
0218  * @communities: All communities in this pin controller
0219  * @ncommunities: Number of communities in this pin controller
0220  * @context: Configuration saved over system sleep
0221  * @irq: pinctrl/GPIO chip irq number
0222  */
0223 struct intel_pinctrl {
0224     struct device *dev;
0225     raw_spinlock_t lock;
0226     struct pinctrl_desc pctldesc;
0227     struct pinctrl_dev *pctldev;
0228     struct gpio_chip chip;
0229     const struct intel_pinctrl_soc_data *soc;
0230     struct intel_community *communities;
0231     size_t ncommunities;
0232     struct intel_pinctrl_context context;
0233     int irq;
0234 };
0235
0236 int intel_pinctrl_probe_by_hid(struct platform_device *pdev);
0237 int intel_pinctrl_probe_by_uid(struct platform_device *pdev);
0238
0239 #ifdef CONFIG_PM_SLEEP
0240 int intel_pinctrl_suspend_noirq(struct device *dev);
0241 int intel_pinctrl_resume_noirq(struct device *dev);
0242 #endif
0243
0244 #define INTEL_PINCTRL_PM_OPS(_name)                 \
0245 const struct dev_pm_ops _name = {                   \
0246     SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend_noirq,  \
0247                       intel_pinctrl_resume_noirq)   \
0248 }
0249
0250 #endif /* PINCTRL_INTEL_H */