Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Intel pinctrl/GPIO core driver.
0004  *
0005  * Copyright (C) 2015, Intel Corporation
0006  * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
0007  *          Mika Westerberg <mika.westerberg@linux.intel.com>
0008  */
0009 
0010 #include <linux/acpi.h>
0011 #include <linux/gpio/driver.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/log2.h>
0014 #include <linux/module.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/property.h>
0017 #include <linux/time.h>
0018 
0019 #include <linux/pinctrl/pinctrl.h>
0020 #include <linux/pinctrl/pinmux.h>
0021 #include <linux/pinctrl/pinconf.h>
0022 #include <linux/pinctrl/pinconf-generic.h>
0023 
0024 #include "../core.h"
0025 #include "pinctrl-intel.h"
0026 
0027 /* Offset from regs */
0028 #define REVID               0x000
0029 #define REVID_SHIFT         16
0030 #define REVID_MASK          GENMASK(31, 16)
0031 
0032 #define CAPLIST             0x004
0033 #define CAPLIST_ID_SHIFT        16
0034 #define CAPLIST_ID_MASK         GENMASK(23, 16)
0035 #define CAPLIST_ID_GPIO_HW_INFO     1
0036 #define CAPLIST_ID_PWM          2
0037 #define CAPLIST_ID_BLINK        3
0038 #define CAPLIST_ID_EXP          4
0039 #define CAPLIST_NEXT_SHIFT      0
0040 #define CAPLIST_NEXT_MASK       GENMASK(15, 0)
0041 
0042 #define PADBAR              0x00c
0043 
0044 #define PADOWN_BITS         4
0045 #define PADOWN_SHIFT(p)         ((p) % 8 * PADOWN_BITS)
0046 #define PADOWN_MASK(p)          (GENMASK(3, 0) << PADOWN_SHIFT(p))
0047 #define PADOWN_GPP(p)           ((p) / 8)
0048 
0049 /* Offset from pad_regs */
0050 #define PADCFG0             0x000
0051 #define PADCFG0_RXEVCFG_SHIFT       25
0052 #define PADCFG0_RXEVCFG_MASK        GENMASK(26, 25)
0053 #define PADCFG0_RXEVCFG_LEVEL       0
0054 #define PADCFG0_RXEVCFG_EDGE        1
0055 #define PADCFG0_RXEVCFG_DISABLED    2
0056 #define PADCFG0_RXEVCFG_EDGE_BOTH   3
0057 #define PADCFG0_PREGFRXSEL      BIT(24)
0058 #define PADCFG0_RXINV           BIT(23)
0059 #define PADCFG0_GPIROUTIOXAPIC      BIT(20)
0060 #define PADCFG0_GPIROUTSCI      BIT(19)
0061 #define PADCFG0_GPIROUTSMI      BIT(18)
0062 #define PADCFG0_GPIROUTNMI      BIT(17)
0063 #define PADCFG0_PMODE_SHIFT     10
0064 #define PADCFG0_PMODE_MASK      GENMASK(13, 10)
0065 #define PADCFG0_PMODE_GPIO      0
0066 #define PADCFG0_GPIORXDIS       BIT(9)
0067 #define PADCFG0_GPIOTXDIS       BIT(8)
0068 #define PADCFG0_GPIORXSTATE     BIT(1)
0069 #define PADCFG0_GPIOTXSTATE     BIT(0)
0070 
0071 #define PADCFG1             0x004
0072 #define PADCFG1_TERM_UP         BIT(13)
0073 #define PADCFG1_TERM_SHIFT      10
0074 #define PADCFG1_TERM_MASK       GENMASK(12, 10)
0075 #define PADCFG1_TERM_20K        BIT(2)
0076 #define PADCFG1_TERM_5K         BIT(1)
0077 #define PADCFG1_TERM_1K         BIT(0)
0078 #define PADCFG1_TERM_833        (BIT(1) | BIT(0))
0079 
0080 #define PADCFG2             0x008
0081 #define PADCFG2_DEBEN           BIT(0)
0082 #define PADCFG2_DEBOUNCE_SHIFT      1
0083 #define PADCFG2_DEBOUNCE_MASK       GENMASK(4, 1)
0084 
0085 #define DEBOUNCE_PERIOD_NSEC        31250
0086 
0087 struct intel_pad_context {
0088     u32 padcfg0;
0089     u32 padcfg1;
0090     u32 padcfg2;
0091 };
0092 
0093 struct intel_community_context {
0094     u32 *intmask;
0095     u32 *hostown;
0096 };
0097 
0098 #define pin_to_padno(c, p)  ((p) - (c)->pin_base)
0099 #define padgroup_offset(g, p)   ((p) - (g)->base)
0100 
0101 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
0102                            unsigned int pin)
0103 {
0104     struct intel_community *community;
0105     int i;
0106 
0107     for (i = 0; i < pctrl->ncommunities; i++) {
0108         community = &pctrl->communities[i];
0109         if (pin >= community->pin_base &&
0110             pin < community->pin_base + community->npins)
0111             return community;
0112     }
0113 
0114     dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
0115     return NULL;
0116 }
0117 
0118 static const struct intel_padgroup *
0119 intel_community_get_padgroup(const struct intel_community *community,
0120                  unsigned int pin)
0121 {
0122     int i;
0123 
0124     for (i = 0; i < community->ngpps; i++) {
0125         const struct intel_padgroup *padgrp = &community->gpps[i];
0126 
0127         if (pin >= padgrp->base && pin < padgrp->base + padgrp->size)
0128             return padgrp;
0129     }
0130 
0131     return NULL;
0132 }
0133 
0134 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl,
0135                       unsigned int pin, unsigned int reg)
0136 {
0137     const struct intel_community *community;
0138     unsigned int padno;
0139     size_t nregs;
0140 
0141     community = intel_get_community(pctrl, pin);
0142     if (!community)
0143         return NULL;
0144 
0145     padno = pin_to_padno(community, pin);
0146     nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2;
0147 
0148     if (reg >= nregs * 4)
0149         return NULL;
0150 
0151     return community->pad_regs + reg + padno * nregs * 4;
0152 }
0153 
0154 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned int pin)
0155 {
0156     const struct intel_community *community;
0157     const struct intel_padgroup *padgrp;
0158     unsigned int gpp, offset, gpp_offset;
0159     void __iomem *padown;
0160 
0161     community = intel_get_community(pctrl, pin);
0162     if (!community)
0163         return false;
0164     if (!community->padown_offset)
0165         return true;
0166 
0167     padgrp = intel_community_get_padgroup(community, pin);
0168     if (!padgrp)
0169         return false;
0170 
0171     gpp_offset = padgroup_offset(padgrp, pin);
0172     gpp = PADOWN_GPP(gpp_offset);
0173     offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4;
0174     padown = community->regs + offset;
0175 
0176     return !(readl(padown) & PADOWN_MASK(gpp_offset));
0177 }
0178 
0179 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned int pin)
0180 {
0181     const struct intel_community *community;
0182     const struct intel_padgroup *padgrp;
0183     unsigned int offset, gpp_offset;
0184     void __iomem *hostown;
0185 
0186     community = intel_get_community(pctrl, pin);
0187     if (!community)
0188         return true;
0189     if (!community->hostown_offset)
0190         return false;
0191 
0192     padgrp = intel_community_get_padgroup(community, pin);
0193     if (!padgrp)
0194         return true;
0195 
0196     gpp_offset = padgroup_offset(padgrp, pin);
0197     offset = community->hostown_offset + padgrp->reg_num * 4;
0198     hostown = community->regs + offset;
0199 
0200     return !(readl(hostown) & BIT(gpp_offset));
0201 }
0202 
0203 /**
0204  * enum - Locking variants of the pad configuration
0205  *
0206  * @PAD_UNLOCKED:   pad is fully controlled by the configuration registers
0207  * @PAD_LOCKED:     pad configuration registers, except TX state, are locked
0208  * @PAD_LOCKED_TX:  pad configuration TX state is locked
0209  * @PAD_LOCKED_FULL:    pad configuration registers are locked completely
0210  *
0211  * Locking is considered as read-only mode for corresponding registers and
0212  * their respective fields. That said, TX state bit is locked separately from
0213  * the main locking scheme.
0214  */
0215 enum {
0216     PAD_UNLOCKED    = 0,
0217     PAD_LOCKED  = 1,
0218     PAD_LOCKED_TX   = 2,
0219     PAD_LOCKED_FULL = PAD_LOCKED | PAD_LOCKED_TX,
0220 };
0221 
0222 static int intel_pad_locked(struct intel_pinctrl *pctrl, unsigned int pin)
0223 {
0224     struct intel_community *community;
0225     const struct intel_padgroup *padgrp;
0226     unsigned int offset, gpp_offset;
0227     u32 value;
0228     int ret = PAD_UNLOCKED;
0229 
0230     community = intel_get_community(pctrl, pin);
0231     if (!community)
0232         return PAD_LOCKED_FULL;
0233     if (!community->padcfglock_offset)
0234         return PAD_UNLOCKED;
0235 
0236     padgrp = intel_community_get_padgroup(community, pin);
0237     if (!padgrp)
0238         return PAD_LOCKED_FULL;
0239 
0240     gpp_offset = padgroup_offset(padgrp, pin);
0241 
0242     /*
0243      * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
0244      * the pad is considered unlocked. Any other case means that it is
0245      * either fully or partially locked.
0246      */
0247     offset = community->padcfglock_offset + 0 + padgrp->reg_num * 8;
0248     value = readl(community->regs + offset);
0249     if (value & BIT(gpp_offset))
0250         ret |= PAD_LOCKED;
0251 
0252     offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8;
0253     value = readl(community->regs + offset);
0254     if (value & BIT(gpp_offset))
0255         ret |= PAD_LOCKED_TX;
0256 
0257     return ret;
0258 }
0259 
0260 static bool intel_pad_is_unlocked(struct intel_pinctrl *pctrl, unsigned int pin)
0261 {
0262     return (intel_pad_locked(pctrl, pin) & PAD_LOCKED) == PAD_UNLOCKED;
0263 }
0264 
0265 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned int pin)
0266 {
0267     return intel_pad_owned_by_host(pctrl, pin) && intel_pad_is_unlocked(pctrl, pin);
0268 }
0269 
0270 static int intel_get_groups_count(struct pinctrl_dev *pctldev)
0271 {
0272     struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0273 
0274     return pctrl->soc->ngroups;
0275 }
0276 
0277 static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
0278                       unsigned int group)
0279 {
0280     struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0281 
0282     return pctrl->soc->groups[group].grp.name;
0283 }
0284 
0285 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
0286                   const unsigned int **pins, unsigned int *npins)
0287 {
0288     struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0289 
0290     *pins = pctrl->soc->groups[group].grp.pins;
0291     *npins = pctrl->soc->groups[group].grp.npins;
0292     return 0;
0293 }
0294 
0295 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
0296                    unsigned int pin)
0297 {
0298     struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0299     void __iomem *padcfg;
0300     u32 cfg0, cfg1, mode;
0301     int locked;
0302     bool acpi;
0303 
0304     if (!intel_pad_owned_by_host(pctrl, pin)) {
0305         seq_puts(s, "not available");
0306         return;
0307     }
0308 
0309     cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
0310     cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
0311 
0312     mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
0313     if (mode == PADCFG0_PMODE_GPIO)
0314         seq_puts(s, "GPIO ");
0315     else
0316         seq_printf(s, "mode %d ", mode);
0317 
0318     seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
0319 
0320     /* Dump the additional PADCFG registers if available */
0321     padcfg = intel_get_padcfg(pctrl, pin, PADCFG2);
0322     if (padcfg)
0323         seq_printf(s, " 0x%08x", readl(padcfg));
0324 
0325     locked = intel_pad_locked(pctrl, pin);
0326     acpi = intel_pad_acpi_mode(pctrl, pin);
0327 
0328     if (locked || acpi) {
0329         seq_puts(s, " [");
0330         if (locked)
0331             seq_puts(s, "LOCKED");
0332         if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_TX)
0333             seq_puts(s, " tx");
0334         else if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_FULL)
0335             seq_puts(s, " full");
0336 
0337         if (locked && acpi)
0338             seq_puts(s, ", ");
0339 
0340         if (acpi)
0341             seq_puts(s, "ACPI");
0342         seq_puts(s, "]");
0343     }
0344 }
0345 
0346 static const struct pinctrl_ops intel_pinctrl_ops = {
0347     .get_groups_count = intel_get_groups_count,
0348     .get_group_name = intel_get_group_name,
0349     .get_group_pins = intel_get_group_pins,
0350     .pin_dbg_show = intel_pin_dbg_show,
0351 };
0352 
0353 static int intel_get_functions_count(struct pinctrl_dev *pctldev)
0354 {
0355     struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0356 
0357     return pctrl->soc->nfunctions;
0358 }
0359 
0360 static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
0361                        unsigned int function)
0362 {
0363     struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0364 
0365     return pctrl->soc->functions[function].name;
0366 }
0367 
0368 static int intel_get_function_groups(struct pinctrl_dev *pctldev,
0369                      unsigned int function,
0370                      const char * const **groups,
0371                      unsigned int * const ngroups)
0372 {
0373     struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0374 
0375     *groups = pctrl->soc->functions[function].groups;
0376     *ngroups = pctrl->soc->functions[function].ngroups;
0377     return 0;
0378 }
0379 
0380 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev,
0381                 unsigned int function, unsigned int group)
0382 {
0383     struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0384     const struct intel_pingroup *grp = &pctrl->soc->groups[group];
0385     unsigned long flags;
0386     int i;
0387 
0388     raw_spin_lock_irqsave(&pctrl->lock, flags);
0389 
0390     /*
0391      * All pins in the groups needs to be accessible and writable
0392      * before we can enable the mux for this group.
0393      */
0394     for (i = 0; i < grp->grp.npins; i++) {
0395         if (!intel_pad_usable(pctrl, grp->grp.pins[i])) {
0396             raw_spin_unlock_irqrestore(&pctrl->lock, flags);
0397             return -EBUSY;
0398         }
0399     }
0400 
0401     /* Now enable the mux setting for each pin in the group */
0402     for (i = 0; i < grp->grp.npins; i++) {
0403         void __iomem *padcfg0;
0404         u32 value;
0405 
0406         padcfg0 = intel_get_padcfg(pctrl, grp->grp.pins[i], PADCFG0);
0407         value = readl(padcfg0);
0408 
0409         value &= ~PADCFG0_PMODE_MASK;
0410 
0411         if (grp->modes)
0412             value |= grp->modes[i] << PADCFG0_PMODE_SHIFT;
0413         else
0414             value |= grp->mode << PADCFG0_PMODE_SHIFT;
0415 
0416         writel(value, padcfg0);
0417     }
0418 
0419     raw_spin_unlock_irqrestore(&pctrl->lock, flags);
0420 
0421     return 0;
0422 }
0423 
0424 static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
0425 {
0426     u32 value;
0427 
0428     value = readl(padcfg0);
0429     if (input) {
0430         value &= ~PADCFG0_GPIORXDIS;
0431         value |= PADCFG0_GPIOTXDIS;
0432     } else {
0433         value &= ~PADCFG0_GPIOTXDIS;
0434         value |= PADCFG0_GPIORXDIS;
0435     }
0436     writel(value, padcfg0);
0437 }
0438 
0439 static int intel_gpio_get_gpio_mode(void __iomem *padcfg0)
0440 {
0441     return (readl(padcfg0) & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
0442 }
0443 
0444 static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
0445 {
0446     u32 value;
0447 
0448     value = readl(padcfg0);
0449 
0450     /* Put the pad into GPIO mode */
0451     value &= ~PADCFG0_PMODE_MASK;
0452     value |= PADCFG0_PMODE_GPIO;
0453 
0454     /* Disable TX buffer and enable RX (this will be input) */
0455     value &= ~PADCFG0_GPIORXDIS;
0456     value |= PADCFG0_GPIOTXDIS;
0457 
0458     /* Disable SCI/SMI/NMI generation */
0459     value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
0460     value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
0461 
0462     writel(value, padcfg0);
0463 }
0464 
0465 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
0466                      struct pinctrl_gpio_range *range,
0467                      unsigned int pin)
0468 {
0469     struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0470     void __iomem *padcfg0;
0471     unsigned long flags;
0472 
0473     padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
0474 
0475     raw_spin_lock_irqsave(&pctrl->lock, flags);
0476 
0477     if (!intel_pad_owned_by_host(pctrl, pin)) {
0478         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
0479         return -EBUSY;
0480     }
0481 
0482     if (!intel_pad_is_unlocked(pctrl, pin)) {
0483         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
0484         return 0;
0485     }
0486 
0487     /*
0488      * If pin is already configured in GPIO mode, we assume that
0489      * firmware provides correct settings. In such case we avoid
0490      * potential glitches on the pin. Otherwise, for the pin in
0491      * alternative mode, consumer has to supply respective flags.
0492      */
0493     if (intel_gpio_get_gpio_mode(padcfg0) == PADCFG0_PMODE_GPIO) {
0494         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
0495         return 0;
0496     }
0497 
0498     intel_gpio_set_gpio_mode(padcfg0);
0499 
0500     raw_spin_unlock_irqrestore(&pctrl->lock, flags);
0501 
0502     return 0;
0503 }
0504 
0505 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
0506                     struct pinctrl_gpio_range *range,
0507                     unsigned int pin, bool input)
0508 {
0509     struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0510     void __iomem *padcfg0;
0511     unsigned long flags;
0512 
0513     padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
0514 
0515     raw_spin_lock_irqsave(&pctrl->lock, flags);
0516     __intel_gpio_set_direction(padcfg0, input);
0517     raw_spin_unlock_irqrestore(&pctrl->lock, flags);
0518 
0519     return 0;
0520 }
0521 
0522 static const struct pinmux_ops intel_pinmux_ops = {
0523     .get_functions_count = intel_get_functions_count,
0524     .get_function_name = intel_get_function_name,
0525     .get_function_groups = intel_get_function_groups,
0526     .set_mux = intel_pinmux_set_mux,
0527     .gpio_request_enable = intel_gpio_request_enable,
0528     .gpio_set_direction = intel_gpio_set_direction,
0529 };
0530 
0531 static int intel_config_get_pull(struct intel_pinctrl *pctrl, unsigned int pin,
0532                  enum pin_config_param param, u32 *arg)
0533 {
0534     const struct intel_community *community;
0535     void __iomem *padcfg1;
0536     unsigned long flags;
0537     u32 value, term;
0538 
0539     community = intel_get_community(pctrl, pin);
0540     padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
0541 
0542     raw_spin_lock_irqsave(&pctrl->lock, flags);
0543     value = readl(padcfg1);
0544     raw_spin_unlock_irqrestore(&pctrl->lock, flags);
0545 
0546     term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
0547 
0548     switch (param) {
0549     case PIN_CONFIG_BIAS_DISABLE:
0550         if (term)
0551             return -EINVAL;
0552         break;
0553 
0554     case PIN_CONFIG_BIAS_PULL_UP:
0555         if (!term || !(value & PADCFG1_TERM_UP))
0556             return -EINVAL;
0557 
0558         switch (term) {
0559         case PADCFG1_TERM_833:
0560             *arg = 833;
0561             break;
0562         case PADCFG1_TERM_1K:
0563             *arg = 1000;
0564             break;
0565         case PADCFG1_TERM_5K:
0566             *arg = 5000;
0567             break;
0568         case PADCFG1_TERM_20K:
0569             *arg = 20000;
0570             break;
0571         }
0572 
0573         break;
0574 
0575     case PIN_CONFIG_BIAS_PULL_DOWN:
0576         if (!term || value & PADCFG1_TERM_UP)
0577             return -EINVAL;
0578 
0579         switch (term) {
0580         case PADCFG1_TERM_833:
0581             if (!(community->features & PINCTRL_FEATURE_1K_PD))
0582                 return -EINVAL;
0583             *arg = 833;
0584             break;
0585         case PADCFG1_TERM_1K:
0586             if (!(community->features & PINCTRL_FEATURE_1K_PD))
0587                 return -EINVAL;
0588             *arg = 1000;
0589             break;
0590         case PADCFG1_TERM_5K:
0591             *arg = 5000;
0592             break;
0593         case PADCFG1_TERM_20K:
0594             *arg = 20000;
0595             break;
0596         }
0597 
0598         break;
0599 
0600     default:
0601         return -EINVAL;
0602     }
0603 
0604     return 0;
0605 }
0606 
0607 static int intel_config_get_debounce(struct intel_pinctrl *pctrl, unsigned int pin,
0608                      enum pin_config_param param, u32 *arg)
0609 {
0610     void __iomem *padcfg2;
0611     unsigned long flags;
0612     unsigned long v;
0613     u32 value2;
0614 
0615     padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
0616     if (!padcfg2)
0617         return -ENOTSUPP;
0618 
0619     raw_spin_lock_irqsave(&pctrl->lock, flags);
0620     value2 = readl(padcfg2);
0621     raw_spin_unlock_irqrestore(&pctrl->lock, flags);
0622     if (!(value2 & PADCFG2_DEBEN))
0623         return -EINVAL;
0624 
0625     v = (value2 & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
0626     *arg = BIT(v) * DEBOUNCE_PERIOD_NSEC / NSEC_PER_USEC;
0627 
0628     return 0;
0629 }
0630 
0631 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
0632                 unsigned long *config)
0633 {
0634     struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0635     enum pin_config_param param = pinconf_to_config_param(*config);
0636     u32 arg = 0;
0637     int ret;
0638 
0639     if (!intel_pad_owned_by_host(pctrl, pin))
0640         return -ENOTSUPP;
0641 
0642     switch (param) {
0643     case PIN_CONFIG_BIAS_DISABLE:
0644     case PIN_CONFIG_BIAS_PULL_UP:
0645     case PIN_CONFIG_BIAS_PULL_DOWN:
0646         ret = intel_config_get_pull(pctrl, pin, param, &arg);
0647         if (ret)
0648             return ret;
0649         break;
0650 
0651     case PIN_CONFIG_INPUT_DEBOUNCE:
0652         ret = intel_config_get_debounce(pctrl, pin, param, &arg);
0653         if (ret)
0654             return ret;
0655         break;
0656 
0657     default:
0658         return -ENOTSUPP;
0659     }
0660 
0661     *config = pinconf_to_config_packed(param, arg);
0662     return 0;
0663 }
0664 
0665 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
0666                  unsigned long config)
0667 {
0668     unsigned int param = pinconf_to_config_param(config);
0669     unsigned int arg = pinconf_to_config_argument(config);
0670     const struct intel_community *community;
0671     void __iomem *padcfg1;
0672     unsigned long flags;
0673     int ret = 0;
0674     u32 value;
0675 
0676     community = intel_get_community(pctrl, pin);
0677     padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
0678 
0679     raw_spin_lock_irqsave(&pctrl->lock, flags);
0680 
0681     value = readl(padcfg1);
0682 
0683     switch (param) {
0684     case PIN_CONFIG_BIAS_DISABLE:
0685         value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
0686         break;
0687 
0688     case PIN_CONFIG_BIAS_PULL_UP:
0689         value &= ~PADCFG1_TERM_MASK;
0690 
0691         value |= PADCFG1_TERM_UP;
0692 
0693         /* Set default strength value in case none is given */
0694         if (arg == 1)
0695             arg = 5000;
0696 
0697         switch (arg) {
0698         case 20000:
0699             value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
0700             break;
0701         case 5000:
0702             value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
0703             break;
0704         case 1000:
0705             value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
0706             break;
0707         case 833:
0708             value |= PADCFG1_TERM_833 << PADCFG1_TERM_SHIFT;
0709             break;
0710         default:
0711             ret = -EINVAL;
0712         }
0713 
0714         break;
0715 
0716     case PIN_CONFIG_BIAS_PULL_DOWN:
0717         value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);
0718 
0719         /* Set default strength value in case none is given */
0720         if (arg == 1)
0721             arg = 5000;
0722 
0723         switch (arg) {
0724         case 20000:
0725             value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
0726             break;
0727         case 5000:
0728             value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
0729             break;
0730         case 1000:
0731             if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
0732                 ret = -EINVAL;
0733                 break;
0734             }
0735             value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
0736             break;
0737         case 833:
0738             if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
0739                 ret = -EINVAL;
0740                 break;
0741             }
0742             value |= PADCFG1_TERM_833 << PADCFG1_TERM_SHIFT;
0743             break;
0744         default:
0745             ret = -EINVAL;
0746         }
0747 
0748         break;
0749     }
0750 
0751     if (!ret)
0752         writel(value, padcfg1);
0753 
0754     raw_spin_unlock_irqrestore(&pctrl->lock, flags);
0755 
0756     return ret;
0757 }
0758 
0759 static int intel_config_set_debounce(struct intel_pinctrl *pctrl,
0760                      unsigned int pin, unsigned int debounce)
0761 {
0762     void __iomem *padcfg0, *padcfg2;
0763     unsigned long flags;
0764     u32 value0, value2;
0765 
0766     padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
0767     if (!padcfg2)
0768         return -ENOTSUPP;
0769 
0770     padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
0771 
0772     raw_spin_lock_irqsave(&pctrl->lock, flags);
0773 
0774     value0 = readl(padcfg0);
0775     value2 = readl(padcfg2);
0776 
0777     /* Disable glitch filter and debouncer */
0778     value0 &= ~PADCFG0_PREGFRXSEL;
0779     value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK);
0780 
0781     if (debounce) {
0782         unsigned long v;
0783 
0784         v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC);
0785         if (v < 3 || v > 15) {
0786             raw_spin_unlock_irqrestore(&pctrl->lock, flags);
0787             return -EINVAL;
0788         }
0789 
0790         /* Enable glitch filter and debouncer */
0791         value0 |= PADCFG0_PREGFRXSEL;
0792         value2 |= v << PADCFG2_DEBOUNCE_SHIFT;
0793         value2 |= PADCFG2_DEBEN;
0794     }
0795 
0796     writel(value0, padcfg0);
0797     writel(value2, padcfg2);
0798 
0799     raw_spin_unlock_irqrestore(&pctrl->lock, flags);
0800 
0801     return 0;
0802 }
0803 
0804 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
0805               unsigned long *configs, unsigned int nconfigs)
0806 {
0807     struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0808     int i, ret;
0809 
0810     if (!intel_pad_usable(pctrl, pin))
0811         return -ENOTSUPP;
0812 
0813     for (i = 0; i < nconfigs; i++) {
0814         switch (pinconf_to_config_param(configs[i])) {
0815         case PIN_CONFIG_BIAS_DISABLE:
0816         case PIN_CONFIG_BIAS_PULL_UP:
0817         case PIN_CONFIG_BIAS_PULL_DOWN:
0818             ret = intel_config_set_pull(pctrl, pin, configs[i]);
0819             if (ret)
0820                 return ret;
0821             break;
0822 
0823         case PIN_CONFIG_INPUT_DEBOUNCE:
0824             ret = intel_config_set_debounce(pctrl, pin,
0825                 pinconf_to_config_argument(configs[i]));
0826             if (ret)
0827                 return ret;
0828             break;
0829 
0830         default:
0831             return -ENOTSUPP;
0832         }
0833     }
0834 
0835     return 0;
0836 }
0837 
0838 static const struct pinconf_ops intel_pinconf_ops = {
0839     .is_generic = true,
0840     .pin_config_get = intel_config_get,
0841     .pin_config_set = intel_config_set,
0842 };
0843 
0844 static const struct pinctrl_desc intel_pinctrl_desc = {
0845     .pctlops = &intel_pinctrl_ops,
0846     .pmxops = &intel_pinmux_ops,
0847     .confops = &intel_pinconf_ops,
0848     .owner = THIS_MODULE,
0849 };
0850 
0851 /**
0852  * intel_gpio_to_pin() - Translate from GPIO offset to pin number
0853  * @pctrl: Pinctrl structure
0854  * @offset: GPIO offset from gpiolib
0855  * @community: Community is filled here if not %NULL
0856  * @padgrp: Pad group is filled here if not %NULL
0857  *
0858  * When coming through gpiolib irqchip, the GPIO offset is not
0859  * automatically translated to pinctrl pin number. This function can be
0860  * used to find out the corresponding pinctrl pin.
0861  *
0862  * Return: a pin number and pointers to the community and pad group, which
0863  * the pin belongs to, or negative error code if translation can't be done.
0864  */
0865 static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset,
0866                  const struct intel_community **community,
0867                  const struct intel_padgroup **padgrp)
0868 {
0869     int i;
0870 
0871     for (i = 0; i < pctrl->ncommunities; i++) {
0872         const struct intel_community *comm = &pctrl->communities[i];
0873         int j;
0874 
0875         for (j = 0; j < comm->ngpps; j++) {
0876             const struct intel_padgroup *pgrp = &comm->gpps[j];
0877 
0878             if (pgrp->gpio_base == INTEL_GPIO_BASE_NOMAP)
0879                 continue;
0880 
0881             if (offset >= pgrp->gpio_base &&
0882                 offset < pgrp->gpio_base + pgrp->size) {
0883                 int pin;
0884 
0885                 pin = pgrp->base + offset - pgrp->gpio_base;
0886                 if (community)
0887                     *community = comm;
0888                 if (padgrp)
0889                     *padgrp = pgrp;
0890 
0891                 return pin;
0892             }
0893         }
0894     }
0895 
0896     return -EINVAL;
0897 }
0898 
0899 /**
0900  * intel_pin_to_gpio() - Translate from pin number to GPIO offset
0901  * @pctrl: Pinctrl structure
0902  * @pin: pin number
0903  *
0904  * Translate the pin number of pinctrl to GPIO offset
0905  *
0906  * Return: a GPIO offset, or negative error code if translation can't be done.
0907  */
0908 static __maybe_unused int intel_pin_to_gpio(struct intel_pinctrl *pctrl, int pin)
0909 {
0910     const struct intel_community *community;
0911     const struct intel_padgroup *padgrp;
0912 
0913     community = intel_get_community(pctrl, pin);
0914     if (!community)
0915         return -EINVAL;
0916 
0917     padgrp = intel_community_get_padgroup(community, pin);
0918     if (!padgrp)
0919         return -EINVAL;
0920 
0921     return pin - padgrp->base + padgrp->gpio_base;
0922 }
0923 
0924 static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset)
0925 {
0926     struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
0927     void __iomem *reg;
0928     u32 padcfg0;
0929     int pin;
0930 
0931     pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
0932     if (pin < 0)
0933         return -EINVAL;
0934 
0935     reg = intel_get_padcfg(pctrl, pin, PADCFG0);
0936     if (!reg)
0937         return -EINVAL;
0938 
0939     padcfg0 = readl(reg);
0940     if (!(padcfg0 & PADCFG0_GPIOTXDIS))
0941         return !!(padcfg0 & PADCFG0_GPIOTXSTATE);
0942 
0943     return !!(padcfg0 & PADCFG0_GPIORXSTATE);
0944 }
0945 
0946 static void intel_gpio_set(struct gpio_chip *chip, unsigned int offset,
0947                int value)
0948 {
0949     struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
0950     unsigned long flags;
0951     void __iomem *reg;
0952     u32 padcfg0;
0953     int pin;
0954 
0955     pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
0956     if (pin < 0)
0957         return;
0958 
0959     reg = intel_get_padcfg(pctrl, pin, PADCFG0);
0960     if (!reg)
0961         return;
0962 
0963     raw_spin_lock_irqsave(&pctrl->lock, flags);
0964     padcfg0 = readl(reg);
0965     if (value)
0966         padcfg0 |= PADCFG0_GPIOTXSTATE;
0967     else
0968         padcfg0 &= ~PADCFG0_GPIOTXSTATE;
0969     writel(padcfg0, reg);
0970     raw_spin_unlock_irqrestore(&pctrl->lock, flags);
0971 }
0972 
0973 static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
0974 {
0975     struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
0976     unsigned long flags;
0977     void __iomem *reg;
0978     u32 padcfg0;
0979     int pin;
0980 
0981     pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
0982     if (pin < 0)
0983         return -EINVAL;
0984 
0985     reg = intel_get_padcfg(pctrl, pin, PADCFG0);
0986     if (!reg)
0987         return -EINVAL;
0988 
0989     raw_spin_lock_irqsave(&pctrl->lock, flags);
0990     padcfg0 = readl(reg);
0991     raw_spin_unlock_irqrestore(&pctrl->lock, flags);
0992     if (padcfg0 & PADCFG0_PMODE_MASK)
0993         return -EINVAL;
0994 
0995     if (padcfg0 & PADCFG0_GPIOTXDIS)
0996         return GPIO_LINE_DIRECTION_IN;
0997 
0998     return GPIO_LINE_DIRECTION_OUT;
0999 }
1000 
1001 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
1002 {
1003     return pinctrl_gpio_direction_input(chip->base + offset);
1004 }
1005 
1006 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
1007                        int value)
1008 {
1009     intel_gpio_set(chip, offset, value);
1010     return pinctrl_gpio_direction_output(chip->base + offset);
1011 }
1012 
1013 static const struct gpio_chip intel_gpio_chip = {
1014     .owner = THIS_MODULE,
1015     .request = gpiochip_generic_request,
1016     .free = gpiochip_generic_free,
1017     .get_direction = intel_gpio_get_direction,
1018     .direction_input = intel_gpio_direction_input,
1019     .direction_output = intel_gpio_direction_output,
1020     .get = intel_gpio_get,
1021     .set = intel_gpio_set,
1022     .set_config = gpiochip_generic_config,
1023 };
1024 
1025 static void intel_gpio_irq_ack(struct irq_data *d)
1026 {
1027     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1028     struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1029     const struct intel_community *community;
1030     const struct intel_padgroup *padgrp;
1031     int pin;
1032 
1033     pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
1034     if (pin >= 0) {
1035         unsigned int gpp, gpp_offset, is_offset;
1036 
1037         gpp = padgrp->reg_num;
1038         gpp_offset = padgroup_offset(padgrp, pin);
1039         is_offset = community->is_offset + gpp * 4;
1040 
1041         raw_spin_lock(&pctrl->lock);
1042         writel(BIT(gpp_offset), community->regs + is_offset);
1043         raw_spin_unlock(&pctrl->lock);
1044     }
1045 }
1046 
1047 static void intel_gpio_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t hwirq, bool mask)
1048 {
1049     struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1050     const struct intel_community *community;
1051     const struct intel_padgroup *padgrp;
1052     int pin;
1053 
1054     pin = intel_gpio_to_pin(pctrl, hwirq, &community, &padgrp);
1055     if (pin >= 0) {
1056         unsigned int gpp, gpp_offset;
1057         unsigned long flags;
1058         void __iomem *reg, *is;
1059         u32 value;
1060 
1061         gpp = padgrp->reg_num;
1062         gpp_offset = padgroup_offset(padgrp, pin);
1063 
1064         reg = community->regs + community->ie_offset + gpp * 4;
1065         is = community->regs + community->is_offset + gpp * 4;
1066 
1067         raw_spin_lock_irqsave(&pctrl->lock, flags);
1068 
1069         /* Clear interrupt status first to avoid unexpected interrupt */
1070         writel(BIT(gpp_offset), is);
1071 
1072         value = readl(reg);
1073         if (mask)
1074             value &= ~BIT(gpp_offset);
1075         else
1076             value |= BIT(gpp_offset);
1077         writel(value, reg);
1078         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1079     }
1080 }
1081 
1082 static void intel_gpio_irq_mask(struct irq_data *d)
1083 {
1084     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1085     irq_hw_number_t hwirq = irqd_to_hwirq(d);
1086 
1087     intel_gpio_irq_mask_unmask(gc, hwirq, true);
1088     gpiochip_disable_irq(gc, hwirq);
1089 }
1090 
1091 static void intel_gpio_irq_unmask(struct irq_data *d)
1092 {
1093     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1094     irq_hw_number_t hwirq = irqd_to_hwirq(d);
1095 
1096     gpiochip_enable_irq(gc, hwirq);
1097     intel_gpio_irq_mask_unmask(gc, hwirq, false);
1098 }
1099 
1100 static int intel_gpio_irq_type(struct irq_data *d, unsigned int type)
1101 {
1102     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1103     struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1104     unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1105     unsigned long flags;
1106     void __iomem *reg;
1107     u32 value;
1108 
1109     reg = intel_get_padcfg(pctrl, pin, PADCFG0);
1110     if (!reg)
1111         return -EINVAL;
1112 
1113     /*
1114      * If the pin is in ACPI mode it is still usable as a GPIO but it
1115      * cannot be used as IRQ because GPI_IS status bit will not be
1116      * updated by the host controller hardware.
1117      */
1118     if (intel_pad_acpi_mode(pctrl, pin)) {
1119         dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
1120         return -EPERM;
1121     }
1122 
1123     raw_spin_lock_irqsave(&pctrl->lock, flags);
1124 
1125     intel_gpio_set_gpio_mode(reg);
1126 
1127     value = readl(reg);
1128 
1129     value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
1130 
1131     if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
1132         value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
1133     } else if (type & IRQ_TYPE_EDGE_FALLING) {
1134         value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
1135         value |= PADCFG0_RXINV;
1136     } else if (type & IRQ_TYPE_EDGE_RISING) {
1137         value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
1138     } else if (type & IRQ_TYPE_LEVEL_MASK) {
1139         if (type & IRQ_TYPE_LEVEL_LOW)
1140             value |= PADCFG0_RXINV;
1141     } else {
1142         value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
1143     }
1144 
1145     writel(value, reg);
1146 
1147     if (type & IRQ_TYPE_EDGE_BOTH)
1148         irq_set_handler_locked(d, handle_edge_irq);
1149     else if (type & IRQ_TYPE_LEVEL_MASK)
1150         irq_set_handler_locked(d, handle_level_irq);
1151 
1152     raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1153 
1154     return 0;
1155 }
1156 
1157 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
1158 {
1159     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1160     struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1161     unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1162 
1163     if (on)
1164         enable_irq_wake(pctrl->irq);
1165     else
1166         disable_irq_wake(pctrl->irq);
1167 
1168     dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);
1169     return 0;
1170 }
1171 
1172 static const struct irq_chip intel_gpio_irq_chip = {
1173     .name = "intel-gpio",
1174     .irq_ack = intel_gpio_irq_ack,
1175     .irq_mask = intel_gpio_irq_mask,
1176     .irq_unmask = intel_gpio_irq_unmask,
1177     .irq_set_type = intel_gpio_irq_type,
1178     .irq_set_wake = intel_gpio_irq_wake,
1179     .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,
1180     GPIOCHIP_IRQ_RESOURCE_HELPERS,
1181 };
1182 
1183 static int intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
1184                         const struct intel_community *community)
1185 {
1186     struct gpio_chip *gc = &pctrl->chip;
1187     unsigned int gpp;
1188     int ret = 0;
1189 
1190     for (gpp = 0; gpp < community->ngpps; gpp++) {
1191         const struct intel_padgroup *padgrp = &community->gpps[gpp];
1192         unsigned long pending, enabled, gpp_offset;
1193 
1194         raw_spin_lock(&pctrl->lock);
1195 
1196         pending = readl(community->regs + community->is_offset +
1197                 padgrp->reg_num * 4);
1198         enabled = readl(community->regs + community->ie_offset +
1199                 padgrp->reg_num * 4);
1200 
1201         raw_spin_unlock(&pctrl->lock);
1202 
1203         /* Only interrupts that are enabled */
1204         pending &= enabled;
1205 
1206         for_each_set_bit(gpp_offset, &pending, padgrp->size) {
1207             unsigned int irq;
1208 
1209             irq = irq_find_mapping(gc->irq.domain,
1210                            padgrp->gpio_base + gpp_offset);
1211             generic_handle_irq(irq);
1212         }
1213 
1214         ret += pending ? 1 : 0;
1215     }
1216 
1217     return ret;
1218 }
1219 
1220 static irqreturn_t intel_gpio_irq(int irq, void *data)
1221 {
1222     const struct intel_community *community;
1223     struct intel_pinctrl *pctrl = data;
1224     unsigned int i;
1225     int ret = 0;
1226 
1227     /* Need to check all communities for pending interrupts */
1228     for (i = 0; i < pctrl->ncommunities; i++) {
1229         community = &pctrl->communities[i];
1230         ret += intel_gpio_community_irq_handler(pctrl, community);
1231     }
1232 
1233     return IRQ_RETVAL(ret);
1234 }
1235 
1236 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1237 {
1238     int i;
1239 
1240     for (i = 0; i < pctrl->ncommunities; i++) {
1241         const struct intel_community *community;
1242         void __iomem *base;
1243         unsigned int gpp;
1244 
1245         community = &pctrl->communities[i];
1246         base = community->regs;
1247 
1248         for (gpp = 0; gpp < community->ngpps; gpp++) {
1249             /* Mask and clear all interrupts */
1250             writel(0, base + community->ie_offset + gpp * 4);
1251             writel(0xffff, base + community->is_offset + gpp * 4);
1252         }
1253     }
1254 }
1255 
1256 static int intel_gpio_irq_init_hw(struct gpio_chip *gc)
1257 {
1258     struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1259 
1260     /*
1261      * Make sure the interrupt lines are in a proper state before
1262      * further configuration.
1263      */
1264     intel_gpio_irq_init(pctrl);
1265 
1266     return 0;
1267 }
1268 
1269 static int intel_gpio_add_community_ranges(struct intel_pinctrl *pctrl,
1270                 const struct intel_community *community)
1271 {
1272     int ret = 0, i;
1273 
1274     for (i = 0; i < community->ngpps; i++) {
1275         const struct intel_padgroup *gpp = &community->gpps[i];
1276 
1277         if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP)
1278             continue;
1279 
1280         ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
1281                          gpp->gpio_base, gpp->base,
1282                          gpp->size);
1283         if (ret)
1284             return ret;
1285     }
1286 
1287     return ret;
1288 }
1289 
1290 static int intel_gpio_add_pin_ranges(struct gpio_chip *gc)
1291 {
1292     struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1293     int ret, i;
1294 
1295     for (i = 0; i < pctrl->ncommunities; i++) {
1296         struct intel_community *community = &pctrl->communities[i];
1297 
1298         ret = intel_gpio_add_community_ranges(pctrl, community);
1299         if (ret) {
1300             dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1301             return ret;
1302         }
1303     }
1304 
1305     return 0;
1306 }
1307 
1308 static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
1309 {
1310     const struct intel_community *community;
1311     unsigned int ngpio = 0;
1312     int i, j;
1313 
1314     for (i = 0; i < pctrl->ncommunities; i++) {
1315         community = &pctrl->communities[i];
1316         for (j = 0; j < community->ngpps; j++) {
1317             const struct intel_padgroup *gpp = &community->gpps[j];
1318 
1319             if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP)
1320                 continue;
1321 
1322             if (gpp->gpio_base + gpp->size > ngpio)
1323                 ngpio = gpp->gpio_base + gpp->size;
1324         }
1325     }
1326 
1327     return ngpio;
1328 }
1329 
1330 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
1331 {
1332     int ret;
1333     struct gpio_irq_chip *girq;
1334 
1335     pctrl->chip = intel_gpio_chip;
1336 
1337     /* Setup GPIO chip */
1338     pctrl->chip.ngpio = intel_gpio_ngpio(pctrl);
1339     pctrl->chip.label = dev_name(pctrl->dev);
1340     pctrl->chip.parent = pctrl->dev;
1341     pctrl->chip.base = -1;
1342     pctrl->chip.add_pin_ranges = intel_gpio_add_pin_ranges;
1343     pctrl->irq = irq;
1344 
1345     /*
1346      * On some platforms several GPIO controllers share the same interrupt
1347      * line.
1348      */
1349     ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
1350                    IRQF_SHARED | IRQF_NO_THREAD,
1351                    dev_name(pctrl->dev), pctrl);
1352     if (ret) {
1353         dev_err(pctrl->dev, "failed to request interrupt\n");
1354         return ret;
1355     }
1356 
1357     /* Setup IRQ chip */
1358     girq = &pctrl->chip.irq;
1359     gpio_irq_chip_set_chip(girq, &intel_gpio_irq_chip);
1360     /* This will let us handle the IRQ in the driver */
1361     girq->parent_handler = NULL;
1362     girq->num_parents = 0;
1363     girq->default_type = IRQ_TYPE_NONE;
1364     girq->handler = handle_bad_irq;
1365     girq->init_hw = intel_gpio_irq_init_hw;
1366 
1367     ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
1368     if (ret) {
1369         dev_err(pctrl->dev, "failed to register gpiochip\n");
1370         return ret;
1371     }
1372 
1373     return 0;
1374 }
1375 
1376 static int intel_pinctrl_add_padgroups_by_gpps(struct intel_pinctrl *pctrl,
1377                            struct intel_community *community)
1378 {
1379     struct intel_padgroup *gpps;
1380     unsigned int padown_num = 0;
1381     size_t i, ngpps = community->ngpps;
1382 
1383     gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
1384     if (!gpps)
1385         return -ENOMEM;
1386 
1387     for (i = 0; i < ngpps; i++) {
1388         gpps[i] = community->gpps[i];
1389 
1390         if (gpps[i].size > 32)
1391             return -EINVAL;
1392 
1393         /* Special treatment for GPIO base */
1394         switch (gpps[i].gpio_base) {
1395             case INTEL_GPIO_BASE_MATCH:
1396                 gpps[i].gpio_base = gpps[i].base;
1397                 break;
1398             case INTEL_GPIO_BASE_ZERO:
1399                 gpps[i].gpio_base = 0;
1400                 break;
1401             case INTEL_GPIO_BASE_NOMAP:
1402                 break;
1403             default:
1404                 break;
1405         }
1406 
1407         gpps[i].padown_num = padown_num;
1408         padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32);
1409     }
1410 
1411     community->gpps = gpps;
1412 
1413     return 0;
1414 }
1415 
1416 static int intel_pinctrl_add_padgroups_by_size(struct intel_pinctrl *pctrl,
1417                            struct intel_community *community)
1418 {
1419     struct intel_padgroup *gpps;
1420     unsigned int npins = community->npins;
1421     unsigned int padown_num = 0;
1422     size_t i, ngpps = DIV_ROUND_UP(npins, community->gpp_size);
1423 
1424     if (community->gpp_size > 32)
1425         return -EINVAL;
1426 
1427     gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
1428     if (!gpps)
1429         return -ENOMEM;
1430 
1431     for (i = 0; i < ngpps; i++) {
1432         unsigned int gpp_size = community->gpp_size;
1433 
1434         gpps[i].reg_num = i;
1435         gpps[i].base = community->pin_base + i * gpp_size;
1436         gpps[i].size = min(gpp_size, npins);
1437         npins -= gpps[i].size;
1438 
1439         gpps[i].gpio_base = gpps[i].base;
1440         gpps[i].padown_num = padown_num;
1441 
1442         /*
1443          * In older hardware the number of padown registers per
1444          * group is fixed regardless of the group size.
1445          */
1446         if (community->gpp_num_padown_regs)
1447             padown_num += community->gpp_num_padown_regs;
1448         else
1449             padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32);
1450     }
1451 
1452     community->ngpps = ngpps;
1453     community->gpps = gpps;
1454 
1455     return 0;
1456 }
1457 
1458 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
1459 {
1460 #ifdef CONFIG_PM_SLEEP
1461     const struct intel_pinctrl_soc_data *soc = pctrl->soc;
1462     struct intel_community_context *communities;
1463     struct intel_pad_context *pads;
1464     int i;
1465 
1466     pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
1467     if (!pads)
1468         return -ENOMEM;
1469 
1470     communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
1471                    sizeof(*communities), GFP_KERNEL);
1472     if (!communities)
1473         return -ENOMEM;
1474 
1475 
1476     for (i = 0; i < pctrl->ncommunities; i++) {
1477         struct intel_community *community = &pctrl->communities[i];
1478         u32 *intmask, *hostown;
1479 
1480         intmask = devm_kcalloc(pctrl->dev, community->ngpps,
1481                        sizeof(*intmask), GFP_KERNEL);
1482         if (!intmask)
1483             return -ENOMEM;
1484 
1485         communities[i].intmask = intmask;
1486 
1487         hostown = devm_kcalloc(pctrl->dev, community->ngpps,
1488                        sizeof(*hostown), GFP_KERNEL);
1489         if (!hostown)
1490             return -ENOMEM;
1491 
1492         communities[i].hostown = hostown;
1493     }
1494 
1495     pctrl->context.pads = pads;
1496     pctrl->context.communities = communities;
1497 #endif
1498 
1499     return 0;
1500 }
1501 
1502 static int intel_pinctrl_probe(struct platform_device *pdev,
1503                    const struct intel_pinctrl_soc_data *soc_data)
1504 {
1505     struct intel_pinctrl *pctrl;
1506     int i, ret, irq;
1507 
1508     pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1509     if (!pctrl)
1510         return -ENOMEM;
1511 
1512     pctrl->dev = &pdev->dev;
1513     pctrl->soc = soc_data;
1514     raw_spin_lock_init(&pctrl->lock);
1515 
1516     /*
1517      * Make a copy of the communities which we can use to hold pointers
1518      * to the registers.
1519      */
1520     pctrl->ncommunities = pctrl->soc->ncommunities;
1521     pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities,
1522                   sizeof(*pctrl->communities), GFP_KERNEL);
1523     if (!pctrl->communities)
1524         return -ENOMEM;
1525 
1526     for (i = 0; i < pctrl->ncommunities; i++) {
1527         struct intel_community *community = &pctrl->communities[i];
1528         void __iomem *regs;
1529         u32 offset;
1530         u32 value;
1531 
1532         *community = pctrl->soc->communities[i];
1533 
1534         regs = devm_platform_ioremap_resource(pdev, community->barno);
1535         if (IS_ERR(regs))
1536             return PTR_ERR(regs);
1537 
1538         /*
1539          * Determine community features based on the revision.
1540          * A value of all ones means the device is not present.
1541          */
1542         value = readl(regs + REVID);
1543         if (value == ~0u)
1544             return -ENODEV;
1545         if (((value & REVID_MASK) >> REVID_SHIFT) >= 0x94) {
1546             community->features |= PINCTRL_FEATURE_DEBOUNCE;
1547             community->features |= PINCTRL_FEATURE_1K_PD;
1548         }
1549 
1550         /* Determine community features based on the capabilities */
1551         offset = CAPLIST;
1552         do {
1553             value = readl(regs + offset);
1554             switch ((value & CAPLIST_ID_MASK) >> CAPLIST_ID_SHIFT) {
1555             case CAPLIST_ID_GPIO_HW_INFO:
1556                 community->features |= PINCTRL_FEATURE_GPIO_HW_INFO;
1557                 break;
1558             case CAPLIST_ID_PWM:
1559                 community->features |= PINCTRL_FEATURE_PWM;
1560                 break;
1561             case CAPLIST_ID_BLINK:
1562                 community->features |= PINCTRL_FEATURE_BLINK;
1563                 break;
1564             case CAPLIST_ID_EXP:
1565                 community->features |= PINCTRL_FEATURE_EXP;
1566                 break;
1567             default:
1568                 break;
1569             }
1570             offset = (value & CAPLIST_NEXT_MASK) >> CAPLIST_NEXT_SHIFT;
1571         } while (offset);
1572 
1573         dev_dbg(&pdev->dev, "Community%d features: %#08x\n", i, community->features);
1574 
1575         /* Read offset of the pad configuration registers */
1576         offset = readl(regs + PADBAR);
1577 
1578         community->regs = regs;
1579         community->pad_regs = regs + offset;
1580 
1581         if (community->gpps)
1582             ret = intel_pinctrl_add_padgroups_by_gpps(pctrl, community);
1583         else
1584             ret = intel_pinctrl_add_padgroups_by_size(pctrl, community);
1585         if (ret)
1586             return ret;
1587     }
1588 
1589     irq = platform_get_irq(pdev, 0);
1590     if (irq < 0)
1591         return irq;
1592 
1593     ret = intel_pinctrl_pm_init(pctrl);
1594     if (ret)
1595         return ret;
1596 
1597     pctrl->pctldesc = intel_pinctrl_desc;
1598     pctrl->pctldesc.name = dev_name(&pdev->dev);
1599     pctrl->pctldesc.pins = pctrl->soc->pins;
1600     pctrl->pctldesc.npins = pctrl->soc->npins;
1601 
1602     pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1603                            pctrl);
1604     if (IS_ERR(pctrl->pctldev)) {
1605         dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1606         return PTR_ERR(pctrl->pctldev);
1607     }
1608 
1609     ret = intel_gpio_probe(pctrl, irq);
1610     if (ret)
1611         return ret;
1612 
1613     platform_set_drvdata(pdev, pctrl);
1614 
1615     return 0;
1616 }
1617 
1618 int intel_pinctrl_probe_by_hid(struct platform_device *pdev)
1619 {
1620     const struct intel_pinctrl_soc_data *data;
1621 
1622     data = device_get_match_data(&pdev->dev);
1623     if (!data)
1624         return -ENODATA;
1625 
1626     return intel_pinctrl_probe(pdev, data);
1627 }
1628 EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_hid);
1629 
1630 int intel_pinctrl_probe_by_uid(struct platform_device *pdev)
1631 {
1632     const struct intel_pinctrl_soc_data *data;
1633 
1634     data = intel_pinctrl_get_soc_data(pdev);
1635     if (IS_ERR(data))
1636         return PTR_ERR(data);
1637 
1638     return intel_pinctrl_probe(pdev, data);
1639 }
1640 EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_uid);
1641 
1642 const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev)
1643 {
1644     const struct intel_pinctrl_soc_data * const *table;
1645     const struct intel_pinctrl_soc_data *data = NULL;
1646 
1647     table = device_get_match_data(&pdev->dev);
1648     if (table) {
1649         struct acpi_device *adev = ACPI_COMPANION(&pdev->dev);
1650         unsigned int i;
1651 
1652         for (i = 0; table[i]; i++) {
1653             if (!strcmp(adev->pnp.unique_id, table[i]->uid)) {
1654                 data = table[i];
1655                 break;
1656             }
1657         }
1658     } else {
1659         const struct platform_device_id *id;
1660 
1661         id = platform_get_device_id(pdev);
1662         if (!id)
1663             return ERR_PTR(-ENODEV);
1664 
1665         table = (const struct intel_pinctrl_soc_data * const *)id->driver_data;
1666         data = table[pdev->id];
1667     }
1668 
1669     return data ?: ERR_PTR(-ENODATA);
1670 }
1671 EXPORT_SYMBOL_GPL(intel_pinctrl_get_soc_data);
1672 
1673 #ifdef CONFIG_PM_SLEEP
1674 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin)
1675 {
1676     const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);
1677 
1678     if (!pd || !intel_pad_usable(pctrl, pin))
1679         return false;
1680 
1681     /*
1682      * Only restore the pin if it is actually in use by the kernel (or
1683      * by userspace). It is possible that some pins are used by the
1684      * BIOS during resume and those are not always locked down so leave
1685      * them alone.
1686      */
1687     if (pd->mux_owner || pd->gpio_owner ||
1688         gpiochip_line_is_irq(&pctrl->chip, intel_pin_to_gpio(pctrl, pin)))
1689         return true;
1690 
1691     return false;
1692 }
1693 
1694 int intel_pinctrl_suspend_noirq(struct device *dev)
1695 {
1696     struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1697     struct intel_community_context *communities;
1698     struct intel_pad_context *pads;
1699     int i;
1700 
1701     pads = pctrl->context.pads;
1702     for (i = 0; i < pctrl->soc->npins; i++) {
1703         const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1704         void __iomem *padcfg;
1705         u32 val;
1706 
1707         if (!intel_pinctrl_should_save(pctrl, desc->number))
1708             continue;
1709 
1710         val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1711         pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1712         val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1713         pads[i].padcfg1 = val;
1714 
1715         padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1716         if (padcfg)
1717             pads[i].padcfg2 = readl(padcfg);
1718     }
1719 
1720     communities = pctrl->context.communities;
1721     for (i = 0; i < pctrl->ncommunities; i++) {
1722         struct intel_community *community = &pctrl->communities[i];
1723         void __iomem *base;
1724         unsigned int gpp;
1725 
1726         base = community->regs + community->ie_offset;
1727         for (gpp = 0; gpp < community->ngpps; gpp++)
1728             communities[i].intmask[gpp] = readl(base + gpp * 4);
1729 
1730         base = community->regs + community->hostown_offset;
1731         for (gpp = 0; gpp < community->ngpps; gpp++)
1732             communities[i].hostown[gpp] = readl(base + gpp * 4);
1733     }
1734 
1735     return 0;
1736 }
1737 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend_noirq);
1738 
1739 static bool intel_gpio_update_reg(void __iomem *reg, u32 mask, u32 value)
1740 {
1741     u32 curr, updated;
1742 
1743     curr = readl(reg);
1744 
1745     updated = (curr & ~mask) | (value & mask);
1746     if (curr == updated)
1747         return false;
1748 
1749     writel(updated, reg);
1750     return true;
1751 }
1752 
1753 static void intel_restore_hostown(struct intel_pinctrl *pctrl, unsigned int c,
1754                   void __iomem *base, unsigned int gpp, u32 saved)
1755 {
1756     const struct intel_community *community = &pctrl->communities[c];
1757     const struct intel_padgroup *padgrp = &community->gpps[gpp];
1758     struct device *dev = pctrl->dev;
1759     const char *dummy;
1760     u32 requested = 0;
1761     unsigned int i;
1762 
1763     if (padgrp->gpio_base == INTEL_GPIO_BASE_NOMAP)
1764         return;
1765 
1766     for_each_requested_gpio_in_range(&pctrl->chip, i, padgrp->gpio_base, padgrp->size, dummy)
1767         requested |= BIT(i);
1768 
1769     if (!intel_gpio_update_reg(base + gpp * 4, requested, saved))
1770         return;
1771 
1772     dev_dbg(dev, "restored hostown %u/%u %#08x\n", c, gpp, readl(base + gpp * 4));
1773 }
1774 
1775 static void intel_restore_intmask(struct intel_pinctrl *pctrl, unsigned int c,
1776                   void __iomem *base, unsigned int gpp, u32 saved)
1777 {
1778     struct device *dev = pctrl->dev;
1779 
1780     if (!intel_gpio_update_reg(base + gpp * 4, ~0U, saved))
1781         return;
1782 
1783     dev_dbg(dev, "restored mask %u/%u %#08x\n", c, gpp, readl(base + gpp * 4));
1784 }
1785 
1786 static void intel_restore_padcfg(struct intel_pinctrl *pctrl, unsigned int pin,
1787                  unsigned int reg, u32 saved)
1788 {
1789     u32 mask = (reg == PADCFG0) ? PADCFG0_GPIORXSTATE : 0;
1790     unsigned int n = reg / sizeof(u32);
1791     struct device *dev = pctrl->dev;
1792     void __iomem *padcfg;
1793 
1794     padcfg = intel_get_padcfg(pctrl, pin, reg);
1795     if (!padcfg)
1796         return;
1797 
1798     if (!intel_gpio_update_reg(padcfg, ~mask, saved))
1799         return;
1800 
1801     dev_dbg(dev, "restored pin %u padcfg%u %#08x\n", pin, n, readl(padcfg));
1802 }
1803 
1804 int intel_pinctrl_resume_noirq(struct device *dev)
1805 {
1806     struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1807     const struct intel_community_context *communities;
1808     const struct intel_pad_context *pads;
1809     int i;
1810 
1811     /* Mask all interrupts */
1812     intel_gpio_irq_init(pctrl);
1813 
1814     pads = pctrl->context.pads;
1815     for (i = 0; i < pctrl->soc->npins; i++) {
1816         const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1817 
1818         if (!intel_pinctrl_should_save(pctrl, desc->number))
1819             continue;
1820 
1821         intel_restore_padcfg(pctrl, desc->number, PADCFG0, pads[i].padcfg0);
1822         intel_restore_padcfg(pctrl, desc->number, PADCFG1, pads[i].padcfg1);
1823         intel_restore_padcfg(pctrl, desc->number, PADCFG2, pads[i].padcfg2);
1824     }
1825 
1826     communities = pctrl->context.communities;
1827     for (i = 0; i < pctrl->ncommunities; i++) {
1828         struct intel_community *community = &pctrl->communities[i];
1829         void __iomem *base;
1830         unsigned int gpp;
1831 
1832         base = community->regs + community->ie_offset;
1833         for (gpp = 0; gpp < community->ngpps; gpp++)
1834             intel_restore_intmask(pctrl, i, base, gpp, communities[i].intmask[gpp]);
1835 
1836         base = community->regs + community->hostown_offset;
1837         for (gpp = 0; gpp < community->ngpps; gpp++)
1838             intel_restore_hostown(pctrl, i, base, gpp, communities[i].hostown[gpp]);
1839     }
1840 
1841     return 0;
1842 }
1843 EXPORT_SYMBOL_GPL(intel_pinctrl_resume_noirq);
1844 #endif
1845 
1846 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
1847 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1848 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1849 MODULE_LICENSE("GPL v2");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!