pinctrl/intel/pinctrl-geminilake.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Intel Gemini Lake SoC pinctrl/GPIO driver
0004  *
0005  * Copyright (C) 2017 Intel Corporation
0006  * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
0007  */
0008
0009 #include <linux/mod_devicetable.h>
0010 #include <linux/module.h>
0011 #include <linux/platform_device.h>
0012
0013 #include <linux/pinctrl/pinctrl.h>
0014
0015 #include "pinctrl-intel.h"
0016
0017 #define GLK_PAD_OWN 0x020
0018 #define GLK_PADCFGLOCK  0x080
0019 #define GLK_HOSTSW_OWN  0x0b0
0020 #define GLK_GPI_IS  0x100
0021 #define GLK_GPI_IE  0x110
0022
0023 #define GLK_COMMUNITY(s, e)             \
0024     {                       \
0025         .padown_offset = GLK_PAD_OWN,       \
0026         .padcfglock_offset = GLK_PADCFGLOCK,    \
0027         .hostown_offset = GLK_HOSTSW_OWN,   \
0028         .is_offset = GLK_GPI_IS,        \
0029         .ie_offset = GLK_GPI_IE,        \
0030         .gpp_size = 32,                         \
0031         .pin_base = (s),            \
0032         .npins = ((e) - (s) + 1),       \
0033     }
0034
0035 /* GLK */
0036 static const struct pinctrl_pin_desc glk_northwest_pins[] = {
0037     PINCTRL_PIN(0, "TCK"),
0038     PINCTRL_PIN(1, "TRST_B"),
0039     PINCTRL_PIN(2, "TMS"),
0040     PINCTRL_PIN(3, "TDI"),
0041     PINCTRL_PIN(4, "TDO"),
0042     PINCTRL_PIN(5, "JTAGX"),
0043     PINCTRL_PIN(6, "CX_PREQ_B"),
0044     PINCTRL_PIN(7, "CX_PRDY_B"),
0045     PINCTRL_PIN(8, "GPIO_8"),
0046     PINCTRL_PIN(9, "GPIO_9"),
0047     PINCTRL_PIN(10, "GPIO_10"),
0048     PINCTRL_PIN(11, "GPIO_11"),
0049     PINCTRL_PIN(12, "GPIO_12"),
0050     PINCTRL_PIN(13, "GPIO_13"),
0051     PINCTRL_PIN(14, "GPIO_14"),
0052     PINCTRL_PIN(15, "GPIO_15"),
0053     PINCTRL_PIN(16, "GPIO_16"),
0054     PINCTRL_PIN(17, "GPIO_17"),
0055     PINCTRL_PIN(18, "GPIO_18"),
0056     PINCTRL_PIN(19, "GPIO_19"),
0057     PINCTRL_PIN(20, "GPIO_20"),
0058     PINCTRL_PIN(21, "GPIO_21"),
0059     PINCTRL_PIN(22, "GPIO_22"),
0060     PINCTRL_PIN(23, "GPIO_23"),
0061     PINCTRL_PIN(24, "GPIO_24"),
0062     PINCTRL_PIN(25, "GPIO_25"),
0063     PINCTRL_PIN(26, "ISH_GPIO_0"),
0064     PINCTRL_PIN(27, "ISH_GPIO_1"),
0065     PINCTRL_PIN(28, "ISH_GPIO_2"),
0066     PINCTRL_PIN(29, "ISH_GPIO_3"),
0067     PINCTRL_PIN(30, "ISH_GPIO_4"),
0068     PINCTRL_PIN(31, "ISH_GPIO_5"),
0069     PINCTRL_PIN(32, "ISH_GPIO_6"),
0070     PINCTRL_PIN(33, "ISH_GPIO_7"),
0071     PINCTRL_PIN(34, "ISH_GPIO_8"),
0072     PINCTRL_PIN(35, "ISH_GPIO_9"),
0073     PINCTRL_PIN(36, "GPIO_36"),
0074     PINCTRL_PIN(37, "GPIO_37"),
0075     PINCTRL_PIN(38, "GPIO_38"),
0076     PINCTRL_PIN(39, "GPIO_39"),
0077     PINCTRL_PIN(40, "GPIO_40"),
0078     PINCTRL_PIN(41, "GPIO_41"),
0079     PINCTRL_PIN(42, "GP_INTD_DSI_TE1"),
0080     PINCTRL_PIN(43, "GP_INTD_DSI_TE2"),
0081     PINCTRL_PIN(44, "USB_OC0_B"),
0082     PINCTRL_PIN(45, "USB_OC1_B"),
0083     PINCTRL_PIN(46, "DSI_I2C_SDA"),
0084     PINCTRL_PIN(47, "DSI_I2C_SCL"),
0085     PINCTRL_PIN(48, "PMC_I2C_SDA"),
0086     PINCTRL_PIN(49, "PMC_I2C_SCL"),
0087     PINCTRL_PIN(50, "LPSS_I2C0_SDA"),
0088     PINCTRL_PIN(51, "LPSS_I2C0_SCL"),
0089     PINCTRL_PIN(52, "LPSS_I2C1_SDA"),
0090     PINCTRL_PIN(53, "LPSS_I2C1_SCL"),
0091     PINCTRL_PIN(54, "LPSS_I2C2_SDA"),
0092     PINCTRL_PIN(55, "LPSS_I2C2_SCL"),
0093     PINCTRL_PIN(56, "LPSS_I2C3_SDA"),
0094     PINCTRL_PIN(57, "LPSS_I2C3_SCL"),
0095     PINCTRL_PIN(58, "LPSS_I2C4_SDA"),
0096     PINCTRL_PIN(59, "LPSS_I2C4_SCL"),
0097     PINCTRL_PIN(60, "LPSS_UART0_RXD"),
0098     PINCTRL_PIN(61, "LPSS_UART0_TXD"),
0099     PINCTRL_PIN(62, "LPSS_UART0_RTS_B"),
0100     PINCTRL_PIN(63, "LPSS_UART0_CTS_B"),
0101     PINCTRL_PIN(64, "LPSS_UART2_RXD"),
0102     PINCTRL_PIN(65, "LPSS_UART2_TXD"),
0103     PINCTRL_PIN(66, "LPSS_UART2_RTS_B"),
0104     PINCTRL_PIN(67, "LPSS_UART2_CTS_B"),
0105     PINCTRL_PIN(68, "PMC_SPI_FS0"),
0106     PINCTRL_PIN(69, "PMC_SPI_FS1"),
0107     PINCTRL_PIN(70, "PMC_SPI_FS2"),
0108     PINCTRL_PIN(71, "PMC_SPI_RXD"),
0109     PINCTRL_PIN(72, "PMC_SPI_TXD"),
0110     PINCTRL_PIN(73, "PMC_SPI_CLK"),
0111     PINCTRL_PIN(74, "THERMTRIP_B"),
0112     PINCTRL_PIN(75, "PROCHOT_B"),
0113     PINCTRL_PIN(76, "EMMC_RST_B"),
0114     PINCTRL_PIN(77, "GPIO_212"),
0115     PINCTRL_PIN(78, "GPIO_213"),
0116     PINCTRL_PIN(79, "GPIO_214"),
0117 };
0118
0119 static const unsigned int glk_northwest_uart1_pins[] = { 26, 27, 28, 29 };
0120 static const unsigned int glk_northwest_pwm0_pins[] = { 42 };
0121 static const unsigned int glk_northwest_pwm1_pins[] = { 43 };
0122 static const unsigned int glk_northwest_pwm2_pins[] = { 44 };
0123 static const unsigned int glk_northwest_pwm3_pins[] = { 45 };
0124 static const unsigned int glk_northwest_i2c0_pins[] = { 50, 51 };
0125 static const unsigned int glk_northwest_i2c1_pins[] = { 52, 53 };
0126 static const unsigned int glk_northwest_i2c2_pins[] = { 54, 55 };
0127 static const unsigned int glk_northwest_i2c3_pins[] = { 56, 57 };
0128 static const unsigned int glk_northwest_i2c4_pins[] = { 58, 59 };
0129 static const unsigned int glk_northwest_uart0_pins[] = { 60, 61, 62, 63 };
0130 static const unsigned int glk_northwest_uart2_pins[] = { 64, 65, 66, 67 };
0131
0132 static const struct intel_pingroup glk_northwest_groups[] = {
0133     PIN_GROUP("uart1_grp", glk_northwest_uart1_pins, 2),
0134     PIN_GROUP("pwm0_grp", glk_northwest_pwm0_pins, 2),
0135     PIN_GROUP("pwm1_grp", glk_northwest_pwm1_pins, 2),
0136     PIN_GROUP("pwm2_grp", glk_northwest_pwm2_pins, 2),
0137     PIN_GROUP("pwm3_grp", glk_northwest_pwm3_pins, 2),
0138     PIN_GROUP("i2c0_grp", glk_northwest_i2c0_pins, 1),
0139     PIN_GROUP("i2c1_grp", glk_northwest_i2c1_pins, 1),
0140     PIN_GROUP("i2c2_grp", glk_northwest_i2c2_pins, 1),
0141     PIN_GROUP("i2c3_grp", glk_northwest_i2c3_pins, 1),
0142     PIN_GROUP("i2c4_grp", glk_northwest_i2c4_pins, 1),
0143     PIN_GROUP("uart0_grp", glk_northwest_uart0_pins, 1),
0144     PIN_GROUP("uart2_grp", glk_northwest_uart2_pins, 1),
0145 };
0146
0147 static const char * const glk_northwest_uart1_groups[] = { "uart1_grp" };
0148 static const char * const glk_northwest_pwm0_groups[] = { "pwm0_grp" };
0149 static const char * const glk_northwest_pwm1_groups[] = { "pwm1_grp" };
0150 static const char * const glk_northwest_pwm2_groups[] = { "pwm2_grp" };
0151 static const char * const glk_northwest_pwm3_groups[] = { "pwm3_grp" };
0152 static const char * const glk_northwest_i2c0_groups[] = { "i2c0_grp" };
0153 static const char * const glk_northwest_i2c1_groups[] = { "i2c1_grp" };
0154 static const char * const glk_northwest_i2c2_groups[] = { "i2c2_grp" };
0155 static const char * const glk_northwest_i2c3_groups[] = { "i2c3_grp" };
0156 static const char * const glk_northwest_i2c4_groups[] = { "i2c4_grp" };
0157 static const char * const glk_northwest_uart0_groups[] = { "uart0_grp" };
0158 static const char * const glk_northwest_uart2_groups[] = { "uart2_grp" };
0159
0160 static const struct intel_function glk_northwest_functions[] = {
0161     FUNCTION("uart1", glk_northwest_uart1_groups),
0162     FUNCTION("pmw0", glk_northwest_pwm0_groups),
0163     FUNCTION("pmw1", glk_northwest_pwm1_groups),
0164     FUNCTION("pmw2", glk_northwest_pwm2_groups),
0165     FUNCTION("pmw3", glk_northwest_pwm3_groups),
0166     FUNCTION("i2c0", glk_northwest_i2c0_groups),
0167     FUNCTION("i2c1", glk_northwest_i2c1_groups),
0168     FUNCTION("i2c2", glk_northwest_i2c2_groups),
0169     FUNCTION("i2c3", glk_northwest_i2c3_groups),
0170     FUNCTION("i2c4", glk_northwest_i2c4_groups),
0171     FUNCTION("uart0", glk_northwest_uart0_groups),
0172     FUNCTION("uart2", glk_northwest_uart2_groups),
0173 };
0174
0175 static const struct intel_community glk_northwest_communities[] = {
0176     GLK_COMMUNITY(0, 79),
0177 };
0178
0179 static const struct intel_pinctrl_soc_data glk_northwest_soc_data = {
0180     .uid = "1",
0181     .pins = glk_northwest_pins,
0182     .npins = ARRAY_SIZE(glk_northwest_pins),
0183     .groups = glk_northwest_groups,
0184     .ngroups = ARRAY_SIZE(glk_northwest_groups),
0185     .functions = glk_northwest_functions,
0186     .nfunctions = ARRAY_SIZE(glk_northwest_functions),
0187     .communities = glk_northwest_communities,
0188     .ncommunities = ARRAY_SIZE(glk_northwest_communities),
0189 };
0190
0191 static const struct pinctrl_pin_desc glk_north_pins[] = {
0192     PINCTRL_PIN(0, "SVID0_ALERT_B"),
0193     PINCTRL_PIN(1, "SVID0_DATA"),
0194     PINCTRL_PIN(2, "SVID0_CLK"),
0195     PINCTRL_PIN(3, "LPSS_SPI_0_CLK"),
0196     PINCTRL_PIN(4, "LPSS_SPI_0_FS0"),
0197     PINCTRL_PIN(5, "LPSS_SPI_0_FS1"),
0198     PINCTRL_PIN(6, "LPSS_SPI_0_RXD"),
0199     PINCTRL_PIN(7, "LPSS_SPI_0_TXD"),
0200     PINCTRL_PIN(8, "LPSS_SPI_2_CLK"),
0201     PINCTRL_PIN(9, "LPSS_SPI_2_FS0"),
0202     PINCTRL_PIN(10, "LPSS_SPI_2_FS1"),
0203     PINCTRL_PIN(11, "LPSS_SPI_2_FS2"),
0204     PINCTRL_PIN(12, "LPSS_SPI_2_RXD"),
0205     PINCTRL_PIN(13, "LPSS_SPI_2_TXD"),
0206     PINCTRL_PIN(14, "FST_SPI_CS0_B"),
0207     PINCTRL_PIN(15, "FST_SPI_CS1_B"),
0208     PINCTRL_PIN(16, "FST_SPI_MOSI_IO0"),
0209     PINCTRL_PIN(17, "FST_SPI_MISO_IO1"),
0210     PINCTRL_PIN(18, "FST_SPI_IO2"),
0211     PINCTRL_PIN(19, "FST_SPI_IO3"),
0212     PINCTRL_PIN(20, "FST_SPI_CLK"),
0213     PINCTRL_PIN(21, "FST_SPI_CLK_FB"),
0214     PINCTRL_PIN(22, "PMU_PLTRST_B"),
0215     PINCTRL_PIN(23, "PMU_PWRBTN_B"),
0216     PINCTRL_PIN(24, "PMU_SLP_S0_B"),
0217     PINCTRL_PIN(25, "PMU_SLP_S3_B"),
0218     PINCTRL_PIN(26, "PMU_SLP_S4_B"),
0219     PINCTRL_PIN(27, "SUSPWRDNACK"),
0220     PINCTRL_PIN(28, "EMMC_DNX_PWR_EN_B"),
0221     PINCTRL_PIN(29, "GPIO_105"),
0222     PINCTRL_PIN(30, "PMU_BATLOW_B"),
0223     PINCTRL_PIN(31, "PMU_RESETBUTTON_B"),
0224     PINCTRL_PIN(32, "PMU_SUSCLK"),
0225     PINCTRL_PIN(33, "SUS_STAT_B"),
0226     PINCTRL_PIN(34, "LPSS_I2C5_SDA"),
0227     PINCTRL_PIN(35, "LPSS_I2C5_SCL"),
0228     PINCTRL_PIN(36, "LPSS_I2C6_SDA"),
0229     PINCTRL_PIN(37, "LPSS_I2C6_SCL"),
0230     PINCTRL_PIN(38, "LPSS_I2C7_SDA"),
0231     PINCTRL_PIN(39, "LPSS_I2C7_SCL"),
0232     PINCTRL_PIN(40, "PCIE_WAKE0_B"),
0233     PINCTRL_PIN(41, "PCIE_WAKE1_B"),
0234     PINCTRL_PIN(42, "PCIE_WAKE2_B"),
0235     PINCTRL_PIN(43, "PCIE_WAKE3_B"),
0236     PINCTRL_PIN(44, "PCIE_CLKREQ0_B"),
0237     PINCTRL_PIN(45, "PCIE_CLKREQ1_B"),
0238     PINCTRL_PIN(46, "PCIE_CLKREQ2_B"),
0239     PINCTRL_PIN(47, "PCIE_CLKREQ3_B"),
0240     PINCTRL_PIN(48, "HV_DDI0_DDC_SDA"),
0241     PINCTRL_PIN(49, "HV_DDI0_DDC_SCL"),
0242     PINCTRL_PIN(50, "HV_DDI1_DDC_SDA"),
0243     PINCTRL_PIN(51, "HV_DDI1_DDC_SCL"),
0244     PINCTRL_PIN(52, "PANEL0_VDDEN"),
0245     PINCTRL_PIN(53, "PANEL0_BKLTEN"),
0246     PINCTRL_PIN(54, "PANEL0_BKLTCTL"),
0247     PINCTRL_PIN(55, "HV_DDI0_HPD"),
0248     PINCTRL_PIN(56, "HV_DDI1_HPD"),
0249     PINCTRL_PIN(57, "HV_EDP_HPD"),
0250     PINCTRL_PIN(58, "GPIO_134"),
0251     PINCTRL_PIN(59, "GPIO_135"),
0252     PINCTRL_PIN(60, "GPIO_136"),
0253     PINCTRL_PIN(61, "GPIO_137"),
0254     PINCTRL_PIN(62, "GPIO_138"),
0255     PINCTRL_PIN(63, "GPIO_139"),
0256     PINCTRL_PIN(64, "GPIO_140"),
0257     PINCTRL_PIN(65, "GPIO_141"),
0258     PINCTRL_PIN(66, "GPIO_142"),
0259     PINCTRL_PIN(67, "GPIO_143"),
0260     PINCTRL_PIN(68, "GPIO_144"),
0261     PINCTRL_PIN(69, "GPIO_145"),
0262     PINCTRL_PIN(70, "GPIO_146"),
0263     PINCTRL_PIN(71, "LPC_ILB_SERIRQ"),
0264     PINCTRL_PIN(72, "LPC_CLKOUT0"),
0265     PINCTRL_PIN(73, "LPC_CLKOUT1"),
0266     PINCTRL_PIN(74, "LPC_AD0"),
0267     PINCTRL_PIN(75, "LPC_AD1"),
0268     PINCTRL_PIN(76, "LPC_AD2"),
0269     PINCTRL_PIN(77, "LPC_AD3"),
0270     PINCTRL_PIN(78, "LPC_CLKRUNB"),
0271     PINCTRL_PIN(79, "LPC_FRAMEB"),
0272 };
0273
0274 static const unsigned int glk_north_spi0_pins[] = { 3, 4, 5, 6, 7 };
0275 static const unsigned int glk_north_spi1_pins[] = { 8, 9, 10, 11, 12, 13 };
0276 static const unsigned int glk_north_i2c5_pins[] = { 34, 35 };
0277 static const unsigned int glk_north_i2c6_pins[] = { 36, 37 };
0278 static const unsigned int glk_north_i2c7_pins[] = { 38, 39 };
0279 static const unsigned int glk_north_uart0_pins[] = { 62, 63, 64, 65 };
0280 static const unsigned int glk_north_spi0b_pins[] = { 66, 67, 68, 69, 70 };
0281
0282 static const struct intel_pingroup glk_north_groups[] = {
0283     PIN_GROUP("spi0_grp", glk_north_spi0_pins, 1),
0284     PIN_GROUP("spi1_grp", glk_north_spi1_pins, 1),
0285     PIN_GROUP("i2c5_grp", glk_north_i2c5_pins, 1),
0286     PIN_GROUP("i2c6_grp", glk_north_i2c6_pins, 1),
0287     PIN_GROUP("i2c7_grp", glk_north_i2c7_pins, 1),
0288     PIN_GROUP("uart0_grp", glk_north_uart0_pins, 2),
0289     PIN_GROUP("spi0b_grp", glk_north_spi0b_pins, 2),
0290 };
0291
0292 static const char * const glk_north_spi0_groups[] = { "spi0_grp", "spi0b_grp" };
0293 static const char * const glk_north_spi1_groups[] = { "spi1_grp" };
0294 static const char * const glk_north_i2c5_groups[] = { "i2c5_grp" };
0295 static const char * const glk_north_i2c6_groups[] = { "i2c6_grp" };
0296 static const char * const glk_north_i2c7_groups[] = { "i2c7_grp" };
0297 static const char * const glk_north_uart0_groups[] = { "uart0_grp" };
0298
0299 static const struct intel_function glk_north_functions[] = {
0300     FUNCTION("spi0", glk_north_spi0_groups),
0301     FUNCTION("spi1", glk_north_spi1_groups),
0302     FUNCTION("i2c5", glk_north_i2c5_groups),
0303     FUNCTION("i2c6", glk_north_i2c6_groups),
0304     FUNCTION("i2c7", glk_north_i2c7_groups),
0305     FUNCTION("uart0", glk_north_uart0_groups),
0306 };
0307
0308 static const struct intel_community glk_north_communities[] = {
0309     GLK_COMMUNITY(0, 79),
0310 };
0311
0312 static const struct intel_pinctrl_soc_data glk_north_soc_data = {
0313     .uid = "2",
0314     .pins = glk_north_pins,
0315     .npins = ARRAY_SIZE(glk_north_pins),
0316     .groups = glk_north_groups,
0317     .ngroups = ARRAY_SIZE(glk_north_groups),
0318     .functions = glk_north_functions,
0319     .nfunctions = ARRAY_SIZE(glk_north_functions),
0320     .communities = glk_north_communities,
0321     .ncommunities = ARRAY_SIZE(glk_north_communities),
0322 };
0323
0324 static const struct pinctrl_pin_desc glk_audio_pins[] = {
0325     PINCTRL_PIN(0, "AVS_I2S0_MCLK"),
0326     PINCTRL_PIN(1, "AVS_I2S0_BCLK"),
0327     PINCTRL_PIN(2, "AVS_I2S0_WS_SYNC"),
0328     PINCTRL_PIN(3, "AVS_I2S0_SDI"),
0329     PINCTRL_PIN(4, "AVS_I2S0_SDO"),
0330     PINCTRL_PIN(5, "AVS_I2S1_MCLK"),
0331     PINCTRL_PIN(6, "AVS_I2S1_BCLK"),
0332     PINCTRL_PIN(7, "AVS_I2S1_WS_SYNC"),
0333     PINCTRL_PIN(8, "AVS_I2S1_SDI"),
0334     PINCTRL_PIN(9, "AVS_I2S1_SDO"),
0335     PINCTRL_PIN(10, "AVS_HDA_BCLK"),
0336     PINCTRL_PIN(11, "AVS_HDA_WS_SYNC"),
0337     PINCTRL_PIN(12, "AVS_HDA_SDI"),
0338     PINCTRL_PIN(13, "AVS_HDA_SDO"),
0339     PINCTRL_PIN(14, "AVS_HDA_RSTB"),
0340     PINCTRL_PIN(15, "AVS_M_CLK_A1"),
0341     PINCTRL_PIN(16, "AVS_M_CLK_B1"),
0342     PINCTRL_PIN(17, "AVS_M_DATA_1"),
0343     PINCTRL_PIN(18, "AVS_M_CLK_AB2"),
0344     PINCTRL_PIN(19, "AVS_M_DATA_2"),
0345 };
0346
0347 static const struct intel_community glk_audio_communities[] = {
0348     GLK_COMMUNITY(0, 19),
0349 };
0350
0351 static const struct intel_pinctrl_soc_data glk_audio_soc_data = {
0352     .uid = "3",
0353     .pins = glk_audio_pins,
0354     .npins = ARRAY_SIZE(glk_audio_pins),
0355     .communities = glk_audio_communities,
0356     .ncommunities = ARRAY_SIZE(glk_audio_communities),
0357 };
0358
0359 static const struct pinctrl_pin_desc glk_scc_pins[] = {
0360     PINCTRL_PIN(0, "SMB_ALERTB"),
0361     PINCTRL_PIN(1, "SMB_CLK"),
0362     PINCTRL_PIN(2, "SMB_DATA"),
0363     PINCTRL_PIN(3, "SDCARD_LVL_WP"),
0364     PINCTRL_PIN(4, "SDCARD_CLK"),
0365     PINCTRL_PIN(5, "SDCARD_CLK_FB"),
0366     PINCTRL_PIN(6, "SDCARD_D0"),
0367     PINCTRL_PIN(7, "SDCARD_D1"),
0368     PINCTRL_PIN(8, "SDCARD_D2"),
0369     PINCTRL_PIN(9, "SDCARD_D3"),
0370     PINCTRL_PIN(10, "SDCARD_CMD"),
0371     PINCTRL_PIN(11, "SDCARD_CD_B"),
0372     PINCTRL_PIN(12, "SDCARD_PWR_DOWN_B"),
0373     PINCTRL_PIN(13, "GPIO_210"),
0374     PINCTRL_PIN(14, "OSC_CLK_OUT_0"),
0375     PINCTRL_PIN(15, "OSC_CLK_OUT_1"),
0376     PINCTRL_PIN(16, "CNV_BRI_DT"),
0377     PINCTRL_PIN(17, "CNV_BRI_RSP"),
0378     PINCTRL_PIN(18, "CNV_RGI_DT"),
0379     PINCTRL_PIN(19, "CNV_RGI_RSP"),
0380     PINCTRL_PIN(20, "CNV_RF_RESET_B"),
0381     PINCTRL_PIN(21, "XTAL_CLKREQ"),
0382     PINCTRL_PIN(22, "SDIO_CLK_FB"),
0383     PINCTRL_PIN(23, "EMMC0_CLK"),
0384     PINCTRL_PIN(24, "EMMC0_CLK_FB"),
0385     PINCTRL_PIN(25, "EMMC0_D0"),
0386     PINCTRL_PIN(26, "EMMC0_D1"),
0387     PINCTRL_PIN(27, "EMMC0_D2"),
0388     PINCTRL_PIN(28, "EMMC0_D3"),
0389     PINCTRL_PIN(29, "EMMC0_D4"),
0390     PINCTRL_PIN(30, "EMMC0_D5"),
0391     PINCTRL_PIN(31, "EMMC0_D6"),
0392     PINCTRL_PIN(32, "EMMC0_D7"),
0393     PINCTRL_PIN(33, "EMMC0_CMD"),
0394     PINCTRL_PIN(34, "EMMC0_STROBE"),
0395 };
0396
0397 static const unsigned int glk_scc_i2c7_pins[] = { 1, 2 };
0398 static const unsigned int glk_scc_sdcard_pins[] = {
0399     3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
0400 };
0401 static const unsigned int glk_scc_sdio_pins[] = { 16, 17, 18, 19, 20, 21, 22 };
0402 static const unsigned int glk_scc_uart1_pins[] = { 16, 17, 18, 19 };
0403 static const unsigned int glk_scc_emmc_pins[] = {
0404     23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,
0405 };
0406
0407 static const struct intel_pingroup glk_scc_groups[] = {
0408     PIN_GROUP("i2c7_grp", glk_scc_i2c7_pins, 2),
0409     PIN_GROUP("sdcard_grp", glk_scc_sdcard_pins, 1),
0410     PIN_GROUP("sdio_grp", glk_scc_sdio_pins, 2),
0411     PIN_GROUP("uart1_grp", glk_scc_uart1_pins, 3),
0412     PIN_GROUP("emmc_grp", glk_scc_emmc_pins, 1),
0413 };
0414
0415 static const char * const glk_scc_i2c7_groups[] = { "i2c7_grp" };
0416 static const char * const glk_scc_sdcard_groups[] = { "sdcard_grp" };
0417 static const char * const glk_scc_sdio_groups[] = { "sdio_grp" };
0418 static const char * const glk_scc_uart1_groups[] = { "uart1_grp" };
0419 static const char * const glk_scc_emmc_groups[] = { "emmc_grp" };
0420
0421 static const struct intel_function glk_scc_functions[] = {
0422     FUNCTION("i2c7", glk_scc_i2c7_groups),
0423     FUNCTION("sdcard", glk_scc_sdcard_groups),
0424     FUNCTION("sdio", glk_scc_sdio_groups),
0425     FUNCTION("uart1", glk_scc_uart1_groups),
0426     FUNCTION("emmc", glk_scc_emmc_groups),
0427 };
0428
0429 static const struct intel_community glk_scc_communities[] = {
0430     GLK_COMMUNITY(0, 34),
0431 };
0432
0433 static const struct intel_pinctrl_soc_data glk_scc_soc_data = {
0434     .uid = "4",
0435     .pins = glk_scc_pins,
0436     .npins = ARRAY_SIZE(glk_scc_pins),
0437     .groups = glk_scc_groups,
0438     .ngroups = ARRAY_SIZE(glk_scc_groups),
0439     .functions = glk_scc_functions,
0440     .nfunctions = ARRAY_SIZE(glk_scc_functions),
0441     .communities = glk_scc_communities,
0442     .ncommunities = ARRAY_SIZE(glk_scc_communities),
0443 };
0444
0445 static const struct intel_pinctrl_soc_data *glk_pinctrl_soc_data[] = {
0446     &glk_northwest_soc_data,
0447     &glk_north_soc_data,
0448     &glk_audio_soc_data,
0449     &glk_scc_soc_data,
0450     NULL
0451 };
0452
0453 static const struct acpi_device_id glk_pinctrl_acpi_match[] = {
0454     { "INT3453", (kernel_ulong_t)glk_pinctrl_soc_data },
0455     { }
0456 };
0457 MODULE_DEVICE_TABLE(acpi, glk_pinctrl_acpi_match);
0458
0459 static INTEL_PINCTRL_PM_OPS(glk_pinctrl_pm_ops);
0460
0461 static struct platform_driver glk_pinctrl_driver = {
0462     .probe = intel_pinctrl_probe_by_uid,
0463     .driver = {
0464         .name = "geminilake-pinctrl",
0465         .acpi_match_table = glk_pinctrl_acpi_match,
0466         .pm = &glk_pinctrl_pm_ops,
0467     },
0468 };
0469
0470 static int __init glk_pinctrl_init(void)
0471 {
0472     return platform_driver_register(&glk_pinctrl_driver);
0473 }
0474 subsys_initcall(glk_pinctrl_init);
0475
0476 static void __exit glk_pinctrl_exit(void)
0477 {
0478     platform_driver_unregister(&glk_pinctrl_driver);
0479 }
0480 module_exit(glk_pinctrl_exit);
0481
0482 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
0483 MODULE_DESCRIPTION("Intel Gemini Lake SoC pinctrl/GPIO driver");
0484 MODULE_LICENSE("GPL v2");