pinctrl/intel/pinctrl-elkhartlake.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Intel Elkhart Lake PCH pinctrl/GPIO driver
0004  *
0005  * Copyright (C) 2019, Intel Corporation
0006  * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
0007  */
0008
0009 #include <linux/mod_devicetable.h>
0010 #include <linux/module.h>
0011 #include <linux/platform_device.h>
0012
0013 #include <linux/pinctrl/pinctrl.h>
0014
0015 #include "pinctrl-intel.h"
0016
0017 #define EHL_PAD_OWN 0x020
0018 #define EHL_PADCFGLOCK  0x080
0019 #define EHL_HOSTSW_OWN  0x0b0
0020 #define EHL_GPI_IS  0x100
0021 #define EHL_GPI_IE  0x120
0022
0023 #define EHL_GPP(r, s, e)                \
0024     {                       \
0025         .reg_num = (r),             \
0026         .base = (s),                \
0027         .size = ((e) - (s) + 1),        \
0028     }
0029
0030 #define EHL_COMMUNITY(s, e, g)              \
0031     {                       \
0032         .padown_offset = EHL_PAD_OWN,       \
0033         .padcfglock_offset = EHL_PADCFGLOCK,    \
0034         .hostown_offset = EHL_HOSTSW_OWN,   \
0035         .is_offset = EHL_GPI_IS,        \
0036         .ie_offset = EHL_GPI_IE,        \
0037         .pin_base = (s),            \
0038         .npins = ((e) - (s) + 1),       \
0039         .gpps = (g),                \
0040         .ngpps = ARRAY_SIZE(g),         \
0041     }
0042
0043 /* Elkhart Lake */
0044 static const struct pinctrl_pin_desc ehl_community0_pins[] = {
0045     /* GPP_B */
0046     PINCTRL_PIN(0, "CORE_VID_0"),
0047     PINCTRL_PIN(1, "CORE_VID_1"),
0048     PINCTRL_PIN(2, "VRALERTB"),
0049     PINCTRL_PIN(3, "CPU_GP_2"),
0050     PINCTRL_PIN(4, "CPU_GP_3"),
0051     PINCTRL_PIN(5, "OSE_I2C0_SCLK"),
0052     PINCTRL_PIN(6, "OSE_I2C0_SDAT"),
0053     PINCTRL_PIN(7, "OSE_I2C1_SCLK"),
0054     PINCTRL_PIN(8, "OSE_I2C1_SDAT"),
0055     PINCTRL_PIN(9, "I2C5_SDA"),
0056     PINCTRL_PIN(10, "I2C5_SCL"),
0057     PINCTRL_PIN(11, "PMCALERTB"),
0058     PINCTRL_PIN(12, "SLP_S0B"),
0059     PINCTRL_PIN(13, "PLTRSTB"),
0060     PINCTRL_PIN(14, "SPKR"),
0061     PINCTRL_PIN(15, "GSPI0_CS0B"),
0062     PINCTRL_PIN(16, "GSPI0_CLK"),
0063     PINCTRL_PIN(17, "GSPI0_MISO"),
0064     PINCTRL_PIN(18, "GSPI0_MOSI"),
0065     PINCTRL_PIN(19, "GSPI1_CS0B"),
0066     PINCTRL_PIN(20, "GSPI1_CLK"),
0067     PINCTRL_PIN(21, "GSPI1_MISO"),
0068     PINCTRL_PIN(22, "GSPI1_MOSI"),
0069     PINCTRL_PIN(23, "GPPC_B_23"),
0070     PINCTRL_PIN(24, "GSPI0_CLK_LOOPBK"),
0071     PINCTRL_PIN(25, "GSPI1_CLK_LOOPBK"),
0072     /* GPP_T */
0073     PINCTRL_PIN(26, "OSE_QEPA_2"),
0074     PINCTRL_PIN(27, "OSE_QEPB_2"),
0075     PINCTRL_PIN(28, "OSE_QEPI_2"),
0076     PINCTRL_PIN(29, "GPPC_T_3"),
0077     PINCTRL_PIN(30, "RGMII0_INT"),
0078     PINCTRL_PIN(31, "RGMII0_RESETB"),
0079     PINCTRL_PIN(32, "RGMII0_AUXTS"),
0080     PINCTRL_PIN(33, "RGMII0_PPS"),
0081     PINCTRL_PIN(34, "USB2_OCB_2"),
0082     PINCTRL_PIN(35, "OSE_HSUART2_EN"),
0083     PINCTRL_PIN(36, "OSE_HSUART2_RE"),
0084     PINCTRL_PIN(37, "USB2_OCB_3"),
0085     PINCTRL_PIN(38, "OSE_UART2_RXD"),
0086     PINCTRL_PIN(39, "OSE_UART2_TXD"),
0087     PINCTRL_PIN(40, "OSE_UART2_RTSB"),
0088     PINCTRL_PIN(41, "OSE_UART2_CTSB"),
0089     /* GPP_G */
0090     PINCTRL_PIN(42, "SD3_CMD"),
0091     PINCTRL_PIN(43, "SD3_D0"),
0092     PINCTRL_PIN(44, "SD3_D1"),
0093     PINCTRL_PIN(45, "SD3_D2"),
0094     PINCTRL_PIN(46, "SD3_D3"),
0095     PINCTRL_PIN(47, "SD3_CDB"),
0096     PINCTRL_PIN(48, "SD3_CLK"),
0097     PINCTRL_PIN(49, "I2S2_SCLK"),
0098     PINCTRL_PIN(50, "I2S2_SFRM"),
0099     PINCTRL_PIN(51, "I2S2_TXD"),
0100     PINCTRL_PIN(52, "I2S2_RXD"),
0101     PINCTRL_PIN(53, "I2S3_SCLK"),
0102     PINCTRL_PIN(54, "I2S3_SFRM"),
0103     PINCTRL_PIN(55, "I2S3_TXD"),
0104     PINCTRL_PIN(56, "I2S3_RXD"),
0105     PINCTRL_PIN(57, "ESPI_IO_0"),
0106     PINCTRL_PIN(58, "ESPI_IO_1"),
0107     PINCTRL_PIN(59, "ESPI_IO_2"),
0108     PINCTRL_PIN(60, "ESPI_IO_3"),
0109     PINCTRL_PIN(61, "I2S1_SCLK"),
0110     PINCTRL_PIN(62, "ESPI_CSB"),
0111     PINCTRL_PIN(63, "ESPI_CLK"),
0112     PINCTRL_PIN(64, "ESPI_RESETB"),
0113     PINCTRL_PIN(65, "SD3_WP"),
0114     PINCTRL_PIN(66, "ESPI_CLK_LOOPBK"),
0115 };
0116
0117 static const struct intel_padgroup ehl_community0_gpps[] = {
0118     EHL_GPP(0, 0, 25),  /* GPP_B */
0119     EHL_GPP(1, 26, 41), /* GPP_T */
0120     EHL_GPP(2, 42, 66), /* GPP_G */
0121 };
0122
0123 static const struct intel_community ehl_community0[] = {
0124     EHL_COMMUNITY(0, 66, ehl_community0_gpps),
0125 };
0126
0127 static const struct intel_pinctrl_soc_data ehl_community0_soc_data = {
0128     .uid = "0",
0129     .pins = ehl_community0_pins,
0130     .npins = ARRAY_SIZE(ehl_community0_pins),
0131     .communities = ehl_community0,
0132     .ncommunities = ARRAY_SIZE(ehl_community0),
0133 };
0134
0135 static const struct pinctrl_pin_desc ehl_community1_pins[] = {
0136     /* GPP_V */
0137     PINCTRL_PIN(0, "EMMC_CMD"),
0138     PINCTRL_PIN(1, "EMMC_DATA0"),
0139     PINCTRL_PIN(2, "EMMC_DATA1"),
0140     PINCTRL_PIN(3, "EMMC_DATA2"),
0141     PINCTRL_PIN(4, "EMMC_DATA3"),
0142     PINCTRL_PIN(5, "EMMC_DATA4"),
0143     PINCTRL_PIN(6, "EMMC_DATA5"),
0144     PINCTRL_PIN(7, "EMMC_DATA6"),
0145     PINCTRL_PIN(8, "EMMC_DATA7"),
0146     PINCTRL_PIN(9, "EMMC_RCLK"),
0147     PINCTRL_PIN(10, "EMMC_CLK"),
0148     PINCTRL_PIN(11, "EMMC_RESETB"),
0149     PINCTRL_PIN(12, "OSE_TGPIO0"),
0150     PINCTRL_PIN(13, "OSE_TGPIO1"),
0151     PINCTRL_PIN(14, "OSE_TGPIO2"),
0152     PINCTRL_PIN(15, "OSE_TGPIO3"),
0153     /* GPP_H */
0154     PINCTRL_PIN(16, "RGMII1_INT"),
0155     PINCTRL_PIN(17, "RGMII1_RESETB"),
0156     PINCTRL_PIN(18, "RGMII1_AUXTS"),
0157     PINCTRL_PIN(19, "RGMII1_PPS"),
0158     PINCTRL_PIN(20, "I2C2_SDA"),
0159     PINCTRL_PIN(21, "I2C2_SCL"),
0160     PINCTRL_PIN(22, "I2C3_SDA"),
0161     PINCTRL_PIN(23, "I2C3_SCL"),
0162     PINCTRL_PIN(24, "I2C4_SDA"),
0163     PINCTRL_PIN(25, "I2C4_SCL"),
0164     PINCTRL_PIN(26, "SRCCLKREQB_4"),
0165     PINCTRL_PIN(27, "SRCCLKREQB_5"),
0166     PINCTRL_PIN(28, "OSE_UART1_RXD"),
0167     PINCTRL_PIN(29, "OSE_UART1_TXD"),
0168     PINCTRL_PIN(30, "GPPC_H_14"),
0169     PINCTRL_PIN(31, "OSE_UART1_CTSB"),
0170     PINCTRL_PIN(32, "PCIE_LNK_DOWN"),
0171     PINCTRL_PIN(33, "SD_PWR_EN_B"),
0172     PINCTRL_PIN(34, "CPU_C10_GATEB"),
0173     PINCTRL_PIN(35, "GPPC_H_19"),
0174     PINCTRL_PIN(36, "OSE_PWM7"),
0175     PINCTRL_PIN(37, "OSE_HSUART1_DE"),
0176     PINCTRL_PIN(38, "OSE_HSUART1_RE"),
0177     PINCTRL_PIN(39, "OSE_HSUART1_EN"),
0178     /* GPP_D */
0179     PINCTRL_PIN(40, "OSE_QEPA_0"),
0180     PINCTRL_PIN(41, "OSE_QEPB_0"),
0181     PINCTRL_PIN(42, "OSE_QEPI_0"),
0182     PINCTRL_PIN(43, "OSE_PWM6"),
0183     PINCTRL_PIN(44, "OSE_PWM2"),
0184     PINCTRL_PIN(45, "SRCCLKREQB_0"),
0185     PINCTRL_PIN(46, "SRCCLKREQB_1"),
0186     PINCTRL_PIN(47, "SRCCLKREQB_2"),
0187     PINCTRL_PIN(48, "SRCCLKREQB_3"),
0188     PINCTRL_PIN(49, "OSE_SPI0_CSB"),
0189     PINCTRL_PIN(50, "OSE_SPI0_SCLK"),
0190     PINCTRL_PIN(51, "OSE_SPI0_MISO"),
0191     PINCTRL_PIN(52, "OSE_SPI0_MOSI"),
0192     PINCTRL_PIN(53, "OSE_QEPA_1"),
0193     PINCTRL_PIN(54, "OSE_QEPB_1"),
0194     PINCTRL_PIN(55, "OSE_PWM3"),
0195     PINCTRL_PIN(56, "OSE_QEPI_1"),
0196     PINCTRL_PIN(57, "OSE_PWM4"),
0197     PINCTRL_PIN(58, "OSE_PWM5"),
0198     PINCTRL_PIN(59, "I2S_MCLK1_OUT"),
0199     PINCTRL_PIN(60, "GSPI2_CLK_LOOPBK"),
0200     /* GPP_U */
0201     PINCTRL_PIN(61, "RGMII2_INT"),
0202     PINCTRL_PIN(62, "RGMII2_RESETB"),
0203     PINCTRL_PIN(63, "RGMII2_PPS"),
0204     PINCTRL_PIN(64, "RGMII2_AUXTS"),
0205     PINCTRL_PIN(65, "ISI_SPIM_CS"),
0206     PINCTRL_PIN(66, "ISI_SPIM_SCLK"),
0207     PINCTRL_PIN(67, "ISI_SPIM_MISO"),
0208     PINCTRL_PIN(68, "OSE_QEPA_3"),
0209     PINCTRL_PIN(69, "ISI_SPIS_CS"),
0210     PINCTRL_PIN(70, "ISI_SPIS_SCLK"),
0211     PINCTRL_PIN(71, "ISI_SPIS_MISO"),
0212     PINCTRL_PIN(72, "OSE_QEPB_3"),
0213     PINCTRL_PIN(73, "ISI_CHX_OKNOK_0"),
0214     PINCTRL_PIN(74, "ISI_CHX_OKNOK_1"),
0215     PINCTRL_PIN(75, "ISI_CHX_RLY_SWTCH"),
0216     PINCTRL_PIN(76, "ISI_CHX_PMIC_EN"),
0217     PINCTRL_PIN(77, "ISI_OKNOK_0"),
0218     PINCTRL_PIN(78, "ISI_OKNOK_1"),
0219     PINCTRL_PIN(79, "ISI_ALERT"),
0220     PINCTRL_PIN(80, "OSE_QEPI_3"),
0221     PINCTRL_PIN(81, "GSPI3_CLK_LOOPBK"),
0222     PINCTRL_PIN(82, "GSPI4_CLK_LOOPBK"),
0223     PINCTRL_PIN(83, "GSPI5_CLK_LOOPBK"),
0224     PINCTRL_PIN(84, "GSPI6_CLK_LOOPBK"),
0225     /* vGPIO */
0226     PINCTRL_PIN(85, "CNV_BTEN"),
0227     PINCTRL_PIN(86, "CNV_BT_HOST_WAKEB"),
0228     PINCTRL_PIN(87, "CNV_BT_IF_SELECT"),
0229     PINCTRL_PIN(88, "vCNV_BT_UART_TXD"),
0230     PINCTRL_PIN(89, "vCNV_BT_UART_RXD"),
0231     PINCTRL_PIN(90, "vCNV_BT_UART_CTS_B"),
0232     PINCTRL_PIN(91, "vCNV_BT_UART_RTS_B"),
0233     PINCTRL_PIN(92, "vCNV_MFUART1_TXD"),
0234     PINCTRL_PIN(93, "vCNV_MFUART1_RXD"),
0235     PINCTRL_PIN(94, "vCNV_MFUART1_CTS_B"),
0236     PINCTRL_PIN(95, "vCNV_MFUART1_RTS_B"),
0237     PINCTRL_PIN(96, "vUART0_TXD"),
0238     PINCTRL_PIN(97, "vUART0_RXD"),
0239     PINCTRL_PIN(98, "vUART0_CTS_B"),
0240     PINCTRL_PIN(99, "vUART0_RTS_B"),
0241     PINCTRL_PIN(100, "vOSE_UART0_TXD"),
0242     PINCTRL_PIN(101, "vOSE_UART0_RXD"),
0243     PINCTRL_PIN(102, "vOSE_UART0_CTS_B"),
0244     PINCTRL_PIN(103, "vOSE_UART0_RTS_B"),
0245     PINCTRL_PIN(104, "vCNV_BT_I2S_BCLK"),
0246     PINCTRL_PIN(105, "vCNV_BT_I2S_WS_SYNC"),
0247     PINCTRL_PIN(106, "vCNV_BT_I2S_SDO"),
0248     PINCTRL_PIN(107, "vCNV_BT_I2S_SDI"),
0249     PINCTRL_PIN(108, "vI2S2_SCLK"),
0250     PINCTRL_PIN(109, "vI2S2_SFRM"),
0251     PINCTRL_PIN(110, "vI2S2_TXD"),
0252     PINCTRL_PIN(111, "vI2S2_RXD"),
0253     PINCTRL_PIN(112, "vSD3_CD_B"),
0254 };
0255
0256 static const struct intel_padgroup ehl_community1_gpps[] = {
0257     EHL_GPP(0, 0, 15),  /* GPP_V */
0258     EHL_GPP(1, 16, 39), /* GPP_H */
0259     EHL_GPP(2, 40, 60), /* GPP_D */
0260     EHL_GPP(3, 61, 84), /* GPP_U */
0261     EHL_GPP(4, 85, 112),    /* vGPIO */
0262 };
0263
0264 static const struct intel_community ehl_community1[] = {
0265     EHL_COMMUNITY(0, 112, ehl_community1_gpps),
0266 };
0267
0268 static const struct intel_pinctrl_soc_data ehl_community1_soc_data = {
0269     .uid = "1",
0270     .pins = ehl_community1_pins,
0271     .npins = ARRAY_SIZE(ehl_community1_pins),
0272     .communities = ehl_community1,
0273     .ncommunities = ARRAY_SIZE(ehl_community1),
0274 };
0275
0276 static const struct pinctrl_pin_desc ehl_community3_pins[] = {
0277     /* CPU */
0278     PINCTRL_PIN(0, "HDACPU_SDI"),
0279     PINCTRL_PIN(1, "HDACPU_SDO"),
0280     PINCTRL_PIN(2, "HDACPU_BCLK"),
0281     PINCTRL_PIN(3, "PM_SYNC"),
0282     PINCTRL_PIN(4, "PECI"),
0283     PINCTRL_PIN(5, "CPUPWRGD"),
0284     PINCTRL_PIN(6, "THRMTRIPB"),
0285     PINCTRL_PIN(7, "PLTRST_CPUB"),
0286     PINCTRL_PIN(8, "PM_DOWN"),
0287     PINCTRL_PIN(9, "TRIGGER_IN"),
0288     PINCTRL_PIN(10, "TRIGGER_OUT"),
0289     PINCTRL_PIN(11, "UFS_RESETB"),
0290     PINCTRL_PIN(12, "CLKOUT_CPURTC"),
0291     PINCTRL_PIN(13, "VCCST_OVERRIDE"),
0292     PINCTRL_PIN(14, "C10_WAKE"),
0293     PINCTRL_PIN(15, "PROCHOTB"),
0294     PINCTRL_PIN(16, "CATERRB"),
0295     /* GPP_S */
0296     PINCTRL_PIN(17, "UFS_REF_CLK_0"),
0297     PINCTRL_PIN(18, "UFS_REF_CLK_1"),
0298     /* GPP_A */
0299     PINCTRL_PIN(19, "RGMII0_TXDATA_3"),
0300     PINCTRL_PIN(20, "RGMII0_TXDATA_2"),
0301     PINCTRL_PIN(21, "RGMII0_TXDATA_1"),
0302     PINCTRL_PIN(22, "RGMII0_TXDATA_0"),
0303     PINCTRL_PIN(23, "RGMII0_TXCLK"),
0304     PINCTRL_PIN(24, "RGMII0_TXCTL"),
0305     PINCTRL_PIN(25, "RGMII0_RXCLK"),
0306     PINCTRL_PIN(26, "RGMII0_RXDATA_3"),
0307     PINCTRL_PIN(27, "RGMII0_RXDATA_2"),
0308     PINCTRL_PIN(28, "RGMII0_RXDATA_1"),
0309     PINCTRL_PIN(29, "RGMII0_RXDATA_0"),
0310     PINCTRL_PIN(30, "RGMII1_TXDATA_3"),
0311     PINCTRL_PIN(31, "RGMII1_TXDATA_2"),
0312     PINCTRL_PIN(32, "RGMII1_TXDATA_1"),
0313     PINCTRL_PIN(33, "RGMII1_TXDATA_0"),
0314     PINCTRL_PIN(34, "RGMII1_TXCLK"),
0315     PINCTRL_PIN(35, "RGMII1_TXCTL"),
0316     PINCTRL_PIN(36, "RGMII1_RXCLK"),
0317     PINCTRL_PIN(37, "RGMII1_RXCTL"),
0318     PINCTRL_PIN(38, "RGMII1_RXDATA_3"),
0319     PINCTRL_PIN(39, "RGMII1_RXDATA_2"),
0320     PINCTRL_PIN(40, "RGMII1_RXDATA_1"),
0321     PINCTRL_PIN(41, "RGMII1_RXDATA_0"),
0322     PINCTRL_PIN(42, "RGMII0_RXCTL"),
0323     /* vGPIO_3 */
0324     PINCTRL_PIN(43, "ESPI_USB_OCB_0"),
0325     PINCTRL_PIN(44, "ESPI_USB_OCB_1"),
0326     PINCTRL_PIN(45, "ESPI_USB_OCB_2"),
0327     PINCTRL_PIN(46, "ESPI_USB_OCB_3"),
0328 };
0329
0330 static const struct intel_padgroup ehl_community3_gpps[] = {
0331     EHL_GPP(0, 0, 16),  /* CPU */
0332     EHL_GPP(1, 17, 18), /* GPP_S */
0333     EHL_GPP(2, 19, 42), /* GPP_A */
0334     EHL_GPP(3, 43, 46), /* vGPIO_3 */
0335 };
0336
0337 static const struct intel_community ehl_community3[] = {
0338     EHL_COMMUNITY(0, 46, ehl_community3_gpps),
0339 };
0340
0341 static const struct intel_pinctrl_soc_data ehl_community3_soc_data = {
0342     .uid = "3",
0343     .pins = ehl_community3_pins,
0344     .npins = ARRAY_SIZE(ehl_community3_pins),
0345     .communities = ehl_community3,
0346     .ncommunities = ARRAY_SIZE(ehl_community3),
0347 };
0348
0349 static const struct pinctrl_pin_desc ehl_community4_pins[] = {
0350     /* GPP_C */
0351     PINCTRL_PIN(0, "SMBCLK"),
0352     PINCTRL_PIN(1, "SMBDATA"),
0353     PINCTRL_PIN(2, "OSE_PWM0"),
0354     PINCTRL_PIN(3, "RGMII0_MDC"),
0355     PINCTRL_PIN(4, "RGMII0_MDIO"),
0356     PINCTRL_PIN(5, "OSE_PWM1"),
0357     PINCTRL_PIN(6, "RGMII1_MDC"),
0358     PINCTRL_PIN(7, "RGMII1_MDIO"),
0359     PINCTRL_PIN(8, "OSE_TGPIO4"),
0360     PINCTRL_PIN(9, "OSE_HSUART0_EN"),
0361     PINCTRL_PIN(10, "OSE_TGPIO5"),
0362     PINCTRL_PIN(11, "OSE_HSUART0_RE"),
0363     PINCTRL_PIN(12, "OSE_UART0_RXD"),
0364     PINCTRL_PIN(13, "OSE_UART0_TXD"),
0365     PINCTRL_PIN(14, "OSE_UART0_RTSB"),
0366     PINCTRL_PIN(15, "OSE_UART0_CTSB"),
0367     PINCTRL_PIN(16, "RGMII2_MDIO"),
0368     PINCTRL_PIN(17, "RGMII2_MDC"),
0369     PINCTRL_PIN(18, "OSE_I2C4_SDAT"),
0370     PINCTRL_PIN(19, "OSE_I2C4_SCLK"),
0371     PINCTRL_PIN(20, "OSE_UART4_RXD"),
0372     PINCTRL_PIN(21, "OSE_UART4_TXD"),
0373     PINCTRL_PIN(22, "OSE_UART4_RTSB"),
0374     PINCTRL_PIN(23, "OSE_UART4_CTSB"),
0375     /* GPP_F */
0376     PINCTRL_PIN(24, "CNV_BRI_DT"),
0377     PINCTRL_PIN(25, "CNV_BRI_RSP"),
0378     PINCTRL_PIN(26, "CNV_RGI_DT"),
0379     PINCTRL_PIN(27, "CNV_RGI_RSP"),
0380     PINCTRL_PIN(28, "CNV_RF_RESET_B"),
0381     PINCTRL_PIN(29, "EMMC_HIP_MON"),
0382     PINCTRL_PIN(30, "CNV_PA_BLANKING"),
0383     PINCTRL_PIN(31, "OSE_I2S1_SCLK"),
0384     PINCTRL_PIN(32, "I2S_MCLK2_INOUT"),
0385     PINCTRL_PIN(33, "BOOTMPC"),
0386     PINCTRL_PIN(34, "OSE_I2S1_SFRM"),
0387     PINCTRL_PIN(35, "GPPC_F_11"),
0388     PINCTRL_PIN(36, "GSXDOUT"),
0389     PINCTRL_PIN(37, "GSXSLOAD"),
0390     PINCTRL_PIN(38, "GSXDIN"),
0391     PINCTRL_PIN(39, "GSXSRESETB"),
0392     PINCTRL_PIN(40, "GSXCLK"),
0393     PINCTRL_PIN(41, "GPPC_F_17"),
0394     PINCTRL_PIN(42, "OSE_I2S1_TXD"),
0395     PINCTRL_PIN(43, "OSE_I2S1_RXD"),
0396     PINCTRL_PIN(44, "EXT_PWR_GATEB"),
0397     PINCTRL_PIN(45, "EXT_PWR_GATE2B"),
0398     PINCTRL_PIN(46, "VNN_CTRL"),
0399     PINCTRL_PIN(47, "V1P05_CTRL"),
0400     PINCTRL_PIN(48, "GPPF_CLK_LOOPBACK"),
0401     /* HVCMOS */
0402     PINCTRL_PIN(49, "L_BKLTEN"),
0403     PINCTRL_PIN(50, "L_BKLTCTL"),
0404     PINCTRL_PIN(51, "L_VDDEN"),
0405     PINCTRL_PIN(52, "SYS_PWROK"),
0406     PINCTRL_PIN(53, "SYS_RESETB"),
0407     PINCTRL_PIN(54, "MLK_RSTB"),
0408     /* GPP_E */
0409     PINCTRL_PIN(55, "SATA_LEDB"),
0410     PINCTRL_PIN(56, "GPPC_E_1"),
0411     PINCTRL_PIN(57, "GPPC_E_2"),
0412     PINCTRL_PIN(58, "DDSP_HPD_B"),
0413     PINCTRL_PIN(59, "SATA_DEVSLP_0"),
0414     PINCTRL_PIN(60, "DDPB_CTRLDATA"),
0415     PINCTRL_PIN(61, "GPPC_E_6"),
0416     PINCTRL_PIN(62, "DDPB_CTRLCLK"),
0417     PINCTRL_PIN(63, "GPPC_E_8"),
0418     PINCTRL_PIN(64, "USB2_OCB_0"),
0419     PINCTRL_PIN(65, "GPPC_E_10"),
0420     PINCTRL_PIN(66, "GPPC_E_11"),
0421     PINCTRL_PIN(67, "GPPC_E_12"),
0422     PINCTRL_PIN(68, "GPPC_E_13"),
0423     PINCTRL_PIN(69, "DDSP_HPD_A"),
0424     PINCTRL_PIN(70, "OSE_I2S0_RXD"),
0425     PINCTRL_PIN(71, "OSE_I2S0_TXD"),
0426     PINCTRL_PIN(72, "DDSP_HPD_C"),
0427     PINCTRL_PIN(73, "DDPA_CTRLDATA"),
0428     PINCTRL_PIN(74, "DDPA_CTRLCLK"),
0429     PINCTRL_PIN(75, "OSE_I2S0_SCLK"),
0430     PINCTRL_PIN(76, "OSE_I2S0_SFRM"),
0431     PINCTRL_PIN(77, "DDPC_CTRLDATA"),
0432     PINCTRL_PIN(78, "DDPC_CTRLCLK"),
0433     PINCTRL_PIN(79, "SPI1_CLK_LOOPBK"),
0434 };
0435
0436 static const struct intel_padgroup ehl_community4_gpps[] = {
0437     EHL_GPP(0, 0, 23),  /* GPP_C */
0438     EHL_GPP(1, 24, 48), /* GPP_F */
0439     EHL_GPP(2, 49, 54), /* HVCMOS */
0440     EHL_GPP(3, 55, 79), /* GPP_E */
0441 };
0442
0443 static const struct intel_community ehl_community4[] = {
0444     EHL_COMMUNITY(0, 79, ehl_community4_gpps),
0445 };
0446
0447 static const struct intel_pinctrl_soc_data ehl_community4_soc_data = {
0448     .uid = "4",
0449     .pins = ehl_community4_pins,
0450     .npins = ARRAY_SIZE(ehl_community4_pins),
0451     .communities = ehl_community4,
0452     .ncommunities = ARRAY_SIZE(ehl_community4),
0453 };
0454
0455 static const struct pinctrl_pin_desc ehl_community5_pins[] = {
0456     /* GPP_R */
0457     PINCTRL_PIN(0, "HDA_BCLK"),
0458     PINCTRL_PIN(1, "HDA_SYNC"),
0459     PINCTRL_PIN(2, "HDA_SDO"),
0460     PINCTRL_PIN(3, "HDA_SDI_0"),
0461     PINCTRL_PIN(4, "HDA_RSTB"),
0462     PINCTRL_PIN(5, "HDA_SDI_1"),
0463     PINCTRL_PIN(6, "GPP_R_6"),
0464     PINCTRL_PIN(7, "GPP_R_7"),
0465 };
0466
0467 static const struct intel_padgroup ehl_community5_gpps[] = {
0468     EHL_GPP(0, 0, 7),   /* GPP_R */
0469 };
0470
0471 static const struct intel_community ehl_community5[] = {
0472     EHL_COMMUNITY(0, 7, ehl_community5_gpps),
0473 };
0474
0475 static const struct intel_pinctrl_soc_data ehl_community5_soc_data = {
0476     .uid = "5",
0477     .pins = ehl_community5_pins,
0478     .npins = ARRAY_SIZE(ehl_community5_pins),
0479     .communities = ehl_community5,
0480     .ncommunities = ARRAY_SIZE(ehl_community5),
0481 };
0482
0483 static const struct intel_pinctrl_soc_data *ehl_soc_data_array[] = {
0484     &ehl_community0_soc_data,
0485     &ehl_community1_soc_data,
0486     &ehl_community3_soc_data,
0487     &ehl_community4_soc_data,
0488     &ehl_community5_soc_data,
0489     NULL
0490 };
0491
0492 static const struct acpi_device_id ehl_pinctrl_acpi_match[] = {
0493     { "INTC1020", (kernel_ulong_t)ehl_soc_data_array },
0494     { }
0495 };
0496 MODULE_DEVICE_TABLE(acpi, ehl_pinctrl_acpi_match);
0497
0498 static INTEL_PINCTRL_PM_OPS(ehl_pinctrl_pm_ops);
0499
0500 static struct platform_driver ehl_pinctrl_driver = {
0501     .probe = intel_pinctrl_probe_by_uid,
0502     .driver = {
0503         .name = "elkhartlake-pinctrl",
0504         .acpi_match_table = ehl_pinctrl_acpi_match,
0505         .pm = &ehl_pinctrl_pm_ops,
0506     },
0507 };
0508
0509 module_platform_driver(ehl_pinctrl_driver);
0510
0511 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
0512 MODULE_DESCRIPTION("Intel Elkhart Lake PCH pinctrl/GPIO driver");
0513 MODULE_LICENSE("GPL v2");