pinctrl/intel/pinctrl-denverton.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Intel Denverton SoC pinctrl/GPIO driver
0004  *
0005  * Copyright (C) 2017, Intel Corporation
0006  * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
0007  */
0008
0009 #include <linux/mod_devicetable.h>
0010 #include <linux/module.h>
0011 #include <linux/platform_device.h>
0012
0013 #include <linux/pinctrl/pinctrl.h>
0014
0015 #include "pinctrl-intel.h"
0016
0017 #define DNV_PAD_OWN 0x020
0018 #define DNV_PADCFGLOCK  0x090
0019 #define DNV_HOSTSW_OWN  0x0C0
0020 #define DNV_GPI_IS  0x100
0021 #define DNV_GPI_IE  0x120
0022
0023 #define DNV_GPP(n, s, e)                \
0024     {                       \
0025         .reg_num = (n),             \
0026         .base = (s),                \
0027         .size = ((e) - (s) + 1),        \
0028     }
0029
0030 #define DNV_COMMUNITY(b, s, e, g)           \
0031     {                       \
0032         .barno = (b),               \
0033         .padown_offset = DNV_PAD_OWN,       \
0034         .padcfglock_offset = DNV_PADCFGLOCK,    \
0035         .hostown_offset = DNV_HOSTSW_OWN,   \
0036         .is_offset = DNV_GPI_IS,        \
0037         .ie_offset = DNV_GPI_IE,        \
0038         .pin_base = (s),            \
0039         .npins = ((e) - (s) + 1),       \
0040         .gpps = (g),                \
0041         .ngpps = ARRAY_SIZE(g),         \
0042     }
0043
0044 /* Denverton */
0045 static const struct pinctrl_pin_desc dnv_pins[] = {
0046     /* North ALL */
0047     PINCTRL_PIN(0, "GBE0_SDP0"),
0048     PINCTRL_PIN(1, "GBE1_SDP0"),
0049     PINCTRL_PIN(2, "GBE0_SDP1"),
0050     PINCTRL_PIN(3, "GBE1_SDP1"),
0051     PINCTRL_PIN(4, "GBE0_SDP2"),
0052     PINCTRL_PIN(5, "GBE1_SDP2"),
0053     PINCTRL_PIN(6, "GBE0_SDP3"),
0054     PINCTRL_PIN(7, "GBE1_SDP3"),
0055     PINCTRL_PIN(8, "GBE2_LED0"),
0056     PINCTRL_PIN(9, "GBE2_LED1"),
0057     PINCTRL_PIN(10, "GBE0_I2C_CLK"),
0058     PINCTRL_PIN(11, "GBE0_I2C_DATA"),
0059     PINCTRL_PIN(12, "GBE1_I2C_CLK"),
0060     PINCTRL_PIN(13, "GBE1_I2C_DATA"),
0061     PINCTRL_PIN(14, "NCSI_RXD0"),
0062     PINCTRL_PIN(15, "NCSI_CLK_IN"),
0063     PINCTRL_PIN(16, "NCSI_RXD1"),
0064     PINCTRL_PIN(17, "NCSI_CRS_DV"),
0065     PINCTRL_PIN(18, "IDSLDO_VID_TICKLE"),
0066     PINCTRL_PIN(19, "NCSI_TX_EN"),
0067     PINCTRL_PIN(20, "NCSI_TXD0"),
0068     PINCTRL_PIN(21, "NCSI_TXD1"),
0069     PINCTRL_PIN(22, "NCSI_ARB_OUT"),
0070     PINCTRL_PIN(23, "GBE0_LED0"),
0071     PINCTRL_PIN(24, "GBE0_LED1"),
0072     PINCTRL_PIN(25, "GBE1_LED0"),
0073     PINCTRL_PIN(26, "GBE1_LED1"),
0074     PINCTRL_PIN(27, "SPARE_0"),
0075     PINCTRL_PIN(28, "PCIE_CLKREQ0_N"),
0076     PINCTRL_PIN(29, "PCIE_CLKREQ1_N"),
0077     PINCTRL_PIN(30, "PCIE_CLKREQ2_N"),
0078     PINCTRL_PIN(31, "PCIE_CLKREQ3_N"),
0079     PINCTRL_PIN(32, "PCIE_CLKREQ4_N"),
0080     PINCTRL_PIN(33, "GBE_MDC"),
0081     PINCTRL_PIN(34, "GBE_MDIO"),
0082     PINCTRL_PIN(35, "SVID_ALERT_N"),
0083     PINCTRL_PIN(36, "SVID_DATA"),
0084     PINCTRL_PIN(37, "SVID_CLK"),
0085     PINCTRL_PIN(38, "THERMTRIP_N"),
0086     PINCTRL_PIN(39, "PROCHOT_N"),
0087     PINCTRL_PIN(40, "MEMHOT_N"),
0088     /* South DFX */
0089     PINCTRL_PIN(41, "DFX_PORT_CLK0"),
0090     PINCTRL_PIN(42, "DFX_PORT_CLK1"),
0091     PINCTRL_PIN(43, "DFX_PORT0"),
0092     PINCTRL_PIN(44, "DFX_PORT1"),
0093     PINCTRL_PIN(45, "DFX_PORT2"),
0094     PINCTRL_PIN(46, "DFX_PORT3"),
0095     PINCTRL_PIN(47, "DFX_PORT4"),
0096     PINCTRL_PIN(48, "DFX_PORT5"),
0097     PINCTRL_PIN(49, "DFX_PORT6"),
0098     PINCTRL_PIN(50, "DFX_PORT7"),
0099     PINCTRL_PIN(51, "DFX_PORT8"),
0100     PINCTRL_PIN(52, "DFX_PORT9"),
0101     PINCTRL_PIN(53, "DFX_PORT10"),
0102     PINCTRL_PIN(54, "DFX_PORT11"),
0103     PINCTRL_PIN(55, "DFX_PORT12"),
0104     PINCTRL_PIN(56, "DFX_PORT13"),
0105     PINCTRL_PIN(57, "DFX_PORT14"),
0106     PINCTRL_PIN(58, "DFX_PORT15"),
0107     /* South GPP0 */
0108     PINCTRL_PIN(59, "SPI_TPM_CS_N"),
0109     PINCTRL_PIN(60, "UART2_CTS"),
0110     PINCTRL_PIN(61, "PCIE_CLKREQ5_N"),
0111     PINCTRL_PIN(62, "PCIE_CLKREQ6_N"),
0112     PINCTRL_PIN(63, "PCIE_CLKREQ7_N"),
0113     PINCTRL_PIN(64, "UART0_RXD"),
0114     PINCTRL_PIN(65, "UART0_TXD"),
0115     PINCTRL_PIN(66, "CPU_RESET_N"),
0116     PINCTRL_PIN(67, "NMI"),
0117     PINCTRL_PIN(68, "ERROR2_N"),
0118     PINCTRL_PIN(69, "ERROR1_N"),
0119     PINCTRL_PIN(70, "ERROR0_N"),
0120     PINCTRL_PIN(71, "IERR_N"),
0121     PINCTRL_PIN(72, "MCERR_N"),
0122     PINCTRL_PIN(73, "SMB0_LEG_CLK"),
0123     PINCTRL_PIN(74, "SMB0_LEG_DATA"),
0124     PINCTRL_PIN(75, "SMB0_LEG_ALRT_N"),
0125     PINCTRL_PIN(76, "SMB1_HOST_DATA"),
0126     PINCTRL_PIN(77, "SMB1_HOST_CLK"),
0127     PINCTRL_PIN(78, "SMB2_PECI_DATA"),
0128     PINCTRL_PIN(79, "SMB2_PECI_CLK"),
0129     PINCTRL_PIN(80, "SMB4_CSME0_DATA"),
0130     PINCTRL_PIN(81, "SMB4_CSME0_CLK"),
0131     PINCTRL_PIN(82, "SMB4_CSME0_ALRT_N"),
0132     PINCTRL_PIN(83, "USB_OC0_N"),
0133     PINCTRL_PIN(84, "FLEX_CLK_SE0"),
0134     PINCTRL_PIN(85, "FLEX_CLK_SE1"),
0135     PINCTRL_PIN(86, "SPARE_4"),
0136     PINCTRL_PIN(87, "SMB3_IE0_CLK"),
0137     PINCTRL_PIN(88, "SMB3_IE0_DATA"),
0138     PINCTRL_PIN(89, "SMB3_IE0_ALRT_N"),
0139     PINCTRL_PIN(90, "SATA0_LED_N"),
0140     PINCTRL_PIN(91, "SATA1_LED_N"),
0141     PINCTRL_PIN(92, "SATA_PDETECT0"),
0142     PINCTRL_PIN(93, "SATA_PDETECT1"),
0143     PINCTRL_PIN(94, "UART1_RTS"),
0144     PINCTRL_PIN(95, "UART1_CTS"),
0145     PINCTRL_PIN(96, "UART1_RXD"),
0146     PINCTRL_PIN(97, "UART1_TXD"),
0147     PINCTRL_PIN(98, "SPARE_8"),
0148     PINCTRL_PIN(99, "SPARE_9"),
0149     PINCTRL_PIN(100, "TCK"),
0150     PINCTRL_PIN(101, "TRST_N"),
0151     PINCTRL_PIN(102, "TMS"),
0152     PINCTRL_PIN(103, "TDI"),
0153     PINCTRL_PIN(104, "TDO"),
0154     PINCTRL_PIN(105, "CX_PRDY_N"),
0155     PINCTRL_PIN(106, "CX_PREQ_N"),
0156     PINCTRL_PIN(107, "TAP1_TCK"),
0157     PINCTRL_PIN(108, "TAP1_TRST_N"),
0158     PINCTRL_PIN(109, "TAP1_TMS"),
0159     PINCTRL_PIN(110, "TAP1_TDI"),
0160     PINCTRL_PIN(111, "TAP1_TDO"),
0161     /* South GPP1 */
0162     PINCTRL_PIN(112, "SUSPWRDNACK"),
0163     PINCTRL_PIN(113, "PMU_SUSCLK"),
0164     PINCTRL_PIN(114, "ADR_TRIGGER"),
0165     PINCTRL_PIN(115, "PMU_SLP_S45_N"),
0166     PINCTRL_PIN(116, "PMU_SLP_S3_N"),
0167     PINCTRL_PIN(117, "PMU_WAKE_N"),
0168     PINCTRL_PIN(118, "PMU_PWRBTN_N"),
0169     PINCTRL_PIN(119, "PMU_RESETBUTTON_N"),
0170     PINCTRL_PIN(120, "PMU_PLTRST_N"),
0171     PINCTRL_PIN(121, "SUS_STAT_N"),
0172     PINCTRL_PIN(122, "SLP_S0IX_N"),
0173     PINCTRL_PIN(123, "SPI_CS0_N"),
0174     PINCTRL_PIN(124, "SPI_CS1_N"),
0175     PINCTRL_PIN(125, "SPI_MOSI_IO0"),
0176     PINCTRL_PIN(126, "SPI_MISO_IO1"),
0177     PINCTRL_PIN(127, "SPI_IO2"),
0178     PINCTRL_PIN(128, "SPI_IO3"),
0179     PINCTRL_PIN(129, "SPI_CLK"),
0180     PINCTRL_PIN(130, "SPI_CLK_LOOPBK"),
0181     PINCTRL_PIN(131, "ESPI_IO0"),
0182     PINCTRL_PIN(132, "ESPI_IO1"),
0183     PINCTRL_PIN(133, "ESPI_IO2"),
0184     PINCTRL_PIN(134, "ESPI_IO3"),
0185     PINCTRL_PIN(135, "ESPI_CS0_N"),
0186     PINCTRL_PIN(136, "ESPI_CLK"),
0187     PINCTRL_PIN(137, "ESPI_RST_N"),
0188     PINCTRL_PIN(138, "ESPI_ALRT0_N"),
0189     PINCTRL_PIN(139, "ESPI_CS1_N"),
0190     PINCTRL_PIN(140, "ESPI_ALRT1_N"),
0191     PINCTRL_PIN(141, "ESPI_CLK_LOOPBK"),
0192     PINCTRL_PIN(142, "EMMC_CMD"),
0193     PINCTRL_PIN(143, "EMMC_STROBE"),
0194     PINCTRL_PIN(144, "EMMC_CLK"),
0195     PINCTRL_PIN(145, "EMMC_D0"),
0196     PINCTRL_PIN(146, "EMMC_D1"),
0197     PINCTRL_PIN(147, "EMMC_D2"),
0198     PINCTRL_PIN(148, "EMMC_D3"),
0199     PINCTRL_PIN(149, "EMMC_D4"),
0200     PINCTRL_PIN(150, "EMMC_D5"),
0201     PINCTRL_PIN(151, "EMMC_D6"),
0202     PINCTRL_PIN(152, "EMMC_D7"),
0203     PINCTRL_PIN(153, "SPARE_3"),
0204 };
0205
0206 static const unsigned int dnv_uart0_pins[] = { 60, 61, 64, 65 };
0207 static const unsigned int dnv_uart0_modes[] = { 2, 3, 1, 1 };
0208 static const unsigned int dnv_uart1_pins[] = { 94, 95, 96, 97 };
0209 static const unsigned int dnv_uart2_pins[] = { 60, 61, 62, 63 };
0210 static const unsigned int dnv_uart2_modes[] = { 1, 2, 2, 2 };
0211 static const unsigned int dnv_emmc_pins[] = {
0212     142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152,
0213 };
0214
0215 static const struct intel_pingroup dnv_groups[] = {
0216     PIN_GROUP("uart0_grp", dnv_uart0_pins, dnv_uart0_modes),
0217     PIN_GROUP("uart1_grp", dnv_uart1_pins, 1),
0218     PIN_GROUP("uart2_grp", dnv_uart2_pins, dnv_uart2_modes),
0219     PIN_GROUP("emmc_grp", dnv_emmc_pins, 1),
0220 };
0221
0222 static const char * const dnv_uart0_groups[] = { "uart0_grp" };
0223 static const char * const dnv_uart1_groups[] = { "uart1_grp" };
0224 static const char * const dnv_uart2_groups[] = { "uart2_grp" };
0225 static const char * const dnv_emmc_groups[] = { "emmc_grp" };
0226
0227 static const struct intel_function dnv_functions[] = {
0228     FUNCTION("uart0", dnv_uart0_groups),
0229     FUNCTION("uart1", dnv_uart1_groups),
0230     FUNCTION("uart2", dnv_uart2_groups),
0231     FUNCTION("emmc", dnv_emmc_groups),
0232 };
0233
0234 static const struct intel_padgroup dnv_north_gpps[] = {
0235     DNV_GPP(0, 0, 31),  /* North ALL_0 */
0236     DNV_GPP(1, 32, 40), /* North ALL_1 */
0237 };
0238
0239 static const struct intel_padgroup dnv_south_gpps[] = {
0240     DNV_GPP(0, 41, 58), /* South DFX */
0241     DNV_GPP(1, 59, 90), /* South GPP0_0 */
0242     DNV_GPP(2, 91, 111),    /* South GPP0_1 */
0243     DNV_GPP(3, 112, 143),   /* South GPP1_0 */
0244     DNV_GPP(4, 144, 153),   /* South GPP1_1 */
0245 };
0246
0247 static const struct intel_community dnv_communities[] = {
0248     DNV_COMMUNITY(0, 0, 40, dnv_north_gpps),
0249     DNV_COMMUNITY(1, 41, 153, dnv_south_gpps),
0250 };
0251
0252 static const struct intel_pinctrl_soc_data dnv_soc_data = {
0253     .pins = dnv_pins,
0254     .npins = ARRAY_SIZE(dnv_pins),
0255     .groups = dnv_groups,
0256     .ngroups = ARRAY_SIZE(dnv_groups),
0257     .functions = dnv_functions,
0258     .nfunctions = ARRAY_SIZE(dnv_functions),
0259     .communities = dnv_communities,
0260     .ncommunities = ARRAY_SIZE(dnv_communities),
0261 };
0262
0263 static INTEL_PINCTRL_PM_OPS(dnv_pinctrl_pm_ops);
0264
0265 static const struct acpi_device_id dnv_pinctrl_acpi_match[] = {
0266     { "INTC3000", (kernel_ulong_t)&dnv_soc_data },
0267     { }
0268 };
0269 MODULE_DEVICE_TABLE(acpi, dnv_pinctrl_acpi_match);
0270
0271 static struct platform_driver dnv_pinctrl_driver = {
0272     .probe = intel_pinctrl_probe_by_hid,
0273     .driver = {
0274         .name = "denverton-pinctrl",
0275         .acpi_match_table = dnv_pinctrl_acpi_match,
0276         .pm = &dnv_pinctrl_pm_ops,
0277     },
0278 };
0279
0280 static int __init dnv_pinctrl_init(void)
0281 {
0282     return platform_driver_register(&dnv_pinctrl_driver);
0283 }
0284 subsys_initcall(dnv_pinctrl_init);
0285
0286 static void __exit dnv_pinctrl_exit(void)
0287 {
0288     platform_driver_unregister(&dnv_pinctrl_driver);
0289 }
0290 module_exit(dnv_pinctrl_exit);
0291
0292 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
0293 MODULE_DESCRIPTION("Intel Denverton SoC pinctrl/GPIO driver");
0294 MODULE_LICENSE("GPL v2");