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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Cherryview/Braswell pinctrl driver
0004  *
0005  * Copyright (C) 2014, 2020 Intel Corporation
0006  * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
0007  *
0008  * This driver is based on the original Cherryview GPIO driver by
0009  *   Ning Li <ning.li@intel.com>
0010  *   Alan Cox <alan@linux.intel.com>
0011  */
0012 
0013 #include <linux/acpi.h>
0014 #include <linux/dmi.h>
0015 #include <linux/gpio/driver.h>
0016 #include <linux/kernel.h>
0017 #include <linux/module.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/types.h>
0020 
0021 #include <linux/pinctrl/pinctrl.h>
0022 #include <linux/pinctrl/pinmux.h>
0023 #include <linux/pinctrl/pinconf.h>
0024 #include <linux/pinctrl/pinconf-generic.h>
0025 
0026 #include "pinctrl-intel.h"
0027 
0028 #define CHV_INTSTAT         0x300
0029 #define CHV_INTMASK         0x380
0030 
0031 #define FAMILY_PAD_REGS_OFF     0x4400
0032 #define FAMILY_PAD_REGS_SIZE        0x400
0033 #define MAX_FAMILY_PAD_GPIO_NO      15
0034 #define GPIO_REGS_SIZE          8
0035 
0036 #define CHV_PADCTRL0            0x000
0037 #define CHV_PADCTRL0_INTSEL_SHIFT   28
0038 #define CHV_PADCTRL0_INTSEL_MASK    GENMASK(31, 28)
0039 #define CHV_PADCTRL0_TERM_UP        BIT(23)
0040 #define CHV_PADCTRL0_TERM_SHIFT     20
0041 #define CHV_PADCTRL0_TERM_MASK      GENMASK(22, 20)
0042 #define CHV_PADCTRL0_TERM_20K       1
0043 #define CHV_PADCTRL0_TERM_5K        2
0044 #define CHV_PADCTRL0_TERM_1K        4
0045 #define CHV_PADCTRL0_PMODE_SHIFT    16
0046 #define CHV_PADCTRL0_PMODE_MASK     GENMASK(19, 16)
0047 #define CHV_PADCTRL0_GPIOEN     BIT(15)
0048 #define CHV_PADCTRL0_GPIOCFG_SHIFT  8
0049 #define CHV_PADCTRL0_GPIOCFG_MASK   GENMASK(10, 8)
0050 #define CHV_PADCTRL0_GPIOCFG_GPIO   0
0051 #define CHV_PADCTRL0_GPIOCFG_GPO    1
0052 #define CHV_PADCTRL0_GPIOCFG_GPI    2
0053 #define CHV_PADCTRL0_GPIOCFG_HIZ    3
0054 #define CHV_PADCTRL0_GPIOTXSTATE    BIT(1)
0055 #define CHV_PADCTRL0_GPIORXSTATE    BIT(0)
0056 
0057 #define CHV_PADCTRL1            0x004
0058 #define CHV_PADCTRL1_CFGLOCK        BIT(31)
0059 #define CHV_PADCTRL1_INVRXTX_SHIFT  4
0060 #define CHV_PADCTRL1_INVRXTX_MASK   GENMASK(7, 4)
0061 #define CHV_PADCTRL1_INVRXTX_TXDATA BIT(7)
0062 #define CHV_PADCTRL1_INVRXTX_RXDATA BIT(6)
0063 #define CHV_PADCTRL1_INVRXTX_TXENABLE   BIT(5)
0064 #define CHV_PADCTRL1_ODEN       BIT(3)
0065 #define CHV_PADCTRL1_INTWAKECFG_MASK    GENMASK(2, 0)
0066 #define CHV_PADCTRL1_INTWAKECFG_FALLING 1
0067 #define CHV_PADCTRL1_INTWAKECFG_RISING  2
0068 #define CHV_PADCTRL1_INTWAKECFG_BOTH    3
0069 #define CHV_PADCTRL1_INTWAKECFG_LEVEL   4
0070 
0071 struct intel_pad_context {
0072     u32 padctrl0;
0073     u32 padctrl1;
0074 };
0075 
0076 #define CHV_INVALID_HWIRQ   ((unsigned int)INVALID_HWIRQ)
0077 
0078 /**
0079  * struct intel_community_context - community context for Cherryview
0080  * @intr_lines: Mapping between 16 HW interrupt wires and GPIO offset (in GPIO number space)
0081  * @saved_intmask: Interrupt mask saved for system sleep
0082  */
0083 struct intel_community_context {
0084     unsigned int intr_lines[16];
0085     u32 saved_intmask;
0086 };
0087 
0088 #define PINMODE_INVERT_OE   BIT(15)
0089 
0090 #define PINMODE(m, i)       ((m) | ((i) * PINMODE_INVERT_OE))
0091 
0092 #define CHV_GPP(start, end)         \
0093     {                   \
0094         .base = (start),        \
0095         .size = (end) - (start) + 1,    \
0096     }
0097 
0098 #define CHV_COMMUNITY(g, i, a)          \
0099     {                   \
0100         .gpps = (g),            \
0101         .ngpps = ARRAY_SIZE(g),     \
0102         .nirqs = (i),           \
0103         .acpi_space_id = (a),       \
0104     }
0105 
0106 static const struct pinctrl_pin_desc southwest_pins[] = {
0107     PINCTRL_PIN(0, "FST_SPI_D2"),
0108     PINCTRL_PIN(1, "FST_SPI_D0"),
0109     PINCTRL_PIN(2, "FST_SPI_CLK"),
0110     PINCTRL_PIN(3, "FST_SPI_D3"),
0111     PINCTRL_PIN(4, "FST_SPI_CS1_B"),
0112     PINCTRL_PIN(5, "FST_SPI_D1"),
0113     PINCTRL_PIN(6, "FST_SPI_CS0_B"),
0114     PINCTRL_PIN(7, "FST_SPI_CS2_B"),
0115 
0116     PINCTRL_PIN(15, "UART1_RTS_B"),
0117     PINCTRL_PIN(16, "UART1_RXD"),
0118     PINCTRL_PIN(17, "UART2_RXD"),
0119     PINCTRL_PIN(18, "UART1_CTS_B"),
0120     PINCTRL_PIN(19, "UART2_RTS_B"),
0121     PINCTRL_PIN(20, "UART1_TXD"),
0122     PINCTRL_PIN(21, "UART2_TXD"),
0123     PINCTRL_PIN(22, "UART2_CTS_B"),
0124 
0125     PINCTRL_PIN(30, "MF_HDA_CLK"),
0126     PINCTRL_PIN(31, "MF_HDA_RSTB"),
0127     PINCTRL_PIN(32, "MF_HDA_SDIO"),
0128     PINCTRL_PIN(33, "MF_HDA_SDO"),
0129     PINCTRL_PIN(34, "MF_HDA_DOCKRSTB"),
0130     PINCTRL_PIN(35, "MF_HDA_SYNC"),
0131     PINCTRL_PIN(36, "MF_HDA_SDI1"),
0132     PINCTRL_PIN(37, "MF_HDA_DOCKENB"),
0133 
0134     PINCTRL_PIN(45, "I2C5_SDA"),
0135     PINCTRL_PIN(46, "I2C4_SDA"),
0136     PINCTRL_PIN(47, "I2C6_SDA"),
0137     PINCTRL_PIN(48, "I2C5_SCL"),
0138     PINCTRL_PIN(49, "I2C_NFC_SDA"),
0139     PINCTRL_PIN(50, "I2C4_SCL"),
0140     PINCTRL_PIN(51, "I2C6_SCL"),
0141     PINCTRL_PIN(52, "I2C_NFC_SCL"),
0142 
0143     PINCTRL_PIN(60, "I2C1_SDA"),
0144     PINCTRL_PIN(61, "I2C0_SDA"),
0145     PINCTRL_PIN(62, "I2C2_SDA"),
0146     PINCTRL_PIN(63, "I2C1_SCL"),
0147     PINCTRL_PIN(64, "I2C3_SDA"),
0148     PINCTRL_PIN(65, "I2C0_SCL"),
0149     PINCTRL_PIN(66, "I2C2_SCL"),
0150     PINCTRL_PIN(67, "I2C3_SCL"),
0151 
0152     PINCTRL_PIN(75, "SATA_GP0"),
0153     PINCTRL_PIN(76, "SATA_GP1"),
0154     PINCTRL_PIN(77, "SATA_LEDN"),
0155     PINCTRL_PIN(78, "SATA_GP2"),
0156     PINCTRL_PIN(79, "MF_SMB_ALERTB"),
0157     PINCTRL_PIN(80, "SATA_GP3"),
0158     PINCTRL_PIN(81, "MF_SMB_CLK"),
0159     PINCTRL_PIN(82, "MF_SMB_DATA"),
0160 
0161     PINCTRL_PIN(90, "PCIE_CLKREQ0B"),
0162     PINCTRL_PIN(91, "PCIE_CLKREQ1B"),
0163     PINCTRL_PIN(92, "GP_SSP_2_CLK"),
0164     PINCTRL_PIN(93, "PCIE_CLKREQ2B"),
0165     PINCTRL_PIN(94, "GP_SSP_2_RXD"),
0166     PINCTRL_PIN(95, "PCIE_CLKREQ3B"),
0167     PINCTRL_PIN(96, "GP_SSP_2_FS"),
0168     PINCTRL_PIN(97, "GP_SSP_2_TXD"),
0169 };
0170 
0171 static const unsigned southwest_uart0_pins[] = { 16, 20 };
0172 static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 };
0173 static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 };
0174 static const unsigned southwest_i2c0_pins[] = { 61, 65 };
0175 static const unsigned southwest_hda_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37 };
0176 static const unsigned southwest_lpe_pins[] = {
0177     30, 31, 32, 33, 34, 35, 36, 37, 92, 94, 96, 97,
0178 };
0179 static const unsigned southwest_i2c1_pins[] = { 60, 63 };
0180 static const unsigned southwest_i2c2_pins[] = { 62, 66 };
0181 static const unsigned southwest_i2c3_pins[] = { 64, 67 };
0182 static const unsigned southwest_i2c4_pins[] = { 46, 50 };
0183 static const unsigned southwest_i2c5_pins[] = { 45, 48 };
0184 static const unsigned southwest_i2c6_pins[] = { 47, 51 };
0185 static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 };
0186 static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 };
0187 
0188 /* Some of LPE I2S TXD pins need to have OE inversion set */
0189 static const unsigned int southwest_lpe_altfuncs[] = {
0190     PINMODE(1, 1), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), /* 30, 31, 32, 33 */
0191     PINMODE(1, 1), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), /* 34, 35, 36, 37 */
0192     PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 1), /* 92, 94, 96, 97 */
0193 };
0194 
0195 /*
0196  * Two spi3 chipselects are available in different mode than the main spi3
0197  * functionality, which is using mode 2.
0198  */
0199 static const unsigned int southwest_spi3_altfuncs[] = {
0200     PINMODE(3, 0), PINMODE(2, 0), PINMODE(3, 0), PINMODE(2, 0), /* 76, 79, 80, 81 */
0201     PINMODE(2, 0),                          /* 82 */
0202 };
0203 
0204 static const struct intel_pingroup southwest_groups[] = {
0205     PIN_GROUP("uart0_grp", southwest_uart0_pins, PINMODE(2, 0)),
0206     PIN_GROUP("uart1_grp", southwest_uart1_pins, PINMODE(1, 0)),
0207     PIN_GROUP("uart2_grp", southwest_uart2_pins, PINMODE(1, 0)),
0208     PIN_GROUP("hda_grp", southwest_hda_pins, PINMODE(2, 0)),
0209     PIN_GROUP("i2c0_grp", southwest_i2c0_pins, PINMODE(1, 1)),
0210     PIN_GROUP("i2c1_grp", southwest_i2c1_pins, PINMODE(1, 1)),
0211     PIN_GROUP("i2c2_grp", southwest_i2c2_pins, PINMODE(1, 1)),
0212     PIN_GROUP("i2c3_grp", southwest_i2c3_pins, PINMODE(1, 1)),
0213     PIN_GROUP("i2c4_grp", southwest_i2c4_pins, PINMODE(1, 1)),
0214     PIN_GROUP("i2c5_grp", southwest_i2c5_pins, PINMODE(1, 1)),
0215     PIN_GROUP("i2c6_grp", southwest_i2c6_pins, PINMODE(1, 1)),
0216     PIN_GROUP("i2c_nfc_grp", southwest_i2c_nfc_pins, PINMODE(2, 1)),
0217     PIN_GROUP("lpe_grp", southwest_lpe_pins, southwest_lpe_altfuncs),
0218     PIN_GROUP("spi3_grp", southwest_spi3_pins, southwest_spi3_altfuncs),
0219 };
0220 
0221 static const char * const southwest_uart0_groups[] = { "uart0_grp" };
0222 static const char * const southwest_uart1_groups[] = { "uart1_grp" };
0223 static const char * const southwest_uart2_groups[] = { "uart2_grp" };
0224 static const char * const southwest_hda_groups[] = { "hda_grp" };
0225 static const char * const southwest_lpe_groups[] = { "lpe_grp" };
0226 static const char * const southwest_i2c0_groups[] = { "i2c0_grp" };
0227 static const char * const southwest_i2c1_groups[] = { "i2c1_grp" };
0228 static const char * const southwest_i2c2_groups[] = { "i2c2_grp" };
0229 static const char * const southwest_i2c3_groups[] = { "i2c3_grp" };
0230 static const char * const southwest_i2c4_groups[] = { "i2c4_grp" };
0231 static const char * const southwest_i2c5_groups[] = { "i2c5_grp" };
0232 static const char * const southwest_i2c6_groups[] = { "i2c6_grp" };
0233 static const char * const southwest_i2c_nfc_groups[] = { "i2c_nfc_grp" };
0234 static const char * const southwest_spi3_groups[] = { "spi3_grp" };
0235 
0236 /*
0237  * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are
0238  * enabled only as GPIOs.
0239  */
0240 static const struct intel_function southwest_functions[] = {
0241     FUNCTION("uart0", southwest_uart0_groups),
0242     FUNCTION("uart1", southwest_uart1_groups),
0243     FUNCTION("uart2", southwest_uart2_groups),
0244     FUNCTION("hda", southwest_hda_groups),
0245     FUNCTION("lpe", southwest_lpe_groups),
0246     FUNCTION("i2c0", southwest_i2c0_groups),
0247     FUNCTION("i2c1", southwest_i2c1_groups),
0248     FUNCTION("i2c2", southwest_i2c2_groups),
0249     FUNCTION("i2c3", southwest_i2c3_groups),
0250     FUNCTION("i2c4", southwest_i2c4_groups),
0251     FUNCTION("i2c5", southwest_i2c5_groups),
0252     FUNCTION("i2c6", southwest_i2c6_groups),
0253     FUNCTION("i2c_nfc", southwest_i2c_nfc_groups),
0254     FUNCTION("spi3", southwest_spi3_groups),
0255 };
0256 
0257 static const struct intel_padgroup southwest_gpps[] = {
0258     CHV_GPP(0, 7),
0259     CHV_GPP(15, 22),
0260     CHV_GPP(30, 37),
0261     CHV_GPP(45, 52),
0262     CHV_GPP(60, 67),
0263     CHV_GPP(75, 82),
0264     CHV_GPP(90, 97),
0265 };
0266 
0267 /*
0268  * Southwest community can generate GPIO interrupts only for the first 8
0269  * interrupts. The upper half (8-15) can only be used to trigger GPEs.
0270  */
0271 static const struct intel_community southwest_communities[] = {
0272     CHV_COMMUNITY(southwest_gpps, 8, 0x91),
0273 };
0274 
0275 static const struct intel_pinctrl_soc_data southwest_soc_data = {
0276     .uid = "1",
0277     .pins = southwest_pins,
0278     .npins = ARRAY_SIZE(southwest_pins),
0279     .groups = southwest_groups,
0280     .ngroups = ARRAY_SIZE(southwest_groups),
0281     .functions = southwest_functions,
0282     .nfunctions = ARRAY_SIZE(southwest_functions),
0283     .communities = southwest_communities,
0284     .ncommunities = ARRAY_SIZE(southwest_communities),
0285 };
0286 
0287 static const struct pinctrl_pin_desc north_pins[] = {
0288     PINCTRL_PIN(0, "GPIO_DFX_0"),
0289     PINCTRL_PIN(1, "GPIO_DFX_3"),
0290     PINCTRL_PIN(2, "GPIO_DFX_7"),
0291     PINCTRL_PIN(3, "GPIO_DFX_1"),
0292     PINCTRL_PIN(4, "GPIO_DFX_5"),
0293     PINCTRL_PIN(5, "GPIO_DFX_4"),
0294     PINCTRL_PIN(6, "GPIO_DFX_8"),
0295     PINCTRL_PIN(7, "GPIO_DFX_2"),
0296     PINCTRL_PIN(8, "GPIO_DFX_6"),
0297 
0298     PINCTRL_PIN(15, "GPIO_SUS0"),
0299     PINCTRL_PIN(16, "SEC_GPIO_SUS10"),
0300     PINCTRL_PIN(17, "GPIO_SUS3"),
0301     PINCTRL_PIN(18, "GPIO_SUS7"),
0302     PINCTRL_PIN(19, "GPIO_SUS1"),
0303     PINCTRL_PIN(20, "GPIO_SUS5"),
0304     PINCTRL_PIN(21, "SEC_GPIO_SUS11"),
0305     PINCTRL_PIN(22, "GPIO_SUS4"),
0306     PINCTRL_PIN(23, "SEC_GPIO_SUS8"),
0307     PINCTRL_PIN(24, "GPIO_SUS2"),
0308     PINCTRL_PIN(25, "GPIO_SUS6"),
0309     PINCTRL_PIN(26, "CX_PREQ_B"),
0310     PINCTRL_PIN(27, "SEC_GPIO_SUS9"),
0311 
0312     PINCTRL_PIN(30, "TRST_B"),
0313     PINCTRL_PIN(31, "TCK"),
0314     PINCTRL_PIN(32, "PROCHOT_B"),
0315     PINCTRL_PIN(33, "SVIDO_DATA"),
0316     PINCTRL_PIN(34, "TMS"),
0317     PINCTRL_PIN(35, "CX_PRDY_B_2"),
0318     PINCTRL_PIN(36, "TDO_2"),
0319     PINCTRL_PIN(37, "CX_PRDY_B"),
0320     PINCTRL_PIN(38, "SVIDO_ALERT_B"),
0321     PINCTRL_PIN(39, "TDO"),
0322     PINCTRL_PIN(40, "SVIDO_CLK"),
0323     PINCTRL_PIN(41, "TDI"),
0324 
0325     PINCTRL_PIN(45, "GP_CAMERASB_05"),
0326     PINCTRL_PIN(46, "GP_CAMERASB_02"),
0327     PINCTRL_PIN(47, "GP_CAMERASB_08"),
0328     PINCTRL_PIN(48, "GP_CAMERASB_00"),
0329     PINCTRL_PIN(49, "GP_CAMERASB_06"),
0330     PINCTRL_PIN(50, "GP_CAMERASB_10"),
0331     PINCTRL_PIN(51, "GP_CAMERASB_03"),
0332     PINCTRL_PIN(52, "GP_CAMERASB_09"),
0333     PINCTRL_PIN(53, "GP_CAMERASB_01"),
0334     PINCTRL_PIN(54, "GP_CAMERASB_07"),
0335     PINCTRL_PIN(55, "GP_CAMERASB_11"),
0336     PINCTRL_PIN(56, "GP_CAMERASB_04"),
0337 
0338     PINCTRL_PIN(60, "PANEL0_BKLTEN"),
0339     PINCTRL_PIN(61, "HV_DDI0_HPD"),
0340     PINCTRL_PIN(62, "HV_DDI2_DDC_SDA"),
0341     PINCTRL_PIN(63, "PANEL1_BKLTCTL"),
0342     PINCTRL_PIN(64, "HV_DDI1_HPD"),
0343     PINCTRL_PIN(65, "PANEL0_BKLTCTL"),
0344     PINCTRL_PIN(66, "HV_DDI0_DDC_SDA"),
0345     PINCTRL_PIN(67, "HV_DDI2_DDC_SCL"),
0346     PINCTRL_PIN(68, "HV_DDI2_HPD"),
0347     PINCTRL_PIN(69, "PANEL1_VDDEN"),
0348     PINCTRL_PIN(70, "PANEL1_BKLTEN"),
0349     PINCTRL_PIN(71, "HV_DDI0_DDC_SCL"),
0350     PINCTRL_PIN(72, "PANEL0_VDDEN"),
0351 };
0352 
0353 static const struct intel_padgroup north_gpps[] = {
0354     CHV_GPP(0, 8),
0355     CHV_GPP(15, 27),
0356     CHV_GPP(30, 41),
0357     CHV_GPP(45, 56),
0358     CHV_GPP(60, 72),
0359 };
0360 
0361 /*
0362  * North community can generate GPIO interrupts only for the first 8
0363  * interrupts. The upper half (8-15) can only be used to trigger GPEs.
0364  */
0365 static const struct intel_community north_communities[] = {
0366     CHV_COMMUNITY(north_gpps, 8, 0x92),
0367 };
0368 
0369 static const struct intel_pinctrl_soc_data north_soc_data = {
0370     .uid = "2",
0371     .pins = north_pins,
0372     .npins = ARRAY_SIZE(north_pins),
0373     .communities = north_communities,
0374     .ncommunities = ARRAY_SIZE(north_communities),
0375 };
0376 
0377 static const struct pinctrl_pin_desc east_pins[] = {
0378     PINCTRL_PIN(0, "PMU_SLP_S3_B"),
0379     PINCTRL_PIN(1, "PMU_BATLOW_B"),
0380     PINCTRL_PIN(2, "SUS_STAT_B"),
0381     PINCTRL_PIN(3, "PMU_SLP_S0IX_B"),
0382     PINCTRL_PIN(4, "PMU_AC_PRESENT"),
0383     PINCTRL_PIN(5, "PMU_PLTRST_B"),
0384     PINCTRL_PIN(6, "PMU_SUSCLK"),
0385     PINCTRL_PIN(7, "PMU_SLP_LAN_B"),
0386     PINCTRL_PIN(8, "PMU_PWRBTN_B"),
0387     PINCTRL_PIN(9, "PMU_SLP_S4_B"),
0388     PINCTRL_PIN(10, "PMU_WAKE_B"),
0389     PINCTRL_PIN(11, "PMU_WAKE_LAN_B"),
0390 
0391     PINCTRL_PIN(15, "MF_ISH_GPIO_3"),
0392     PINCTRL_PIN(16, "MF_ISH_GPIO_7"),
0393     PINCTRL_PIN(17, "MF_ISH_I2C1_SCL"),
0394     PINCTRL_PIN(18, "MF_ISH_GPIO_1"),
0395     PINCTRL_PIN(19, "MF_ISH_GPIO_5"),
0396     PINCTRL_PIN(20, "MF_ISH_GPIO_9"),
0397     PINCTRL_PIN(21, "MF_ISH_GPIO_0"),
0398     PINCTRL_PIN(22, "MF_ISH_GPIO_4"),
0399     PINCTRL_PIN(23, "MF_ISH_GPIO_8"),
0400     PINCTRL_PIN(24, "MF_ISH_GPIO_2"),
0401     PINCTRL_PIN(25, "MF_ISH_GPIO_6"),
0402     PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"),
0403 };
0404 
0405 static const struct intel_padgroup east_gpps[] = {
0406     CHV_GPP(0, 11),
0407     CHV_GPP(15, 26),
0408 };
0409 
0410 static const struct intel_community east_communities[] = {
0411     CHV_COMMUNITY(east_gpps, 16, 0x93),
0412 };
0413 
0414 static const struct intel_pinctrl_soc_data east_soc_data = {
0415     .uid = "3",
0416     .pins = east_pins,
0417     .npins = ARRAY_SIZE(east_pins),
0418     .communities = east_communities,
0419     .ncommunities = ARRAY_SIZE(east_communities),
0420 };
0421 
0422 static const struct pinctrl_pin_desc southeast_pins[] = {
0423     PINCTRL_PIN(0, "MF_PLT_CLK0"),
0424     PINCTRL_PIN(1, "PWM1"),
0425     PINCTRL_PIN(2, "MF_PLT_CLK1"),
0426     PINCTRL_PIN(3, "MF_PLT_CLK4"),
0427     PINCTRL_PIN(4, "MF_PLT_CLK3"),
0428     PINCTRL_PIN(5, "PWM0"),
0429     PINCTRL_PIN(6, "MF_PLT_CLK5"),
0430     PINCTRL_PIN(7, "MF_PLT_CLK2"),
0431 
0432     PINCTRL_PIN(15, "SDMMC2_D3_CD_B"),
0433     PINCTRL_PIN(16, "SDMMC1_CLK"),
0434     PINCTRL_PIN(17, "SDMMC1_D0"),
0435     PINCTRL_PIN(18, "SDMMC2_D1"),
0436     PINCTRL_PIN(19, "SDMMC2_CLK"),
0437     PINCTRL_PIN(20, "SDMMC1_D2"),
0438     PINCTRL_PIN(21, "SDMMC2_D2"),
0439     PINCTRL_PIN(22, "SDMMC2_CMD"),
0440     PINCTRL_PIN(23, "SDMMC1_CMD"),
0441     PINCTRL_PIN(24, "SDMMC1_D1"),
0442     PINCTRL_PIN(25, "SDMMC2_D0"),
0443     PINCTRL_PIN(26, "SDMMC1_D3_CD_B"),
0444 
0445     PINCTRL_PIN(30, "SDMMC3_D1"),
0446     PINCTRL_PIN(31, "SDMMC3_CLK"),
0447     PINCTRL_PIN(32, "SDMMC3_D3"),
0448     PINCTRL_PIN(33, "SDMMC3_D2"),
0449     PINCTRL_PIN(34, "SDMMC3_CMD"),
0450     PINCTRL_PIN(35, "SDMMC3_D0"),
0451 
0452     PINCTRL_PIN(45, "MF_LPC_AD2"),
0453     PINCTRL_PIN(46, "LPC_CLKRUNB"),
0454     PINCTRL_PIN(47, "MF_LPC_AD0"),
0455     PINCTRL_PIN(48, "LPC_FRAMEB"),
0456     PINCTRL_PIN(49, "MF_LPC_CLKOUT1"),
0457     PINCTRL_PIN(50, "MF_LPC_AD3"),
0458     PINCTRL_PIN(51, "MF_LPC_CLKOUT0"),
0459     PINCTRL_PIN(52, "MF_LPC_AD1"),
0460 
0461     PINCTRL_PIN(60, "SPI1_MISO"),
0462     PINCTRL_PIN(61, "SPI1_CSO_B"),
0463     PINCTRL_PIN(62, "SPI1_CLK"),
0464     PINCTRL_PIN(63, "MMC1_D6"),
0465     PINCTRL_PIN(64, "SPI1_MOSI"),
0466     PINCTRL_PIN(65, "MMC1_D5"),
0467     PINCTRL_PIN(66, "SPI1_CS1_B"),
0468     PINCTRL_PIN(67, "MMC1_D4_SD_WE"),
0469     PINCTRL_PIN(68, "MMC1_D7"),
0470     PINCTRL_PIN(69, "MMC1_RCLK"),
0471 
0472     PINCTRL_PIN(75, "USB_OC1_B"),
0473     PINCTRL_PIN(76, "PMU_RESETBUTTON_B"),
0474     PINCTRL_PIN(77, "GPIO_ALERT"),
0475     PINCTRL_PIN(78, "SDMMC3_PWR_EN_B"),
0476     PINCTRL_PIN(79, "ILB_SERIRQ"),
0477     PINCTRL_PIN(80, "USB_OC0_B"),
0478     PINCTRL_PIN(81, "SDMMC3_CD_B"),
0479     PINCTRL_PIN(82, "SPKR"),
0480     PINCTRL_PIN(83, "SUSPWRDNACK"),
0481     PINCTRL_PIN(84, "SPARE_PIN"),
0482     PINCTRL_PIN(85, "SDMMC3_1P8_EN"),
0483 };
0484 
0485 static const unsigned southeast_pwm0_pins[] = { 5 };
0486 static const unsigned southeast_pwm1_pins[] = { 1 };
0487 static const unsigned southeast_sdmmc1_pins[] = {
0488     16, 17, 20, 23, 24, 26, 63, 65, 67, 68, 69,
0489 };
0490 static const unsigned southeast_sdmmc2_pins[] = { 15, 18, 19, 21, 22, 25 };
0491 static const unsigned southeast_sdmmc3_pins[] = {
0492     30, 31, 32, 33, 34, 35, 78, 81, 85,
0493 };
0494 static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 };
0495 static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 };
0496 
0497 static const struct intel_pingroup southeast_groups[] = {
0498     PIN_GROUP("pwm0_grp", southeast_pwm0_pins, PINMODE(1, 0)),
0499     PIN_GROUP("pwm1_grp", southeast_pwm1_pins, PINMODE(1, 0)),
0500     PIN_GROUP("sdmmc1_grp", southeast_sdmmc1_pins, PINMODE(1, 0)),
0501     PIN_GROUP("sdmmc2_grp", southeast_sdmmc2_pins, PINMODE(1, 0)),
0502     PIN_GROUP("sdmmc3_grp", southeast_sdmmc3_pins, PINMODE(1, 0)),
0503     PIN_GROUP("spi1_grp", southeast_spi1_pins, PINMODE(1, 0)),
0504     PIN_GROUP("spi2_grp", southeast_spi2_pins, PINMODE(4, 0)),
0505 };
0506 
0507 static const char * const southeast_pwm0_groups[] = { "pwm0_grp" };
0508 static const char * const southeast_pwm1_groups[] = { "pwm1_grp" };
0509 static const char * const southeast_sdmmc1_groups[] = { "sdmmc1_grp" };
0510 static const char * const southeast_sdmmc2_groups[] = { "sdmmc2_grp" };
0511 static const char * const southeast_sdmmc3_groups[] = { "sdmmc3_grp" };
0512 static const char * const southeast_spi1_groups[] = { "spi1_grp" };
0513 static const char * const southeast_spi2_groups[] = { "spi2_grp" };
0514 
0515 static const struct intel_function southeast_functions[] = {
0516     FUNCTION("pwm0", southeast_pwm0_groups),
0517     FUNCTION("pwm1", southeast_pwm1_groups),
0518     FUNCTION("sdmmc1", southeast_sdmmc1_groups),
0519     FUNCTION("sdmmc2", southeast_sdmmc2_groups),
0520     FUNCTION("sdmmc3", southeast_sdmmc3_groups),
0521     FUNCTION("spi1", southeast_spi1_groups),
0522     FUNCTION("spi2", southeast_spi2_groups),
0523 };
0524 
0525 static const struct intel_padgroup southeast_gpps[] = {
0526     CHV_GPP(0, 7),
0527     CHV_GPP(15, 26),
0528     CHV_GPP(30, 35),
0529     CHV_GPP(45, 52),
0530     CHV_GPP(60, 69),
0531     CHV_GPP(75, 85),
0532 };
0533 
0534 static const struct intel_community southeast_communities[] = {
0535     CHV_COMMUNITY(southeast_gpps, 16, 0x94),
0536 };
0537 
0538 static const struct intel_pinctrl_soc_data southeast_soc_data = {
0539     .uid = "4",
0540     .pins = southeast_pins,
0541     .npins = ARRAY_SIZE(southeast_pins),
0542     .groups = southeast_groups,
0543     .ngroups = ARRAY_SIZE(southeast_groups),
0544     .functions = southeast_functions,
0545     .nfunctions = ARRAY_SIZE(southeast_functions),
0546     .communities = southeast_communities,
0547     .ncommunities = ARRAY_SIZE(southeast_communities),
0548 };
0549 
0550 static const struct intel_pinctrl_soc_data *chv_soc_data[] = {
0551     &southwest_soc_data,
0552     &north_soc_data,
0553     &east_soc_data,
0554     &southeast_soc_data,
0555     NULL
0556 };
0557 
0558 /*
0559  * Lock to serialize register accesses
0560  *
0561  * Due to a silicon issue, a shared lock must be used to prevent
0562  * concurrent accesses across the 4 GPIO controllers.
0563  *
0564  * See Intel Atom Z8000 Processor Series Specification Update (Rev. 005),
0565  * errata #CHT34, for further information.
0566  */
0567 static DEFINE_RAW_SPINLOCK(chv_lock);
0568 
0569 static u32 chv_pctrl_readl(struct intel_pinctrl *pctrl, unsigned int offset)
0570 {
0571     const struct intel_community *community = &pctrl->communities[0];
0572 
0573     return readl(community->regs + offset);
0574 }
0575 
0576 static void chv_pctrl_writel(struct intel_pinctrl *pctrl, unsigned int offset, u32 value)
0577 {
0578     const struct intel_community *community = &pctrl->communities[0];
0579     void __iomem *reg = community->regs + offset;
0580 
0581     /* Write and simple read back to confirm the bus transferring done */
0582     writel(value, reg);
0583     readl(reg);
0584 }
0585 
0586 static void __iomem *chv_padreg(struct intel_pinctrl *pctrl, unsigned int offset,
0587                 unsigned int reg)
0588 {
0589     const struct intel_community *community = &pctrl->communities[0];
0590     unsigned int family_no = offset / MAX_FAMILY_PAD_GPIO_NO;
0591     unsigned int pad_no = offset % MAX_FAMILY_PAD_GPIO_NO;
0592 
0593     offset = FAMILY_PAD_REGS_SIZE * family_no + GPIO_REGS_SIZE * pad_no;
0594 
0595     return community->pad_regs + offset + reg;
0596 }
0597 
0598 static u32 chv_readl(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int offset)
0599 {
0600     return readl(chv_padreg(pctrl, pin, offset));
0601 }
0602 
0603 static void chv_writel(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int offset, u32 value)
0604 {
0605     void __iomem *reg = chv_padreg(pctrl, pin, offset);
0606 
0607     /* Write and simple read back to confirm the bus transferring done */
0608     writel(value, reg);
0609     readl(reg);
0610 }
0611 
0612 /* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */
0613 static bool chv_pad_locked(struct intel_pinctrl *pctrl, unsigned int offset)
0614 {
0615     return chv_readl(pctrl, offset, CHV_PADCTRL1) & CHV_PADCTRL1_CFGLOCK;
0616 }
0617 
0618 static int chv_get_groups_count(struct pinctrl_dev *pctldev)
0619 {
0620     struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0621 
0622     return pctrl->soc->ngroups;
0623 }
0624 
0625 static const char *chv_get_group_name(struct pinctrl_dev *pctldev,
0626                       unsigned int group)
0627 {
0628     struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0629 
0630     return pctrl->soc->groups[group].grp.name;
0631 }
0632 
0633 static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
0634                   const unsigned int **pins, unsigned int *npins)
0635 {
0636     struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0637 
0638     *pins = pctrl->soc->groups[group].grp.pins;
0639     *npins = pctrl->soc->groups[group].grp.npins;
0640     return 0;
0641 }
0642 
0643 static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
0644                  unsigned int offset)
0645 {
0646     struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0647     unsigned long flags;
0648     u32 ctrl0, ctrl1;
0649     bool locked;
0650 
0651     raw_spin_lock_irqsave(&chv_lock, flags);
0652 
0653     ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
0654     ctrl1 = chv_readl(pctrl, offset, CHV_PADCTRL1);
0655     locked = chv_pad_locked(pctrl, offset);
0656 
0657     raw_spin_unlock_irqrestore(&chv_lock, flags);
0658 
0659     if (ctrl0 & CHV_PADCTRL0_GPIOEN) {
0660         seq_puts(s, "GPIO ");
0661     } else {
0662         u32 mode;
0663 
0664         mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK;
0665         mode >>= CHV_PADCTRL0_PMODE_SHIFT;
0666 
0667         seq_printf(s, "mode %d ", mode);
0668     }
0669 
0670     seq_printf(s, "0x%08x 0x%08x", ctrl0, ctrl1);
0671 
0672     if (locked)
0673         seq_puts(s, " [LOCKED]");
0674 }
0675 
0676 static const struct pinctrl_ops chv_pinctrl_ops = {
0677     .get_groups_count = chv_get_groups_count,
0678     .get_group_name = chv_get_group_name,
0679     .get_group_pins = chv_get_group_pins,
0680     .pin_dbg_show = chv_pin_dbg_show,
0681 };
0682 
0683 static int chv_get_functions_count(struct pinctrl_dev *pctldev)
0684 {
0685     struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0686 
0687     return pctrl->soc->nfunctions;
0688 }
0689 
0690 static const char *chv_get_function_name(struct pinctrl_dev *pctldev,
0691                      unsigned int function)
0692 {
0693     struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0694 
0695     return pctrl->soc->functions[function].name;
0696 }
0697 
0698 static int chv_get_function_groups(struct pinctrl_dev *pctldev,
0699                    unsigned int function,
0700                    const char * const **groups,
0701                    unsigned int * const ngroups)
0702 {
0703     struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0704 
0705     *groups = pctrl->soc->functions[function].groups;
0706     *ngroups = pctrl->soc->functions[function].ngroups;
0707     return 0;
0708 }
0709 
0710 static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev,
0711                   unsigned int function, unsigned int group)
0712 {
0713     struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0714     struct device *dev = pctrl->dev;
0715     const struct intel_pingroup *grp;
0716     unsigned long flags;
0717     int i;
0718 
0719     grp = &pctrl->soc->groups[group];
0720 
0721     raw_spin_lock_irqsave(&chv_lock, flags);
0722 
0723     /* Check first that the pad is not locked */
0724     for (i = 0; i < grp->grp.npins; i++) {
0725         if (chv_pad_locked(pctrl, grp->grp.pins[i])) {
0726             raw_spin_unlock_irqrestore(&chv_lock, flags);
0727             dev_warn(dev, "unable to set mode for locked pin %u\n", grp->grp.pins[i]);
0728             return -EBUSY;
0729         }
0730     }
0731 
0732     for (i = 0; i < grp->grp.npins; i++) {
0733         int pin = grp->grp.pins[i];
0734         unsigned int mode;
0735         bool invert_oe;
0736         u32 value;
0737 
0738         /* Check if there is pin-specific config */
0739         if (grp->modes)
0740             mode = grp->modes[i];
0741         else
0742             mode = grp->mode;
0743 
0744         /* Extract OE inversion */
0745         invert_oe = mode & PINMODE_INVERT_OE;
0746         mode &= ~PINMODE_INVERT_OE;
0747 
0748         value = chv_readl(pctrl, pin, CHV_PADCTRL0);
0749         /* Disable GPIO mode */
0750         value &= ~CHV_PADCTRL0_GPIOEN;
0751         /* Set to desired mode */
0752         value &= ~CHV_PADCTRL0_PMODE_MASK;
0753         value |= mode << CHV_PADCTRL0_PMODE_SHIFT;
0754         chv_writel(pctrl, pin, CHV_PADCTRL0, value);
0755 
0756         /* Update for invert_oe */
0757         value = chv_readl(pctrl, pin, CHV_PADCTRL1) & ~CHV_PADCTRL1_INVRXTX_MASK;
0758         if (invert_oe)
0759             value |= CHV_PADCTRL1_INVRXTX_TXENABLE;
0760         chv_writel(pctrl, pin, CHV_PADCTRL1, value);
0761 
0762         dev_dbg(dev, "configured pin %u mode %u OE %sinverted\n", pin, mode,
0763             invert_oe ? "" : "not ");
0764     }
0765 
0766     raw_spin_unlock_irqrestore(&chv_lock, flags);
0767 
0768     return 0;
0769 }
0770 
0771 static void chv_gpio_clear_triggering(struct intel_pinctrl *pctrl,
0772                       unsigned int offset)
0773 {
0774     u32 invrxtx_mask = CHV_PADCTRL1_INVRXTX_MASK;
0775     u32 value;
0776 
0777     /*
0778      * One some devices the GPIO should output the inverted value from what
0779      * device-drivers / ACPI code expects (inverted external buffer?). The
0780      * BIOS makes this work by setting the CHV_PADCTRL1_INVRXTX_TXDATA flag,
0781      * preserve this flag if the pin is already setup as GPIO.
0782      */
0783     value = chv_readl(pctrl, offset, CHV_PADCTRL0);
0784     if (value & CHV_PADCTRL0_GPIOEN)
0785         invrxtx_mask &= ~CHV_PADCTRL1_INVRXTX_TXDATA;
0786 
0787     value = chv_readl(pctrl, offset, CHV_PADCTRL1);
0788     value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
0789     value &= ~invrxtx_mask;
0790     chv_writel(pctrl, offset, CHV_PADCTRL1, value);
0791 }
0792 
0793 static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
0794                    struct pinctrl_gpio_range *range,
0795                    unsigned int offset)
0796 {
0797     struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0798     unsigned long flags;
0799     u32 value;
0800 
0801     raw_spin_lock_irqsave(&chv_lock, flags);
0802 
0803     if (chv_pad_locked(pctrl, offset)) {
0804         value = chv_readl(pctrl, offset, CHV_PADCTRL0);
0805         if (!(value & CHV_PADCTRL0_GPIOEN)) {
0806             /* Locked so cannot enable */
0807             raw_spin_unlock_irqrestore(&chv_lock, flags);
0808             return -EBUSY;
0809         }
0810     } else {
0811         struct intel_community_context *cctx = &pctrl->context.communities[0];
0812         int i;
0813 
0814         /* Reset the interrupt mapping */
0815         for (i = 0; i < ARRAY_SIZE(cctx->intr_lines); i++) {
0816             if (cctx->intr_lines[i] == offset) {
0817                 cctx->intr_lines[i] = CHV_INVALID_HWIRQ;
0818                 break;
0819             }
0820         }
0821 
0822         /* Disable interrupt generation */
0823         chv_gpio_clear_triggering(pctrl, offset);
0824 
0825         value = chv_readl(pctrl, offset, CHV_PADCTRL0);
0826 
0827         /*
0828          * If the pin is in HiZ mode (both TX and RX buffers are
0829          * disabled) we turn it to be input now.
0830          */
0831         if ((value & CHV_PADCTRL0_GPIOCFG_MASK) ==
0832              (CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) {
0833             value &= ~CHV_PADCTRL0_GPIOCFG_MASK;
0834             value |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT;
0835         }
0836 
0837         /* Switch to a GPIO mode */
0838         value |= CHV_PADCTRL0_GPIOEN;
0839         chv_writel(pctrl, offset, CHV_PADCTRL0, value);
0840     }
0841 
0842     raw_spin_unlock_irqrestore(&chv_lock, flags);
0843 
0844     return 0;
0845 }
0846 
0847 static void chv_gpio_disable_free(struct pinctrl_dev *pctldev,
0848                   struct pinctrl_gpio_range *range,
0849                   unsigned int offset)
0850 {
0851     struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0852     unsigned long flags;
0853 
0854     raw_spin_lock_irqsave(&chv_lock, flags);
0855 
0856     if (!chv_pad_locked(pctrl, offset))
0857         chv_gpio_clear_triggering(pctrl, offset);
0858 
0859     raw_spin_unlock_irqrestore(&chv_lock, flags);
0860 }
0861 
0862 static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
0863                   struct pinctrl_gpio_range *range,
0864                   unsigned int offset, bool input)
0865 {
0866     struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0867     unsigned long flags;
0868     u32 ctrl0;
0869 
0870     raw_spin_lock_irqsave(&chv_lock, flags);
0871 
0872     ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0) & ~CHV_PADCTRL0_GPIOCFG_MASK;
0873     if (input)
0874         ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT;
0875     else
0876         ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT;
0877     chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0);
0878 
0879     raw_spin_unlock_irqrestore(&chv_lock, flags);
0880 
0881     return 0;
0882 }
0883 
0884 static const struct pinmux_ops chv_pinmux_ops = {
0885     .get_functions_count = chv_get_functions_count,
0886     .get_function_name = chv_get_function_name,
0887     .get_function_groups = chv_get_function_groups,
0888     .set_mux = chv_pinmux_set_mux,
0889     .gpio_request_enable = chv_gpio_request_enable,
0890     .gpio_disable_free = chv_gpio_disable_free,
0891     .gpio_set_direction = chv_gpio_set_direction,
0892 };
0893 
0894 static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
0895               unsigned long *config)
0896 {
0897     struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0898     enum pin_config_param param = pinconf_to_config_param(*config);
0899     unsigned long flags;
0900     u32 ctrl0, ctrl1;
0901     u16 arg = 0;
0902     u32 term;
0903 
0904     raw_spin_lock_irqsave(&chv_lock, flags);
0905     ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0);
0906     ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1);
0907     raw_spin_unlock_irqrestore(&chv_lock, flags);
0908 
0909     term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT;
0910 
0911     switch (param) {
0912     case PIN_CONFIG_BIAS_DISABLE:
0913         if (term)
0914             return -EINVAL;
0915         break;
0916 
0917     case PIN_CONFIG_BIAS_PULL_UP:
0918         if (!(ctrl0 & CHV_PADCTRL0_TERM_UP))
0919             return -EINVAL;
0920 
0921         switch (term) {
0922         case CHV_PADCTRL0_TERM_20K:
0923             arg = 20000;
0924             break;
0925         case CHV_PADCTRL0_TERM_5K:
0926             arg = 5000;
0927             break;
0928         case CHV_PADCTRL0_TERM_1K:
0929             arg = 1000;
0930             break;
0931         }
0932 
0933         break;
0934 
0935     case PIN_CONFIG_BIAS_PULL_DOWN:
0936         if (!term || (ctrl0 & CHV_PADCTRL0_TERM_UP))
0937             return -EINVAL;
0938 
0939         switch (term) {
0940         case CHV_PADCTRL0_TERM_20K:
0941             arg = 20000;
0942             break;
0943         case CHV_PADCTRL0_TERM_5K:
0944             arg = 5000;
0945             break;
0946         }
0947 
0948         break;
0949 
0950     case PIN_CONFIG_DRIVE_OPEN_DRAIN:
0951         if (!(ctrl1 & CHV_PADCTRL1_ODEN))
0952             return -EINVAL;
0953         break;
0954 
0955     case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: {
0956         u32 cfg;
0957 
0958         cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
0959         cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
0960         if (cfg != CHV_PADCTRL0_GPIOCFG_HIZ)
0961             return -EINVAL;
0962 
0963         break;
0964     }
0965 
0966     default:
0967         return -ENOTSUPP;
0968     }
0969 
0970     *config = pinconf_to_config_packed(param, arg);
0971     return 0;
0972 }
0973 
0974 static int chv_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
0975                    enum pin_config_param param, u32 arg)
0976 {
0977     unsigned long flags;
0978     u32 ctrl0, pull;
0979 
0980     raw_spin_lock_irqsave(&chv_lock, flags);
0981     ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0);
0982 
0983     switch (param) {
0984     case PIN_CONFIG_BIAS_DISABLE:
0985         ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
0986         break;
0987 
0988     case PIN_CONFIG_BIAS_PULL_UP:
0989         ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
0990 
0991         switch (arg) {
0992         case 1000:
0993             /* For 1k there is only pull up */
0994             pull = CHV_PADCTRL0_TERM_1K << CHV_PADCTRL0_TERM_SHIFT;
0995             break;
0996         case 5000:
0997             pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
0998             break;
0999         case 20000:
1000             pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
1001             break;
1002         default:
1003             raw_spin_unlock_irqrestore(&chv_lock, flags);
1004             return -EINVAL;
1005         }
1006 
1007         ctrl0 |= CHV_PADCTRL0_TERM_UP | pull;
1008         break;
1009 
1010     case PIN_CONFIG_BIAS_PULL_DOWN:
1011         ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1012 
1013         switch (arg) {
1014         case 5000:
1015             pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
1016             break;
1017         case 20000:
1018             pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
1019             break;
1020         default:
1021             raw_spin_unlock_irqrestore(&chv_lock, flags);
1022             return -EINVAL;
1023         }
1024 
1025         ctrl0 |= pull;
1026         break;
1027 
1028     default:
1029         raw_spin_unlock_irqrestore(&chv_lock, flags);
1030         return -EINVAL;
1031     }
1032 
1033     chv_writel(pctrl, pin, CHV_PADCTRL0, ctrl0);
1034     raw_spin_unlock_irqrestore(&chv_lock, flags);
1035 
1036     return 0;
1037 }
1038 
1039 static int chv_config_set_oden(struct intel_pinctrl *pctrl, unsigned int pin,
1040                    bool enable)
1041 {
1042     unsigned long flags;
1043     u32 ctrl1;
1044 
1045     raw_spin_lock_irqsave(&chv_lock, flags);
1046     ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1);
1047 
1048     if (enable)
1049         ctrl1 |= CHV_PADCTRL1_ODEN;
1050     else
1051         ctrl1 &= ~CHV_PADCTRL1_ODEN;
1052 
1053     chv_writel(pctrl, pin, CHV_PADCTRL1, ctrl1);
1054     raw_spin_unlock_irqrestore(&chv_lock, flags);
1055 
1056     return 0;
1057 }
1058 
1059 static int chv_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
1060               unsigned long *configs, unsigned int nconfigs)
1061 {
1062     struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1063     struct device *dev = pctrl->dev;
1064     enum pin_config_param param;
1065     int i, ret;
1066     u32 arg;
1067 
1068     if (chv_pad_locked(pctrl, pin))
1069         return -EBUSY;
1070 
1071     for (i = 0; i < nconfigs; i++) {
1072         param = pinconf_to_config_param(configs[i]);
1073         arg = pinconf_to_config_argument(configs[i]);
1074 
1075         switch (param) {
1076         case PIN_CONFIG_BIAS_DISABLE:
1077         case PIN_CONFIG_BIAS_PULL_UP:
1078         case PIN_CONFIG_BIAS_PULL_DOWN:
1079             ret = chv_config_set_pull(pctrl, pin, param, arg);
1080             if (ret)
1081                 return ret;
1082             break;
1083 
1084         case PIN_CONFIG_DRIVE_PUSH_PULL:
1085             ret = chv_config_set_oden(pctrl, pin, false);
1086             if (ret)
1087                 return ret;
1088             break;
1089 
1090         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1091             ret = chv_config_set_oden(pctrl, pin, true);
1092             if (ret)
1093                 return ret;
1094             break;
1095 
1096         default:
1097             return -ENOTSUPP;
1098         }
1099 
1100         dev_dbg(dev, "pin %d set config %d arg %u\n", pin, param, arg);
1101     }
1102 
1103     return 0;
1104 }
1105 
1106 static int chv_config_group_get(struct pinctrl_dev *pctldev,
1107                 unsigned int group,
1108                 unsigned long *config)
1109 {
1110     const unsigned int *pins;
1111     unsigned int npins;
1112     int ret;
1113 
1114     ret = chv_get_group_pins(pctldev, group, &pins, &npins);
1115     if (ret)
1116         return ret;
1117 
1118     ret = chv_config_get(pctldev, pins[0], config);
1119     if (ret)
1120         return ret;
1121 
1122     return 0;
1123 }
1124 
1125 static int chv_config_group_set(struct pinctrl_dev *pctldev,
1126                 unsigned int group, unsigned long *configs,
1127                 unsigned int num_configs)
1128 {
1129     const unsigned int *pins;
1130     unsigned int npins;
1131     int i, ret;
1132 
1133     ret = chv_get_group_pins(pctldev, group, &pins, &npins);
1134     if (ret)
1135         return ret;
1136 
1137     for (i = 0; i < npins; i++) {
1138         ret = chv_config_set(pctldev, pins[i], configs, num_configs);
1139         if (ret)
1140             return ret;
1141     }
1142 
1143     return 0;
1144 }
1145 
1146 static const struct pinconf_ops chv_pinconf_ops = {
1147     .is_generic = true,
1148     .pin_config_set = chv_config_set,
1149     .pin_config_get = chv_config_get,
1150     .pin_config_group_get = chv_config_group_get,
1151     .pin_config_group_set = chv_config_group_set,
1152 };
1153 
1154 static struct pinctrl_desc chv_pinctrl_desc = {
1155     .pctlops = &chv_pinctrl_ops,
1156     .pmxops = &chv_pinmux_ops,
1157     .confops = &chv_pinconf_ops,
1158     .owner = THIS_MODULE,
1159 };
1160 
1161 static int chv_gpio_get(struct gpio_chip *chip, unsigned int offset)
1162 {
1163     struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1164     unsigned long flags;
1165     u32 ctrl0, cfg;
1166 
1167     raw_spin_lock_irqsave(&chv_lock, flags);
1168     ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
1169     raw_spin_unlock_irqrestore(&chv_lock, flags);
1170 
1171     cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1172     cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1173 
1174     if (cfg == CHV_PADCTRL0_GPIOCFG_GPO)
1175         return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE);
1176     return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE);
1177 }
1178 
1179 static void chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
1180 {
1181     struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1182     unsigned long flags;
1183     u32 ctrl0;
1184 
1185     raw_spin_lock_irqsave(&chv_lock, flags);
1186 
1187     ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
1188 
1189     if (value)
1190         ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE;
1191     else
1192         ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE;
1193 
1194     chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0);
1195 
1196     raw_spin_unlock_irqrestore(&chv_lock, flags);
1197 }
1198 
1199 static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1200 {
1201     struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1202     u32 ctrl0, direction;
1203     unsigned long flags;
1204 
1205     raw_spin_lock_irqsave(&chv_lock, flags);
1206     ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
1207     raw_spin_unlock_irqrestore(&chv_lock, flags);
1208 
1209     direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1210     direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1211 
1212     if (direction == CHV_PADCTRL0_GPIOCFG_GPO)
1213         return GPIO_LINE_DIRECTION_OUT;
1214 
1215     return GPIO_LINE_DIRECTION_IN;
1216 }
1217 
1218 static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
1219 {
1220     return pinctrl_gpio_direction_input(chip->base + offset);
1221 }
1222 
1223 static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
1224                      int value)
1225 {
1226     chv_gpio_set(chip, offset, value);
1227     return pinctrl_gpio_direction_output(chip->base + offset);
1228 }
1229 
1230 static const struct gpio_chip chv_gpio_chip = {
1231     .owner = THIS_MODULE,
1232     .request = gpiochip_generic_request,
1233     .free = gpiochip_generic_free,
1234     .get_direction = chv_gpio_get_direction,
1235     .direction_input = chv_gpio_direction_input,
1236     .direction_output = chv_gpio_direction_output,
1237     .get = chv_gpio_get,
1238     .set = chv_gpio_set,
1239 };
1240 
1241 static void chv_gpio_irq_ack(struct irq_data *d)
1242 {
1243     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1244     struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1245     irq_hw_number_t hwirq = irqd_to_hwirq(d);
1246     u32 intr_line;
1247 
1248     raw_spin_lock(&chv_lock);
1249 
1250     intr_line = chv_readl(pctrl, hwirq, CHV_PADCTRL0);
1251     intr_line &= CHV_PADCTRL0_INTSEL_MASK;
1252     intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
1253     chv_pctrl_writel(pctrl, CHV_INTSTAT, BIT(intr_line));
1254 
1255     raw_spin_unlock(&chv_lock);
1256 }
1257 
1258 static void chv_gpio_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t hwirq, bool mask)
1259 {
1260     struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1261     u32 value, intr_line;
1262     unsigned long flags;
1263 
1264     raw_spin_lock_irqsave(&chv_lock, flags);
1265 
1266     intr_line = chv_readl(pctrl, hwirq, CHV_PADCTRL0);
1267     intr_line &= CHV_PADCTRL0_INTSEL_MASK;
1268     intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
1269 
1270     value = chv_pctrl_readl(pctrl, CHV_INTMASK);
1271     if (mask)
1272         value &= ~BIT(intr_line);
1273     else
1274         value |= BIT(intr_line);
1275     chv_pctrl_writel(pctrl, CHV_INTMASK, value);
1276 
1277     raw_spin_unlock_irqrestore(&chv_lock, flags);
1278 }
1279 
1280 static void chv_gpio_irq_mask(struct irq_data *d)
1281 {
1282     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1283     irq_hw_number_t hwirq = irqd_to_hwirq(d);
1284 
1285     chv_gpio_irq_mask_unmask(gc, hwirq, true);
1286     gpiochip_disable_irq(gc, hwirq);
1287 }
1288 
1289 static void chv_gpio_irq_unmask(struct irq_data *d)
1290 {
1291     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1292     irq_hw_number_t hwirq = irqd_to_hwirq(d);
1293 
1294     gpiochip_enable_irq(gc, hwirq);
1295     chv_gpio_irq_mask_unmask(gc, hwirq, false);
1296 }
1297 
1298 static unsigned chv_gpio_irq_startup(struct irq_data *d)
1299 {
1300     /*
1301      * Check if the interrupt has been requested with 0 as triggering
1302      * type. In that case it is assumed that the current values
1303      * programmed to the hardware are used (e.g BIOS configured
1304      * defaults).
1305      *
1306      * In that case ->irq_set_type() will never be called so we need to
1307      * read back the values from hardware now, set correct flow handler
1308      * and update mappings before the interrupt is being used.
1309      */
1310     if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) {
1311         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1312         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1313         struct device *dev = pctrl->dev;
1314         struct intel_community_context *cctx = &pctrl->context.communities[0];
1315         irq_hw_number_t hwirq = irqd_to_hwirq(d);
1316         irq_flow_handler_t handler;
1317         unsigned long flags;
1318         u32 intsel, value;
1319 
1320         raw_spin_lock_irqsave(&chv_lock, flags);
1321         intsel = chv_readl(pctrl, hwirq, CHV_PADCTRL0);
1322         intsel &= CHV_PADCTRL0_INTSEL_MASK;
1323         intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
1324 
1325         value = chv_readl(pctrl, hwirq, CHV_PADCTRL1);
1326         if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL)
1327             handler = handle_level_irq;
1328         else
1329             handler = handle_edge_irq;
1330 
1331         if (cctx->intr_lines[intsel] == CHV_INVALID_HWIRQ) {
1332             irq_set_handler_locked(d, handler);
1333             dev_dbg(dev, "using interrupt line %u for IRQ_TYPE_NONE on pin %lu\n",
1334                 intsel, hwirq);
1335             cctx->intr_lines[intsel] = hwirq;
1336         }
1337         raw_spin_unlock_irqrestore(&chv_lock, flags);
1338     }
1339 
1340     chv_gpio_irq_unmask(d);
1341     return 0;
1342 }
1343 
1344 static int chv_gpio_set_intr_line(struct intel_pinctrl *pctrl, unsigned int pin)
1345 {
1346     struct device *dev = pctrl->dev;
1347     struct intel_community_context *cctx = &pctrl->context.communities[0];
1348     const struct intel_community *community = &pctrl->communities[0];
1349     u32 value, intsel;
1350     int i;
1351 
1352     value = chv_readl(pctrl, pin, CHV_PADCTRL0);
1353     intsel = (value & CHV_PADCTRL0_INTSEL_MASK) >> CHV_PADCTRL0_INTSEL_SHIFT;
1354 
1355     if (cctx->intr_lines[intsel] == pin)
1356         return 0;
1357 
1358     if (cctx->intr_lines[intsel] == CHV_INVALID_HWIRQ) {
1359         dev_dbg(dev, "using interrupt line %u for pin %u\n", intsel, pin);
1360         cctx->intr_lines[intsel] = pin;
1361         return 0;
1362     }
1363 
1364     /*
1365      * The interrupt line selected by the BIOS is already in use by
1366      * another pin, this is a known BIOS bug found on several models.
1367      * But this may also be caused by Linux deciding to use a pin as
1368      * IRQ which was not expected to be used as such by the BIOS authors,
1369      * so log this at info level only.
1370      */
1371     dev_info(dev, "interrupt line %u is used by both pin %u and pin %u\n", intsel,
1372          cctx->intr_lines[intsel], pin);
1373 
1374     if (chv_pad_locked(pctrl, pin))
1375         return -EBUSY;
1376 
1377     /*
1378      * The BIOS fills the interrupt lines from 0 counting up, start at
1379      * the other end to find a free interrupt line to workaround this.
1380      */
1381     for (i = community->nirqs - 1; i >= 0; i--) {
1382         if (cctx->intr_lines[i] == CHV_INVALID_HWIRQ)
1383             break;
1384     }
1385     if (i < 0)
1386         return -EBUSY;
1387 
1388     dev_info(dev, "changing the interrupt line for pin %u to %d\n", pin, i);
1389 
1390     value = (value & ~CHV_PADCTRL0_INTSEL_MASK) | (i << CHV_PADCTRL0_INTSEL_SHIFT);
1391     chv_writel(pctrl, pin, CHV_PADCTRL0, value);
1392     cctx->intr_lines[i] = pin;
1393 
1394     return 0;
1395 }
1396 
1397 static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
1398 {
1399     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1400     struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1401     irq_hw_number_t hwirq = irqd_to_hwirq(d);
1402     unsigned long flags;
1403     u32 value;
1404     int ret;
1405 
1406     raw_spin_lock_irqsave(&chv_lock, flags);
1407 
1408     ret = chv_gpio_set_intr_line(pctrl, hwirq);
1409     if (ret)
1410         goto out_unlock;
1411 
1412     /*
1413      * Pins which can be used as shared interrupt are configured in
1414      * BIOS. Driver trusts BIOS configurations and assigns different
1415      * handler according to the irq type.
1416      *
1417      * Driver needs to save the mapping between each pin and
1418      * its interrupt line.
1419      * 1. If the pin cfg is locked in BIOS:
1420      *  Trust BIOS has programmed IntWakeCfg bits correctly,
1421      *  driver just needs to save the mapping.
1422      * 2. If the pin cfg is not locked in BIOS:
1423      *  Driver programs the IntWakeCfg bits and save the mapping.
1424      */
1425     if (!chv_pad_locked(pctrl, hwirq)) {
1426         value = chv_readl(pctrl, hwirq, CHV_PADCTRL1);
1427         value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
1428         value &= ~CHV_PADCTRL1_INVRXTX_MASK;
1429 
1430         if (type & IRQ_TYPE_EDGE_BOTH) {
1431             if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
1432                 value |= CHV_PADCTRL1_INTWAKECFG_BOTH;
1433             else if (type & IRQ_TYPE_EDGE_RISING)
1434                 value |= CHV_PADCTRL1_INTWAKECFG_RISING;
1435             else if (type & IRQ_TYPE_EDGE_FALLING)
1436                 value |= CHV_PADCTRL1_INTWAKECFG_FALLING;
1437         } else if (type & IRQ_TYPE_LEVEL_MASK) {
1438             value |= CHV_PADCTRL1_INTWAKECFG_LEVEL;
1439             if (type & IRQ_TYPE_LEVEL_LOW)
1440                 value |= CHV_PADCTRL1_INVRXTX_RXDATA;
1441         }
1442 
1443         chv_writel(pctrl, hwirq, CHV_PADCTRL1, value);
1444     }
1445 
1446     if (type & IRQ_TYPE_EDGE_BOTH)
1447         irq_set_handler_locked(d, handle_edge_irq);
1448     else if (type & IRQ_TYPE_LEVEL_MASK)
1449         irq_set_handler_locked(d, handle_level_irq);
1450 
1451 out_unlock:
1452     raw_spin_unlock_irqrestore(&chv_lock, flags);
1453 
1454     return ret;
1455 }
1456 
1457 static const struct irq_chip chv_gpio_irq_chip = {
1458     .name       = "chv-gpio",
1459     .irq_startup    = chv_gpio_irq_startup,
1460     .irq_ack    = chv_gpio_irq_ack,
1461     .irq_mask   = chv_gpio_irq_mask,
1462     .irq_unmask = chv_gpio_irq_unmask,
1463     .irq_set_type   = chv_gpio_irq_type,
1464     .flags      = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE,
1465     GPIOCHIP_IRQ_RESOURCE_HELPERS,
1466 };
1467 
1468 static void chv_gpio_irq_handler(struct irq_desc *desc)
1469 {
1470     struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1471     struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1472     struct device *dev = pctrl->dev;
1473     const struct intel_community *community = &pctrl->communities[0];
1474     struct intel_community_context *cctx = &pctrl->context.communities[0];
1475     struct irq_chip *chip = irq_desc_get_chip(desc);
1476     unsigned long pending;
1477     unsigned long flags;
1478     u32 intr_line;
1479 
1480     chained_irq_enter(chip, desc);
1481 
1482     raw_spin_lock_irqsave(&chv_lock, flags);
1483     pending = chv_pctrl_readl(pctrl, CHV_INTSTAT);
1484     raw_spin_unlock_irqrestore(&chv_lock, flags);
1485 
1486     for_each_set_bit(intr_line, &pending, community->nirqs) {
1487         unsigned int offset;
1488 
1489         offset = cctx->intr_lines[intr_line];
1490         if (offset == CHV_INVALID_HWIRQ) {
1491             dev_warn_once(dev, "interrupt on unmapped interrupt line %u\n", intr_line);
1492             /* Some boards expect hwirq 0 to trigger in this case */
1493             offset = 0;
1494         }
1495 
1496         generic_handle_domain_irq(gc->irq.domain, offset);
1497     }
1498 
1499     chained_irq_exit(chip, desc);
1500 }
1501 
1502 /*
1503  * Certain machines seem to hardcode Linux IRQ numbers in their ACPI
1504  * tables. Since we leave GPIOs that are not capable of generating
1505  * interrupts out of the irqdomain the numbering will be different and
1506  * cause devices using the hardcoded IRQ numbers fail. In order not to
1507  * break such machines we will only mask pins from irqdomain if the machine
1508  * is not listed below.
1509  */
1510 static const struct dmi_system_id chv_no_valid_mask[] = {
1511     /* See https://bugzilla.kernel.org/show_bug.cgi?id=194945 */
1512     {
1513         .ident = "Intel_Strago based Chromebooks (All models)",
1514         .matches = {
1515             DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1516             DMI_MATCH(DMI_PRODUCT_FAMILY, "Intel_Strago"),
1517         },
1518     },
1519     {
1520         .ident = "HP Chromebook 11 G5 (Setzer)",
1521         .matches = {
1522             DMI_MATCH(DMI_SYS_VENDOR, "HP"),
1523             DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"),
1524         },
1525     },
1526     {
1527         .ident = "Acer Chromebook R11 (Cyan)",
1528         .matches = {
1529             DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1530             DMI_MATCH(DMI_PRODUCT_NAME, "Cyan"),
1531         },
1532     },
1533     {
1534         .ident = "Samsung Chromebook 3 (Celes)",
1535         .matches = {
1536             DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1537             DMI_MATCH(DMI_PRODUCT_NAME, "Celes"),
1538         },
1539     },
1540     {}
1541 };
1542 
1543 static void chv_init_irq_valid_mask(struct gpio_chip *chip,
1544                     unsigned long *valid_mask,
1545                     unsigned int ngpios)
1546 {
1547     struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1548     const struct intel_community *community = &pctrl->communities[0];
1549     int i;
1550 
1551     /* Do not add GPIOs that can only generate GPEs to the IRQ domain */
1552     for (i = 0; i < pctrl->soc->npins; i++) {
1553         const struct pinctrl_pin_desc *desc;
1554         u32 intsel;
1555 
1556         desc = &pctrl->soc->pins[i];
1557 
1558         intsel = chv_readl(pctrl, desc->number, CHV_PADCTRL0);
1559         intsel &= CHV_PADCTRL0_INTSEL_MASK;
1560         intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
1561 
1562         if (intsel >= community->nirqs)
1563             clear_bit(desc->number, valid_mask);
1564     }
1565 }
1566 
1567 static int chv_gpio_irq_init_hw(struct gpio_chip *chip)
1568 {
1569     struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1570     const struct intel_community *community = &pctrl->communities[0];
1571 
1572     /*
1573      * The same set of machines in chv_no_valid_mask[] have incorrectly
1574      * configured GPIOs that generate spurious interrupts so we use
1575      * this same list to apply another quirk for them.
1576      *
1577      * See also https://bugzilla.kernel.org/show_bug.cgi?id=197953.
1578      */
1579     if (!pctrl->chip.irq.init_valid_mask) {
1580         /*
1581          * Mask all interrupts the community is able to generate
1582          * but leave the ones that can only generate GPEs unmasked.
1583          */
1584         chv_pctrl_writel(pctrl, CHV_INTMASK, GENMASK(31, community->nirqs));
1585     }
1586 
1587     /* Clear all interrupts */
1588     chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff);
1589 
1590     return 0;
1591 }
1592 
1593 static int chv_gpio_add_pin_ranges(struct gpio_chip *chip)
1594 {
1595     struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
1596     struct device *dev = pctrl->dev;
1597     const struct intel_community *community = &pctrl->communities[0];
1598     const struct intel_padgroup *gpp;
1599     int ret, i;
1600 
1601     for (i = 0; i < community->ngpps; i++) {
1602         gpp = &community->gpps[i];
1603         ret = gpiochip_add_pin_range(chip, dev_name(dev), gpp->base, gpp->base, gpp->size);
1604         if (ret) {
1605             dev_err(dev, "failed to add GPIO pin range\n");
1606             return ret;
1607         }
1608     }
1609 
1610     return 0;
1611 }
1612 
1613 static int chv_gpio_probe(struct intel_pinctrl *pctrl, int irq)
1614 {
1615     const struct intel_community *community = &pctrl->communities[0];
1616     const struct intel_padgroup *gpp;
1617     struct gpio_chip *chip = &pctrl->chip;
1618     struct device *dev = pctrl->dev;
1619     bool need_valid_mask = !dmi_check_system(chv_no_valid_mask);
1620     int ret, i, irq_base;
1621 
1622     *chip = chv_gpio_chip;
1623 
1624     chip->ngpio = pctrl->soc->pins[pctrl->soc->npins - 1].number + 1;
1625     chip->label = dev_name(dev);
1626     chip->add_pin_ranges = chv_gpio_add_pin_ranges;
1627     chip->parent = dev;
1628     chip->base = -1;
1629 
1630     pctrl->irq = irq;
1631 
1632     gpio_irq_chip_set_chip(&chip->irq, &chv_gpio_irq_chip);
1633     chip->irq.init_hw = chv_gpio_irq_init_hw;
1634     chip->irq.parent_handler = chv_gpio_irq_handler;
1635     chip->irq.num_parents = 1;
1636     chip->irq.parents = &pctrl->irq;
1637     chip->irq.default_type = IRQ_TYPE_NONE;
1638     chip->irq.handler = handle_bad_irq;
1639     if (need_valid_mask) {
1640         chip->irq.init_valid_mask = chv_init_irq_valid_mask;
1641     } else {
1642         irq_base = devm_irq_alloc_descs(dev, -1, 0, pctrl->soc->npins, NUMA_NO_NODE);
1643         if (irq_base < 0) {
1644             dev_err(dev, "Failed to allocate IRQ numbers\n");
1645             return irq_base;
1646         }
1647     }
1648 
1649     ret = devm_gpiochip_add_data(dev, chip, pctrl);
1650     if (ret) {
1651         dev_err(dev, "Failed to register gpiochip\n");
1652         return ret;
1653     }
1654 
1655     if (!need_valid_mask) {
1656         for (i = 0; i < community->ngpps; i++) {
1657             gpp = &community->gpps[i];
1658 
1659             irq_domain_associate_many(chip->irq.domain, irq_base,
1660                           gpp->base, gpp->size);
1661             irq_base += gpp->size;
1662         }
1663     }
1664 
1665     return 0;
1666 }
1667 
1668 static acpi_status chv_pinctrl_mmio_access_handler(u32 function,
1669     acpi_physical_address address, u32 bits, u64 *value,
1670     void *handler_context, void *region_context)
1671 {
1672     struct intel_pinctrl *pctrl = region_context;
1673     unsigned long flags;
1674     acpi_status ret = AE_OK;
1675 
1676     raw_spin_lock_irqsave(&chv_lock, flags);
1677 
1678     if (function == ACPI_WRITE)
1679         chv_pctrl_writel(pctrl, address, *value);
1680     else if (function == ACPI_READ)
1681         *value = chv_pctrl_readl(pctrl, address);
1682     else
1683         ret = AE_BAD_PARAMETER;
1684 
1685     raw_spin_unlock_irqrestore(&chv_lock, flags);
1686 
1687     return ret;
1688 }
1689 
1690 static int chv_pinctrl_probe(struct platform_device *pdev)
1691 {
1692     const struct intel_pinctrl_soc_data *soc_data;
1693     struct intel_community_context *cctx;
1694     struct intel_community *community;
1695     struct device *dev = &pdev->dev;
1696     struct acpi_device *adev = ACPI_COMPANION(dev);
1697     struct intel_pinctrl *pctrl;
1698     acpi_status status;
1699     unsigned int i;
1700     int ret, irq;
1701 
1702     soc_data = intel_pinctrl_get_soc_data(pdev);
1703     if (IS_ERR(soc_data))
1704         return PTR_ERR(soc_data);
1705 
1706     pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
1707     if (!pctrl)
1708         return -ENOMEM;
1709 
1710     pctrl->dev = dev;
1711     pctrl->soc = soc_data;
1712 
1713     pctrl->ncommunities = pctrl->soc->ncommunities;
1714     pctrl->communities = devm_kmemdup(dev, pctrl->soc->communities,
1715                       pctrl->ncommunities * sizeof(*pctrl->communities),
1716                       GFP_KERNEL);
1717     if (!pctrl->communities)
1718         return -ENOMEM;
1719 
1720     community = &pctrl->communities[0];
1721     community->regs = devm_platform_ioremap_resource(pdev, 0);
1722     if (IS_ERR(community->regs))
1723         return PTR_ERR(community->regs);
1724 
1725     community->pad_regs = community->regs + FAMILY_PAD_REGS_OFF;
1726 
1727 #ifdef CONFIG_PM_SLEEP
1728     pctrl->context.pads = devm_kcalloc(dev, pctrl->soc->npins,
1729                        sizeof(*pctrl->context.pads),
1730                        GFP_KERNEL);
1731     if (!pctrl->context.pads)
1732         return -ENOMEM;
1733 #endif
1734 
1735     pctrl->context.communities = devm_kcalloc(dev, pctrl->soc->ncommunities,
1736                           sizeof(*pctrl->context.communities),
1737                           GFP_KERNEL);
1738     if (!pctrl->context.communities)
1739         return -ENOMEM;
1740 
1741     cctx = &pctrl->context.communities[0];
1742     for (i = 0; i < ARRAY_SIZE(cctx->intr_lines); i++)
1743         cctx->intr_lines[i] = CHV_INVALID_HWIRQ;
1744 
1745     irq = platform_get_irq(pdev, 0);
1746     if (irq < 0)
1747         return irq;
1748 
1749     pctrl->pctldesc = chv_pinctrl_desc;
1750     pctrl->pctldesc.name = dev_name(dev);
1751     pctrl->pctldesc.pins = pctrl->soc->pins;
1752     pctrl->pctldesc.npins = pctrl->soc->npins;
1753 
1754     pctrl->pctldev = devm_pinctrl_register(dev, &pctrl->pctldesc, pctrl);
1755     if (IS_ERR(pctrl->pctldev)) {
1756         dev_err(dev, "failed to register pinctrl driver\n");
1757         return PTR_ERR(pctrl->pctldev);
1758     }
1759 
1760     ret = chv_gpio_probe(pctrl, irq);
1761     if (ret)
1762         return ret;
1763 
1764     status = acpi_install_address_space_handler(adev->handle,
1765                     community->acpi_space_id,
1766                     chv_pinctrl_mmio_access_handler,
1767                     NULL, pctrl);
1768     if (ACPI_FAILURE(status))
1769         dev_err(dev, "failed to install ACPI addr space handler\n");
1770 
1771     platform_set_drvdata(pdev, pctrl);
1772 
1773     return 0;
1774 }
1775 
1776 static int chv_pinctrl_remove(struct platform_device *pdev)
1777 {
1778     struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1779     const struct intel_community *community = &pctrl->communities[0];
1780 
1781     acpi_remove_address_space_handler(ACPI_COMPANION(&pdev->dev),
1782                       community->acpi_space_id,
1783                       chv_pinctrl_mmio_access_handler);
1784 
1785     return 0;
1786 }
1787 
1788 #ifdef CONFIG_PM_SLEEP
1789 static int chv_pinctrl_suspend_noirq(struct device *dev)
1790 {
1791     struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1792     struct intel_community_context *cctx = &pctrl->context.communities[0];
1793     unsigned long flags;
1794     int i;
1795 
1796     raw_spin_lock_irqsave(&chv_lock, flags);
1797 
1798     cctx->saved_intmask = chv_pctrl_readl(pctrl, CHV_INTMASK);
1799 
1800     for (i = 0; i < pctrl->soc->npins; i++) {
1801         const struct pinctrl_pin_desc *desc;
1802         struct intel_pad_context *ctx = &pctrl->context.pads[i];
1803 
1804         desc = &pctrl->soc->pins[i];
1805         if (chv_pad_locked(pctrl, desc->number))
1806             continue;
1807 
1808         ctx->padctrl0 = chv_readl(pctrl, desc->number, CHV_PADCTRL0);
1809         ctx->padctrl0 &= ~CHV_PADCTRL0_GPIORXSTATE;
1810 
1811         ctx->padctrl1 = chv_readl(pctrl, desc->number, CHV_PADCTRL1);
1812     }
1813 
1814     raw_spin_unlock_irqrestore(&chv_lock, flags);
1815 
1816     return 0;
1817 }
1818 
1819 static int chv_pinctrl_resume_noirq(struct device *dev)
1820 {
1821     struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1822     struct intel_community_context *cctx = &pctrl->context.communities[0];
1823     unsigned long flags;
1824     int i;
1825 
1826     raw_spin_lock_irqsave(&chv_lock, flags);
1827 
1828     /*
1829      * Mask all interrupts before restoring per-pin configuration
1830      * registers because we don't know in which state BIOS left them
1831      * upon exiting suspend.
1832      */
1833     chv_pctrl_writel(pctrl, CHV_INTMASK, 0x0000);
1834 
1835     for (i = 0; i < pctrl->soc->npins; i++) {
1836         const struct pinctrl_pin_desc *desc;
1837         struct intel_pad_context *ctx = &pctrl->context.pads[i];
1838         u32 val;
1839 
1840         desc = &pctrl->soc->pins[i];
1841         if (chv_pad_locked(pctrl, desc->number))
1842             continue;
1843 
1844         /* Only restore if our saved state differs from the current */
1845         val = chv_readl(pctrl, desc->number, CHV_PADCTRL0);
1846         val &= ~CHV_PADCTRL0_GPIORXSTATE;
1847         if (ctx->padctrl0 != val) {
1848             chv_writel(pctrl, desc->number, CHV_PADCTRL0, ctx->padctrl0);
1849             dev_dbg(dev, "restored pin %2u ctrl0 0x%08x\n", desc->number,
1850                 chv_readl(pctrl, desc->number, CHV_PADCTRL0));
1851         }
1852 
1853         val = chv_readl(pctrl, desc->number, CHV_PADCTRL1);
1854         if (ctx->padctrl1 != val) {
1855             chv_writel(pctrl, desc->number, CHV_PADCTRL1, ctx->padctrl1);
1856             dev_dbg(dev, "restored pin %2u ctrl1 0x%08x\n", desc->number,
1857                 chv_readl(pctrl, desc->number, CHV_PADCTRL1));
1858         }
1859     }
1860 
1861     /*
1862      * Now that all pins are restored to known state, we can restore
1863      * the interrupt mask register as well.
1864      */
1865     chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff);
1866     chv_pctrl_writel(pctrl, CHV_INTMASK, cctx->saved_intmask);
1867 
1868     raw_spin_unlock_irqrestore(&chv_lock, flags);
1869 
1870     return 0;
1871 }
1872 #endif
1873 
1874 static const struct dev_pm_ops chv_pinctrl_pm_ops = {
1875     SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend_noirq,
1876                       chv_pinctrl_resume_noirq)
1877 };
1878 
1879 static const struct acpi_device_id chv_pinctrl_acpi_match[] = {
1880     { "INT33FF", (kernel_ulong_t)chv_soc_data },
1881     { }
1882 };
1883 MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match);
1884 
1885 static struct platform_driver chv_pinctrl_driver = {
1886     .probe = chv_pinctrl_probe,
1887     .remove = chv_pinctrl_remove,
1888     .driver = {
1889         .name = "cherryview-pinctrl",
1890         .pm = &chv_pinctrl_pm_ops,
1891         .acpi_match_table = chv_pinctrl_acpi_match,
1892     },
1893 };
1894 
1895 static int __init chv_pinctrl_init(void)
1896 {
1897     return platform_driver_register(&chv_pinctrl_driver);
1898 }
1899 subsys_initcall(chv_pinctrl_init);
1900 
1901 static void __exit chv_pinctrl_exit(void)
1902 {
1903     platform_driver_unregister(&chv_pinctrl_driver);
1904 }
1905 module_exit(chv_pinctrl_exit);
1906 
1907 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1908 MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver");
1909 MODULE_LICENSE("GPL v2");
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