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0009 #include <linux/mod_devicetable.h>
0010 #include <linux/module.h>
0011 #include <linux/platform_device.h>
0012
0013 #include <linux/pinctrl/pinctrl.h>
0014
0015 #include "pinctrl-intel.h"
0016
0017 #define BXT_PAD_OWN 0x020
0018 #define BXT_PADCFGLOCK 0x060
0019 #define BXT_HOSTSW_OWN 0x080
0020 #define BXT_GPI_IS 0x100
0021 #define BXT_GPI_IE 0x110
0022
0023 #define BXT_COMMUNITY(s, e) \
0024 { \
0025 .padown_offset = BXT_PAD_OWN, \
0026 .padcfglock_offset = BXT_PADCFGLOCK, \
0027 .hostown_offset = BXT_HOSTSW_OWN, \
0028 .is_offset = BXT_GPI_IS, \
0029 .ie_offset = BXT_GPI_IE, \
0030 .gpp_size = 32, \
0031 .pin_base = (s), \
0032 .npins = ((e) - (s) + 1), \
0033 }
0034
0035
0036 static const struct pinctrl_pin_desc bxt_north_pins[] = {
0037 PINCTRL_PIN(0, "GPIO_0"),
0038 PINCTRL_PIN(1, "GPIO_1"),
0039 PINCTRL_PIN(2, "GPIO_2"),
0040 PINCTRL_PIN(3, "GPIO_3"),
0041 PINCTRL_PIN(4, "GPIO_4"),
0042 PINCTRL_PIN(5, "GPIO_5"),
0043 PINCTRL_PIN(6, "GPIO_6"),
0044 PINCTRL_PIN(7, "GPIO_7"),
0045 PINCTRL_PIN(8, "GPIO_8"),
0046 PINCTRL_PIN(9, "GPIO_9"),
0047 PINCTRL_PIN(10, "GPIO_10"),
0048 PINCTRL_PIN(11, "GPIO_11"),
0049 PINCTRL_PIN(12, "GPIO_12"),
0050 PINCTRL_PIN(13, "GPIO_13"),
0051 PINCTRL_PIN(14, "GPIO_14"),
0052 PINCTRL_PIN(15, "GPIO_15"),
0053 PINCTRL_PIN(16, "GPIO_16"),
0054 PINCTRL_PIN(17, "GPIO_17"),
0055 PINCTRL_PIN(18, "GPIO_18"),
0056 PINCTRL_PIN(19, "GPIO_19"),
0057 PINCTRL_PIN(20, "GPIO_20"),
0058 PINCTRL_PIN(21, "GPIO_21"),
0059 PINCTRL_PIN(22, "GPIO_22"),
0060 PINCTRL_PIN(23, "GPIO_23"),
0061 PINCTRL_PIN(24, "GPIO_24"),
0062 PINCTRL_PIN(25, "GPIO_25"),
0063 PINCTRL_PIN(26, "GPIO_26"),
0064 PINCTRL_PIN(27, "GPIO_27"),
0065 PINCTRL_PIN(28, "GPIO_28"),
0066 PINCTRL_PIN(29, "GPIO_29"),
0067 PINCTRL_PIN(30, "GPIO_30"),
0068 PINCTRL_PIN(31, "GPIO_31"),
0069 PINCTRL_PIN(32, "GPIO_32"),
0070 PINCTRL_PIN(33, "GPIO_33"),
0071 PINCTRL_PIN(34, "PWM0"),
0072 PINCTRL_PIN(35, "PWM1"),
0073 PINCTRL_PIN(36, "PWM2"),
0074 PINCTRL_PIN(37, "PWM3"),
0075 PINCTRL_PIN(38, "LPSS_UART0_RXD"),
0076 PINCTRL_PIN(39, "LPSS_UART0_TXD"),
0077 PINCTRL_PIN(40, "LPSS_UART0_RTS_B"),
0078 PINCTRL_PIN(41, "LPSS_UART0_CTS_B"),
0079 PINCTRL_PIN(42, "LPSS_UART1_RXD"),
0080 PINCTRL_PIN(43, "LPSS_UART1_TXD"),
0081 PINCTRL_PIN(44, "LPSS_UART1_RTS_B"),
0082 PINCTRL_PIN(45, "LPSS_UART1_CTS_B"),
0083 PINCTRL_PIN(46, "LPSS_UART2_RXD"),
0084 PINCTRL_PIN(47, "LPSS_UART2_TXD"),
0085 PINCTRL_PIN(48, "LPSS_UART2_RTS_B"),
0086 PINCTRL_PIN(49, "LPSS_UART2_CTS_B"),
0087 PINCTRL_PIN(50, "ISH_UART0_RXD"),
0088 PINCTRL_PIN(51, "ISH_UART0_TXT"),
0089 PINCTRL_PIN(52, "ISH_UART0_RTS_B"),
0090 PINCTRL_PIN(53, "ISH_UART0_CTS_B"),
0091 PINCTRL_PIN(54, "ISH_UART1_RXD"),
0092 PINCTRL_PIN(55, "ISH_UART1_TXT"),
0093 PINCTRL_PIN(56, "ISH_UART1_RTS_B"),
0094 PINCTRL_PIN(57, "ISH_UART1_CTS_B"),
0095 PINCTRL_PIN(58, "ISH_UART2_RXD"),
0096 PINCTRL_PIN(59, "ISH_UART2_TXD"),
0097 PINCTRL_PIN(60, "ISH_UART2_RTS_B"),
0098 PINCTRL_PIN(61, "ISH_UART2_CTS_B"),
0099 PINCTRL_PIN(62, "GP_CAMERASB00"),
0100 PINCTRL_PIN(63, "GP_CAMERASB01"),
0101 PINCTRL_PIN(64, "GP_CAMERASB02"),
0102 PINCTRL_PIN(65, "GP_CAMERASB03"),
0103 PINCTRL_PIN(66, "GP_CAMERASB04"),
0104 PINCTRL_PIN(67, "GP_CAMERASB05"),
0105 PINCTRL_PIN(68, "GP_CAMERASB06"),
0106 PINCTRL_PIN(69, "GP_CAMERASB07"),
0107 PINCTRL_PIN(70, "GP_CAMERASB08"),
0108 PINCTRL_PIN(71, "GP_CAMERASB09"),
0109 PINCTRL_PIN(72, "GP_CAMERASB10"),
0110 PINCTRL_PIN(73, "GP_CAMERASB11"),
0111 PINCTRL_PIN(74, "TCK"),
0112 PINCTRL_PIN(75, "TRST_B"),
0113 PINCTRL_PIN(76, "TMS"),
0114 PINCTRL_PIN(77, "TDI"),
0115 PINCTRL_PIN(78, "CX_PMODE"),
0116 PINCTRL_PIN(79, "CX_PREQ_B"),
0117 PINCTRL_PIN(80, "JTAGX"),
0118 PINCTRL_PIN(81, "CX_PRDY_B"),
0119 PINCTRL_PIN(82, "TDO"),
0120 };
0121
0122 static const unsigned int bxt_north_pwm0_pins[] = { 34 };
0123 static const unsigned int bxt_north_pwm1_pins[] = { 35 };
0124 static const unsigned int bxt_north_pwm2_pins[] = { 36 };
0125 static const unsigned int bxt_north_pwm3_pins[] = { 37 };
0126 static const unsigned int bxt_north_uart0_pins[] = { 38, 39, 40, 41 };
0127 static const unsigned int bxt_north_uart1_pins[] = { 42, 43, 44, 45 };
0128 static const unsigned int bxt_north_uart2_pins[] = { 46, 47, 48, 49 };
0129 static const unsigned int bxt_north_uart0b_pins[] = { 50, 51, 52, 53 };
0130 static const unsigned int bxt_north_uart1b_pins[] = { 54, 55, 56, 57 };
0131 static const unsigned int bxt_north_uart2b_pins[] = { 58, 59, 60, 61 };
0132 static const unsigned int bxt_north_uart3_pins[] = { 58, 59, 60, 61 };
0133
0134 static const struct intel_pingroup bxt_north_groups[] = {
0135 PIN_GROUP("pwm0_grp", bxt_north_pwm0_pins, 1),
0136 PIN_GROUP("pwm1_grp", bxt_north_pwm1_pins, 1),
0137 PIN_GROUP("pwm2_grp", bxt_north_pwm2_pins, 1),
0138 PIN_GROUP("pwm3_grp", bxt_north_pwm3_pins, 1),
0139 PIN_GROUP("uart0_grp", bxt_north_uart0_pins, 1),
0140 PIN_GROUP("uart1_grp", bxt_north_uart1_pins, 1),
0141 PIN_GROUP("uart2_grp", bxt_north_uart2_pins, 1),
0142 PIN_GROUP("uart0b_grp", bxt_north_uart0b_pins, 2),
0143 PIN_GROUP("uart1b_grp", bxt_north_uart1b_pins, 2),
0144 PIN_GROUP("uart2b_grp", bxt_north_uart2b_pins, 2),
0145 PIN_GROUP("uart3_grp", bxt_north_uart3_pins, 3),
0146 };
0147
0148 static const char * const bxt_north_pwm0_groups[] = { "pwm0_grp" };
0149 static const char * const bxt_north_pwm1_groups[] = { "pwm1_grp" };
0150 static const char * const bxt_north_pwm2_groups[] = { "pwm2_grp" };
0151 static const char * const bxt_north_pwm3_groups[] = { "pwm3_grp" };
0152 static const char * const bxt_north_uart0_groups[] = {
0153 "uart0_grp", "uart0b_grp",
0154 };
0155 static const char * const bxt_north_uart1_groups[] = {
0156 "uart1_grp", "uart1b_grp",
0157 };
0158 static const char * const bxt_north_uart2_groups[] = {
0159 "uart2_grp", "uart2b_grp",
0160 };
0161 static const char * const bxt_north_uart3_groups[] = { "uart3_grp" };
0162
0163 static const struct intel_function bxt_north_functions[] = {
0164 FUNCTION("pwm0", bxt_north_pwm0_groups),
0165 FUNCTION("pwm1", bxt_north_pwm1_groups),
0166 FUNCTION("pwm2", bxt_north_pwm2_groups),
0167 FUNCTION("pwm3", bxt_north_pwm3_groups),
0168 FUNCTION("uart0", bxt_north_uart0_groups),
0169 FUNCTION("uart1", bxt_north_uart1_groups),
0170 FUNCTION("uart2", bxt_north_uart2_groups),
0171 FUNCTION("uart3", bxt_north_uart3_groups),
0172 };
0173
0174 static const struct intel_community bxt_north_communities[] = {
0175 BXT_COMMUNITY(0, 82),
0176 };
0177
0178 static const struct intel_pinctrl_soc_data bxt_north_soc_data = {
0179 .uid = "1",
0180 .pins = bxt_north_pins,
0181 .npins = ARRAY_SIZE(bxt_north_pins),
0182 .groups = bxt_north_groups,
0183 .ngroups = ARRAY_SIZE(bxt_north_groups),
0184 .functions = bxt_north_functions,
0185 .nfunctions = ARRAY_SIZE(bxt_north_functions),
0186 .communities = bxt_north_communities,
0187 .ncommunities = ARRAY_SIZE(bxt_north_communities),
0188 };
0189
0190 static const struct pinctrl_pin_desc bxt_northwest_pins[] = {
0191 PINCTRL_PIN(0, "PMC_SPI_FS0"),
0192 PINCTRL_PIN(1, "PMC_SPI_FS1"),
0193 PINCTRL_PIN(2, "PMC_SPI_FS2"),
0194 PINCTRL_PIN(3, "PMC_SPI_RXD"),
0195 PINCTRL_PIN(4, "PMC_SPI_TXD"),
0196 PINCTRL_PIN(5, "PMC_SPI_CLK"),
0197 PINCTRL_PIN(6, "PMC_UART_RXD"),
0198 PINCTRL_PIN(7, "PMC_UART_TXD"),
0199 PINCTRL_PIN(8, "PMIC_PWRGOOD"),
0200 PINCTRL_PIN(9, "PMIC_RESET_B"),
0201 PINCTRL_PIN(10, "RTC_CLK"),
0202 PINCTRL_PIN(11, "PMIC_SDWN_B"),
0203 PINCTRL_PIN(12, "PMIC_BCUDISW2"),
0204 PINCTRL_PIN(13, "PMIC_BCUDISCRIT"),
0205 PINCTRL_PIN(14, "PMIC_THERMTRIP_B"),
0206 PINCTRL_PIN(15, "PMIC_STDBY"),
0207 PINCTRL_PIN(16, "SVID0_ALERT_B"),
0208 PINCTRL_PIN(17, "SVID0_DATA"),
0209 PINCTRL_PIN(18, "SVID0_CLK"),
0210 PINCTRL_PIN(19, "PMIC_I2C_SCL"),
0211 PINCTRL_PIN(20, "PMIC_I2C_SDA"),
0212 PINCTRL_PIN(21, "AVS_I2S1_MCLK"),
0213 PINCTRL_PIN(22, "AVS_I2S1_BCLK"),
0214 PINCTRL_PIN(23, "AVS_I2S1_WS_SYNC"),
0215 PINCTRL_PIN(24, "AVS_I2S1_SDI"),
0216 PINCTRL_PIN(25, "AVS_I2S1_SDO"),
0217 PINCTRL_PIN(26, "AVS_M_CLK_A1"),
0218 PINCTRL_PIN(27, "AVS_M_CLK_B1"),
0219 PINCTRL_PIN(28, "AVS_M_DATA_1"),
0220 PINCTRL_PIN(29, "AVS_M_CLK_AB2"),
0221 PINCTRL_PIN(30, "AVS_M_DATA_2"),
0222 PINCTRL_PIN(31, "AVS_I2S2_MCLK"),
0223 PINCTRL_PIN(32, "AVS_I2S2_BCLK"),
0224 PINCTRL_PIN(33, "AVS_I2S2_WS_SYNC"),
0225 PINCTRL_PIN(34, "AVS_I2S2_SDI"),
0226 PINCTRL_PIN(35, "AVS_I2S2_SDOK"),
0227 PINCTRL_PIN(36, "AVS_I2S3_BCLK"),
0228 PINCTRL_PIN(37, "AVS_I2S3_WS_SYNC"),
0229 PINCTRL_PIN(38, "AVS_I2S3_SDI"),
0230 PINCTRL_PIN(39, "AVS_I2S3_SDO"),
0231 PINCTRL_PIN(40, "AVS_I2S4_BCLK"),
0232 PINCTRL_PIN(41, "AVS_I2S4_WS_SYNC"),
0233 PINCTRL_PIN(42, "AVS_I2S4_SDI"),
0234 PINCTRL_PIN(43, "AVS_I2S4_SDO"),
0235 PINCTRL_PIN(44, "PROCHOT_B"),
0236 PINCTRL_PIN(45, "FST_SPI_CS0_B"),
0237 PINCTRL_PIN(46, "FST_SPI_CS1_B"),
0238 PINCTRL_PIN(47, "FST_SPI_MOSI_IO0"),
0239 PINCTRL_PIN(48, "FST_SPI_MISO_IO1"),
0240 PINCTRL_PIN(49, "FST_SPI_IO2"),
0241 PINCTRL_PIN(50, "FST_SPI_IO3"),
0242 PINCTRL_PIN(51, "FST_SPI_CLK"),
0243 PINCTRL_PIN(52, "FST_SPI_CLK_FB"),
0244 PINCTRL_PIN(53, "GP_SSP_0_CLK"),
0245 PINCTRL_PIN(54, "GP_SSP_0_FS0"),
0246 PINCTRL_PIN(55, "GP_SSP_0_FS1"),
0247 PINCTRL_PIN(56, "GP_SSP_0_FS2"),
0248 PINCTRL_PIN(57, "GP_SSP_0_RXD"),
0249 PINCTRL_PIN(58, "GP_SSP_0_TXD"),
0250 PINCTRL_PIN(59, "GP_SSP_1_CLK"),
0251 PINCTRL_PIN(60, "GP_SSP_1_FS0"),
0252 PINCTRL_PIN(61, "GP_SSP_1_FS1"),
0253 PINCTRL_PIN(62, "GP_SSP_1_FS2"),
0254 PINCTRL_PIN(63, "GP_SSP_1_FS3"),
0255 PINCTRL_PIN(64, "GP_SSP_1_RXD"),
0256 PINCTRL_PIN(65, "GP_SSP_1_TXD"),
0257 PINCTRL_PIN(66, "GP_SSP_2_CLK"),
0258 PINCTRL_PIN(67, "GP_SSP_2_FS0"),
0259 PINCTRL_PIN(68, "GP_SSP_2_FS1"),
0260 PINCTRL_PIN(69, "GP_SSP_2_FS2"),
0261 PINCTRL_PIN(70, "GP_SSP_2_RXD"),
0262 PINCTRL_PIN(71, "GP_SSP_2_TXD"),
0263 };
0264
0265 static const unsigned int bxt_northwest_ssp0_pins[] = { 53, 54, 55, 56, 57, 58 };
0266 static const unsigned int bxt_northwest_ssp1_pins[] = {
0267 59, 60, 61, 62, 63, 64, 65
0268 };
0269 static const unsigned int bxt_northwest_ssp2_pins[] = { 66, 67, 68, 69, 70, 71 };
0270 static const unsigned int bxt_northwest_uart3_pins[] = { 67, 68, 69, 70 };
0271
0272 static const struct intel_pingroup bxt_northwest_groups[] = {
0273 PIN_GROUP("ssp0_grp", bxt_northwest_ssp0_pins, 1),
0274 PIN_GROUP("ssp1_grp", bxt_northwest_ssp1_pins, 1),
0275 PIN_GROUP("ssp2_grp", bxt_northwest_ssp2_pins, 1),
0276 PIN_GROUP("uart3_grp", bxt_northwest_uart3_pins, 2),
0277 };
0278
0279 static const char * const bxt_northwest_ssp0_groups[] = { "ssp0_grp" };
0280 static const char * const bxt_northwest_ssp1_groups[] = { "ssp1_grp" };
0281 static const char * const bxt_northwest_ssp2_groups[] = { "ssp2_grp" };
0282 static const char * const bxt_northwest_uart3_groups[] = { "uart3_grp" };
0283
0284 static const struct intel_function bxt_northwest_functions[] = {
0285 FUNCTION("ssp0", bxt_northwest_ssp0_groups),
0286 FUNCTION("ssp1", bxt_northwest_ssp1_groups),
0287 FUNCTION("ssp2", bxt_northwest_ssp2_groups),
0288 FUNCTION("uart3", bxt_northwest_uart3_groups),
0289 };
0290
0291 static const struct intel_community bxt_northwest_communities[] = {
0292 BXT_COMMUNITY(0, 71),
0293 };
0294
0295 static const struct intel_pinctrl_soc_data bxt_northwest_soc_data = {
0296 .uid = "2",
0297 .pins = bxt_northwest_pins,
0298 .npins = ARRAY_SIZE(bxt_northwest_pins),
0299 .groups = bxt_northwest_groups,
0300 .ngroups = ARRAY_SIZE(bxt_northwest_groups),
0301 .functions = bxt_northwest_functions,
0302 .nfunctions = ARRAY_SIZE(bxt_northwest_functions),
0303 .communities = bxt_northwest_communities,
0304 .ncommunities = ARRAY_SIZE(bxt_northwest_communities),
0305 };
0306
0307 static const struct pinctrl_pin_desc bxt_west_pins[] = {
0308 PINCTRL_PIN(0, "LPSS_I2C0_SDA"),
0309 PINCTRL_PIN(1, "LPSS_I2C0_SCL"),
0310 PINCTRL_PIN(2, "LPSS_I2C1_SDA"),
0311 PINCTRL_PIN(3, "LPSS_I2C1_SCL"),
0312 PINCTRL_PIN(4, "LPSS_I2C2_SDA"),
0313 PINCTRL_PIN(5, "LPSS_I2C2_SCL"),
0314 PINCTRL_PIN(6, "LPSS_I2C3_SDA"),
0315 PINCTRL_PIN(7, "LPSS_I2C3_SCL"),
0316 PINCTRL_PIN(8, "LPSS_I2C4_SDA"),
0317 PINCTRL_PIN(9, "LPSS_I2C4_SCL"),
0318 PINCTRL_PIN(10, "LPSS_I2C5_SDA"),
0319 PINCTRL_PIN(11, "LPSS_I2C5_SCL"),
0320 PINCTRL_PIN(12, "LPSS_I2C6_SDA"),
0321 PINCTRL_PIN(13, "LPSS_I2C6_SCL"),
0322 PINCTRL_PIN(14, "LPSS_I2C7_SDA"),
0323 PINCTRL_PIN(15, "LPSS_I2C7_SCL"),
0324 PINCTRL_PIN(16, "ISH_I2C0_SDA"),
0325 PINCTRL_PIN(17, "ISH_I2C0_SCL"),
0326 PINCTRL_PIN(18, "ISH_I2C1_SDA"),
0327 PINCTRL_PIN(19, "ISH_I2C1_SCL"),
0328 PINCTRL_PIN(20, "ISH_I2C2_SDA"),
0329 PINCTRL_PIN(21, "ISH_I2C2_SCL"),
0330 PINCTRL_PIN(22, "ISH_GPIO_0"),
0331 PINCTRL_PIN(23, "ISH_GPIO_1"),
0332 PINCTRL_PIN(24, "ISH_GPIO_2"),
0333 PINCTRL_PIN(25, "ISH_GPIO_3"),
0334 PINCTRL_PIN(26, "ISH_GPIO_4"),
0335 PINCTRL_PIN(27, "ISH_GPIO_5"),
0336 PINCTRL_PIN(28, "ISH_GPIO_6"),
0337 PINCTRL_PIN(29, "ISH_GPIO_7"),
0338 PINCTRL_PIN(30, "ISH_GPIO_8"),
0339 PINCTRL_PIN(31, "ISH_GPIO_9"),
0340 PINCTRL_PIN(32, "MODEM_CLKREQ"),
0341 PINCTRL_PIN(33, "DGCLKDBG_PMC_0"),
0342 PINCTRL_PIN(34, "DGCLKDBG_PMC_1"),
0343 PINCTRL_PIN(35, "DGCLKDBG_PMC_2"),
0344 PINCTRL_PIN(36, "DGCLKDBG_ICLK_0"),
0345 PINCTRL_PIN(37, "DGCLKDBG_ICLK_1"),
0346 PINCTRL_PIN(38, "OSC_CLK_OUT_0"),
0347 PINCTRL_PIN(39, "OSC_CLK_OUT_1"),
0348 PINCTRL_PIN(40, "OSC_CLK_OUT_2"),
0349 PINCTRL_PIN(41, "OSC_CLK_OUT_3"),
0350 };
0351
0352 static const unsigned int bxt_west_i2c0_pins[] = { 0, 1 };
0353 static const unsigned int bxt_west_i2c1_pins[] = { 2, 3 };
0354 static const unsigned int bxt_west_i2c2_pins[] = { 4, 5 };
0355 static const unsigned int bxt_west_i2c3_pins[] = { 6, 7 };
0356 static const unsigned int bxt_west_i2c4_pins[] = { 8, 9 };
0357 static const unsigned int bxt_west_i2c5_pins[] = { 10, 11 };
0358 static const unsigned int bxt_west_i2c6_pins[] = { 12, 13 };
0359 static const unsigned int bxt_west_i2c7_pins[] = { 14, 15 };
0360 static const unsigned int bxt_west_i2c5b_pins[] = { 16, 17 };
0361 static const unsigned int bxt_west_i2c6b_pins[] = { 18, 19 };
0362 static const unsigned int bxt_west_i2c7b_pins[] = { 20, 21 };
0363
0364 static const struct intel_pingroup bxt_west_groups[] = {
0365 PIN_GROUP("i2c0_grp", bxt_west_i2c0_pins, 1),
0366 PIN_GROUP("i2c1_grp", bxt_west_i2c1_pins, 1),
0367 PIN_GROUP("i2c2_grp", bxt_west_i2c2_pins, 1),
0368 PIN_GROUP("i2c3_grp", bxt_west_i2c3_pins, 1),
0369 PIN_GROUP("i2c4_grp", bxt_west_i2c4_pins, 1),
0370 PIN_GROUP("i2c5_grp", bxt_west_i2c5_pins, 1),
0371 PIN_GROUP("i2c6_grp", bxt_west_i2c6_pins, 1),
0372 PIN_GROUP("i2c7_grp", bxt_west_i2c7_pins, 1),
0373 PIN_GROUP("i2c5b_grp", bxt_west_i2c5b_pins, 2),
0374 PIN_GROUP("i2c6b_grp", bxt_west_i2c6b_pins, 2),
0375 PIN_GROUP("i2c7b_grp", bxt_west_i2c7b_pins, 2),
0376 };
0377
0378 static const char * const bxt_west_i2c0_groups[] = { "i2c0_grp" };
0379 static const char * const bxt_west_i2c1_groups[] = { "i2c1_grp" };
0380 static const char * const bxt_west_i2c2_groups[] = { "i2c2_grp" };
0381 static const char * const bxt_west_i2c3_groups[] = { "i2c3_grp" };
0382 static const char * const bxt_west_i2c4_groups[] = { "i2c4_grp" };
0383 static const char * const bxt_west_i2c5_groups[] = { "i2c5_grp", "i2c5b_grp" };
0384 static const char * const bxt_west_i2c6_groups[] = { "i2c6_grp", "i2c6b_grp" };
0385 static const char * const bxt_west_i2c7_groups[] = { "i2c7_grp", "i2c7b_grp" };
0386
0387 static const struct intel_function bxt_west_functions[] = {
0388 FUNCTION("i2c0", bxt_west_i2c0_groups),
0389 FUNCTION("i2c1", bxt_west_i2c1_groups),
0390 FUNCTION("i2c2", bxt_west_i2c2_groups),
0391 FUNCTION("i2c3", bxt_west_i2c3_groups),
0392 FUNCTION("i2c4", bxt_west_i2c4_groups),
0393 FUNCTION("i2c5", bxt_west_i2c5_groups),
0394 FUNCTION("i2c6", bxt_west_i2c6_groups),
0395 FUNCTION("i2c7", bxt_west_i2c7_groups),
0396 };
0397
0398 static const struct intel_community bxt_west_communities[] = {
0399 BXT_COMMUNITY(0, 41),
0400 };
0401
0402 static const struct intel_pinctrl_soc_data bxt_west_soc_data = {
0403 .uid = "3",
0404 .pins = bxt_west_pins,
0405 .npins = ARRAY_SIZE(bxt_west_pins),
0406 .groups = bxt_west_groups,
0407 .ngroups = ARRAY_SIZE(bxt_west_groups),
0408 .functions = bxt_west_functions,
0409 .nfunctions = ARRAY_SIZE(bxt_west_functions),
0410 .communities = bxt_west_communities,
0411 .ncommunities = ARRAY_SIZE(bxt_west_communities),
0412 };
0413
0414 static const struct pinctrl_pin_desc bxt_southwest_pins[] = {
0415 PINCTRL_PIN(0, "EMMC0_CLK"),
0416 PINCTRL_PIN(1, "EMMC0_D0"),
0417 PINCTRL_PIN(2, "EMMC0_D1"),
0418 PINCTRL_PIN(3, "EMMC0_D2"),
0419 PINCTRL_PIN(4, "EMMC0_D3"),
0420 PINCTRL_PIN(5, "EMMC0_D4"),
0421 PINCTRL_PIN(6, "EMMC0_D5"),
0422 PINCTRL_PIN(7, "EMMC0_D6"),
0423 PINCTRL_PIN(8, "EMMC0_D7"),
0424 PINCTRL_PIN(9, "EMMC0_CMD"),
0425 PINCTRL_PIN(10, "SDIO_CLK"),
0426 PINCTRL_PIN(11, "SDIO_D0"),
0427 PINCTRL_PIN(12, "SDIO_D1"),
0428 PINCTRL_PIN(13, "SDIO_D2"),
0429 PINCTRL_PIN(14, "SDIO_D3"),
0430 PINCTRL_PIN(15, "SDIO_CMD"),
0431 PINCTRL_PIN(16, "SDCARD_CLK"),
0432 PINCTRL_PIN(17, "SDCARD_D0"),
0433 PINCTRL_PIN(18, "SDCARD_D1"),
0434 PINCTRL_PIN(19, "SDCARD_D2"),
0435 PINCTRL_PIN(20, "SDCARD_D3"),
0436 PINCTRL_PIN(21, "SDCARD_CD_B"),
0437 PINCTRL_PIN(22, "SDCARD_CMD"),
0438 PINCTRL_PIN(23, "SDCARD_LVL_CLK_FB"),
0439 PINCTRL_PIN(24, "SDCARD_LVL_CMD_DIR"),
0440 PINCTRL_PIN(25, "SDCARD_LVL_DAT_DIR"),
0441 PINCTRL_PIN(26, "EMMC0_STROBE"),
0442 PINCTRL_PIN(27, "SDIO_PWR_DOWN_B"),
0443 PINCTRL_PIN(28, "SDCARD_PWR_DOWN_B"),
0444 PINCTRL_PIN(29, "SDCARD_LVL_SEL"),
0445 PINCTRL_PIN(30, "SDCARD_LVL_WP"),
0446 };
0447
0448 static const unsigned int bxt_southwest_emmc0_pins[] = {
0449 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 26,
0450 };
0451 static const unsigned int bxt_southwest_sdio_pins[] = {
0452 10, 11, 12, 13, 14, 15, 27,
0453 };
0454 static const unsigned int bxt_southwest_sdcard_pins[] = {
0455 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 28, 29, 30,
0456 };
0457
0458 static const struct intel_pingroup bxt_southwest_groups[] = {
0459 PIN_GROUP("emmc0_grp", bxt_southwest_emmc0_pins, 1),
0460 PIN_GROUP("sdio_grp", bxt_southwest_sdio_pins, 1),
0461 PIN_GROUP("sdcard_grp", bxt_southwest_sdcard_pins, 1),
0462 };
0463
0464 static const char * const bxt_southwest_emmc0_groups[] = { "emmc0_grp" };
0465 static const char * const bxt_southwest_sdio_groups[] = { "sdio_grp" };
0466 static const char * const bxt_southwest_sdcard_groups[] = { "sdcard_grp" };
0467
0468 static const struct intel_function bxt_southwest_functions[] = {
0469 FUNCTION("emmc0", bxt_southwest_emmc0_groups),
0470 FUNCTION("sdio", bxt_southwest_sdio_groups),
0471 FUNCTION("sdcard", bxt_southwest_sdcard_groups),
0472 };
0473
0474 static const struct intel_community bxt_southwest_communities[] = {
0475 BXT_COMMUNITY(0, 30),
0476 };
0477
0478 static const struct intel_pinctrl_soc_data bxt_southwest_soc_data = {
0479 .uid = "4",
0480 .pins = bxt_southwest_pins,
0481 .npins = ARRAY_SIZE(bxt_southwest_pins),
0482 .groups = bxt_southwest_groups,
0483 .ngroups = ARRAY_SIZE(bxt_southwest_groups),
0484 .functions = bxt_southwest_functions,
0485 .nfunctions = ARRAY_SIZE(bxt_southwest_functions),
0486 .communities = bxt_southwest_communities,
0487 .ncommunities = ARRAY_SIZE(bxt_southwest_communities),
0488 };
0489
0490 static const struct pinctrl_pin_desc bxt_south_pins[] = {
0491 PINCTRL_PIN(0, "HV_DDI0_DDC_SDA"),
0492 PINCTRL_PIN(1, "HV_DDI0_DDC_SCL"),
0493 PINCTRL_PIN(2, "HV_DDI1_DDC_SDA"),
0494 PINCTRL_PIN(3, "HV_DDI1_DDC_SCL"),
0495 PINCTRL_PIN(4, "DBI_SDA"),
0496 PINCTRL_PIN(5, "DBI_SCL"),
0497 PINCTRL_PIN(6, "PANEL0_VDDEN"),
0498 PINCTRL_PIN(7, "PANEL0_BKLTEN"),
0499 PINCTRL_PIN(8, "PANEL0_BKLTCTL"),
0500 PINCTRL_PIN(9, "PANEL1_VDDEN"),
0501 PINCTRL_PIN(10, "PANEL1_BKLTEN"),
0502 PINCTRL_PIN(11, "PANEL1_BKLTCTL"),
0503 PINCTRL_PIN(12, "DBI_CSX"),
0504 PINCTRL_PIN(13, "DBI_RESX"),
0505 PINCTRL_PIN(14, "GP_INTD_DSI_TE1"),
0506 PINCTRL_PIN(15, "GP_INTD_DSI_TE2"),
0507 PINCTRL_PIN(16, "USB_OC0_B"),
0508 PINCTRL_PIN(17, "USB_OC1_B"),
0509 PINCTRL_PIN(18, "MEX_WAKE0_B"),
0510 PINCTRL_PIN(19, "MEX_WAKE1_B"),
0511 };
0512
0513 static const struct intel_community bxt_south_communities[] = {
0514 BXT_COMMUNITY(0, 19),
0515 };
0516
0517 static const struct intel_pinctrl_soc_data bxt_south_soc_data = {
0518 .uid = "5",
0519 .pins = bxt_south_pins,
0520 .npins = ARRAY_SIZE(bxt_south_pins),
0521 .communities = bxt_south_communities,
0522 .ncommunities = ARRAY_SIZE(bxt_south_communities),
0523 };
0524
0525 static const struct intel_pinctrl_soc_data *bxt_pinctrl_soc_data[] = {
0526 &bxt_north_soc_data,
0527 &bxt_northwest_soc_data,
0528 &bxt_west_soc_data,
0529 &bxt_southwest_soc_data,
0530 &bxt_south_soc_data,
0531 NULL
0532 };
0533
0534
0535 static const struct pinctrl_pin_desc apl_north_pins[] = {
0536 PINCTRL_PIN(0, "GPIO_0"),
0537 PINCTRL_PIN(1, "GPIO_1"),
0538 PINCTRL_PIN(2, "GPIO_2"),
0539 PINCTRL_PIN(3, "GPIO_3"),
0540 PINCTRL_PIN(4, "GPIO_4"),
0541 PINCTRL_PIN(5, "GPIO_5"),
0542 PINCTRL_PIN(6, "GPIO_6"),
0543 PINCTRL_PIN(7, "GPIO_7"),
0544 PINCTRL_PIN(8, "GPIO_8"),
0545 PINCTRL_PIN(9, "GPIO_9"),
0546 PINCTRL_PIN(10, "GPIO_10"),
0547 PINCTRL_PIN(11, "GPIO_11"),
0548 PINCTRL_PIN(12, "GPIO_12"),
0549 PINCTRL_PIN(13, "GPIO_13"),
0550 PINCTRL_PIN(14, "GPIO_14"),
0551 PINCTRL_PIN(15, "GPIO_15"),
0552 PINCTRL_PIN(16, "GPIO_16"),
0553 PINCTRL_PIN(17, "GPIO_17"),
0554 PINCTRL_PIN(18, "GPIO_18"),
0555 PINCTRL_PIN(19, "GPIO_19"),
0556 PINCTRL_PIN(20, "GPIO_20"),
0557 PINCTRL_PIN(21, "GPIO_21"),
0558 PINCTRL_PIN(22, "GPIO_22"),
0559 PINCTRL_PIN(23, "GPIO_23"),
0560 PINCTRL_PIN(24, "GPIO_24"),
0561 PINCTRL_PIN(25, "GPIO_25"),
0562 PINCTRL_PIN(26, "GPIO_26"),
0563 PINCTRL_PIN(27, "GPIO_27"),
0564 PINCTRL_PIN(28, "GPIO_28"),
0565 PINCTRL_PIN(29, "GPIO_29"),
0566 PINCTRL_PIN(30, "GPIO_30"),
0567 PINCTRL_PIN(31, "GPIO_31"),
0568 PINCTRL_PIN(32, "GPIO_32"),
0569 PINCTRL_PIN(33, "GPIO_33"),
0570 PINCTRL_PIN(34, "PWM0"),
0571 PINCTRL_PIN(35, "PWM1"),
0572 PINCTRL_PIN(36, "PWM2"),
0573 PINCTRL_PIN(37, "PWM3"),
0574 PINCTRL_PIN(38, "LPSS_UART0_RXD"),
0575 PINCTRL_PIN(39, "LPSS_UART0_TXD"),
0576 PINCTRL_PIN(40, "LPSS_UART0_RTS_B"),
0577 PINCTRL_PIN(41, "LPSS_UART0_CTS_B"),
0578 PINCTRL_PIN(42, "LPSS_UART1_RXD"),
0579 PINCTRL_PIN(43, "LPSS_UART1_TXD"),
0580 PINCTRL_PIN(44, "LPSS_UART1_RTS_B"),
0581 PINCTRL_PIN(45, "LPSS_UART1_CTS_B"),
0582 PINCTRL_PIN(46, "LPSS_UART2_RXD"),
0583 PINCTRL_PIN(47, "LPSS_UART2_TXD"),
0584 PINCTRL_PIN(48, "LPSS_UART2_RTS_B"),
0585 PINCTRL_PIN(49, "LPSS_UART2_CTS_B"),
0586 PINCTRL_PIN(50, "GP_CAMERASB00"),
0587 PINCTRL_PIN(51, "GP_CAMERASB01"),
0588 PINCTRL_PIN(52, "GP_CAMERASB02"),
0589 PINCTRL_PIN(53, "GP_CAMERASB03"),
0590 PINCTRL_PIN(54, "GP_CAMERASB04"),
0591 PINCTRL_PIN(55, "GP_CAMERASB05"),
0592 PINCTRL_PIN(56, "GP_CAMERASB06"),
0593 PINCTRL_PIN(57, "GP_CAMERASB07"),
0594 PINCTRL_PIN(58, "GP_CAMERASB08"),
0595 PINCTRL_PIN(59, "GP_CAMERASB09"),
0596 PINCTRL_PIN(60, "GP_CAMERASB10"),
0597 PINCTRL_PIN(61, "GP_CAMERASB11"),
0598 PINCTRL_PIN(62, "TCK"),
0599 PINCTRL_PIN(63, "TRST_B"),
0600 PINCTRL_PIN(64, "TMS"),
0601 PINCTRL_PIN(65, "TDI"),
0602 PINCTRL_PIN(66, "CX_PMODE"),
0603 PINCTRL_PIN(67, "CX_PREQ_B"),
0604 PINCTRL_PIN(68, "JTAGX"),
0605 PINCTRL_PIN(69, "CX_PRDY_B"),
0606 PINCTRL_PIN(70, "TDO"),
0607 PINCTRL_PIN(71, "CNV_BRI_DT"),
0608 PINCTRL_PIN(72, "CNV_BRI_RSP"),
0609 PINCTRL_PIN(73, "CNV_RGI_DT"),
0610 PINCTRL_PIN(74, "CNV_RGI_RSP"),
0611 PINCTRL_PIN(75, "SVID0_ALERT_B"),
0612 PINCTRL_PIN(76, "SVID0_DATA"),
0613 PINCTRL_PIN(77, "SVID0_CLK"),
0614 };
0615
0616 static const unsigned int apl_north_pwm0_pins[] = { 34 };
0617 static const unsigned int apl_north_pwm1_pins[] = { 35 };
0618 static const unsigned int apl_north_pwm2_pins[] = { 36 };
0619 static const unsigned int apl_north_pwm3_pins[] = { 37 };
0620 static const unsigned int apl_north_uart0_pins[] = { 38, 39, 40, 41 };
0621 static const unsigned int apl_north_uart1_pins[] = { 42, 43, 44, 45 };
0622 static const unsigned int apl_north_uart2_pins[] = { 46, 47, 48, 49 };
0623
0624 static const struct intel_pingroup apl_north_groups[] = {
0625 PIN_GROUP("pwm0_grp", apl_north_pwm0_pins, 1),
0626 PIN_GROUP("pwm1_grp", apl_north_pwm1_pins, 1),
0627 PIN_GROUP("pwm2_grp", apl_north_pwm2_pins, 1),
0628 PIN_GROUP("pwm3_grp", apl_north_pwm3_pins, 1),
0629 PIN_GROUP("uart0_grp", apl_north_uart0_pins, 1),
0630 PIN_GROUP("uart1_grp", apl_north_uart1_pins, 1),
0631 PIN_GROUP("uart2_grp", apl_north_uart2_pins, 1),
0632 };
0633
0634 static const char * const apl_north_pwm0_groups[] = { "pwm0_grp" };
0635 static const char * const apl_north_pwm1_groups[] = { "pwm1_grp" };
0636 static const char * const apl_north_pwm2_groups[] = { "pwm2_grp" };
0637 static const char * const apl_north_pwm3_groups[] = { "pwm3_grp" };
0638 static const char * const apl_north_uart0_groups[] = { "uart0_grp" };
0639 static const char * const apl_north_uart1_groups[] = { "uart1_grp" };
0640 static const char * const apl_north_uart2_groups[] = { "uart2_grp" };
0641
0642 static const struct intel_function apl_north_functions[] = {
0643 FUNCTION("pwm0", apl_north_pwm0_groups),
0644 FUNCTION("pwm1", apl_north_pwm1_groups),
0645 FUNCTION("pwm2", apl_north_pwm2_groups),
0646 FUNCTION("pwm3", apl_north_pwm3_groups),
0647 FUNCTION("uart0", apl_north_uart0_groups),
0648 FUNCTION("uart1", apl_north_uart1_groups),
0649 FUNCTION("uart2", apl_north_uart2_groups),
0650 };
0651
0652 static const struct intel_community apl_north_communities[] = {
0653 BXT_COMMUNITY(0, 77),
0654 };
0655
0656 static const struct intel_pinctrl_soc_data apl_north_soc_data = {
0657 .uid = "1",
0658 .pins = apl_north_pins,
0659 .npins = ARRAY_SIZE(apl_north_pins),
0660 .groups = apl_north_groups,
0661 .ngroups = ARRAY_SIZE(apl_north_groups),
0662 .functions = apl_north_functions,
0663 .nfunctions = ARRAY_SIZE(apl_north_functions),
0664 .communities = apl_north_communities,
0665 .ncommunities = ARRAY_SIZE(apl_north_communities),
0666 };
0667
0668 static const struct pinctrl_pin_desc apl_northwest_pins[] = {
0669 PINCTRL_PIN(0, "HV_DDI0_DDC_SDA"),
0670 PINCTRL_PIN(1, "HV_DDI0_DDC_SCL"),
0671 PINCTRL_PIN(2, "HV_DDI1_DDC_SDA"),
0672 PINCTRL_PIN(3, "HV_DDI1_DDC_SCL"),
0673 PINCTRL_PIN(4, "DBI_SDA"),
0674 PINCTRL_PIN(5, "DBI_SCL"),
0675 PINCTRL_PIN(6, "PANEL0_VDDEN"),
0676 PINCTRL_PIN(7, "PANEL0_BKLTEN"),
0677 PINCTRL_PIN(8, "PANEL0_BKLTCTL"),
0678 PINCTRL_PIN(9, "PANEL1_VDDEN"),
0679 PINCTRL_PIN(10, "PANEL1_BKLTEN"),
0680 PINCTRL_PIN(11, "PANEL1_BKLTCTL"),
0681 PINCTRL_PIN(12, "DBI_CSX"),
0682 PINCTRL_PIN(13, "DBI_RESX"),
0683 PINCTRL_PIN(14, "GP_INTD_DSI_TE1"),
0684 PINCTRL_PIN(15, "GP_INTD_DSI_TE2"),
0685 PINCTRL_PIN(16, "USB_OC0_B"),
0686 PINCTRL_PIN(17, "USB_OC1_B"),
0687 PINCTRL_PIN(18, "PMC_SPI_FS0"),
0688 PINCTRL_PIN(19, "PMC_SPI_FS1"),
0689 PINCTRL_PIN(20, "PMC_SPI_FS2"),
0690 PINCTRL_PIN(21, "PMC_SPI_RXD"),
0691 PINCTRL_PIN(22, "PMC_SPI_TXD"),
0692 PINCTRL_PIN(23, "PMC_SPI_CLK"),
0693 PINCTRL_PIN(24, "PMIC_PWRGOOD"),
0694 PINCTRL_PIN(25, "PMIC_RESET_B"),
0695 PINCTRL_PIN(26, "PMIC_SDWN_B"),
0696 PINCTRL_PIN(27, "PMIC_BCUDISW2"),
0697 PINCTRL_PIN(28, "PMIC_BCUDISCRIT"),
0698 PINCTRL_PIN(29, "PMIC_THERMTRIP_B"),
0699 PINCTRL_PIN(30, "PMIC_STDBY"),
0700 PINCTRL_PIN(31, "PROCHOT_B"),
0701 PINCTRL_PIN(32, "PMIC_I2C_SCL"),
0702 PINCTRL_PIN(33, "PMIC_I2C_SDA"),
0703 PINCTRL_PIN(34, "AVS_I2S1_MCLK"),
0704 PINCTRL_PIN(35, "AVS_I2S1_BCLK"),
0705 PINCTRL_PIN(36, "AVS_I2S1_WS_SYNC"),
0706 PINCTRL_PIN(37, "AVS_I2S1_SDI"),
0707 PINCTRL_PIN(38, "AVS_I2S1_SDO"),
0708 PINCTRL_PIN(39, "AVS_M_CLK_A1"),
0709 PINCTRL_PIN(40, "AVS_M_CLK_B1"),
0710 PINCTRL_PIN(41, "AVS_M_DATA_1"),
0711 PINCTRL_PIN(42, "AVS_M_CLK_AB2"),
0712 PINCTRL_PIN(43, "AVS_M_DATA_2"),
0713 PINCTRL_PIN(44, "AVS_I2S2_MCLK"),
0714 PINCTRL_PIN(45, "AVS_I2S2_BCLK"),
0715 PINCTRL_PIN(46, "AVS_I2S2_WS_SYNC"),
0716 PINCTRL_PIN(47, "AVS_I2S2_SDI"),
0717 PINCTRL_PIN(48, "AVS_I2S2_SDO"),
0718 PINCTRL_PIN(49, "AVS_I2S3_BCLK"),
0719 PINCTRL_PIN(50, "AVS_I2S3_WS_SYNC"),
0720 PINCTRL_PIN(51, "AVS_I2S3_SDI"),
0721 PINCTRL_PIN(52, "AVS_I2S3_SDO"),
0722 PINCTRL_PIN(53, "FST_SPI_CS0_B"),
0723 PINCTRL_PIN(54, "FST_SPI_CS1_B"),
0724 PINCTRL_PIN(55, "FST_SPI_MOSI_IO0"),
0725 PINCTRL_PIN(56, "FST_SPI_MISO_IO1"),
0726 PINCTRL_PIN(57, "FST_SPI_IO2"),
0727 PINCTRL_PIN(58, "FST_SPI_IO3"),
0728 PINCTRL_PIN(59, "FST_SPI_CLK"),
0729 PINCTRL_PIN(60, "FST_SPI_CLK_FB"),
0730 PINCTRL_PIN(61, "GP_SSP_0_CLK"),
0731 PINCTRL_PIN(62, "GP_SSP_0_FS0"),
0732 PINCTRL_PIN(63, "GP_SSP_0_FS1"),
0733 PINCTRL_PIN(64, "GP_SSP_0_RXD"),
0734 PINCTRL_PIN(65, "GP_SSP_0_TXD"),
0735 PINCTRL_PIN(66, "GP_SSP_1_CLK"),
0736 PINCTRL_PIN(67, "GP_SSP_1_FS0"),
0737 PINCTRL_PIN(68, "GP_SSP_1_FS1"),
0738 PINCTRL_PIN(69, "GP_SSP_1_RXD"),
0739 PINCTRL_PIN(70, "GP_SSP_1_TXD"),
0740 PINCTRL_PIN(71, "GP_SSP_2_CLK"),
0741 PINCTRL_PIN(72, "GP_SSP_2_FS0"),
0742 PINCTRL_PIN(73, "GP_SSP_2_FS1"),
0743 PINCTRL_PIN(74, "GP_SSP_2_FS2"),
0744 PINCTRL_PIN(75, "GP_SSP_2_RXD"),
0745 PINCTRL_PIN(76, "GP_SSP_2_TXD"),
0746 };
0747
0748 static const unsigned int apl_northwest_ssp0_pins[] = { 61, 62, 63, 64, 65 };
0749 static const unsigned int apl_northwest_ssp1_pins[] = { 66, 67, 68, 69, 70 };
0750 static const unsigned int apl_northwest_ssp2_pins[] = { 71, 72, 73, 74, 75, 76 };
0751 static const unsigned int apl_northwest_uart3_pins[] = { 67, 68, 69, 70 };
0752
0753 static const struct intel_pingroup apl_northwest_groups[] = {
0754 PIN_GROUP("ssp0_grp", apl_northwest_ssp0_pins, 1),
0755 PIN_GROUP("ssp1_grp", apl_northwest_ssp1_pins, 1),
0756 PIN_GROUP("ssp2_grp", apl_northwest_ssp2_pins, 1),
0757 PIN_GROUP("uart3_grp", apl_northwest_uart3_pins, 2),
0758 };
0759
0760 static const char * const apl_northwest_ssp0_groups[] = { "ssp0_grp" };
0761 static const char * const apl_northwest_ssp1_groups[] = { "ssp1_grp" };
0762 static const char * const apl_northwest_ssp2_groups[] = { "ssp2_grp" };
0763 static const char * const apl_northwest_uart3_groups[] = { "uart3_grp" };
0764
0765 static const struct intel_function apl_northwest_functions[] = {
0766 FUNCTION("ssp0", apl_northwest_ssp0_groups),
0767 FUNCTION("ssp1", apl_northwest_ssp1_groups),
0768 FUNCTION("ssp2", apl_northwest_ssp2_groups),
0769 FUNCTION("uart3", apl_northwest_uart3_groups),
0770 };
0771
0772 static const struct intel_community apl_northwest_communities[] = {
0773 BXT_COMMUNITY(0, 76),
0774 };
0775
0776 static const struct intel_pinctrl_soc_data apl_northwest_soc_data = {
0777 .uid = "2",
0778 .pins = apl_northwest_pins,
0779 .npins = ARRAY_SIZE(apl_northwest_pins),
0780 .groups = apl_northwest_groups,
0781 .ngroups = ARRAY_SIZE(apl_northwest_groups),
0782 .functions = apl_northwest_functions,
0783 .nfunctions = ARRAY_SIZE(apl_northwest_functions),
0784 .communities = apl_northwest_communities,
0785 .ncommunities = ARRAY_SIZE(apl_northwest_communities),
0786 };
0787
0788 static const struct pinctrl_pin_desc apl_west_pins[] = {
0789 PINCTRL_PIN(0, "LPSS_I2C0_SDA"),
0790 PINCTRL_PIN(1, "LPSS_I2C0_SCL"),
0791 PINCTRL_PIN(2, "LPSS_I2C1_SDA"),
0792 PINCTRL_PIN(3, "LPSS_I2C1_SCL"),
0793 PINCTRL_PIN(4, "LPSS_I2C2_SDA"),
0794 PINCTRL_PIN(5, "LPSS_I2C2_SCL"),
0795 PINCTRL_PIN(6, "LPSS_I2C3_SDA"),
0796 PINCTRL_PIN(7, "LPSS_I2C3_SCL"),
0797 PINCTRL_PIN(8, "LPSS_I2C4_SDA"),
0798 PINCTRL_PIN(9, "LPSS_I2C4_SCL"),
0799 PINCTRL_PIN(10, "LPSS_I2C5_SDA"),
0800 PINCTRL_PIN(11, "LPSS_I2C5_SCL"),
0801 PINCTRL_PIN(12, "LPSS_I2C6_SDA"),
0802 PINCTRL_PIN(13, "LPSS_I2C6_SCL"),
0803 PINCTRL_PIN(14, "LPSS_I2C7_SDA"),
0804 PINCTRL_PIN(15, "LPSS_I2C7_SCL"),
0805 PINCTRL_PIN(16, "ISH_GPIO_0"),
0806 PINCTRL_PIN(17, "ISH_GPIO_1"),
0807 PINCTRL_PIN(18, "ISH_GPIO_2"),
0808 PINCTRL_PIN(19, "ISH_GPIO_3"),
0809 PINCTRL_PIN(20, "ISH_GPIO_4"),
0810 PINCTRL_PIN(21, "ISH_GPIO_5"),
0811 PINCTRL_PIN(22, "ISH_GPIO_6"),
0812 PINCTRL_PIN(23, "ISH_GPIO_7"),
0813 PINCTRL_PIN(24, "ISH_GPIO_8"),
0814 PINCTRL_PIN(25, "ISH_GPIO_9"),
0815 PINCTRL_PIN(26, "PCIE_CLKREQ0_B"),
0816 PINCTRL_PIN(27, "PCIE_CLKREQ1_B"),
0817 PINCTRL_PIN(28, "PCIE_CLKREQ2_B"),
0818 PINCTRL_PIN(29, "PCIE_CLKREQ3_B"),
0819 PINCTRL_PIN(30, "OSC_CLK_OUT_0"),
0820 PINCTRL_PIN(31, "OSC_CLK_OUT_1"),
0821 PINCTRL_PIN(32, "OSC_CLK_OUT_2"),
0822 PINCTRL_PIN(33, "OSC_CLK_OUT_3"),
0823 PINCTRL_PIN(34, "OSC_CLK_OUT_4"),
0824 PINCTRL_PIN(35, "PMU_AC_PRESENT"),
0825 PINCTRL_PIN(36, "PMU_BATLOW_B"),
0826 PINCTRL_PIN(37, "PMU_PLTRST_B"),
0827 PINCTRL_PIN(38, "PMU_PWRBTN_B"),
0828 PINCTRL_PIN(39, "PMU_RESETBUTTON_B"),
0829 PINCTRL_PIN(40, "PMU_SLP_S0_B"),
0830 PINCTRL_PIN(41, "PMU_SLP_S3_B"),
0831 PINCTRL_PIN(42, "PMU_SLP_S4_B"),
0832 PINCTRL_PIN(43, "PMU_SUSCLK"),
0833 PINCTRL_PIN(44, "PMU_WAKE_B"),
0834 PINCTRL_PIN(45, "SUS_STAT_B"),
0835 PINCTRL_PIN(46, "SUSPWRDNACK"),
0836 };
0837
0838 static const unsigned int apl_west_i2c0_pins[] = { 0, 1 };
0839 static const unsigned int apl_west_i2c1_pins[] = { 2, 3 };
0840 static const unsigned int apl_west_i2c2_pins[] = { 4, 5 };
0841 static const unsigned int apl_west_i2c3_pins[] = { 6, 7 };
0842 static const unsigned int apl_west_i2c4_pins[] = { 8, 9 };
0843 static const unsigned int apl_west_i2c5_pins[] = { 10, 11 };
0844 static const unsigned int apl_west_i2c6_pins[] = { 12, 13 };
0845 static const unsigned int apl_west_i2c7_pins[] = { 14, 15 };
0846 static const unsigned int apl_west_uart2_pins[] = { 20, 21, 22, 34 };
0847
0848 static const struct intel_pingroup apl_west_groups[] = {
0849 PIN_GROUP("i2c0_grp", apl_west_i2c0_pins, 1),
0850 PIN_GROUP("i2c1_grp", apl_west_i2c1_pins, 1),
0851 PIN_GROUP("i2c2_grp", apl_west_i2c2_pins, 1),
0852 PIN_GROUP("i2c3_grp", apl_west_i2c3_pins, 1),
0853 PIN_GROUP("i2c4_grp", apl_west_i2c4_pins, 1),
0854 PIN_GROUP("i2c5_grp", apl_west_i2c5_pins, 1),
0855 PIN_GROUP("i2c6_grp", apl_west_i2c6_pins, 1),
0856 PIN_GROUP("i2c7_grp", apl_west_i2c7_pins, 1),
0857 PIN_GROUP("uart2_grp", apl_west_uart2_pins, 3),
0858 };
0859
0860 static const char * const apl_west_i2c0_groups[] = { "i2c0_grp" };
0861 static const char * const apl_west_i2c1_groups[] = { "i2c1_grp" };
0862 static const char * const apl_west_i2c2_groups[] = { "i2c2_grp" };
0863 static const char * const apl_west_i2c3_groups[] = { "i2c3_grp" };
0864 static const char * const apl_west_i2c4_groups[] = { "i2c4_grp" };
0865 static const char * const apl_west_i2c5_groups[] = { "i2c5_grp" };
0866 static const char * const apl_west_i2c6_groups[] = { "i2c6_grp" };
0867 static const char * const apl_west_i2c7_groups[] = { "i2c7_grp" };
0868 static const char * const apl_west_uart2_groups[] = { "uart2_grp" };
0869
0870 static const struct intel_function apl_west_functions[] = {
0871 FUNCTION("i2c0", apl_west_i2c0_groups),
0872 FUNCTION("i2c1", apl_west_i2c1_groups),
0873 FUNCTION("i2c2", apl_west_i2c2_groups),
0874 FUNCTION("i2c3", apl_west_i2c3_groups),
0875 FUNCTION("i2c4", apl_west_i2c4_groups),
0876 FUNCTION("i2c5", apl_west_i2c5_groups),
0877 FUNCTION("i2c6", apl_west_i2c6_groups),
0878 FUNCTION("i2c7", apl_west_i2c7_groups),
0879 FUNCTION("uart2", apl_west_uart2_groups),
0880 };
0881
0882 static const struct intel_community apl_west_communities[] = {
0883 BXT_COMMUNITY(0, 46),
0884 };
0885
0886 static const struct intel_pinctrl_soc_data apl_west_soc_data = {
0887 .uid = "3",
0888 .pins = apl_west_pins,
0889 .npins = ARRAY_SIZE(apl_west_pins),
0890 .groups = apl_west_groups,
0891 .ngroups = ARRAY_SIZE(apl_west_groups),
0892 .functions = apl_west_functions,
0893 .nfunctions = ARRAY_SIZE(apl_west_functions),
0894 .communities = apl_west_communities,
0895 .ncommunities = ARRAY_SIZE(apl_west_communities),
0896 };
0897
0898 static const struct pinctrl_pin_desc apl_southwest_pins[] = {
0899 PINCTRL_PIN(0, "PCIE_WAKE0_B"),
0900 PINCTRL_PIN(1, "PCIE_WAKE1_B"),
0901 PINCTRL_PIN(2, "PCIE_WAKE2_B"),
0902 PINCTRL_PIN(3, "PCIE_WAKE3_B"),
0903 PINCTRL_PIN(4, "EMMC0_CLK"),
0904 PINCTRL_PIN(5, "EMMC0_D0"),
0905 PINCTRL_PIN(6, "EMMC0_D1"),
0906 PINCTRL_PIN(7, "EMMC0_D2"),
0907 PINCTRL_PIN(8, "EMMC0_D3"),
0908 PINCTRL_PIN(9, "EMMC0_D4"),
0909 PINCTRL_PIN(10, "EMMC0_D5"),
0910 PINCTRL_PIN(11, "EMMC0_D6"),
0911 PINCTRL_PIN(12, "EMMC0_D7"),
0912 PINCTRL_PIN(13, "EMMC0_CMD"),
0913 PINCTRL_PIN(14, "SDIO_CLK"),
0914 PINCTRL_PIN(15, "SDIO_D0"),
0915 PINCTRL_PIN(16, "SDIO_D1"),
0916 PINCTRL_PIN(17, "SDIO_D2"),
0917 PINCTRL_PIN(18, "SDIO_D3"),
0918 PINCTRL_PIN(19, "SDIO_CMD"),
0919 PINCTRL_PIN(20, "SDCARD_CLK"),
0920 PINCTRL_PIN(21, "SDCARD_CLK_FB"),
0921 PINCTRL_PIN(22, "SDCARD_D0"),
0922 PINCTRL_PIN(23, "SDCARD_D1"),
0923 PINCTRL_PIN(24, "SDCARD_D2"),
0924 PINCTRL_PIN(25, "SDCARD_D3"),
0925 PINCTRL_PIN(26, "SDCARD_CD_B"),
0926 PINCTRL_PIN(27, "SDCARD_CMD"),
0927 PINCTRL_PIN(28, "SDCARD_LVL_WP"),
0928 PINCTRL_PIN(29, "EMMC0_STROBE"),
0929 PINCTRL_PIN(30, "SDIO_PWR_DOWN_B"),
0930 PINCTRL_PIN(31, "SMB_ALERTB"),
0931 PINCTRL_PIN(32, "SMB_CLK"),
0932 PINCTRL_PIN(33, "SMB_DATA"),
0933 PINCTRL_PIN(34, "LPC_ILB_SERIRQ"),
0934 PINCTRL_PIN(35, "LPC_CLKOUT0"),
0935 PINCTRL_PIN(36, "LPC_CLKOUT1"),
0936 PINCTRL_PIN(37, "LPC_AD0"),
0937 PINCTRL_PIN(38, "LPC_AD1"),
0938 PINCTRL_PIN(39, "LPC_AD2"),
0939 PINCTRL_PIN(40, "LPC_AD3"),
0940 PINCTRL_PIN(41, "LPC_CLKRUNB"),
0941 PINCTRL_PIN(42, "LPC_FRAMEB"),
0942 };
0943
0944 static const unsigned int apl_southwest_emmc0_pins[] = {
0945 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 29,
0946 };
0947 static const unsigned int apl_southwest_sdio_pins[] = {
0948 14, 15, 16, 17, 18, 19, 30,
0949 };
0950 static const unsigned int apl_southwest_sdcard_pins[] = {
0951 20, 21, 22, 23, 24, 25, 26, 27, 28,
0952 };
0953 static const unsigned int apl_southwest_i2c7_pins[] = { 32, 33 };
0954
0955 static const struct intel_pingroup apl_southwest_groups[] = {
0956 PIN_GROUP("emmc0_grp", apl_southwest_emmc0_pins, 1),
0957 PIN_GROUP("sdio_grp", apl_southwest_sdio_pins, 1),
0958 PIN_GROUP("sdcard_grp", apl_southwest_sdcard_pins, 1),
0959 PIN_GROUP("i2c7_grp", apl_southwest_i2c7_pins, 2),
0960 };
0961
0962 static const char * const apl_southwest_emmc0_groups[] = { "emmc0_grp" };
0963 static const char * const apl_southwest_sdio_groups[] = { "sdio_grp" };
0964 static const char * const apl_southwest_sdcard_groups[] = { "sdcard_grp" };
0965 static const char * const apl_southwest_i2c7_groups[] = { "i2c7_grp" };
0966
0967 static const struct intel_function apl_southwest_functions[] = {
0968 FUNCTION("emmc0", apl_southwest_emmc0_groups),
0969 FUNCTION("sdio", apl_southwest_sdio_groups),
0970 FUNCTION("sdcard", apl_southwest_sdcard_groups),
0971 FUNCTION("i2c7", apl_southwest_i2c7_groups),
0972 };
0973
0974 static const struct intel_community apl_southwest_communities[] = {
0975 BXT_COMMUNITY(0, 42),
0976 };
0977
0978 static const struct intel_pinctrl_soc_data apl_southwest_soc_data = {
0979 .uid = "4",
0980 .pins = apl_southwest_pins,
0981 .npins = ARRAY_SIZE(apl_southwest_pins),
0982 .groups = apl_southwest_groups,
0983 .ngroups = ARRAY_SIZE(apl_southwest_groups),
0984 .functions = apl_southwest_functions,
0985 .nfunctions = ARRAY_SIZE(apl_southwest_functions),
0986 .communities = apl_southwest_communities,
0987 .ncommunities = ARRAY_SIZE(apl_southwest_communities),
0988 };
0989
0990 static const struct intel_pinctrl_soc_data *apl_pinctrl_soc_data[] = {
0991 &apl_north_soc_data,
0992 &apl_northwest_soc_data,
0993 &apl_west_soc_data,
0994 &apl_southwest_soc_data,
0995 NULL
0996 };
0997
0998 static const struct acpi_device_id bxt_pinctrl_acpi_match[] = {
0999 { "INT3452", (kernel_ulong_t)apl_pinctrl_soc_data },
1000 { "INT34D1", (kernel_ulong_t)bxt_pinctrl_soc_data },
1001 { }
1002 };
1003 MODULE_DEVICE_TABLE(acpi, bxt_pinctrl_acpi_match);
1004
1005 static const struct platform_device_id bxt_pinctrl_platform_ids[] = {
1006 { "apollolake-pinctrl", (kernel_ulong_t)apl_pinctrl_soc_data },
1007 { "broxton-pinctrl", (kernel_ulong_t)bxt_pinctrl_soc_data },
1008 { }
1009 };
1010
1011 static INTEL_PINCTRL_PM_OPS(bxt_pinctrl_pm_ops);
1012
1013 static struct platform_driver bxt_pinctrl_driver = {
1014 .probe = intel_pinctrl_probe_by_uid,
1015 .driver = {
1016 .name = "broxton-pinctrl",
1017 .acpi_match_table = bxt_pinctrl_acpi_match,
1018 .pm = &bxt_pinctrl_pm_ops,
1019 },
1020 .id_table = bxt_pinctrl_platform_ids,
1021 };
1022
1023 static int __init bxt_pinctrl_init(void)
1024 {
1025 return platform_driver_register(&bxt_pinctrl_driver);
1026 }
1027 subsys_initcall(bxt_pinctrl_init);
1028
1029 static void __exit bxt_pinctrl_exit(void)
1030 {
1031 platform_driver_unregister(&bxt_pinctrl_driver);
1032 }
1033 module_exit(bxt_pinctrl_exit);
1034
1035 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1036 MODULE_DESCRIPTION("Intel Broxton SoC pinctrl/GPIO driver");
1037 MODULE_LICENSE("GPL v2");
1038 MODULE_ALIAS("platform:apollolake-pinctrl");
1039 MODULE_ALIAS("platform:broxton-pinctrl");
