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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Pinctrl GPIO driver for Intel Baytrail
0004  *
0005  * Copyright (c) 2012-2013, Intel Corporation
0006  * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
0007  */
0008 
0009 #include <linux/acpi.h>
0010 #include <linux/bitops.h>
0011 #include <linux/gpio/driver.h>
0012 #include <linux/init.h>
0013 #include <linux/interrupt.h>
0014 #include <linux/io.h>
0015 #include <linux/kernel.h>
0016 #include <linux/types.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/pm_runtime.h>
0019 #include <linux/property.h>
0020 #include <linux/seq_file.h>
0021 
0022 #include <linux/pinctrl/pinctrl.h>
0023 #include <linux/pinctrl/pinmux.h>
0024 #include <linux/pinctrl/pinconf.h>
0025 #include <linux/pinctrl/pinconf-generic.h>
0026 
0027 #include "pinctrl-intel.h"
0028 
0029 /* memory mapped register offsets */
0030 #define BYT_CONF0_REG       0x000
0031 #define BYT_CONF1_REG       0x004
0032 #define BYT_VAL_REG     0x008
0033 #define BYT_DFT_REG     0x00c
0034 #define BYT_INT_STAT_REG    0x800
0035 #define BYT_DIRECT_IRQ_REG  0x980
0036 #define BYT_DEBOUNCE_REG    0x9d0
0037 
0038 /* BYT_CONF0_REG register bits */
0039 #define BYT_IODEN       BIT(31)
0040 #define BYT_DIRECT_IRQ_EN   BIT(27)
0041 #define BYT_TRIG_MASK       GENMASK(26, 24)
0042 #define BYT_TRIG_NEG        BIT(26)
0043 #define BYT_TRIG_POS        BIT(25)
0044 #define BYT_TRIG_LVL        BIT(24)
0045 #define BYT_DEBOUNCE_EN     BIT(20)
0046 #define BYT_GLITCH_FILTER_EN    BIT(19)
0047 #define BYT_GLITCH_F_SLOW_CLK   BIT(17)
0048 #define BYT_GLITCH_F_FAST_CLK   BIT(16)
0049 #define BYT_PULL_STR_SHIFT  9
0050 #define BYT_PULL_STR_MASK   GENMASK(10, 9)
0051 #define BYT_PULL_STR_2K     (0 << BYT_PULL_STR_SHIFT)
0052 #define BYT_PULL_STR_10K    (1 << BYT_PULL_STR_SHIFT)
0053 #define BYT_PULL_STR_20K    (2 << BYT_PULL_STR_SHIFT)
0054 #define BYT_PULL_STR_40K    (3 << BYT_PULL_STR_SHIFT)
0055 #define BYT_PULL_ASSIGN_SHIFT   7
0056 #define BYT_PULL_ASSIGN_MASK    GENMASK(8, 7)
0057 #define BYT_PULL_ASSIGN_UP  (1 << BYT_PULL_ASSIGN_SHIFT)
0058 #define BYT_PULL_ASSIGN_DOWN    (2 << BYT_PULL_ASSIGN_SHIFT)
0059 #define BYT_PIN_MUX     GENMASK(2, 0)
0060 
0061 /* BYT_VAL_REG register bits */
0062 #define BYT_DIR_MASK        GENMASK(2, 1)
0063 #define BYT_INPUT_EN        BIT(2)  /* 0: input enabled (active low)*/
0064 #define BYT_OUTPUT_EN       BIT(1)  /* 0: output enabled (active low)*/
0065 #define BYT_LEVEL       BIT(0)
0066 
0067 #define BYT_CONF0_RESTORE_MASK  (BYT_DIRECT_IRQ_EN | BYT_TRIG_MASK | BYT_PIN_MUX)
0068 #define BYT_VAL_RESTORE_MASK    (BYT_DIR_MASK | BYT_LEVEL)
0069 
0070 /* BYT_DEBOUNCE_REG bits */
0071 #define BYT_DEBOUNCE_PULSE_MASK     GENMASK(2, 0)
0072 #define BYT_DEBOUNCE_PULSE_375US    1
0073 #define BYT_DEBOUNCE_PULSE_750US    2
0074 #define BYT_DEBOUNCE_PULSE_1500US   3
0075 #define BYT_DEBOUNCE_PULSE_3MS      4
0076 #define BYT_DEBOUNCE_PULSE_6MS      5
0077 #define BYT_DEBOUNCE_PULSE_12MS     6
0078 #define BYT_DEBOUNCE_PULSE_24MS     7
0079 
0080 #define BYT_NGPIO_SCORE     102
0081 #define BYT_NGPIO_NCORE     28
0082 #define BYT_NGPIO_SUS       44
0083 
0084 #define BYT_SCORE_ACPI_UID  "1"
0085 #define BYT_NCORE_ACPI_UID  "2"
0086 #define BYT_SUS_ACPI_UID    "3"
0087 
0088 /*
0089  * This is the function value most pins have for GPIO muxing. If the value
0090  * differs from the default one, it must be explicitly mentioned. Otherwise, the
0091  * pin control implementation will set the muxing value to default GPIO if it
0092  * does not find a match for the requested function.
0093  */
0094 #define BYT_DEFAULT_GPIO_MUX    0
0095 #define BYT_ALTER_GPIO_MUX  1
0096 
0097 struct intel_pad_context {
0098     u32 conf0;
0099     u32 val;
0100 };
0101 
0102 #define COMMUNITY(p, n, map)        \
0103     {               \
0104         .pin_base   = (p),  \
0105         .npins      = (n),  \
0106         .pad_map    = (map),\
0107     }
0108 
0109 /* SCORE pins, aka GPIOC_<pin_no> or GPIO_S0_SC[<pin_no>] */
0110 static const struct pinctrl_pin_desc byt_score_pins[] = {
0111     PINCTRL_PIN(0, "SATA_GP0"),
0112     PINCTRL_PIN(1, "SATA_GP1"),
0113     PINCTRL_PIN(2, "SATA_LED#"),
0114     PINCTRL_PIN(3, "PCIE_CLKREQ0"),
0115     PINCTRL_PIN(4, "PCIE_CLKREQ1"),
0116     PINCTRL_PIN(5, "PCIE_CLKREQ2"),
0117     PINCTRL_PIN(6, "PCIE_CLKREQ3"),
0118     PINCTRL_PIN(7, "SD3_WP"),
0119     PINCTRL_PIN(8, "HDA_RST"),
0120     PINCTRL_PIN(9, "HDA_SYNC"),
0121     PINCTRL_PIN(10, "HDA_CLK"),
0122     PINCTRL_PIN(11, "HDA_SDO"),
0123     PINCTRL_PIN(12, "HDA_SDI0"),
0124     PINCTRL_PIN(13, "HDA_SDI1"),
0125     PINCTRL_PIN(14, "GPIO_S0_SC14"),
0126     PINCTRL_PIN(15, "GPIO_S0_SC15"),
0127     PINCTRL_PIN(16, "MMC1_CLK"),
0128     PINCTRL_PIN(17, "MMC1_D0"),
0129     PINCTRL_PIN(18, "MMC1_D1"),
0130     PINCTRL_PIN(19, "MMC1_D2"),
0131     PINCTRL_PIN(20, "MMC1_D3"),
0132     PINCTRL_PIN(21, "MMC1_D4"),
0133     PINCTRL_PIN(22, "MMC1_D5"),
0134     PINCTRL_PIN(23, "MMC1_D6"),
0135     PINCTRL_PIN(24, "MMC1_D7"),
0136     PINCTRL_PIN(25, "MMC1_CMD"),
0137     PINCTRL_PIN(26, "MMC1_RST"),
0138     PINCTRL_PIN(27, "SD2_CLK"),
0139     PINCTRL_PIN(28, "SD2_D0"),
0140     PINCTRL_PIN(29, "SD2_D1"),
0141     PINCTRL_PIN(30, "SD2_D2"),
0142     PINCTRL_PIN(31, "SD2_D3_CD"),
0143     PINCTRL_PIN(32, "SD2_CMD"),
0144     PINCTRL_PIN(33, "SD3_CLK"),
0145     PINCTRL_PIN(34, "SD3_D0"),
0146     PINCTRL_PIN(35, "SD3_D1"),
0147     PINCTRL_PIN(36, "SD3_D2"),
0148     PINCTRL_PIN(37, "SD3_D3"),
0149     PINCTRL_PIN(38, "SD3_CD"),
0150     PINCTRL_PIN(39, "SD3_CMD"),
0151     PINCTRL_PIN(40, "SD3_1P8EN"),
0152     PINCTRL_PIN(41, "SD3_PWREN#"),
0153     PINCTRL_PIN(42, "ILB_LPC_AD0"),
0154     PINCTRL_PIN(43, "ILB_LPC_AD1"),
0155     PINCTRL_PIN(44, "ILB_LPC_AD2"),
0156     PINCTRL_PIN(45, "ILB_LPC_AD3"),
0157     PINCTRL_PIN(46, "ILB_LPC_FRAME"),
0158     PINCTRL_PIN(47, "ILB_LPC_CLK0"),
0159     PINCTRL_PIN(48, "ILB_LPC_CLK1"),
0160     PINCTRL_PIN(49, "ILB_LPC_CLKRUN"),
0161     PINCTRL_PIN(50, "ILB_LPC_SERIRQ"),
0162     PINCTRL_PIN(51, "PCU_SMB_DATA"),
0163     PINCTRL_PIN(52, "PCU_SMB_CLK"),
0164     PINCTRL_PIN(53, "PCU_SMB_ALERT"),
0165     PINCTRL_PIN(54, "ILB_8254_SPKR"),
0166     PINCTRL_PIN(55, "GPIO_S0_SC55"),
0167     PINCTRL_PIN(56, "GPIO_S0_SC56"),
0168     PINCTRL_PIN(57, "GPIO_S0_SC57"),
0169     PINCTRL_PIN(58, "GPIO_S0_SC58"),
0170     PINCTRL_PIN(59, "GPIO_S0_SC59"),
0171     PINCTRL_PIN(60, "GPIO_S0_SC60"),
0172     PINCTRL_PIN(61, "GPIO_S0_SC61"),
0173     PINCTRL_PIN(62, "LPE_I2S2_CLK"),
0174     PINCTRL_PIN(63, "LPE_I2S2_FRM"),
0175     PINCTRL_PIN(64, "LPE_I2S2_DATAIN"),
0176     PINCTRL_PIN(65, "LPE_I2S2_DATAOUT"),
0177     PINCTRL_PIN(66, "SIO_SPI_CS"),
0178     PINCTRL_PIN(67, "SIO_SPI_MISO"),
0179     PINCTRL_PIN(68, "SIO_SPI_MOSI"),
0180     PINCTRL_PIN(69, "SIO_SPI_CLK"),
0181     PINCTRL_PIN(70, "SIO_UART1_RXD"),
0182     PINCTRL_PIN(71, "SIO_UART1_TXD"),
0183     PINCTRL_PIN(72, "SIO_UART1_RTS"),
0184     PINCTRL_PIN(73, "SIO_UART1_CTS"),
0185     PINCTRL_PIN(74, "SIO_UART2_RXD"),
0186     PINCTRL_PIN(75, "SIO_UART2_TXD"),
0187     PINCTRL_PIN(76, "SIO_UART2_RTS"),
0188     PINCTRL_PIN(77, "SIO_UART2_CTS"),
0189     PINCTRL_PIN(78, "SIO_I2C0_DATA"),
0190     PINCTRL_PIN(79, "SIO_I2C0_CLK"),
0191     PINCTRL_PIN(80, "SIO_I2C1_DATA"),
0192     PINCTRL_PIN(81, "SIO_I2C1_CLK"),
0193     PINCTRL_PIN(82, "SIO_I2C2_DATA"),
0194     PINCTRL_PIN(83, "SIO_I2C2_CLK"),
0195     PINCTRL_PIN(84, "SIO_I2C3_DATA"),
0196     PINCTRL_PIN(85, "SIO_I2C3_CLK"),
0197     PINCTRL_PIN(86, "SIO_I2C4_DATA"),
0198     PINCTRL_PIN(87, "SIO_I2C4_CLK"),
0199     PINCTRL_PIN(88, "SIO_I2C5_DATA"),
0200     PINCTRL_PIN(89, "SIO_I2C5_CLK"),
0201     PINCTRL_PIN(90, "SIO_I2C6_DATA"),
0202     PINCTRL_PIN(91, "SIO_I2C6_CLK"),
0203     PINCTRL_PIN(92, "GPIO_S0_SC92"),
0204     PINCTRL_PIN(93, "GPIO_S0_SC93"),
0205     PINCTRL_PIN(94, "SIO_PWM0"),
0206     PINCTRL_PIN(95, "SIO_PWM1"),
0207     PINCTRL_PIN(96, "PMC_PLT_CLK0"),
0208     PINCTRL_PIN(97, "PMC_PLT_CLK1"),
0209     PINCTRL_PIN(98, "PMC_PLT_CLK2"),
0210     PINCTRL_PIN(99, "PMC_PLT_CLK3"),
0211     PINCTRL_PIN(100, "PMC_PLT_CLK4"),
0212     PINCTRL_PIN(101, "PMC_PLT_CLK5"),
0213 };
0214 
0215 static const unsigned int byt_score_pins_map[BYT_NGPIO_SCORE] = {
0216     85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
0217     36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
0218     54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
0219     52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
0220     95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
0221     86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
0222     80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
0223     2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
0224     31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
0225     24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
0226     97, 100,
0227 };
0228 
0229 /* SCORE groups */
0230 static const unsigned int byt_score_uart1_pins[] = { 70, 71, 72, 73 };
0231 static const unsigned int byt_score_uart2_pins[] = { 74, 75, 76, 77 };
0232 
0233 static const unsigned int byt_score_pwm0_pins[] = { 94 };
0234 static const unsigned int byt_score_pwm1_pins[] = { 95 };
0235 
0236 static const unsigned int byt_score_sio_spi_pins[] = { 66, 67, 68, 69 };
0237 
0238 static const unsigned int byt_score_i2c5_pins[] = { 88, 89 };
0239 static const unsigned int byt_score_i2c6_pins[] = { 90, 91 };
0240 static const unsigned int byt_score_i2c4_pins[] = { 86, 87 };
0241 static const unsigned int byt_score_i2c3_pins[] = { 84, 85 };
0242 static const unsigned int byt_score_i2c2_pins[] = { 82, 83 };
0243 static const unsigned int byt_score_i2c1_pins[] = { 80, 81 };
0244 static const unsigned int byt_score_i2c0_pins[] = { 78, 79 };
0245 
0246 static const unsigned int byt_score_ssp0_pins[] = { 8, 9, 10, 11 };
0247 static const unsigned int byt_score_ssp1_pins[] = { 12, 13, 14, 15 };
0248 static const unsigned int byt_score_ssp2_pins[] = { 62, 63, 64, 65 };
0249 
0250 static const unsigned int byt_score_sdcard_pins[] = {
0251     7, 33, 34, 35, 36, 37, 38, 39, 40, 41,
0252 };
0253 static const unsigned int byt_score_sdcard_mux_values[] = {
0254     2, 1, 1, 1, 1, 1, 1, 1, 1, 1,
0255 };
0256 
0257 static const unsigned int byt_score_sdio_pins[] = { 27, 28, 29, 30, 31, 32 };
0258 
0259 static const unsigned int byt_score_emmc_pins[] = {
0260     16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26,
0261 };
0262 
0263 static const unsigned int byt_score_ilb_lpc_pins[] = {
0264     42, 43, 44, 45, 46, 47, 48, 49, 50,
0265 };
0266 
0267 static const unsigned int byt_score_sata_pins[] = { 0, 1, 2 };
0268 
0269 static const unsigned int byt_score_plt_clk0_pins[] = { 96 };
0270 static const unsigned int byt_score_plt_clk1_pins[] = { 97 };
0271 static const unsigned int byt_score_plt_clk2_pins[] = { 98 };
0272 static const unsigned int byt_score_plt_clk3_pins[] = { 99 };
0273 static const unsigned int byt_score_plt_clk4_pins[] = { 100 };
0274 static const unsigned int byt_score_plt_clk5_pins[] = { 101 };
0275 
0276 static const unsigned int byt_score_smbus_pins[] = { 51, 52, 53 };
0277 
0278 static const struct intel_pingroup byt_score_groups[] = {
0279     PIN_GROUP("uart1_grp", byt_score_uart1_pins, 1),
0280     PIN_GROUP("uart2_grp", byt_score_uart2_pins, 1),
0281     PIN_GROUP("pwm0_grp", byt_score_pwm0_pins, 1),
0282     PIN_GROUP("pwm1_grp", byt_score_pwm1_pins, 1),
0283     PIN_GROUP("ssp2_grp", byt_score_ssp2_pins, 1),
0284     PIN_GROUP("sio_spi_grp", byt_score_sio_spi_pins, 1),
0285     PIN_GROUP("i2c5_grp", byt_score_i2c5_pins, 1),
0286     PIN_GROUP("i2c6_grp", byt_score_i2c6_pins, 1),
0287     PIN_GROUP("i2c4_grp", byt_score_i2c4_pins, 1),
0288     PIN_GROUP("i2c3_grp", byt_score_i2c3_pins, 1),
0289     PIN_GROUP("i2c2_grp", byt_score_i2c2_pins, 1),
0290     PIN_GROUP("i2c1_grp", byt_score_i2c1_pins, 1),
0291     PIN_GROUP("i2c0_grp", byt_score_i2c0_pins, 1),
0292     PIN_GROUP("ssp0_grp", byt_score_ssp0_pins, 1),
0293     PIN_GROUP("ssp1_grp", byt_score_ssp1_pins, 1),
0294     PIN_GROUP("sdcard_grp", byt_score_sdcard_pins, byt_score_sdcard_mux_values),
0295     PIN_GROUP("sdio_grp", byt_score_sdio_pins, 1),
0296     PIN_GROUP("emmc_grp", byt_score_emmc_pins, 1),
0297     PIN_GROUP("lpc_grp", byt_score_ilb_lpc_pins, 1),
0298     PIN_GROUP("sata_grp", byt_score_sata_pins, 1),
0299     PIN_GROUP("plt_clk0_grp", byt_score_plt_clk0_pins, 1),
0300     PIN_GROUP("plt_clk1_grp", byt_score_plt_clk1_pins, 1),
0301     PIN_GROUP("plt_clk2_grp", byt_score_plt_clk2_pins, 1),
0302     PIN_GROUP("plt_clk3_grp", byt_score_plt_clk3_pins, 1),
0303     PIN_GROUP("plt_clk4_grp", byt_score_plt_clk4_pins, 1),
0304     PIN_GROUP("plt_clk5_grp", byt_score_plt_clk5_pins, 1),
0305     PIN_GROUP("smbus_grp", byt_score_smbus_pins, 1),
0306 };
0307 
0308 static const char * const byt_score_uart_groups[] = {
0309     "uart1_grp", "uart2_grp",
0310 };
0311 static const char * const byt_score_pwm_groups[] = {
0312     "pwm0_grp", "pwm1_grp",
0313 };
0314 static const char * const byt_score_ssp_groups[] = {
0315     "ssp0_grp", "ssp1_grp", "ssp2_grp",
0316 };
0317 static const char * const byt_score_spi_groups[] = { "sio_spi_grp" };
0318 static const char * const byt_score_i2c_groups[] = {
0319     "i2c0_grp", "i2c1_grp", "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp",
0320     "i2c6_grp",
0321 };
0322 static const char * const byt_score_sdcard_groups[] = { "sdcard_grp" };
0323 static const char * const byt_score_sdio_groups[] = { "sdio_grp" };
0324 static const char * const byt_score_emmc_groups[] = { "emmc_grp" };
0325 static const char * const byt_score_lpc_groups[] = { "lpc_grp" };
0326 static const char * const byt_score_sata_groups[] = { "sata_grp" };
0327 static const char * const byt_score_plt_clk_groups[] = {
0328     "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
0329     "plt_clk4_grp", "plt_clk5_grp",
0330 };
0331 static const char * const byt_score_smbus_groups[] = { "smbus_grp" };
0332 static const char * const byt_score_gpio_groups[] = {
0333     "uart1_grp", "uart2_grp", "pwm0_grp", "pwm1_grp", "ssp0_grp",
0334     "ssp1_grp", "ssp2_grp", "sio_spi_grp", "i2c0_grp", "i2c1_grp",
0335     "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", "i2c6_grp",
0336     "sdcard_grp", "sdio_grp", "emmc_grp", "lpc_grp", "sata_grp",
0337     "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
0338     "plt_clk4_grp", "plt_clk5_grp", "smbus_grp",
0339 };
0340 
0341 static const struct intel_function byt_score_functions[] = {
0342     FUNCTION("uart", byt_score_uart_groups),
0343     FUNCTION("pwm", byt_score_pwm_groups),
0344     FUNCTION("ssp", byt_score_ssp_groups),
0345     FUNCTION("spi", byt_score_spi_groups),
0346     FUNCTION("i2c", byt_score_i2c_groups),
0347     FUNCTION("sdcard", byt_score_sdcard_groups),
0348     FUNCTION("sdio", byt_score_sdio_groups),
0349     FUNCTION("emmc", byt_score_emmc_groups),
0350     FUNCTION("lpc", byt_score_lpc_groups),
0351     FUNCTION("sata", byt_score_sata_groups),
0352     FUNCTION("plt_clk", byt_score_plt_clk_groups),
0353     FUNCTION("smbus", byt_score_smbus_groups),
0354     FUNCTION("gpio", byt_score_gpio_groups),
0355 };
0356 
0357 static const struct intel_community byt_score_communities[] = {
0358     COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map),
0359 };
0360 
0361 static const struct intel_pinctrl_soc_data byt_score_soc_data = {
0362     .uid        = BYT_SCORE_ACPI_UID,
0363     .pins       = byt_score_pins,
0364     .npins      = ARRAY_SIZE(byt_score_pins),
0365     .groups     = byt_score_groups,
0366     .ngroups    = ARRAY_SIZE(byt_score_groups),
0367     .functions  = byt_score_functions,
0368     .nfunctions = ARRAY_SIZE(byt_score_functions),
0369     .communities    = byt_score_communities,
0370     .ncommunities   = ARRAY_SIZE(byt_score_communities),
0371 };
0372 
0373 /* SUS pins, aka GPIOS_<pin_no> or GPIO_S5[<pin_no>]  */
0374 static const struct pinctrl_pin_desc byt_sus_pins[] = {
0375     PINCTRL_PIN(0, "GPIO_S50"),
0376     PINCTRL_PIN(1, "GPIO_S51"),
0377     PINCTRL_PIN(2, "GPIO_S52"),
0378     PINCTRL_PIN(3, "GPIO_S53"),
0379     PINCTRL_PIN(4, "GPIO_S54"),
0380     PINCTRL_PIN(5, "GPIO_S55"),
0381     PINCTRL_PIN(6, "GPIO_S56"),
0382     PINCTRL_PIN(7, "GPIO_S57"),
0383     PINCTRL_PIN(8, "GPIO_S58"),
0384     PINCTRL_PIN(9, "GPIO_S59"),
0385     PINCTRL_PIN(10, "GPIO_S510"),
0386     PINCTRL_PIN(11, "PMC_SUSPWRDNACK"),
0387     PINCTRL_PIN(12, "PMC_SUSCLK0"),
0388     PINCTRL_PIN(13, "GPIO_S513"),
0389     PINCTRL_PIN(14, "USB_ULPI_RST"),
0390     PINCTRL_PIN(15, "PMC_WAKE_PCIE0#"),
0391     PINCTRL_PIN(16, "PMC_PWRBTN"),
0392     PINCTRL_PIN(17, "GPIO_S517"),
0393     PINCTRL_PIN(18, "PMC_SUS_STAT"),
0394     PINCTRL_PIN(19, "USB_OC0"),
0395     PINCTRL_PIN(20, "USB_OC1"),
0396     PINCTRL_PIN(21, "PCU_SPI_CS1"),
0397     PINCTRL_PIN(22, "GPIO_S522"),
0398     PINCTRL_PIN(23, "GPIO_S523"),
0399     PINCTRL_PIN(24, "GPIO_S524"),
0400     PINCTRL_PIN(25, "GPIO_S525"),
0401     PINCTRL_PIN(26, "GPIO_S526"),
0402     PINCTRL_PIN(27, "GPIO_S527"),
0403     PINCTRL_PIN(28, "GPIO_S528"),
0404     PINCTRL_PIN(29, "GPIO_S529"),
0405     PINCTRL_PIN(30, "GPIO_S530"),
0406     PINCTRL_PIN(31, "USB_ULPI_CLK"),
0407     PINCTRL_PIN(32, "USB_ULPI_DATA0"),
0408     PINCTRL_PIN(33, "USB_ULPI_DATA1"),
0409     PINCTRL_PIN(34, "USB_ULPI_DATA2"),
0410     PINCTRL_PIN(35, "USB_ULPI_DATA3"),
0411     PINCTRL_PIN(36, "USB_ULPI_DATA4"),
0412     PINCTRL_PIN(37, "USB_ULPI_DATA5"),
0413     PINCTRL_PIN(38, "USB_ULPI_DATA6"),
0414     PINCTRL_PIN(39, "USB_ULPI_DATA7"),
0415     PINCTRL_PIN(40, "USB_ULPI_DIR"),
0416     PINCTRL_PIN(41, "USB_ULPI_NXT"),
0417     PINCTRL_PIN(42, "USB_ULPI_STP"),
0418     PINCTRL_PIN(43, "USB_ULPI_REFCLK"),
0419 };
0420 
0421 static const unsigned int byt_sus_pins_map[BYT_NGPIO_SUS] = {
0422     29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
0423     18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
0424     0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
0425     26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
0426     52, 53, 59, 40,
0427 };
0428 
0429 static const unsigned int byt_sus_usb_over_current_pins[] = { 19, 20 };
0430 static const unsigned int byt_sus_usb_over_current_mode_values[] = { 0, 0 };
0431 static const unsigned int byt_sus_usb_over_current_gpio_mode_values[] = { 1, 1 };
0432 
0433 static const unsigned int byt_sus_usb_ulpi_pins[] = {
0434     14, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
0435 };
0436 static const unsigned int byt_sus_usb_ulpi_mode_values[] = {
0437     2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
0438 };
0439 static const unsigned int byt_sus_usb_ulpi_gpio_mode_values[] = {
0440     1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0441 };
0442 
0443 static const unsigned int byt_sus_pcu_spi_pins[] = { 21 };
0444 static const unsigned int byt_sus_pcu_spi_mode_values[] = { 0 };
0445 static const unsigned int byt_sus_pcu_spi_gpio_mode_values[] = { 1 };
0446 
0447 static const unsigned int byt_sus_pmu_clk1_pins[] = { 5 };
0448 static const unsigned int byt_sus_pmu_clk2_pins[] = { 6 };
0449 
0450 static const struct intel_pingroup byt_sus_groups[] = {
0451     PIN_GROUP("usb_oc_grp", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_mode_values),
0452     PIN_GROUP("usb_ulpi_grp", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_mode_values),
0453     PIN_GROUP("pcu_spi_grp", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_mode_values),
0454     PIN_GROUP("usb_oc_grp_gpio", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_gpio_mode_values),
0455     PIN_GROUP("usb_ulpi_grp_gpio", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_gpio_mode_values),
0456     PIN_GROUP("pcu_spi_grp_gpio", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_gpio_mode_values),
0457     PIN_GROUP("pmu_clk1_grp", byt_sus_pmu_clk1_pins, 1),
0458     PIN_GROUP("pmu_clk2_grp", byt_sus_pmu_clk2_pins, 1),
0459 };
0460 
0461 static const char * const byt_sus_usb_groups[] = {
0462     "usb_oc_grp", "usb_ulpi_grp",
0463 };
0464 static const char * const byt_sus_spi_groups[] = { "pcu_spi_grp" };
0465 static const char * const byt_sus_pmu_clk_groups[] = {
0466     "pmu_clk1_grp", "pmu_clk2_grp",
0467 };
0468 static const char * const byt_sus_gpio_groups[] = {
0469     "usb_oc_grp_gpio", "usb_ulpi_grp_gpio", "pcu_spi_grp_gpio",
0470     "pmu_clk1_grp", "pmu_clk2_grp",
0471 };
0472 
0473 static const struct intel_function byt_sus_functions[] = {
0474     FUNCTION("usb", byt_sus_usb_groups),
0475     FUNCTION("spi", byt_sus_spi_groups),
0476     FUNCTION("gpio", byt_sus_gpio_groups),
0477     FUNCTION("pmu_clk", byt_sus_pmu_clk_groups),
0478 };
0479 
0480 static const struct intel_community byt_sus_communities[] = {
0481     COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map),
0482 };
0483 
0484 static const struct intel_pinctrl_soc_data byt_sus_soc_data = {
0485     .uid        = BYT_SUS_ACPI_UID,
0486     .pins       = byt_sus_pins,
0487     .npins      = ARRAY_SIZE(byt_sus_pins),
0488     .groups     = byt_sus_groups,
0489     .ngroups    = ARRAY_SIZE(byt_sus_groups),
0490     .functions  = byt_sus_functions,
0491     .nfunctions = ARRAY_SIZE(byt_sus_functions),
0492     .communities    = byt_sus_communities,
0493     .ncommunities   = ARRAY_SIZE(byt_sus_communities),
0494 };
0495 
0496 static const struct pinctrl_pin_desc byt_ncore_pins[] = {
0497     PINCTRL_PIN(0, "HV_DDI0_HPD"),
0498     PINCTRL_PIN(1, "HV_DDI0_DDC_SDA"),
0499     PINCTRL_PIN(2, "HV_DDI0_DDC_SCL"),
0500     PINCTRL_PIN(3, "PANEL0_VDDEN"),
0501     PINCTRL_PIN(4, "PANEL0_BKLTEN"),
0502     PINCTRL_PIN(5, "PANEL0_BKLTCTL"),
0503     PINCTRL_PIN(6, "HV_DDI1_HPD"),
0504     PINCTRL_PIN(7, "HV_DDI1_DDC_SDA"),
0505     PINCTRL_PIN(8, "HV_DDI1_DDC_SCL"),
0506     PINCTRL_PIN(9, "PANEL1_VDDEN"),
0507     PINCTRL_PIN(10, "PANEL1_BKLTEN"),
0508     PINCTRL_PIN(11, "PANEL1_BKLTCTL"),
0509     PINCTRL_PIN(12, "GP_INTD_DSI_TE1"),
0510     PINCTRL_PIN(13, "HV_DDI2_DDC_SDA"),
0511     PINCTRL_PIN(14, "HV_DDI2_DDC_SCL"),
0512     PINCTRL_PIN(15, "GP_CAMERASB00"),
0513     PINCTRL_PIN(16, "GP_CAMERASB01"),
0514     PINCTRL_PIN(17, "GP_CAMERASB02"),
0515     PINCTRL_PIN(18, "GP_CAMERASB03"),
0516     PINCTRL_PIN(19, "GP_CAMERASB04"),
0517     PINCTRL_PIN(20, "GP_CAMERASB05"),
0518     PINCTRL_PIN(21, "GP_CAMERASB06"),
0519     PINCTRL_PIN(22, "GP_CAMERASB07"),
0520     PINCTRL_PIN(23, "GP_CAMERASB08"),
0521     PINCTRL_PIN(24, "GP_CAMERASB09"),
0522     PINCTRL_PIN(25, "GP_CAMERASB10"),
0523     PINCTRL_PIN(26, "GP_CAMERASB11"),
0524     PINCTRL_PIN(27, "GP_INTD_DSI_TE2"),
0525 };
0526 
0527 static const unsigned int byt_ncore_pins_map[BYT_NGPIO_NCORE] = {
0528     19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
0529     14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
0530     3, 6, 10, 13, 2, 5, 9, 7,
0531 };
0532 
0533 static const struct intel_community byt_ncore_communities[] = {
0534     COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map),
0535 };
0536 
0537 static const struct intel_pinctrl_soc_data byt_ncore_soc_data = {
0538     .uid        = BYT_NCORE_ACPI_UID,
0539     .pins       = byt_ncore_pins,
0540     .npins      = ARRAY_SIZE(byt_ncore_pins),
0541     .communities    = byt_ncore_communities,
0542     .ncommunities   = ARRAY_SIZE(byt_ncore_communities),
0543 };
0544 
0545 static const struct intel_pinctrl_soc_data *byt_soc_data[] = {
0546     &byt_score_soc_data,
0547     &byt_sus_soc_data,
0548     &byt_ncore_soc_data,
0549     NULL
0550 };
0551 
0552 static DEFINE_RAW_SPINLOCK(byt_lock);
0553 
0554 static struct intel_community *byt_get_community(struct intel_pinctrl *vg,
0555                          unsigned int pin)
0556 {
0557     struct intel_community *comm;
0558     int i;
0559 
0560     for (i = 0; i < vg->ncommunities; i++) {
0561         comm = vg->communities + i;
0562         if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base)
0563             return comm;
0564     }
0565 
0566     return NULL;
0567 }
0568 
0569 static void __iomem *byt_gpio_reg(struct intel_pinctrl *vg, unsigned int offset,
0570                   int reg)
0571 {
0572     struct intel_community *comm = byt_get_community(vg, offset);
0573     u32 reg_offset;
0574 
0575     if (!comm)
0576         return NULL;
0577 
0578     offset -= comm->pin_base;
0579     switch (reg) {
0580     case BYT_INT_STAT_REG:
0581         reg_offset = (offset / 32) * 4;
0582         break;
0583     case BYT_DEBOUNCE_REG:
0584         reg_offset = 0;
0585         break;
0586     default:
0587         reg_offset = comm->pad_map[offset] * 16;
0588         break;
0589     }
0590 
0591     return comm->pad_regs + reg_offset + reg;
0592 }
0593 
0594 static int byt_get_groups_count(struct pinctrl_dev *pctldev)
0595 {
0596     struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
0597 
0598     return vg->soc->ngroups;
0599 }
0600 
0601 static const char *byt_get_group_name(struct pinctrl_dev *pctldev,
0602                       unsigned int selector)
0603 {
0604     struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
0605 
0606     return vg->soc->groups[selector].grp.name;
0607 }
0608 
0609 static int byt_get_group_pins(struct pinctrl_dev *pctldev,
0610                   unsigned int selector,
0611                   const unsigned int **pins,
0612                   unsigned int *num_pins)
0613 {
0614     struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
0615 
0616     *pins       = vg->soc->groups[selector].grp.pins;
0617     *num_pins   = vg->soc->groups[selector].grp.npins;
0618 
0619     return 0;
0620 }
0621 
0622 static const struct pinctrl_ops byt_pinctrl_ops = {
0623     .get_groups_count   = byt_get_groups_count,
0624     .get_group_name     = byt_get_group_name,
0625     .get_group_pins     = byt_get_group_pins,
0626 };
0627 
0628 static int byt_get_functions_count(struct pinctrl_dev *pctldev)
0629 {
0630     struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
0631 
0632     return vg->soc->nfunctions;
0633 }
0634 
0635 static const char *byt_get_function_name(struct pinctrl_dev *pctldev,
0636                      unsigned int selector)
0637 {
0638     struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
0639 
0640     return vg->soc->functions[selector].name;
0641 }
0642 
0643 static int byt_get_function_groups(struct pinctrl_dev *pctldev,
0644                    unsigned int selector,
0645                    const char * const **groups,
0646                    unsigned int *num_groups)
0647 {
0648     struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
0649 
0650     *groups     = vg->soc->functions[selector].groups;
0651     *num_groups = vg->soc->functions[selector].ngroups;
0652 
0653     return 0;
0654 }
0655 
0656 static void byt_set_group_simple_mux(struct intel_pinctrl *vg,
0657                      const struct intel_pingroup group,
0658                      unsigned int func)
0659 {
0660     unsigned long flags;
0661     int i;
0662 
0663     raw_spin_lock_irqsave(&byt_lock, flags);
0664 
0665     for (i = 0; i < group.grp.npins; i++) {
0666         void __iomem *padcfg0;
0667         u32 value;
0668 
0669         padcfg0 = byt_gpio_reg(vg, group.grp.pins[i], BYT_CONF0_REG);
0670         if (!padcfg0) {
0671             dev_warn(vg->dev,
0672                  "Group %s, pin %i not muxed (no padcfg0)\n",
0673                  group.grp.name, i);
0674             continue;
0675         }
0676 
0677         value = readl(padcfg0);
0678         value &= ~BYT_PIN_MUX;
0679         value |= func;
0680         writel(value, padcfg0);
0681     }
0682 
0683     raw_spin_unlock_irqrestore(&byt_lock, flags);
0684 }
0685 
0686 static void byt_set_group_mixed_mux(struct intel_pinctrl *vg,
0687                     const struct intel_pingroup group,
0688                     const unsigned int *func)
0689 {
0690     unsigned long flags;
0691     int i;
0692 
0693     raw_spin_lock_irqsave(&byt_lock, flags);
0694 
0695     for (i = 0; i < group.grp.npins; i++) {
0696         void __iomem *padcfg0;
0697         u32 value;
0698 
0699         padcfg0 = byt_gpio_reg(vg, group.grp.pins[i], BYT_CONF0_REG);
0700         if (!padcfg0) {
0701             dev_warn(vg->dev,
0702                  "Group %s, pin %i not muxed (no padcfg0)\n",
0703                  group.grp.name, i);
0704             continue;
0705         }
0706 
0707         value = readl(padcfg0);
0708         value &= ~BYT_PIN_MUX;
0709         value |= func[i];
0710         writel(value, padcfg0);
0711     }
0712 
0713     raw_spin_unlock_irqrestore(&byt_lock, flags);
0714 }
0715 
0716 static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
0717                unsigned int group_selector)
0718 {
0719     struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
0720     const struct intel_function func = vg->soc->functions[func_selector];
0721     const struct intel_pingroup group = vg->soc->groups[group_selector];
0722 
0723     if (group.modes)
0724         byt_set_group_mixed_mux(vg, group, group.modes);
0725     else if (!strcmp(func.name, "gpio"))
0726         byt_set_group_simple_mux(vg, group, BYT_DEFAULT_GPIO_MUX);
0727     else
0728         byt_set_group_simple_mux(vg, group, group.mode);
0729 
0730     return 0;
0731 }
0732 
0733 static u32 byt_get_gpio_mux(struct intel_pinctrl *vg, unsigned int offset)
0734 {
0735     /* SCORE pin 92-93 */
0736     if (!strcmp(vg->soc->uid, BYT_SCORE_ACPI_UID) &&
0737         offset >= 92 && offset <= 93)
0738         return BYT_ALTER_GPIO_MUX;
0739 
0740     /* SUS pin 11-21 */
0741     if (!strcmp(vg->soc->uid, BYT_SUS_ACPI_UID) &&
0742         offset >= 11 && offset <= 21)
0743         return BYT_ALTER_GPIO_MUX;
0744 
0745     return BYT_DEFAULT_GPIO_MUX;
0746 }
0747 
0748 static void byt_gpio_clear_triggering(struct intel_pinctrl *vg, unsigned int offset)
0749 {
0750     void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
0751     unsigned long flags;
0752     u32 value;
0753 
0754     raw_spin_lock_irqsave(&byt_lock, flags);
0755     value = readl(reg);
0756 
0757     /* Do not clear direct-irq enabled IRQs (from gpio_disable_free) */
0758     if (value & BYT_DIRECT_IRQ_EN)
0759         /* nothing to do */ ;
0760     else
0761         value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
0762 
0763     writel(value, reg);
0764     raw_spin_unlock_irqrestore(&byt_lock, flags);
0765 }
0766 
0767 static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
0768                    struct pinctrl_gpio_range *range,
0769                    unsigned int offset)
0770 {
0771     struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
0772     void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
0773     u32 value, gpio_mux;
0774     unsigned long flags;
0775 
0776     raw_spin_lock_irqsave(&byt_lock, flags);
0777 
0778     /*
0779      * In most cases, func pin mux 000 means GPIO function.
0780      * But, some pins may have func pin mux 001 represents
0781      * GPIO function.
0782      *
0783      * Because there are devices out there where some pins were not
0784      * configured correctly we allow changing the mux value from
0785      * request (but print out warning about that).
0786      */
0787     value = readl(reg) & BYT_PIN_MUX;
0788     gpio_mux = byt_get_gpio_mux(vg, offset);
0789     if (gpio_mux != value) {
0790         value = readl(reg) & ~BYT_PIN_MUX;
0791         value |= gpio_mux;
0792         writel(value, reg);
0793 
0794         dev_warn(vg->dev, FW_BUG "pin %u forcibly re-configured as GPIO\n", offset);
0795     }
0796 
0797     raw_spin_unlock_irqrestore(&byt_lock, flags);
0798 
0799     pm_runtime_get(vg->dev);
0800 
0801     return 0;
0802 }
0803 
0804 static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev,
0805                   struct pinctrl_gpio_range *range,
0806                   unsigned int offset)
0807 {
0808     struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
0809 
0810     byt_gpio_clear_triggering(vg, offset);
0811     pm_runtime_put(vg->dev);
0812 }
0813 
0814 static void byt_gpio_direct_irq_check(struct intel_pinctrl *vg,
0815                       unsigned int offset)
0816 {
0817     void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
0818 
0819     /*
0820      * Before making any direction modifications, do a check if gpio is set
0821      * for direct IRQ. On Bay Trail, setting GPIO to output does not make
0822      * sense, so let's at least inform the caller before they shoot
0823      * themselves in the foot.
0824      */
0825     if (readl(conf_reg) & BYT_DIRECT_IRQ_EN)
0826         dev_info_once(vg->dev, "Potential Error: Setting GPIO with direct_irq_en to output");
0827 }
0828 
0829 static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,
0830                   struct pinctrl_gpio_range *range,
0831                   unsigned int offset,
0832                   bool input)
0833 {
0834     struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
0835     void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
0836     unsigned long flags;
0837     u32 value;
0838 
0839     raw_spin_lock_irqsave(&byt_lock, flags);
0840 
0841     value = readl(val_reg);
0842     value &= ~BYT_DIR_MASK;
0843     if (input)
0844         value |= BYT_OUTPUT_EN;
0845     else
0846         byt_gpio_direct_irq_check(vg, offset);
0847 
0848     writel(value, val_reg);
0849 
0850     raw_spin_unlock_irqrestore(&byt_lock, flags);
0851 
0852     return 0;
0853 }
0854 
0855 static const struct pinmux_ops byt_pinmux_ops = {
0856     .get_functions_count    = byt_get_functions_count,
0857     .get_function_name  = byt_get_function_name,
0858     .get_function_groups    = byt_get_function_groups,
0859     .set_mux        = byt_set_mux,
0860     .gpio_request_enable    = byt_gpio_request_enable,
0861     .gpio_disable_free  = byt_gpio_disable_free,
0862     .gpio_set_direction = byt_gpio_set_direction,
0863 };
0864 
0865 static void byt_get_pull_strength(u32 reg, u16 *strength)
0866 {
0867     switch (reg & BYT_PULL_STR_MASK) {
0868     case BYT_PULL_STR_2K:
0869         *strength = 2000;
0870         break;
0871     case BYT_PULL_STR_10K:
0872         *strength = 10000;
0873         break;
0874     case BYT_PULL_STR_20K:
0875         *strength = 20000;
0876         break;
0877     case BYT_PULL_STR_40K:
0878         *strength = 40000;
0879         break;
0880     }
0881 }
0882 
0883 static int byt_set_pull_strength(u32 *reg, u16 strength)
0884 {
0885     *reg &= ~BYT_PULL_STR_MASK;
0886 
0887     switch (strength) {
0888     case 2000:
0889         *reg |= BYT_PULL_STR_2K;
0890         break;
0891     case 10000:
0892         *reg |= BYT_PULL_STR_10K;
0893         break;
0894     case 20000:
0895         *reg |= BYT_PULL_STR_20K;
0896         break;
0897     case 40000:
0898         *reg |= BYT_PULL_STR_40K;
0899         break;
0900     default:
0901         return -EINVAL;
0902     }
0903 
0904     return 0;
0905 }
0906 
0907 static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
0908                   unsigned long *config)
0909 {
0910     struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
0911     enum pin_config_param param = pinconf_to_config_param(*config);
0912     void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
0913     void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
0914     void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
0915     unsigned long flags;
0916     u32 conf, pull, val, debounce;
0917     u16 arg = 0;
0918 
0919     raw_spin_lock_irqsave(&byt_lock, flags);
0920     conf = readl(conf_reg);
0921     pull = conf & BYT_PULL_ASSIGN_MASK;
0922     val = readl(val_reg);
0923     raw_spin_unlock_irqrestore(&byt_lock, flags);
0924 
0925     switch (param) {
0926     case PIN_CONFIG_BIAS_DISABLE:
0927         if (pull)
0928             return -EINVAL;
0929         break;
0930     case PIN_CONFIG_BIAS_PULL_DOWN:
0931         /* Pull assignment is only applicable in input mode */
0932         if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_DOWN)
0933             return -EINVAL;
0934 
0935         byt_get_pull_strength(conf, &arg);
0936 
0937         break;
0938     case PIN_CONFIG_BIAS_PULL_UP:
0939         /* Pull assignment is only applicable in input mode */
0940         if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_UP)
0941             return -EINVAL;
0942 
0943         byt_get_pull_strength(conf, &arg);
0944 
0945         break;
0946     case PIN_CONFIG_INPUT_DEBOUNCE:
0947         if (!(conf & BYT_DEBOUNCE_EN))
0948             return -EINVAL;
0949 
0950         raw_spin_lock_irqsave(&byt_lock, flags);
0951         debounce = readl(db_reg);
0952         raw_spin_unlock_irqrestore(&byt_lock, flags);
0953 
0954         switch (debounce & BYT_DEBOUNCE_PULSE_MASK) {
0955         case BYT_DEBOUNCE_PULSE_375US:
0956             arg = 375;
0957             break;
0958         case BYT_DEBOUNCE_PULSE_750US:
0959             arg = 750;
0960             break;
0961         case BYT_DEBOUNCE_PULSE_1500US:
0962             arg = 1500;
0963             break;
0964         case BYT_DEBOUNCE_PULSE_3MS:
0965             arg = 3000;
0966             break;
0967         case BYT_DEBOUNCE_PULSE_6MS:
0968             arg = 6000;
0969             break;
0970         case BYT_DEBOUNCE_PULSE_12MS:
0971             arg = 12000;
0972             break;
0973         case BYT_DEBOUNCE_PULSE_24MS:
0974             arg = 24000;
0975             break;
0976         default:
0977             return -EINVAL;
0978         }
0979 
0980         break;
0981     default:
0982         return -ENOTSUPP;
0983     }
0984 
0985     *config = pinconf_to_config_packed(param, arg);
0986 
0987     return 0;
0988 }
0989 
0990 static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
0991                   unsigned int offset,
0992                   unsigned long *configs,
0993                   unsigned int num_configs)
0994 {
0995     struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
0996     unsigned int param, arg;
0997     void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
0998     void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
0999     void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
1000     unsigned long flags;
1001     u32 conf, val, debounce;
1002     int i, ret = 0;
1003 
1004     raw_spin_lock_irqsave(&byt_lock, flags);
1005 
1006     conf = readl(conf_reg);
1007     val = readl(val_reg);
1008 
1009     for (i = 0; i < num_configs; i++) {
1010         param = pinconf_to_config_param(configs[i]);
1011         arg = pinconf_to_config_argument(configs[i]);
1012 
1013         switch (param) {
1014         case PIN_CONFIG_BIAS_DISABLE:
1015             conf &= ~BYT_PULL_ASSIGN_MASK;
1016             break;
1017         case PIN_CONFIG_BIAS_PULL_DOWN:
1018             /* Set default strength value in case none is given */
1019             if (arg == 1)
1020                 arg = 2000;
1021 
1022             /*
1023              * Pull assignment is only applicable in input mode. If
1024              * chip is not in input mode, set it and warn about it.
1025              */
1026             if (val & BYT_INPUT_EN) {
1027                 val &= ~BYT_INPUT_EN;
1028                 writel(val, val_reg);
1029                 dev_warn(vg->dev,
1030                      "pin %u forcibly set to input mode\n",
1031                      offset);
1032             }
1033 
1034             conf &= ~BYT_PULL_ASSIGN_MASK;
1035             conf |= BYT_PULL_ASSIGN_DOWN;
1036             ret = byt_set_pull_strength(&conf, arg);
1037 
1038             break;
1039         case PIN_CONFIG_BIAS_PULL_UP:
1040             /* Set default strength value in case none is given */
1041             if (arg == 1)
1042                 arg = 2000;
1043 
1044             /*
1045              * Pull assignment is only applicable in input mode. If
1046              * chip is not in input mode, set it and warn about it.
1047              */
1048             if (val & BYT_INPUT_EN) {
1049                 val &= ~BYT_INPUT_EN;
1050                 writel(val, val_reg);
1051                 dev_warn(vg->dev,
1052                      "pin %u forcibly set to input mode\n",
1053                      offset);
1054             }
1055 
1056             conf &= ~BYT_PULL_ASSIGN_MASK;
1057             conf |= BYT_PULL_ASSIGN_UP;
1058             ret = byt_set_pull_strength(&conf, arg);
1059 
1060             break;
1061         case PIN_CONFIG_INPUT_DEBOUNCE:
1062             debounce = readl(db_reg);
1063 
1064             if (arg)
1065                 conf |= BYT_DEBOUNCE_EN;
1066             else
1067                 conf &= ~BYT_DEBOUNCE_EN;
1068 
1069             switch (arg) {
1070             case 375:
1071                 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1072                 debounce |= BYT_DEBOUNCE_PULSE_375US;
1073                 break;
1074             case 750:
1075                 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1076                 debounce |= BYT_DEBOUNCE_PULSE_750US;
1077                 break;
1078             case 1500:
1079                 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1080                 debounce |= BYT_DEBOUNCE_PULSE_1500US;
1081                 break;
1082             case 3000:
1083                 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1084                 debounce |= BYT_DEBOUNCE_PULSE_3MS;
1085                 break;
1086             case 6000:
1087                 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1088                 debounce |= BYT_DEBOUNCE_PULSE_6MS;
1089                 break;
1090             case 12000:
1091                 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1092                 debounce |= BYT_DEBOUNCE_PULSE_12MS;
1093                 break;
1094             case 24000:
1095                 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1096                 debounce |= BYT_DEBOUNCE_PULSE_24MS;
1097                 break;
1098             default:
1099                 if (arg)
1100                     ret = -EINVAL;
1101                 break;
1102             }
1103 
1104             if (!ret)
1105                 writel(debounce, db_reg);
1106             break;
1107         default:
1108             ret = -ENOTSUPP;
1109         }
1110 
1111         if (ret)
1112             break;
1113     }
1114 
1115     if (!ret)
1116         writel(conf, conf_reg);
1117 
1118     raw_spin_unlock_irqrestore(&byt_lock, flags);
1119 
1120     return ret;
1121 }
1122 
1123 static const struct pinconf_ops byt_pinconf_ops = {
1124     .is_generic = true,
1125     .pin_config_get = byt_pin_config_get,
1126     .pin_config_set = byt_pin_config_set,
1127 };
1128 
1129 static const struct pinctrl_desc byt_pinctrl_desc = {
1130     .pctlops    = &byt_pinctrl_ops,
1131     .pmxops     = &byt_pinmux_ops,
1132     .confops    = &byt_pinconf_ops,
1133     .owner      = THIS_MODULE,
1134 };
1135 
1136 static int byt_gpio_get(struct gpio_chip *chip, unsigned int offset)
1137 {
1138     struct intel_pinctrl *vg = gpiochip_get_data(chip);
1139     void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1140     unsigned long flags;
1141     u32 val;
1142 
1143     raw_spin_lock_irqsave(&byt_lock, flags);
1144     val = readl(reg);
1145     raw_spin_unlock_irqrestore(&byt_lock, flags);
1146 
1147     return !!(val & BYT_LEVEL);
1148 }
1149 
1150 static void byt_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
1151 {
1152     struct intel_pinctrl *vg = gpiochip_get_data(chip);
1153     void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1154     unsigned long flags;
1155     u32 old_val;
1156 
1157     if (!reg)
1158         return;
1159 
1160     raw_spin_lock_irqsave(&byt_lock, flags);
1161     old_val = readl(reg);
1162     if (value)
1163         writel(old_val | BYT_LEVEL, reg);
1164     else
1165         writel(old_val & ~BYT_LEVEL, reg);
1166     raw_spin_unlock_irqrestore(&byt_lock, flags);
1167 }
1168 
1169 static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1170 {
1171     struct intel_pinctrl *vg = gpiochip_get_data(chip);
1172     void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1173     unsigned long flags;
1174     u32 value;
1175 
1176     if (!reg)
1177         return -EINVAL;
1178 
1179     raw_spin_lock_irqsave(&byt_lock, flags);
1180     value = readl(reg);
1181     raw_spin_unlock_irqrestore(&byt_lock, flags);
1182 
1183     if (!(value & BYT_OUTPUT_EN))
1184         return GPIO_LINE_DIRECTION_OUT;
1185     if (!(value & BYT_INPUT_EN))
1186         return GPIO_LINE_DIRECTION_IN;
1187 
1188     return -EINVAL;
1189 }
1190 
1191 static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
1192 {
1193     struct intel_pinctrl *vg = gpiochip_get_data(chip);
1194     void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1195     unsigned long flags;
1196     u32 reg;
1197 
1198     raw_spin_lock_irqsave(&byt_lock, flags);
1199 
1200     reg = readl(val_reg);
1201     reg &= ~BYT_DIR_MASK;
1202     reg |= BYT_OUTPUT_EN;
1203     writel(reg, val_reg);
1204 
1205     raw_spin_unlock_irqrestore(&byt_lock, flags);
1206     return 0;
1207 }
1208 
1209 /*
1210  * Note despite the temptation this MUST NOT be converted into a call to
1211  * pinctrl_gpio_direction_output() + byt_gpio_set() that does not work this
1212  * MUST be done as a single BYT_VAL_REG register write.
1213  * See the commit message of the commit adding this comment for details.
1214  */
1215 static int byt_gpio_direction_output(struct gpio_chip *chip,
1216                      unsigned int offset, int value)
1217 {
1218     struct intel_pinctrl *vg = gpiochip_get_data(chip);
1219     void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1220     unsigned long flags;
1221     u32 reg;
1222 
1223     raw_spin_lock_irqsave(&byt_lock, flags);
1224 
1225     byt_gpio_direct_irq_check(vg, offset);
1226 
1227     reg = readl(val_reg);
1228     reg &= ~BYT_DIR_MASK;
1229     if (value)
1230         reg |= BYT_LEVEL;
1231     else
1232         reg &= ~BYT_LEVEL;
1233 
1234     writel(reg, val_reg);
1235 
1236     raw_spin_unlock_irqrestore(&byt_lock, flags);
1237     return 0;
1238 }
1239 
1240 static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1241 {
1242     struct intel_pinctrl *vg = gpiochip_get_data(chip);
1243     int i;
1244     u32 conf0, val;
1245 
1246     for (i = 0; i < vg->soc->npins; i++) {
1247         const struct intel_community *comm;
1248         const char *pull_str = NULL;
1249         const char *pull = NULL;
1250         void __iomem *reg;
1251         unsigned long flags;
1252         const char *label;
1253         unsigned int pin;
1254 
1255         raw_spin_lock_irqsave(&byt_lock, flags);
1256         pin = vg->soc->pins[i].number;
1257         reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1258         if (!reg) {
1259             seq_printf(s,
1260                    "Could not retrieve pin %i conf0 reg\n",
1261                    pin);
1262             raw_spin_unlock_irqrestore(&byt_lock, flags);
1263             continue;
1264         }
1265         conf0 = readl(reg);
1266 
1267         reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1268         if (!reg) {
1269             seq_printf(s,
1270                    "Could not retrieve pin %i val reg\n", pin);
1271             raw_spin_unlock_irqrestore(&byt_lock, flags);
1272             continue;
1273         }
1274         val = readl(reg);
1275         raw_spin_unlock_irqrestore(&byt_lock, flags);
1276 
1277         comm = byt_get_community(vg, pin);
1278         if (!comm) {
1279             seq_printf(s,
1280                    "Could not get community for pin %i\n", pin);
1281             continue;
1282         }
1283         label = gpiochip_is_requested(chip, i);
1284         if (!label)
1285             label = "Unrequested";
1286 
1287         switch (conf0 & BYT_PULL_ASSIGN_MASK) {
1288         case BYT_PULL_ASSIGN_UP:
1289             pull = "up";
1290             break;
1291         case BYT_PULL_ASSIGN_DOWN:
1292             pull = "down";
1293             break;
1294         }
1295 
1296         switch (conf0 & BYT_PULL_STR_MASK) {
1297         case BYT_PULL_STR_2K:
1298             pull_str = "2k";
1299             break;
1300         case BYT_PULL_STR_10K:
1301             pull_str = "10k";
1302             break;
1303         case BYT_PULL_STR_20K:
1304             pull_str = "20k";
1305             break;
1306         case BYT_PULL_STR_40K:
1307             pull_str = "40k";
1308             break;
1309         }
1310 
1311         seq_printf(s,
1312                " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s",
1313                pin,
1314                label,
1315                val & BYT_INPUT_EN ? "  " : "in",
1316                val & BYT_OUTPUT_EN ? "   " : "out",
1317                val & BYT_LEVEL ? "hi" : "lo",
1318                comm->pad_map[i], comm->pad_map[i] * 16,
1319                conf0 & 0x7,
1320                conf0 & BYT_TRIG_NEG ? " fall" : "     ",
1321                conf0 & BYT_TRIG_POS ? " rise" : "     ",
1322                conf0 & BYT_TRIG_LVL ? " level" : "      ");
1323 
1324         if (pull && pull_str)
1325             seq_printf(s, " %-4s %-3s", pull, pull_str);
1326         else
1327             seq_puts(s, "          ");
1328 
1329         if (conf0 & BYT_IODEN)
1330             seq_puts(s, " open-drain");
1331 
1332         seq_puts(s, "\n");
1333     }
1334 }
1335 
1336 static const struct gpio_chip byt_gpio_chip = {
1337     .owner          = THIS_MODULE,
1338     .request        = gpiochip_generic_request,
1339     .free           = gpiochip_generic_free,
1340     .get_direction      = byt_gpio_get_direction,
1341     .direction_input    = byt_gpio_direction_input,
1342     .direction_output   = byt_gpio_direction_output,
1343     .get            = byt_gpio_get,
1344     .set            = byt_gpio_set,
1345     .set_config     = gpiochip_generic_config,
1346     .dbg_show       = byt_gpio_dbg_show,
1347 };
1348 
1349 static void byt_irq_ack(struct irq_data *d)
1350 {
1351     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1352     struct intel_pinctrl *vg = gpiochip_get_data(gc);
1353     irq_hw_number_t hwirq = irqd_to_hwirq(d);
1354     void __iomem *reg;
1355 
1356     reg = byt_gpio_reg(vg, hwirq, BYT_INT_STAT_REG);
1357     if (!reg)
1358         return;
1359 
1360     raw_spin_lock(&byt_lock);
1361     writel(BIT(hwirq % 32), reg);
1362     raw_spin_unlock(&byt_lock);
1363 }
1364 
1365 static void byt_irq_mask(struct irq_data *d)
1366 {
1367     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1368     struct intel_pinctrl *vg = gpiochip_get_data(gc);
1369     irq_hw_number_t hwirq = irqd_to_hwirq(d);
1370 
1371     byt_gpio_clear_triggering(vg, hwirq);
1372     gpiochip_disable_irq(gc, hwirq);
1373 }
1374 
1375 static void byt_irq_unmask(struct irq_data *d)
1376 {
1377     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1378     struct intel_pinctrl *vg = gpiochip_get_data(gc);
1379     irq_hw_number_t hwirq = irqd_to_hwirq(d);
1380     unsigned long flags;
1381     void __iomem *reg;
1382     u32 value;
1383 
1384     gpiochip_enable_irq(gc, hwirq);
1385 
1386     reg = byt_gpio_reg(vg, hwirq, BYT_CONF0_REG);
1387     if (!reg)
1388         return;
1389 
1390     raw_spin_lock_irqsave(&byt_lock, flags);
1391     value = readl(reg);
1392 
1393     switch (irqd_get_trigger_type(d)) {
1394     case IRQ_TYPE_LEVEL_HIGH:
1395         value |= BYT_TRIG_LVL;
1396         fallthrough;
1397     case IRQ_TYPE_EDGE_RISING:
1398         value |= BYT_TRIG_POS;
1399         break;
1400     case IRQ_TYPE_LEVEL_LOW:
1401         value |= BYT_TRIG_LVL;
1402         fallthrough;
1403     case IRQ_TYPE_EDGE_FALLING:
1404         value |= BYT_TRIG_NEG;
1405         break;
1406     case IRQ_TYPE_EDGE_BOTH:
1407         value |= (BYT_TRIG_NEG | BYT_TRIG_POS);
1408         break;
1409     }
1410 
1411     writel(value, reg);
1412 
1413     raw_spin_unlock_irqrestore(&byt_lock, flags);
1414 }
1415 
1416 static int byt_irq_type(struct irq_data *d, unsigned int type)
1417 {
1418     struct intel_pinctrl *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d));
1419     irq_hw_number_t hwirq = irqd_to_hwirq(d);
1420     u32 value;
1421     unsigned long flags;
1422     void __iomem *reg;
1423 
1424     reg = byt_gpio_reg(vg, hwirq, BYT_CONF0_REG);
1425     if (!reg)
1426         return -EINVAL;
1427 
1428     raw_spin_lock_irqsave(&byt_lock, flags);
1429     value = readl(reg);
1430 
1431     WARN(value & BYT_DIRECT_IRQ_EN,
1432          "Bad pad config for io mode, force direct_irq_en bit clearing");
1433 
1434     /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
1435      * are used to indicate high and low level triggering
1436      */
1437     value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG |
1438            BYT_TRIG_LVL);
1439     /* Enable glitch filtering */
1440     value |= BYT_GLITCH_FILTER_EN | BYT_GLITCH_F_SLOW_CLK |
1441          BYT_GLITCH_F_FAST_CLK;
1442 
1443     writel(value, reg);
1444 
1445     if (type & IRQ_TYPE_EDGE_BOTH)
1446         irq_set_handler_locked(d, handle_edge_irq);
1447     else if (type & IRQ_TYPE_LEVEL_MASK)
1448         irq_set_handler_locked(d, handle_level_irq);
1449 
1450     raw_spin_unlock_irqrestore(&byt_lock, flags);
1451 
1452     return 0;
1453 }
1454 
1455 static const struct irq_chip byt_gpio_irq_chip = {
1456     .name       = "BYT-GPIO",
1457     .irq_ack    = byt_irq_ack,
1458     .irq_mask   = byt_irq_mask,
1459     .irq_unmask = byt_irq_unmask,
1460     .irq_set_type   = byt_irq_type,
1461     .flags      = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED | IRQCHIP_IMMUTABLE,
1462     GPIOCHIP_IRQ_RESOURCE_HELPERS,
1463 };
1464 
1465 static void byt_gpio_irq_handler(struct irq_desc *desc)
1466 {
1467     struct irq_data *data = irq_desc_get_irq_data(desc);
1468     struct intel_pinctrl *vg = gpiochip_get_data(irq_desc_get_handler_data(desc));
1469     struct irq_chip *chip = irq_data_get_irq_chip(data);
1470     u32 base, pin;
1471     void __iomem *reg;
1472     unsigned long pending;
1473 
1474     /* check from GPIO controller which pin triggered the interrupt */
1475     for (base = 0; base < vg->chip.ngpio; base += 32) {
1476         reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1477 
1478         if (!reg) {
1479             dev_warn(vg->dev,
1480                  "Pin %i: could not retrieve interrupt status register\n",
1481                  base);
1482             continue;
1483         }
1484 
1485         raw_spin_lock(&byt_lock);
1486         pending = readl(reg);
1487         raw_spin_unlock(&byt_lock);
1488         for_each_set_bit(pin, &pending, 32)
1489             generic_handle_domain_irq(vg->chip.irq.domain, base + pin);
1490     }
1491     chip->irq_eoi(data);
1492 }
1493 
1494 static bool byt_direct_irq_sanity_check(struct intel_pinctrl *vg, int pin, u32 conf0)
1495 {
1496     int direct_irq, ioapic_direct_irq_base;
1497     u8 *match, direct_irq_mux[16];
1498     u32 trig;
1499 
1500     memcpy_fromio(direct_irq_mux, vg->communities->pad_regs + BYT_DIRECT_IRQ_REG,
1501               sizeof(direct_irq_mux));
1502     match = memchr(direct_irq_mux, pin, sizeof(direct_irq_mux));
1503     if (!match) {
1504         dev_warn(vg->dev, FW_BUG "pin %i: direct_irq_en set but no IRQ assigned, clearing\n", pin);
1505         return false;
1506     }
1507 
1508     direct_irq = match - direct_irq_mux;
1509     /* Base IO-APIC pin numbers come from atom-e3800-family-datasheet.pdf */
1510     ioapic_direct_irq_base = (vg->communities->npins == BYT_NGPIO_SCORE) ? 51 : 67;
1511     dev_dbg(vg->dev, "Pin %i: uses direct IRQ %d (IO-APIC %d)\n", pin,
1512         direct_irq, direct_irq + ioapic_direct_irq_base);
1513 
1514     /*
1515      * Testing has shown that the way direct IRQs work is that the combination of the
1516      * direct-irq-en flag and the direct IRQ mux connect the output of the GPIO's IRQ
1517      * trigger block, which normally sets the status flag in the IRQ status reg at
1518      * 0x800, to one of the IO-APIC pins according to the mux registers.
1519      *
1520      * This means that:
1521      * 1. The TRIG_MASK bits must be set to configure the GPIO's IRQ trigger block
1522      * 2. The TRIG_LVL bit *must* be set, so that the GPIO's input value is directly
1523      *    passed (1:1 or inverted) to the IO-APIC pin, if TRIG_LVL is not set,
1524      *    selecting edge mode operation then on the first edge the IO-APIC pin goes
1525      *    high, but since no write-to-clear write will be done to the IRQ status reg
1526      *    at 0x800, the detected edge condition will never get cleared.
1527      */
1528     trig = conf0 & BYT_TRIG_MASK;
1529     if (trig != (BYT_TRIG_POS | BYT_TRIG_LVL) &&
1530         trig != (BYT_TRIG_NEG | BYT_TRIG_LVL)) {
1531         dev_warn(vg->dev, FW_BUG "pin %i: direct_irq_en set without trigger (conf0: %xh), clearing\n",
1532              pin, conf0);
1533         return false;
1534     }
1535 
1536     return true;
1537 }
1538 
1539 static void byt_init_irq_valid_mask(struct gpio_chip *chip,
1540                     unsigned long *valid_mask,
1541                     unsigned int ngpios)
1542 {
1543     struct intel_pinctrl *vg = gpiochip_get_data(chip);
1544     void __iomem *reg;
1545     u32 value;
1546     int i;
1547 
1548     /*
1549      * Clear interrupt triggers for all pins that are GPIOs and
1550      * do not use direct IRQ mode. This will prevent spurious
1551      * interrupts from misconfigured pins.
1552      */
1553     for (i = 0; i < vg->soc->npins; i++) {
1554         unsigned int pin = vg->soc->pins[i].number;
1555 
1556         reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1557         if (!reg) {
1558             dev_warn(vg->dev,
1559                  "Pin %i: could not retrieve conf0 register\n",
1560                  i);
1561             continue;
1562         }
1563 
1564         value = readl(reg);
1565         if (value & BYT_DIRECT_IRQ_EN) {
1566             if (byt_direct_irq_sanity_check(vg, i, value)) {
1567                 clear_bit(i, valid_mask);
1568             } else {
1569                 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS |
1570                        BYT_TRIG_NEG | BYT_TRIG_LVL);
1571                 writel(value, reg);
1572             }
1573         } else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) {
1574             byt_gpio_clear_triggering(vg, i);
1575             dev_dbg(vg->dev, "disabling GPIO %d\n", i);
1576         }
1577     }
1578 }
1579 
1580 static int byt_gpio_irq_init_hw(struct gpio_chip *chip)
1581 {
1582     struct intel_pinctrl *vg = gpiochip_get_data(chip);
1583     void __iomem *reg;
1584     u32 base, value;
1585 
1586     /* clear interrupt status trigger registers */
1587     for (base = 0; base < vg->soc->npins; base += 32) {
1588         reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1589 
1590         if (!reg) {
1591             dev_warn(vg->dev,
1592                  "Pin %i: could not retrieve irq status reg\n",
1593                  base);
1594             continue;
1595         }
1596 
1597         writel(0xffffffff, reg);
1598         /* make sure trigger bits are cleared, if not then a pin
1599            might be misconfigured in bios */
1600         value = readl(reg);
1601         if (value)
1602             dev_err(vg->dev,
1603                 "GPIO interrupt error, pins misconfigured. INT_STAT%u: 0x%08x\n",
1604                 base / 32, value);
1605     }
1606 
1607     return 0;
1608 }
1609 
1610 static int byt_gpio_add_pin_ranges(struct gpio_chip *chip)
1611 {
1612     struct intel_pinctrl *vg = gpiochip_get_data(chip);
1613     struct device *dev = vg->dev;
1614     int ret;
1615 
1616     ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, vg->soc->npins);
1617     if (ret)
1618         dev_err(dev, "failed to add GPIO pin range\n");
1619 
1620     return ret;
1621 }
1622 
1623 static int byt_gpio_probe(struct intel_pinctrl *vg)
1624 {
1625     struct platform_device *pdev = to_platform_device(vg->dev);
1626     struct gpio_chip *gc;
1627     int irq, ret;
1628 
1629     /* Set up gpio chip */
1630     vg->chip    = byt_gpio_chip;
1631     gc      = &vg->chip;
1632     gc->label   = dev_name(vg->dev);
1633     gc->base    = -1;
1634     gc->can_sleep   = false;
1635     gc->add_pin_ranges = byt_gpio_add_pin_ranges;
1636     gc->parent  = vg->dev;
1637     gc->ngpio   = vg->soc->npins;
1638 
1639 #ifdef CONFIG_PM_SLEEP
1640     vg->context.pads = devm_kcalloc(vg->dev, gc->ngpio, sizeof(*vg->context.pads),
1641                     GFP_KERNEL);
1642     if (!vg->context.pads)
1643         return -ENOMEM;
1644 #endif
1645 
1646     /* set up interrupts  */
1647     irq = platform_get_irq_optional(pdev, 0);
1648     if (irq > 0) {
1649         struct gpio_irq_chip *girq;
1650 
1651         girq = &gc->irq;
1652         gpio_irq_chip_set_chip(girq, &byt_gpio_irq_chip);
1653         girq->init_hw = byt_gpio_irq_init_hw;
1654         girq->init_valid_mask = byt_init_irq_valid_mask;
1655         girq->parent_handler = byt_gpio_irq_handler;
1656         girq->num_parents = 1;
1657         girq->parents = devm_kcalloc(vg->dev, girq->num_parents,
1658                          sizeof(*girq->parents), GFP_KERNEL);
1659         if (!girq->parents)
1660             return -ENOMEM;
1661         girq->parents[0] = irq;
1662         girq->default_type = IRQ_TYPE_NONE;
1663         girq->handler = handle_bad_irq;
1664     }
1665 
1666     ret = devm_gpiochip_add_data(vg->dev, gc, vg);
1667     if (ret) {
1668         dev_err(vg->dev, "failed adding byt-gpio chip\n");
1669         return ret;
1670     }
1671 
1672     return ret;
1673 }
1674 
1675 static int byt_set_soc_data(struct intel_pinctrl *vg,
1676                 const struct intel_pinctrl_soc_data *soc)
1677 {
1678     struct platform_device *pdev = to_platform_device(vg->dev);
1679     int i;
1680 
1681     vg->soc = soc;
1682 
1683     vg->ncommunities = vg->soc->ncommunities;
1684     vg->communities = devm_kcalloc(vg->dev, vg->ncommunities,
1685                        sizeof(*vg->communities), GFP_KERNEL);
1686     if (!vg->communities)
1687         return -ENOMEM;
1688 
1689     for (i = 0; i < vg->soc->ncommunities; i++) {
1690         struct intel_community *comm = vg->communities + i;
1691 
1692         *comm = vg->soc->communities[i];
1693 
1694         comm->pad_regs = devm_platform_ioremap_resource(pdev, 0);
1695         if (IS_ERR(comm->pad_regs))
1696             return PTR_ERR(comm->pad_regs);
1697     }
1698 
1699     return 0;
1700 }
1701 
1702 static const struct acpi_device_id byt_gpio_acpi_match[] = {
1703     { "INT33B2", (kernel_ulong_t)byt_soc_data },
1704     { "INT33FC", (kernel_ulong_t)byt_soc_data },
1705     { }
1706 };
1707 
1708 static int byt_pinctrl_probe(struct platform_device *pdev)
1709 {
1710     const struct intel_pinctrl_soc_data *soc_data;
1711     struct device *dev = &pdev->dev;
1712     struct intel_pinctrl *vg;
1713     int ret;
1714 
1715     soc_data = intel_pinctrl_get_soc_data(pdev);
1716     if (IS_ERR(soc_data))
1717         return PTR_ERR(soc_data);
1718 
1719     vg = devm_kzalloc(dev, sizeof(*vg), GFP_KERNEL);
1720     if (!vg)
1721         return -ENOMEM;
1722 
1723     vg->dev = dev;
1724     ret = byt_set_soc_data(vg, soc_data);
1725     if (ret) {
1726         dev_err(dev, "failed to set soc data\n");
1727         return ret;
1728     }
1729 
1730     vg->pctldesc        = byt_pinctrl_desc;
1731     vg->pctldesc.name   = dev_name(dev);
1732     vg->pctldesc.pins   = vg->soc->pins;
1733     vg->pctldesc.npins  = vg->soc->npins;
1734 
1735     vg->pctldev = devm_pinctrl_register(dev, &vg->pctldesc, vg);
1736     if (IS_ERR(vg->pctldev)) {
1737         dev_err(dev, "failed to register pinctrl driver\n");
1738         return PTR_ERR(vg->pctldev);
1739     }
1740 
1741     ret = byt_gpio_probe(vg);
1742     if (ret)
1743         return ret;
1744 
1745     platform_set_drvdata(pdev, vg);
1746     pm_runtime_enable(dev);
1747 
1748     return 0;
1749 }
1750 
1751 #ifdef CONFIG_PM_SLEEP
1752 static int byt_gpio_suspend(struct device *dev)
1753 {
1754     struct intel_pinctrl *vg = dev_get_drvdata(dev);
1755     unsigned long flags;
1756     int i;
1757 
1758     raw_spin_lock_irqsave(&byt_lock, flags);
1759 
1760     for (i = 0; i < vg->soc->npins; i++) {
1761         void __iomem *reg;
1762         u32 value;
1763         unsigned int pin = vg->soc->pins[i].number;
1764 
1765         reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1766         if (!reg) {
1767             dev_warn(vg->dev,
1768                  "Pin %i: could not retrieve conf0 register\n",
1769                  i);
1770             continue;
1771         }
1772         value = readl(reg) & BYT_CONF0_RESTORE_MASK;
1773         vg->context.pads[i].conf0 = value;
1774 
1775         reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1776         value = readl(reg) & BYT_VAL_RESTORE_MASK;
1777         vg->context.pads[i].val = value;
1778     }
1779 
1780     raw_spin_unlock_irqrestore(&byt_lock, flags);
1781     return 0;
1782 }
1783 
1784 static int byt_gpio_resume(struct device *dev)
1785 {
1786     struct intel_pinctrl *vg = dev_get_drvdata(dev);
1787     unsigned long flags;
1788     int i;
1789 
1790     raw_spin_lock_irqsave(&byt_lock, flags);
1791 
1792     for (i = 0; i < vg->soc->npins; i++) {
1793         void __iomem *reg;
1794         u32 value;
1795         unsigned int pin = vg->soc->pins[i].number;
1796 
1797         reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1798         if (!reg) {
1799             dev_warn(vg->dev,
1800                  "Pin %i: could not retrieve conf0 register\n",
1801                  i);
1802             continue;
1803         }
1804         value = readl(reg);
1805         if ((value & BYT_CONF0_RESTORE_MASK) !=
1806              vg->context.pads[i].conf0) {
1807             value &= ~BYT_CONF0_RESTORE_MASK;
1808             value |= vg->context.pads[i].conf0;
1809             writel(value, reg);
1810             dev_info(dev, "restored pin %d conf0 %#08x", i, value);
1811         }
1812 
1813         reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1814         value = readl(reg);
1815         if ((value & BYT_VAL_RESTORE_MASK) !=
1816              vg->context.pads[i].val) {
1817             u32 v;
1818 
1819             v = value & ~BYT_VAL_RESTORE_MASK;
1820             v |= vg->context.pads[i].val;
1821             if (v != value) {
1822                 writel(v, reg);
1823                 dev_dbg(dev, "restored pin %d val %#08x\n",
1824                     i, v);
1825             }
1826         }
1827     }
1828 
1829     raw_spin_unlock_irqrestore(&byt_lock, flags);
1830     return 0;
1831 }
1832 #endif
1833 
1834 #ifdef CONFIG_PM
1835 static int byt_gpio_runtime_suspend(struct device *dev)
1836 {
1837     return 0;
1838 }
1839 
1840 static int byt_gpio_runtime_resume(struct device *dev)
1841 {
1842     return 0;
1843 }
1844 #endif
1845 
1846 static const struct dev_pm_ops byt_gpio_pm_ops = {
1847     SET_LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume)
1848     SET_RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume,
1849                NULL)
1850 };
1851 
1852 static struct platform_driver byt_gpio_driver = {
1853     .probe          = byt_pinctrl_probe,
1854     .driver         = {
1855         .name           = "byt_gpio",
1856         .pm         = &byt_gpio_pm_ops,
1857         .acpi_match_table   = byt_gpio_acpi_match,
1858         .suppress_bind_attrs    = true,
1859     },
1860 };
1861 
1862 static int __init byt_gpio_init(void)
1863 {
1864     return platform_driver_register(&byt_gpio_driver);
1865 }
1866 subsys_initcall(byt_gpio_init);
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