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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2020
0004  * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
0005  */
0006 
0007 #include <linux/err.h>
0008 #include <linux/init.h>
0009 #include <linux/of_device.h>
0010 #include <linux/pinctrl/pinctrl.h>
0011 #include <linux/platform_device.h>
0012 
0013 #include "pinctrl-imx.h"
0014 
0015 enum imxrt1050_pads {
0016     IMXRT1050_PAD_RESERVE0 = 0,
0017     IMXRT1050_PAD_RESERVE1 = 1,
0018     IMXRT1050_PAD_RESERVE2 = 2,
0019     IMXRT1050_PAD_RESERVE3 = 3,
0020     IMXRT1050_PAD_RESERVE4 = 4,
0021     IMXRT1050_PAD_RESERVE5 = 5,
0022     IMXRT1050_PAD_RESERVE6 = 6,
0023     IMXRT1050_PAD_RESERVE7 = 7,
0024     IMXRT1050_PAD_RESERVE8 = 8,
0025     IMXRT1050_PAD_RESERVE9 = 9,
0026     IMXRT1050_IOMUXC_GPIO1_IO00 = 10,
0027     IMXRT1050_IOMUXC_GPIO1_IO01 = 11,
0028     IMXRT1050_IOMUXC_GPIO1_IO02 = 12,
0029     IMXRT1050_IOMUXC_GPIO1_IO03 = 13,
0030     IMXRT1050_IOMUXC_GPIO1_IO04 = 14,
0031     IMXRT1050_IOMUXC_GPIO1_IO05 = 15,
0032     IMXRT1050_IOMUXC_GPIO1_IO06 = 16,
0033     IMXRT1050_IOMUXC_GPIO1_IO07 = 17,
0034     IMXRT1050_IOMUXC_GPIO1_IO08 = 18,
0035     IMXRT1050_IOMUXC_GPIO1_IO09 = 19,
0036     IMXRT1050_IOMUXC_GPIO1_IO10 = 20,
0037     IMXRT1050_IOMUXC_GPIO1_IO11 = 21,
0038     IMXRT1050_IOMUXC_GPIO1_IO12 = 22,
0039     IMXRT1050_IOMUXC_GPIO1_IO13 = 23,
0040     IMXRT1050_IOMUXC_GPIO1_IO14 = 24,
0041     IMXRT1050_IOMUXC_GPIO1_IO15 = 25,
0042     IMXRT1050_IOMUXC_ENET_MDC = 26,
0043     IMXRT1050_IOMUXC_ENET_MDIO = 27,
0044     IMXRT1050_IOMUXC_ENET_TD3 = 28,
0045     IMXRT1050_IOMUXC_ENET_TD2 = 29,
0046     IMXRT1050_IOMUXC_ENET_TD1 = 30,
0047     IMXRT1050_IOMUXC_ENET_TD0 = 31,
0048     IMXRT1050_IOMUXC_ENET_TX_CTL = 32,
0049     IMXRT1050_IOMUXC_ENET_TXC = 33,
0050     IMXRT1050_IOMUXC_ENET_RX_CTL = 34,
0051     IMXRT1050_IOMUXC_ENET_RXC = 35,
0052     IMXRT1050_IOMUXC_ENET_RD0 = 36,
0053     IMXRT1050_IOMUXC_ENET_RD1 = 37,
0054     IMXRT1050_IOMUXC_ENET_RD2 = 38,
0055     IMXRT1050_IOMUXC_ENET_RD3 = 39,
0056     IMXRT1050_IOMUXC_SD1_CLK = 40,
0057     IMXRT1050_IOMUXC_SD1_CMD = 41,
0058     IMXRT1050_IOMUXC_SD1_DATA0 = 42,
0059     IMXRT1050_IOMUXC_SD1_DATA1 = 43,
0060     IMXRT1050_IOMUXC_SD1_DATA2 = 44,
0061     IMXRT1050_IOMUXC_SD1_DATA3 = 45,
0062     IMXRT1050_IOMUXC_SD1_DATA4 = 46,
0063     IMXRT1050_IOMUXC_SD1_DATA5 = 47,
0064     IMXRT1050_IOMUXC_SD1_DATA6 = 48,
0065     IMXRT1050_IOMUXC_SD1_DATA7 = 49,
0066     IMXRT1050_IOMUXC_SD1_RESET_B = 50,
0067     IMXRT1050_IOMUXC_SD1_STROBE = 51,
0068     IMXRT1050_IOMUXC_SD2_CD_B = 52,
0069     IMXRT1050_IOMUXC_SD2_CLK = 53,
0070     IMXRT1050_IOMUXC_SD2_CMD = 54,
0071     IMXRT1050_IOMUXC_SD2_DATA0 = 55,
0072     IMXRT1050_IOMUXC_SD2_DATA1 = 56,
0073     IMXRT1050_IOMUXC_SD2_DATA2 = 57,
0074     IMXRT1050_IOMUXC_SD2_DATA3 = 58,
0075     IMXRT1050_IOMUXC_SD2_RESET_B = 59,
0076     IMXRT1050_IOMUXC_SD2_WP = 60,
0077     IMXRT1050_IOMUXC_NAND_ALE = 61,
0078     IMXRT1050_IOMUXC_NAND_CE0 = 62,
0079     IMXRT1050_IOMUXC_NAND_CE1 = 63,
0080     IMXRT1050_IOMUXC_NAND_CE2 = 64,
0081     IMXRT1050_IOMUXC_NAND_CE3 = 65,
0082     IMXRT1050_IOMUXC_NAND_CLE = 66,
0083     IMXRT1050_IOMUXC_NAND_DATA00 = 67,
0084     IMXRT1050_IOMUXC_NAND_DATA01 = 68,
0085     IMXRT1050_IOMUXC_NAND_DATA02 = 69,
0086     IMXRT1050_IOMUXC_NAND_DATA03 = 70,
0087     IMXRT1050_IOMUXC_NAND_DATA04 = 71,
0088     IMXRT1050_IOMUXC_NAND_DATA05 = 72,
0089     IMXRT1050_IOMUXC_NAND_DATA06 = 73,
0090     IMXRT1050_IOMUXC_NAND_DATA07 = 74,
0091     IMXRT1050_IOMUXC_NAND_DQS = 75,
0092     IMXRT1050_IOMUXC_NAND_RE_B = 76,
0093     IMXRT1050_IOMUXC_NAND_READY_B = 77,
0094     IMXRT1050_IOMUXC_NAND_WE_B = 78,
0095     IMXRT1050_IOMUXC_NAND_WP_B = 79,
0096     IMXRT1050_IOMUXC_SAI5_RXFS = 80,
0097     IMXRT1050_IOMUXC_SAI5_RXC = 81,
0098     IMXRT1050_IOMUXC_SAI5_RXD0 = 82,
0099     IMXRT1050_IOMUXC_SAI5_RXD1 = 83,
0100     IMXRT1050_IOMUXC_SAI5_RXD2 = 84,
0101     IMXRT1050_IOMUXC_SAI5_RXD3 = 85,
0102     IMXRT1050_IOMUXC_SAI5_MCLK = 86,
0103     IMXRT1050_IOMUXC_SAI1_RXFS = 87,
0104     IMXRT1050_IOMUXC_SAI1_RXC = 88,
0105     IMXRT1050_IOMUXC_SAI1_RXD0 = 89,
0106     IMXRT1050_IOMUXC_SAI1_RXD1 = 90,
0107     IMXRT1050_IOMUXC_SAI1_RXD2 = 91,
0108     IMXRT1050_IOMUXC_SAI1_RXD3 = 92,
0109     IMXRT1050_IOMUXC_SAI1_RXD4 = 93,
0110     IMXRT1050_IOMUXC_SAI1_RXD5 = 94,
0111     IMXRT1050_IOMUXC_SAI1_RXD6 = 95,
0112     IMXRT1050_IOMUXC_SAI1_RXD7 = 96,
0113     IMXRT1050_IOMUXC_SAI1_TXFS = 97,
0114     IMXRT1050_IOMUXC_SAI1_TXC = 98,
0115     IMXRT1050_IOMUXC_SAI1_TXD0 = 99,
0116     IMXRT1050_IOMUXC_SAI1_TXD1 = 100,
0117     IMXRT1050_IOMUXC_SAI1_TXD2 = 101,
0118     IMXRT1050_IOMUXC_SAI1_TXD3 = 102,
0119     IMXRT1050_IOMUXC_SAI1_TXD4 = 103,
0120     IMXRT1050_IOMUXC_SAI1_TXD5 = 104,
0121     IMXRT1050_IOMUXC_SAI1_TXD6 = 105,
0122     IMXRT1050_IOMUXC_SAI1_TXD7 = 106,
0123     IMXRT1050_IOMUXC_SAI1_MCLK = 107,
0124     IMXRT1050_IOMUXC_SAI2_RXFS = 108,
0125     IMXRT1050_IOMUXC_SAI2_RXC = 109,
0126     IMXRT1050_IOMUXC_SAI2_RXD0 = 110,
0127     IMXRT1050_IOMUXC_SAI2_TXFS = 111,
0128     IMXRT1050_IOMUXC_SAI2_TXC = 112,
0129     IMXRT1050_IOMUXC_SAI2_TXD0 = 113,
0130     IMXRT1050_IOMUXC_SAI2_MCLK = 114,
0131     IMXRT1050_IOMUXC_SAI3_RXFS = 115,
0132     IMXRT1050_IOMUXC_SAI3_RXC = 116,
0133     IMXRT1050_IOMUXC_SAI3_RXD = 117,
0134     IMXRT1050_IOMUXC_SAI3_TXFS = 118,
0135     IMXRT1050_IOMUXC_SAI3_TXC = 119,
0136     IMXRT1050_IOMUXC_SAI3_TXD = 120,
0137     IMXRT1050_IOMUXC_SAI3_MCLK = 121,
0138     IMXRT1050_IOMUXC_SPDIF_TX = 122,
0139     IMXRT1050_IOMUXC_SPDIF_RX = 123,
0140     IMXRT1050_IOMUXC_SPDIF_EXT_CLK = 124,
0141     IMXRT1050_IOMUXC_ECSPI1_SCLK = 125,
0142     IMXRT1050_IOMUXC_ECSPI1_MOSI = 126,
0143     IMXRT1050_IOMUXC_ECSPI1_MISO = 127,
0144     IMXRT1050_IOMUXC_ECSPI1_SS0 = 128,
0145     IMXRT1050_IOMUXC_ECSPI2_SCLK = 129,
0146     IMXRT1050_IOMUXC_ECSPI2_MOSI = 130,
0147     IMXRT1050_IOMUXC_ECSPI2_MISO = 131,
0148     IMXRT1050_IOMUXC_ECSPI2_SS0 = 132,
0149     IMXRT1050_IOMUXC_I2C1_SCL = 133,
0150     IMXRT1050_IOMUXC_I2C1_SDA = 134,
0151     IMXRT1050_IOMUXC_I2C2_SCL = 135,
0152     IMXRT1050_IOMUXC_I2C2_SDA = 136,
0153     IMXRT1050_IOMUXC_I2C3_SCL = 137,
0154     IMXRT1050_IOMUXC_I2C3_SDA = 138,
0155     IMXRT1050_IOMUXC_I2C4_SCL = 139,
0156     IMXRT1050_IOMUXC_I2C4_SDA = 140,
0157     IMXRT1050_IOMUXC_UART1_RXD = 141,
0158     IMXRT1050_IOMUXC_UART1_TXD = 142,
0159     IMXRT1050_IOMUXC_UART2_RXD = 143,
0160     IMXRT1050_IOMUXC_UART2_TXD = 144,
0161     IMXRT1050_IOMUXC_UART3_RXD = 145,
0162     IMXRT1050_IOMUXC_UART3_TXD = 146,
0163     IMXRT1050_IOMUXC_UART4_RXD = 147,
0164     IMXRT1050_IOMUXC_UART4_TXD = 148,
0165 };
0166 
0167 /* Pad names for the pinmux subsystem */
0168 static const struct pinctrl_pin_desc imxrt1050_pinctrl_pads[] = {
0169     IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE0),
0170     IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE1),
0171     IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE2),
0172     IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE3),
0173     IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE4),
0174     IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE5),
0175     IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE6),
0176     IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE7),
0177     IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE8),
0178     IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE9),
0179     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO00),
0180     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO01),
0181     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO02),
0182     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO03),
0183     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO04),
0184     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO05),
0185     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO06),
0186     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO07),
0187     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO08),
0188     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO09),
0189     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO10),
0190     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO11),
0191     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO12),
0192     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO13),
0193     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO14),
0194     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_GPIO1_IO15),
0195     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_MDC),
0196     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_MDIO),
0197     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TD3),
0198     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TD2),
0199     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TD1),
0200     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TD0),
0201     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TX_CTL),
0202     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_TXC),
0203     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RX_CTL),
0204     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RXC),
0205     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RD0),
0206     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RD1),
0207     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RD2),
0208     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ENET_RD3),
0209     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_CLK),
0210     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_CMD),
0211     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA0),
0212     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA1),
0213     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA2),
0214     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA3),
0215     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA4),
0216     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA5),
0217     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA6),
0218     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_DATA7),
0219     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_RESET_B),
0220     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD1_STROBE),
0221     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_CD_B),
0222     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_CLK),
0223     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_CMD),
0224     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_DATA0),
0225     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_DATA1),
0226     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_DATA2),
0227     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_DATA3),
0228     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_RESET_B),
0229     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SD2_WP),
0230     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_ALE),
0231     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_CE0),
0232     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_CE1),
0233     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_CE2),
0234     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_CE3),
0235     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_CLE),
0236     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA00),
0237     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA01),
0238     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA02),
0239     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA03),
0240     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA04),
0241     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA05),
0242     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA06),
0243     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DATA07),
0244     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_DQS),
0245     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_RE_B),
0246     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_READY_B),
0247     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_WE_B),
0248     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_NAND_WP_B),
0249     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXFS),
0250     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXC),
0251     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXD0),
0252     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXD1),
0253     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXD2),
0254     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_RXD3),
0255     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI5_MCLK),
0256     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXFS),
0257     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXC),
0258     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD0),
0259     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD1),
0260     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD2),
0261     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD3),
0262     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD4),
0263     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD5),
0264     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD6),
0265     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_RXD7),
0266     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXFS),
0267     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXC),
0268     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD0),
0269     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD1),
0270     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD2),
0271     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD3),
0272     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD4),
0273     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD5),
0274     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD6),
0275     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_TXD7),
0276     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI1_MCLK),
0277     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_RXFS),
0278     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_RXC),
0279     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_RXD0),
0280     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_TXFS),
0281     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_TXC),
0282     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_TXD0),
0283     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI2_MCLK),
0284     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_RXFS),
0285     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_RXC),
0286     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_RXD),
0287     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_TXFS),
0288     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_TXC),
0289     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_TXD),
0290     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SAI3_MCLK),
0291     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SPDIF_TX),
0292     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SPDIF_RX),
0293     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_SPDIF_EXT_CLK),
0294     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI1_SCLK),
0295     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI1_MOSI),
0296     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI1_MISO),
0297     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI1_SS0),
0298     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI2_SCLK),
0299     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI2_MOSI),
0300     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI2_MISO),
0301     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_ECSPI2_SS0),
0302     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C1_SCL),
0303     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C1_SDA),
0304     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C2_SCL),
0305     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C2_SDA),
0306     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C3_SCL),
0307     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C3_SDA),
0308     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C4_SCL),
0309     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_I2C4_SDA),
0310     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART1_RXD),
0311     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART1_TXD),
0312     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART2_RXD),
0313     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART2_TXD),
0314     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART3_RXD),
0315     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART3_TXD),
0316     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART4_RXD),
0317     IMX_PINCTRL_PIN(IMXRT1050_IOMUXC_UART4_TXD),
0318 };
0319 
0320 static const struct imx_pinctrl_soc_info imxrt1050_pinctrl_info = {
0321     .pins = imxrt1050_pinctrl_pads,
0322     .npins = ARRAY_SIZE(imxrt1050_pinctrl_pads),
0323     .gpr_compatible = "fsl,imxrt1050-iomuxc-gpr",
0324 };
0325 
0326 static const struct of_device_id imxrt1050_pinctrl_of_match[] = {
0327     { .compatible = "fsl,imxrt1050-iomuxc", .data = &imxrt1050_pinctrl_info, },
0328     { /* sentinel */ }
0329 };
0330 
0331 static int imxrt1050_pinctrl_probe(struct platform_device *pdev)
0332 {
0333     return imx_pinctrl_probe(pdev, &imxrt1050_pinctrl_info);
0334 }
0335 
0336 static struct platform_driver imxrt1050_pinctrl_driver = {
0337     .driver = {
0338         .name = "imxrt1050-pinctrl",
0339         .of_match_table = of_match_ptr(imxrt1050_pinctrl_of_match),
0340         .suppress_bind_attrs = true,
0341     },
0342     .probe = imxrt1050_pinctrl_probe,
0343 };
0344 
0345 static int __init imxrt1050_pinctrl_init(void)
0346 {
0347     return platform_driver_register(&imxrt1050_pinctrl_driver);
0348 }
0349 arch_initcall(imxrt1050_pinctrl_init);
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