Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright 2021 NXP
0004  */
0005 
0006 #include <linux/err.h>
0007 #include <linux/init.h>
0008 #include <linux/io.h>
0009 #include <linux/module.h>
0010 #include <linux/of.h>
0011 #include <linux/of_device.h>
0012 #include <linux/pinctrl/pinctrl.h>
0013 
0014 #include "pinctrl-imx.h"
0015 
0016 enum imx8ulp_pads {
0017     IMX8ULP_PAD_PTD0 = 0,
0018     IMX8ULP_PAD_PTD1,
0019     IMX8ULP_PAD_PTD2,
0020     IMX8ULP_PAD_PTD3,
0021     IMX8ULP_PAD_PTD4,
0022     IMX8ULP_PAD_PTD5,
0023     IMX8ULP_PAD_PTD6,
0024     IMX8ULP_PAD_PTD7,
0025     IMX8ULP_PAD_PTD8,
0026     IMX8ULP_PAD_PTD9,
0027     IMX8ULP_PAD_PTD10,
0028     IMX8ULP_PAD_PTD11,
0029     IMX8ULP_PAD_PTD12,
0030     IMX8ULP_PAD_PTD13,
0031     IMX8ULP_PAD_PTD14,
0032     IMX8ULP_PAD_PTD15,
0033     IMX8ULP_PAD_PTD16,
0034     IMX8ULP_PAD_PTD17,
0035     IMX8ULP_PAD_PTD18,
0036     IMX8ULP_PAD_PTD19,
0037     IMX8ULP_PAD_PTD20,
0038     IMX8ULP_PAD_PTD21,
0039     IMX8ULP_PAD_PTD22,
0040     IMX8ULP_PAD_PTD23,
0041     IMX8ULP_PAD_RESERVE0,
0042     IMX8ULP_PAD_RESERVE1,
0043     IMX8ULP_PAD_RESERVE2,
0044     IMX8ULP_PAD_RESERVE3,
0045     IMX8ULP_PAD_RESERVE4,
0046     IMX8ULP_PAD_RESERVE5,
0047     IMX8ULP_PAD_RESERVE6,
0048     IMX8ULP_PAD_RESERVE7,
0049     IMX8ULP_PAD_PTE0,
0050     IMX8ULP_PAD_PTE1,
0051     IMX8ULP_PAD_PTE2,
0052     IMX8ULP_PAD_PTE3,
0053     IMX8ULP_PAD_PTE4,
0054     IMX8ULP_PAD_PTE5,
0055     IMX8ULP_PAD_PTE6,
0056     IMX8ULP_PAD_PTE7,
0057     IMX8ULP_PAD_PTE8,
0058     IMX8ULP_PAD_PTE9,
0059     IMX8ULP_PAD_PTE10,
0060     IMX8ULP_PAD_PTE11,
0061     IMX8ULP_PAD_PTE12,
0062     IMX8ULP_PAD_PTE13,
0063     IMX8ULP_PAD_PTE14,
0064     IMX8ULP_PAD_PTE15,
0065     IMX8ULP_PAD_PTE16,
0066     IMX8ULP_PAD_PTE17,
0067     IMX8ULP_PAD_PTE18,
0068     IMX8ULP_PAD_PTE19,
0069     IMX8ULP_PAD_PTE20,
0070     IMX8ULP_PAD_PTE21,
0071     IMX8ULP_PAD_PTE22,
0072     IMX8ULP_PAD_PTE23,
0073     IMX8ULP_PAD_RESERVE8,
0074     IMX8ULP_PAD_RESERVE9,
0075     IMX8ULP_PAD_RESERVE10,
0076     IMX8ULP_PAD_RESERVE11,
0077     IMX8ULP_PAD_RESERVE12,
0078     IMX8ULP_PAD_RESERVE13,
0079     IMX8ULP_PAD_RESERVE14,
0080     IMX8ULP_PAD_RESERVE15,
0081     IMX8ULP_PAD_PTF0,
0082     IMX8ULP_PAD_PTF1,
0083     IMX8ULP_PAD_PTF2,
0084     IMX8ULP_PAD_PTF3,
0085     IMX8ULP_PAD_PTF4,
0086     IMX8ULP_PAD_PTF5,
0087     IMX8ULP_PAD_PTF6,
0088     IMX8ULP_PAD_PTF7,
0089     IMX8ULP_PAD_PTF8,
0090     IMX8ULP_PAD_PTF9,
0091     IMX8ULP_PAD_PTF10,
0092     IMX8ULP_PAD_PTF11,
0093     IMX8ULP_PAD_PTF12,
0094     IMX8ULP_PAD_PTF13,
0095     IMX8ULP_PAD_PTF14,
0096     IMX8ULP_PAD_PTF15,
0097     IMX8ULP_PAD_PTF16,
0098     IMX8ULP_PAD_PTF17,
0099     IMX8ULP_PAD_PTF18,
0100     IMX8ULP_PAD_PTF19,
0101     IMX8ULP_PAD_PTF20,
0102     IMX8ULP_PAD_PTF21,
0103     IMX8ULP_PAD_PTF22,
0104     IMX8ULP_PAD_PTF23,
0105     IMX8ULP_PAD_PTF24,
0106     IMX8ULP_PAD_PTF25,
0107     IMX8ULP_PAD_PTF26,
0108     IMX8ULP_PAD_PTF27,
0109     IMX8ULP_PAD_PTF28,
0110     IMX8ULP_PAD_PTF29,
0111     IMX8ULP_PAD_PTF30,
0112     IMX8ULP_PAD_PTF31,
0113 };
0114 
0115 /* Pad names for the pinmux subsystem */
0116 static const struct pinctrl_pin_desc imx8ulp_pinctrl_pads[] = {
0117     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD0),
0118     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD1),
0119     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD2),
0120     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD3),
0121     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD4),
0122     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD5),
0123     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD6),
0124     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD7),
0125     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD8),
0126     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD9),
0127     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD10),
0128     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD11),
0129     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD12),
0130     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD13),
0131     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD14),
0132     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD15),
0133     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD16),
0134     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD17),
0135     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD18),
0136     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD19),
0137     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD20),
0138     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD21),
0139     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD22),
0140     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTD23),
0141     IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE0),
0142     IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE1),
0143     IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE2),
0144     IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE3),
0145     IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE4),
0146     IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE5),
0147     IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE6),
0148     IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE7),
0149     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE0),
0150     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE1),
0151     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE2),
0152     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE3),
0153     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE4),
0154     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE5),
0155     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE6),
0156     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE7),
0157     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE8),
0158     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE9),
0159     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE10),
0160     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE11),
0161     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE12),
0162     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE13),
0163     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE14),
0164     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE15),
0165     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE16),
0166     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE17),
0167     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE18),
0168     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE19),
0169     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE20),
0170     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE21),
0171     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE22),
0172     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTE23),
0173     IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE8),
0174     IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE9),
0175     IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE10),
0176     IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE11),
0177     IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE12),
0178     IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE13),
0179     IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE14),
0180     IMX_PINCTRL_PIN(IMX8ULP_PAD_RESERVE15),
0181     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF0),
0182     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF1),
0183     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF2),
0184     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF3),
0185     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF4),
0186     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF5),
0187     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF6),
0188     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF7),
0189     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF8),
0190     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF9),
0191     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF10),
0192     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF11),
0193     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF12),
0194     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF13),
0195     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF14),
0196     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF15),
0197     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF16),
0198     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF17),
0199     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF18),
0200     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF19),
0201     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF20),
0202     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF21),
0203     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF22),
0204     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF23),
0205     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF24),
0206     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF25),
0207     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF26),
0208     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF27),
0209     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF28),
0210     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF29),
0211     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF30),
0212     IMX_PINCTRL_PIN(IMX8ULP_PAD_PTF31),
0213 };
0214 
0215 #define BM_OBE_ENABLED      BIT(17)
0216 #define BM_IBE_ENABLED      BIT(16)
0217 #define BM_MUX_MODE     0xf00
0218 #define BP_MUX_MODE     8
0219 
0220 static int imx8ulp_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
0221                       struct pinctrl_gpio_range *range,
0222                       unsigned offset, bool input)
0223 {
0224     struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
0225     const struct imx_pin_reg *pin_reg;
0226     u32 reg;
0227 
0228     pin_reg = &ipctl->pin_regs[offset];
0229     if (pin_reg->mux_reg == -1)
0230         return -EINVAL;
0231 
0232     reg = readl(ipctl->base + pin_reg->mux_reg);
0233     if (input)
0234         reg = (reg & ~BM_OBE_ENABLED) | BM_IBE_ENABLED;
0235     else
0236         reg = (reg & ~BM_IBE_ENABLED) | BM_OBE_ENABLED;
0237     writel(reg, ipctl->base + pin_reg->mux_reg);
0238 
0239     return 0;
0240 }
0241 
0242 static const struct imx_pinctrl_soc_info imx8ulp_pinctrl_info = {
0243     .pins = imx8ulp_pinctrl_pads,
0244     .npins = ARRAY_SIZE(imx8ulp_pinctrl_pads),
0245     .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG,
0246     .gpio_set_direction = imx8ulp_pmx_gpio_set_direction,
0247     .mux_mask = BM_MUX_MODE,
0248     .mux_shift = BP_MUX_MODE,
0249 };
0250 
0251 static const struct of_device_id imx8ulp_pinctrl_of_match[] = {
0252     { .compatible = "fsl,imx8ulp-iomuxc1", },
0253     { /* sentinel */ }
0254 };
0255 
0256 static int imx8ulp_pinctrl_probe(struct platform_device *pdev)
0257 {
0258     return imx_pinctrl_probe(pdev, &imx8ulp_pinctrl_info);
0259 }
0260 
0261 static struct platform_driver imx8ulp_pinctrl_driver = {
0262     .driver = {
0263         .name = "imx8ulp-pinctrl",
0264         .of_match_table = imx8ulp_pinctrl_of_match,
0265         .suppress_bind_attrs = true,
0266     },
0267     .probe = imx8ulp_pinctrl_probe,
0268 };
0269 
0270 static int __init imx8ulp_pinctrl_init(void)
0271 {
0272     return platform_driver_register(&imx8ulp_pinctrl_driver);
0273 }
0274 arch_initcall(imx8ulp_pinctrl_init);
0275 
0276 MODULE_AUTHOR("Jacky Bai <ping.bai@nxp.com>");
0277 MODULE_DESCRIPTION("NXP i.MX8ULP pinctrl driver");
0278 MODULE_LICENSE("GPL v2");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!