Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Copyright (C) 2016 Freescale Semiconductor, Inc.
0004 // Copyright (C) 2017 NXP
0005 //
0006 // Author: Dong Aisheng <aisheng.dong@nxp.com>
0007 
0008 #include <linux/err.h>
0009 #include <linux/init.h>
0010 #include <linux/io.h>
0011 #include <linux/module.h>
0012 #include <linux/of.h>
0013 #include <linux/of_device.h>
0014 #include <linux/pinctrl/pinctrl.h>
0015 
0016 #include "pinctrl-imx.h"
0017 
0018 enum imx7ulp_pads {
0019     IMX7ULP_PAD_PTC0 = 0,
0020     IMX7ULP_PAD_PTC1,
0021     IMX7ULP_PAD_PTC2,
0022     IMX7ULP_PAD_PTC3,
0023     IMX7ULP_PAD_PTC4,
0024     IMX7ULP_PAD_PTC5,
0025     IMX7ULP_PAD_PTC6,
0026     IMX7ULP_PAD_PTC7,
0027     IMX7ULP_PAD_PTC8,
0028     IMX7ULP_PAD_PTC9,
0029     IMX7ULP_PAD_PTC10,
0030     IMX7ULP_PAD_PTC11,
0031     IMX7ULP_PAD_PTC12,
0032     IMX7ULP_PAD_PTC13,
0033     IMX7ULP_PAD_PTC14,
0034     IMX7ULP_PAD_PTC15,
0035     IMX7ULP_PAD_PTC16,
0036     IMX7ULP_PAD_PTC17,
0037     IMX7ULP_PAD_PTC18,
0038     IMX7ULP_PAD_PTC19,
0039     IMX7ULP_PAD_RESERVE0,
0040     IMX7ULP_PAD_RESERVE1,
0041     IMX7ULP_PAD_RESERVE2,
0042     IMX7ULP_PAD_RESERVE3,
0043     IMX7ULP_PAD_RESERVE4,
0044     IMX7ULP_PAD_RESERVE5,
0045     IMX7ULP_PAD_RESERVE6,
0046     IMX7ULP_PAD_RESERVE7,
0047     IMX7ULP_PAD_RESERVE8,
0048     IMX7ULP_PAD_RESERVE9,
0049     IMX7ULP_PAD_RESERVE10,
0050     IMX7ULP_PAD_RESERVE11,
0051     IMX7ULP_PAD_PTD0,
0052     IMX7ULP_PAD_PTD1,
0053     IMX7ULP_PAD_PTD2,
0054     IMX7ULP_PAD_PTD3,
0055     IMX7ULP_PAD_PTD4,
0056     IMX7ULP_PAD_PTD5,
0057     IMX7ULP_PAD_PTD6,
0058     IMX7ULP_PAD_PTD7,
0059     IMX7ULP_PAD_PTD8,
0060     IMX7ULP_PAD_PTD9,
0061     IMX7ULP_PAD_PTD10,
0062     IMX7ULP_PAD_PTD11,
0063     IMX7ULP_PAD_RESERVE12,
0064     IMX7ULP_PAD_RESERVE13,
0065     IMX7ULP_PAD_RESERVE14,
0066     IMX7ULP_PAD_RESERVE15,
0067     IMX7ULP_PAD_RESERVE16,
0068     IMX7ULP_PAD_RESERVE17,
0069     IMX7ULP_PAD_RESERVE18,
0070     IMX7ULP_PAD_RESERVE19,
0071     IMX7ULP_PAD_RESERVE20,
0072     IMX7ULP_PAD_RESERVE21,
0073     IMX7ULP_PAD_RESERVE22,
0074     IMX7ULP_PAD_RESERVE23,
0075     IMX7ULP_PAD_RESERVE24,
0076     IMX7ULP_PAD_RESERVE25,
0077     IMX7ULP_PAD_RESERVE26,
0078     IMX7ULP_PAD_RESERVE27,
0079     IMX7ULP_PAD_RESERVE28,
0080     IMX7ULP_PAD_RESERVE29,
0081     IMX7ULP_PAD_RESERVE30,
0082     IMX7ULP_PAD_RESERVE31,
0083     IMX7ULP_PAD_PTE0,
0084     IMX7ULP_PAD_PTE1,
0085     IMX7ULP_PAD_PTE2,
0086     IMX7ULP_PAD_PTE3,
0087     IMX7ULP_PAD_PTE4,
0088     IMX7ULP_PAD_PTE5,
0089     IMX7ULP_PAD_PTE6,
0090     IMX7ULP_PAD_PTE7,
0091     IMX7ULP_PAD_PTE8,
0092     IMX7ULP_PAD_PTE9,
0093     IMX7ULP_PAD_PTE10,
0094     IMX7ULP_PAD_PTE11,
0095     IMX7ULP_PAD_PTE12,
0096     IMX7ULP_PAD_PTE13,
0097     IMX7ULP_PAD_PTE14,
0098     IMX7ULP_PAD_PTE15,
0099     IMX7ULP_PAD_RESERVE32,
0100     IMX7ULP_PAD_RESERVE33,
0101     IMX7ULP_PAD_RESERVE34,
0102     IMX7ULP_PAD_RESERVE35,
0103     IMX7ULP_PAD_RESERVE36,
0104     IMX7ULP_PAD_RESERVE37,
0105     IMX7ULP_PAD_RESERVE38,
0106     IMX7ULP_PAD_RESERVE39,
0107     IMX7ULP_PAD_RESERVE40,
0108     IMX7ULP_PAD_RESERVE41,
0109     IMX7ULP_PAD_RESERVE42,
0110     IMX7ULP_PAD_RESERVE43,
0111     IMX7ULP_PAD_RESERVE44,
0112     IMX7ULP_PAD_RESERVE45,
0113     IMX7ULP_PAD_RESERVE46,
0114     IMX7ULP_PAD_RESERVE47,
0115     IMX7ULP_PAD_PTF0,
0116     IMX7ULP_PAD_PTF1,
0117     IMX7ULP_PAD_PTF2,
0118     IMX7ULP_PAD_PTF3,
0119     IMX7ULP_PAD_PTF4,
0120     IMX7ULP_PAD_PTF5,
0121     IMX7ULP_PAD_PTF6,
0122     IMX7ULP_PAD_PTF7,
0123     IMX7ULP_PAD_PTF8,
0124     IMX7ULP_PAD_PTF9,
0125     IMX7ULP_PAD_PTF10,
0126     IMX7ULP_PAD_PTF11,
0127     IMX7ULP_PAD_PTF12,
0128     IMX7ULP_PAD_PTF13,
0129     IMX7ULP_PAD_PTF14,
0130     IMX7ULP_PAD_PTF15,
0131     IMX7ULP_PAD_PTF16,
0132     IMX7ULP_PAD_PTF17,
0133     IMX7ULP_PAD_PTF18,
0134     IMX7ULP_PAD_PTF19,
0135 };
0136 
0137 /* Pad names for the pinmux subsystem */
0138 static const struct pinctrl_pin_desc imx7ulp_pinctrl_pads[] = {
0139     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC0),
0140     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC1),
0141     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC2),
0142     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC3),
0143     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC4),
0144     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC5),
0145     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC6),
0146     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC7),
0147     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC8),
0148     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC9),
0149     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC10),
0150     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC11),
0151     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC12),
0152     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC13),
0153     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC14),
0154     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC15),
0155     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC16),
0156     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC17),
0157     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC18),
0158     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC19),
0159     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE0),
0160     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE1),
0161     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE2),
0162     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE3),
0163     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE4),
0164     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE5),
0165     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE6),
0166     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE7),
0167     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE8),
0168     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE9),
0169     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE10),
0170     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE11),
0171     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD0),
0172     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD1),
0173     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD2),
0174     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD3),
0175     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD4),
0176     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD5),
0177     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD6),
0178     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD7),
0179     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD8),
0180     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD9),
0181     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD10),
0182     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD11),
0183     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE12),
0184     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE13),
0185     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE14),
0186     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE15),
0187     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE16),
0188     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE17),
0189     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE18),
0190     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE19),
0191     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE20),
0192     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE21),
0193     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE22),
0194     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE23),
0195     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE24),
0196     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE25),
0197     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE26),
0198     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE27),
0199     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE28),
0200     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE29),
0201     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE30),
0202     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE31),
0203     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE0),
0204     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE1),
0205     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE2),
0206     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE3),
0207     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE4),
0208     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE5),
0209     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE6),
0210     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE7),
0211     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE8),
0212     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE9),
0213     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE10),
0214     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE11),
0215     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE12),
0216     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE13),
0217     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE14),
0218     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE15),
0219     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE32),
0220     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE33),
0221     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE34),
0222     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE35),
0223     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE36),
0224     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE37),
0225     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE38),
0226     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE39),
0227     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE40),
0228     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE41),
0229     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE42),
0230     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE43),
0231     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE44),
0232     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE45),
0233     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE46),
0234     IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE47),
0235     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF0),
0236     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF1),
0237     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF2),
0238     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF3),
0239     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF4),
0240     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF5),
0241     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF6),
0242     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF7),
0243     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF8),
0244     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF9),
0245     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF10),
0246     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF11),
0247     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF12),
0248     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF13),
0249     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF14),
0250     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF15),
0251     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF16),
0252     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF17),
0253     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF18),
0254     IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF19),
0255 };
0256 
0257 #define BM_OBE_ENABLED      BIT(17)
0258 #define BM_IBE_ENABLED      BIT(16)
0259 #define BM_MUX_MODE     0xf00
0260 #define BP_MUX_MODE     8
0261 
0262 static int imx7ulp_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
0263                       struct pinctrl_gpio_range *range,
0264                       unsigned offset, bool input)
0265 {
0266     struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
0267     const struct imx_pin_reg *pin_reg;
0268     u32 reg;
0269 
0270     pin_reg = &ipctl->pin_regs[offset];
0271     if (pin_reg->mux_reg == -1)
0272         return -EINVAL;
0273 
0274     reg = readl(ipctl->base + pin_reg->mux_reg);
0275     if (input)
0276         reg = (reg & ~BM_OBE_ENABLED) | BM_IBE_ENABLED;
0277     else
0278         reg = (reg & ~BM_IBE_ENABLED) | BM_OBE_ENABLED;
0279     writel(reg, ipctl->base + pin_reg->mux_reg);
0280 
0281     return 0;
0282 }
0283 
0284 static const struct imx_pinctrl_soc_info imx7ulp_pinctrl_info = {
0285     .pins = imx7ulp_pinctrl_pads,
0286     .npins = ARRAY_SIZE(imx7ulp_pinctrl_pads),
0287     .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG,
0288     .gpio_set_direction = imx7ulp_pmx_gpio_set_direction,
0289     .mux_mask = BM_MUX_MODE,
0290     .mux_shift = BP_MUX_MODE,
0291 };
0292 
0293 static const struct of_device_id imx7ulp_pinctrl_of_match[] = {
0294     { .compatible = "fsl,imx7ulp-iomuxc1", },
0295     { /* sentinel */ }
0296 };
0297 
0298 static int imx7ulp_pinctrl_probe(struct platform_device *pdev)
0299 {
0300     return imx_pinctrl_probe(pdev, &imx7ulp_pinctrl_info);
0301 }
0302 
0303 static struct platform_driver imx7ulp_pinctrl_driver = {
0304     .driver = {
0305         .name = "imx7ulp-pinctrl",
0306         .of_match_table = imx7ulp_pinctrl_of_match,
0307         .suppress_bind_attrs = true,
0308     },
0309     .probe = imx7ulp_pinctrl_probe,
0310 };
0311 
0312 static int __init imx7ulp_pinctrl_init(void)
0313 {
0314     return platform_driver_register(&imx7ulp_pinctrl_driver);
0315 }
0316 arch_initcall(imx7ulp_pinctrl_init);
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!