pinctrl/freescale/pinctrl-imx1-core.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 //
0003 // Core driver for the imx pin controller in imx1/21/27
0004 //
0005 // Copyright (C) 2013 Pengutronix
0006 // Author: Markus Pargmann <mpa@pengutronix.de>
0007 //
0008 // Based on pinctrl-imx.c:
0009 //  Author: Dong Aisheng <dong.aisheng@linaro.org>
0010 //  Copyright (C) 2012 Freescale Semiconductor, Inc.
0011 //  Copyright (C) 2012 Linaro Ltd.
0012
0013 #include <linux/bitops.h>
0014 #include <linux/err.h>
0015 #include <linux/init.h>
0016 #include <linux/io.h>
0017 #include <linux/of.h>
0018 #include <linux/of_device.h>
0019 #include <linux/pinctrl/machine.h>
0020 #include <linux/pinctrl/pinconf.h>
0021 #include <linux/pinctrl/pinctrl.h>
0022 #include <linux/pinctrl/pinmux.h>
0023 #include <linux/slab.h>
0024
0025 #include "../core.h"
0026 #include "pinctrl-imx1.h"
0027
0028 struct imx1_pinctrl {
0029     struct device *dev;
0030     struct pinctrl_dev *pctl;
0031     void __iomem *base;
0032     const struct imx1_pinctrl_soc_info *info;
0033 };
0034
0035 /*
0036  * MX1 register offsets
0037  */
0038
0039 #define MX1_DDIR 0x00
0040 #define MX1_OCR 0x04
0041 #define MX1_ICONFA 0x0c
0042 #define MX1_ICONFB 0x14
0043 #define MX1_GIUS 0x20
0044 #define MX1_GPR 0x38
0045 #define MX1_PUEN 0x40
0046
0047 #define MX1_PORT_STRIDE 0x100
0048
0049
0050 /*
0051  * MUX_ID format defines
0052  */
0053 #define MX1_MUX_FUNCTION(val) (BIT(0) & val)
0054 #define MX1_MUX_GPIO(val) ((BIT(1) & val) >> 1)
0055 #define MX1_MUX_DIR(val) ((BIT(2) & val) >> 2)
0056 #define MX1_MUX_OCONF(val) (((BIT(4) | BIT(5)) & val) >> 4)
0057 #define MX1_MUX_ICONFA(val) (((BIT(8) | BIT(9)) & val) >> 8)
0058 #define MX1_MUX_ICONFB(val) (((BIT(10) | BIT(11)) & val) >> 10)
0059
0060
0061 /*
0062  * IMX1 IOMUXC manages the pins based on ports. Each port has 32 pins. IOMUX
0063  * control registers are separated into function, output configuration, input
0064  * configuration A, input configuration B, GPIO in use and data direction.
0065  *
0066  * Those controls that are represented by 1 bit have a direct mapping between
0067  * bit position and pin id. If they are represented by 2 bit, the lower 16 pins
0068  * are in the first register and the upper 16 pins in the second (next)
0069  * register. pin_id is stored in bit (pin_id%16)*2 and the bit above.
0070  */
0071
0072 /*
0073  * Calculates the register offset from a pin_id
0074  */
0075 static void __iomem *imx1_mem(struct imx1_pinctrl *ipctl, unsigned int pin_id)
0076 {
0077     unsigned int port = pin_id / 32;
0078     return ipctl->base + port * MX1_PORT_STRIDE;
0079 }
0080
0081 /*
0082  * Write to a register with 2 bits per pin. The function will automatically
0083  * use the next register if the pin is managed in the second register.
0084  */
0085 static void imx1_write_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
0086         u32 value, u32 reg_offset)
0087 {
0088     void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
0089     int offset = (pin_id % 16) * 2; /* offset, regardless of register used */
0090     int mask = ~(0x3 << offset); /* Mask for 2 bits at offset */
0091     u32 old_val;
0092     u32 new_val;
0093
0094     /* Use the next register if the pin's port pin number is >=16 */
0095     if (pin_id % 32 >= 16)
0096         reg += 0x04;
0097
0098     dev_dbg(ipctl->dev, "write: register 0x%p offset %d value 0x%x\n",
0099             reg, offset, value);
0100
0101     /* Get current state of pins */
0102     old_val = readl(reg);
0103     old_val &= mask;
0104
0105     new_val = value & 0x3; /* Make sure value is really 2 bit */
0106     new_val <<= offset;
0107     new_val |= old_val;/* Set new state for pin_id */
0108
0109     writel(new_val, reg);
0110 }
0111
0112 static void imx1_write_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
0113         u32 value, u32 reg_offset)
0114 {
0115     void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
0116     int offset = pin_id % 32;
0117     int mask = ~BIT_MASK(offset);
0118     u32 old_val;
0119     u32 new_val;
0120
0121     /* Get current state of pins */
0122     old_val = readl(reg);
0123     old_val &= mask;
0124
0125     new_val = value & 0x1; /* Make sure value is really 1 bit */
0126     new_val <<= offset;
0127     new_val |= old_val;/* Set new state for pin_id */
0128
0129     writel(new_val, reg);
0130 }
0131
0132 static int imx1_read_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
0133         u32 reg_offset)
0134 {
0135     void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
0136     int offset = (pin_id % 16) * 2;
0137
0138     /* Use the next register if the pin's port pin number is >=16 */
0139     if (pin_id % 32 >= 16)
0140         reg += 0x04;
0141
0142     return (readl(reg) & (BIT(offset) | BIT(offset+1))) >> offset;
0143 }
0144
0145 static int imx1_read_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
0146         u32 reg_offset)
0147 {
0148     void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
0149     int offset = pin_id % 32;
0150
0151     return !!(readl(reg) & BIT(offset));
0152 }
0153
0154 static inline const struct imx1_pin_group *imx1_pinctrl_find_group_by_name(
0155                 const struct imx1_pinctrl_soc_info *info,
0156                 const char *name)
0157 {
0158     const struct imx1_pin_group *grp = NULL;
0159     int i;
0160
0161     for (i = 0; i < info->ngroups; i++) {
0162         if (!strcmp(info->groups[i].name, name)) {
0163             grp = &info->groups[i];
0164             break;
0165         }
0166     }
0167
0168     return grp;
0169 }
0170
0171 static int imx1_get_groups_count(struct pinctrl_dev *pctldev)
0172 {
0173     struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
0174     const struct imx1_pinctrl_soc_info *info = ipctl->info;
0175
0176     return info->ngroups;
0177 }
0178
0179 static const char *imx1_get_group_name(struct pinctrl_dev *pctldev,
0180                        unsigned selector)
0181 {
0182     struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
0183     const struct imx1_pinctrl_soc_info *info = ipctl->info;
0184
0185     return info->groups[selector].name;
0186 }
0187
0188 static int imx1_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
0189                    const unsigned int **pins,
0190                    unsigned *npins)
0191 {
0192     struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
0193     const struct imx1_pinctrl_soc_info *info = ipctl->info;
0194
0195     if (selector >= info->ngroups)
0196         return -EINVAL;
0197
0198     *pins = info->groups[selector].pin_ids;
0199     *npins = info->groups[selector].npins;
0200
0201     return 0;
0202 }
0203
0204 static void imx1_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
0205            unsigned offset)
0206 {
0207     struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
0208
0209     seq_printf(s, "GPIO %d, function %d, direction %d, oconf %d, iconfa %d, iconfb %d",
0210             imx1_read_bit(ipctl, offset, MX1_GIUS),
0211             imx1_read_bit(ipctl, offset, MX1_GPR),
0212             imx1_read_bit(ipctl, offset, MX1_DDIR),
0213             imx1_read_2bit(ipctl, offset, MX1_OCR),
0214             imx1_read_2bit(ipctl, offset, MX1_ICONFA),
0215             imx1_read_2bit(ipctl, offset, MX1_ICONFB));
0216 }
0217
0218 static int imx1_dt_node_to_map(struct pinctrl_dev *pctldev,
0219             struct device_node *np,
0220             struct pinctrl_map **map, unsigned *num_maps)
0221 {
0222     struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
0223     const struct imx1_pinctrl_soc_info *info = ipctl->info;
0224     const struct imx1_pin_group *grp;
0225     struct pinctrl_map *new_map;
0226     struct device_node *parent;
0227     int map_num = 1;
0228     int i, j;
0229
0230     /*
0231      * first find the group of this node and check if we need create
0232      * config maps for pins
0233      */
0234     grp = imx1_pinctrl_find_group_by_name(info, np->name);
0235     if (!grp) {
0236         dev_err(info->dev, "unable to find group for node %pOFn\n",
0237             np);
0238         return -EINVAL;
0239     }
0240
0241     for (i = 0; i < grp->npins; i++)
0242         map_num++;
0243
0244     new_map = kmalloc_array(map_num, sizeof(struct pinctrl_map),
0245                 GFP_KERNEL);
0246     if (!new_map)
0247         return -ENOMEM;
0248
0249     *map = new_map;
0250     *num_maps = map_num;
0251
0252     /* create mux map */
0253     parent = of_get_parent(np);
0254     if (!parent) {
0255         kfree(new_map);
0256         return -EINVAL;
0257     }
0258     new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
0259     new_map[0].data.mux.function = parent->name;
0260     new_map[0].data.mux.group = np->name;
0261     of_node_put(parent);
0262
0263     /* create config map */
0264     new_map++;
0265     for (i = j = 0; i < grp->npins; i++) {
0266         new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
0267         new_map[j].data.configs.group_or_pin =
0268                 pin_get_name(pctldev, grp->pins[i].pin_id);
0269         new_map[j].data.configs.configs = &grp->pins[i].config;
0270         new_map[j].data.configs.num_configs = 1;
0271         j++;
0272     }
0273
0274     dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
0275         (*map)->data.mux.function, (*map)->data.mux.group, map_num);
0276
0277     return 0;
0278 }
0279
0280 static void imx1_dt_free_map(struct pinctrl_dev *pctldev,
0281                 struct pinctrl_map *map, unsigned num_maps)
0282 {
0283     kfree(map);
0284 }
0285
0286 static const struct pinctrl_ops imx1_pctrl_ops = {
0287     .get_groups_count = imx1_get_groups_count,
0288     .get_group_name = imx1_get_group_name,
0289     .get_group_pins = imx1_get_group_pins,
0290     .pin_dbg_show = imx1_pin_dbg_show,
0291     .dt_node_to_map = imx1_dt_node_to_map,
0292     .dt_free_map = imx1_dt_free_map,
0293 };
0294
0295 static int imx1_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
0296             unsigned group)
0297 {
0298     struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
0299     const struct imx1_pinctrl_soc_info *info = ipctl->info;
0300     const struct imx1_pin *pins;
0301     unsigned int npins;
0302     int i;
0303
0304     /*
0305      * Configure the mux mode for each pin in the group for a specific
0306      * function.
0307      */
0308     pins = info->groups[group].pins;
0309     npins = info->groups[group].npins;
0310
0311     WARN_ON(!pins || !npins);
0312
0313     dev_dbg(ipctl->dev, "enable function %s group %s\n",
0314         info->functions[selector].name, info->groups[group].name);
0315
0316     for (i = 0; i < npins; i++) {
0317         unsigned int mux = pins[i].mux_id;
0318         unsigned int pin_id = pins[i].pin_id;
0319         unsigned int afunction = MX1_MUX_FUNCTION(mux);
0320         unsigned int gpio_in_use = MX1_MUX_GPIO(mux);
0321         unsigned int direction = MX1_MUX_DIR(mux);
0322         unsigned int gpio_oconf = MX1_MUX_OCONF(mux);
0323         unsigned int gpio_iconfa = MX1_MUX_ICONFA(mux);
0324         unsigned int gpio_iconfb = MX1_MUX_ICONFB(mux);
0325
0326         dev_dbg(pctldev->dev, "%s, pin 0x%x, function %d, gpio %d, direction %d, oconf %d, iconfa %d, iconfb %d\n",
0327                 __func__, pin_id, afunction, gpio_in_use,
0328                 direction, gpio_oconf, gpio_iconfa,
0329                 gpio_iconfb);
0330
0331         imx1_write_bit(ipctl, pin_id, gpio_in_use, MX1_GIUS);
0332         imx1_write_bit(ipctl, pin_id, direction, MX1_DDIR);
0333
0334         if (gpio_in_use) {
0335             imx1_write_2bit(ipctl, pin_id, gpio_oconf, MX1_OCR);
0336             imx1_write_2bit(ipctl, pin_id, gpio_iconfa,
0337                     MX1_ICONFA);
0338             imx1_write_2bit(ipctl, pin_id, gpio_iconfb,
0339                     MX1_ICONFB);
0340         } else {
0341             imx1_write_bit(ipctl, pin_id, afunction, MX1_GPR);
0342         }
0343     }
0344
0345     return 0;
0346 }
0347
0348 static int imx1_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
0349 {
0350     struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
0351     const struct imx1_pinctrl_soc_info *info = ipctl->info;
0352
0353     return info->nfunctions;
0354 }
0355
0356 static const char *imx1_pmx_get_func_name(struct pinctrl_dev *pctldev,
0357                       unsigned selector)
0358 {
0359     struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
0360     const struct imx1_pinctrl_soc_info *info = ipctl->info;
0361
0362     return info->functions[selector].name;
0363 }
0364
0365 static int imx1_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
0366                    const char * const **groups,
0367                    unsigned * const num_groups)
0368 {
0369     struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
0370     const struct imx1_pinctrl_soc_info *info = ipctl->info;
0371
0372     *groups = info->functions[selector].groups;
0373     *num_groups = info->functions[selector].num_groups;
0374
0375     return 0;
0376 }
0377
0378 static const struct pinmux_ops imx1_pmx_ops = {
0379     .get_functions_count = imx1_pmx_get_funcs_count,
0380     .get_function_name = imx1_pmx_get_func_name,
0381     .get_function_groups = imx1_pmx_get_groups,
0382     .set_mux = imx1_pmx_set,
0383 };
0384
0385 static int imx1_pinconf_get(struct pinctrl_dev *pctldev,
0386                  unsigned pin_id, unsigned long *config)
0387 {
0388     struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
0389
0390     *config = imx1_read_bit(ipctl, pin_id, MX1_PUEN);
0391
0392     return 0;
0393 }
0394
0395 static int imx1_pinconf_set(struct pinctrl_dev *pctldev,
0396                  unsigned pin_id, unsigned long *configs,
0397                  unsigned num_configs)
0398 {
0399     struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
0400     int i;
0401
0402     for (i = 0; i != num_configs; ++i) {
0403         imx1_write_bit(ipctl, pin_id, configs[i] & 0x01, MX1_PUEN);
0404
0405         dev_dbg(ipctl->dev, "pinconf set pullup pin %s\n",
0406             pin_desc_get(pctldev, pin_id)->name);
0407     }
0408
0409     return 0;
0410 }
0411
0412 static void imx1_pinconf_dbg_show(struct pinctrl_dev *pctldev,
0413                    struct seq_file *s, unsigned pin_id)
0414 {
0415     unsigned long config;
0416
0417     imx1_pinconf_get(pctldev, pin_id, &config);
0418     seq_printf(s, "0x%lx", config);
0419 }
0420
0421 static void imx1_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
0422                      struct seq_file *s, unsigned group)
0423 {
0424     struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
0425     const struct imx1_pinctrl_soc_info *info = ipctl->info;
0426     struct imx1_pin_group *grp;
0427     unsigned long config;
0428     const char *name;
0429     int i, ret;
0430
0431     if (group >= info->ngroups)
0432         return;
0433
0434     seq_puts(s, "\n");
0435     grp = &info->groups[group];
0436     for (i = 0; i < grp->npins; i++) {
0437         name = pin_get_name(pctldev, grp->pins[i].pin_id);
0438         ret = imx1_pinconf_get(pctldev, grp->pins[i].pin_id, &config);
0439         if (ret)
0440             return;
0441         seq_printf(s, "%s: 0x%lx", name, config);
0442     }
0443 }
0444
0445 static const struct pinconf_ops imx1_pinconf_ops = {
0446     .pin_config_get = imx1_pinconf_get,
0447     .pin_config_set = imx1_pinconf_set,
0448     .pin_config_dbg_show = imx1_pinconf_dbg_show,
0449     .pin_config_group_dbg_show = imx1_pinconf_group_dbg_show,
0450 };
0451
0452 static struct pinctrl_desc imx1_pinctrl_desc = {
0453     .pctlops = &imx1_pctrl_ops,
0454     .pmxops = &imx1_pmx_ops,
0455     .confops = &imx1_pinconf_ops,
0456     .owner = THIS_MODULE,
0457 };
0458
0459 static int imx1_pinctrl_parse_groups(struct device_node *np,
0460                     struct imx1_pin_group *grp,
0461                     struct imx1_pinctrl_soc_info *info,
0462                     u32 index)
0463 {
0464     int size;
0465     const __be32 *list;
0466     int i;
0467
0468     dev_dbg(info->dev, "group(%d): %pOFn\n", index, np);
0469
0470     /* Initialise group */
0471     grp->name = np->name;
0472
0473     /*
0474      * the binding format is fsl,pins = <PIN MUX_ID CONFIG>
0475      */
0476     list = of_get_property(np, "fsl,pins", &size);
0477     /* we do not check return since it's safe node passed down */
0478     if (!size || size % 12) {
0479         dev_notice(info->dev, "Not a valid fsl,pins property (%pOFn)\n",
0480                 np);
0481         return -EINVAL;
0482     }
0483
0484     grp->npins = size / 12;
0485     grp->pins = devm_kcalloc(info->dev,
0486             grp->npins, sizeof(struct imx1_pin), GFP_KERNEL);
0487     grp->pin_ids = devm_kcalloc(info->dev,
0488             grp->npins, sizeof(unsigned int), GFP_KERNEL);
0489
0490     if (!grp->pins || !grp->pin_ids)
0491         return -ENOMEM;
0492
0493     for (i = 0; i < grp->npins; i++) {
0494         grp->pins[i].pin_id = be32_to_cpu(*list++);
0495         grp->pins[i].mux_id = be32_to_cpu(*list++);
0496         grp->pins[i].config = be32_to_cpu(*list++);
0497
0498         grp->pin_ids[i] = grp->pins[i].pin_id;
0499     }
0500
0501     return 0;
0502 }
0503
0504 static int imx1_pinctrl_parse_functions(struct device_node *np,
0505                        struct imx1_pinctrl_soc_info *info,
0506                        u32 index)
0507 {
0508     struct device_node *child;
0509     struct imx1_pmx_func *func;
0510     struct imx1_pin_group *grp;
0511     int ret;
0512     static u32 grp_index;
0513     u32 i = 0;
0514
0515     dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np);
0516
0517     func = &info->functions[index];
0518
0519     /* Initialise function */
0520     func->name = np->name;
0521     func->num_groups = of_get_child_count(np);
0522     if (func->num_groups == 0)
0523         return -EINVAL;
0524
0525     func->groups = devm_kcalloc(info->dev,
0526             func->num_groups, sizeof(char *), GFP_KERNEL);
0527
0528     if (!func->groups)
0529         return -ENOMEM;
0530
0531     for_each_child_of_node(np, child) {
0532         func->groups[i] = child->name;
0533         grp = &info->groups[grp_index++];
0534         ret = imx1_pinctrl_parse_groups(child, grp, info, i++);
0535         if (ret == -ENOMEM) {
0536             of_node_put(child);
0537             return ret;
0538         }
0539     }
0540
0541     return 0;
0542 }
0543
0544 static int imx1_pinctrl_parse_dt(struct platform_device *pdev,
0545         struct imx1_pinctrl *pctl, struct imx1_pinctrl_soc_info *info)
0546 {
0547     struct device_node *np = pdev->dev.of_node;
0548     struct device_node *child;
0549     int ret;
0550     u32 nfuncs = 0;
0551     u32 ngroups = 0;
0552     u32 ifunc = 0;
0553
0554     if (!np)
0555         return -ENODEV;
0556
0557     for_each_child_of_node(np, child) {
0558         ++nfuncs;
0559         ngroups += of_get_child_count(child);
0560     }
0561
0562     if (!nfuncs) {
0563         dev_err(&pdev->dev, "No pin functions defined\n");
0564         return -EINVAL;
0565     }
0566
0567     info->nfunctions = nfuncs;
0568     info->functions = devm_kcalloc(&pdev->dev,
0569             nfuncs, sizeof(struct imx1_pmx_func), GFP_KERNEL);
0570
0571     info->ngroups = ngroups;
0572     info->groups = devm_kcalloc(&pdev->dev,
0573             ngroups, sizeof(struct imx1_pin_group), GFP_KERNEL);
0574
0575
0576     if (!info->functions || !info->groups)
0577         return -ENOMEM;
0578
0579     for_each_child_of_node(np, child) {
0580         ret = imx1_pinctrl_parse_functions(child, info, ifunc++);
0581         if (ret == -ENOMEM) {
0582             of_node_put(child);
0583             return -ENOMEM;
0584         }
0585     }
0586
0587     return 0;
0588 }
0589
0590 int imx1_pinctrl_core_probe(struct platform_device *pdev,
0591               struct imx1_pinctrl_soc_info *info)
0592 {
0593     struct imx1_pinctrl *ipctl;
0594     struct resource *res;
0595     struct pinctrl_desc *pctl_desc;
0596     int ret;
0597
0598     if (!info || !info->pins || !info->npins) {
0599         dev_err(&pdev->dev, "wrong pinctrl info\n");
0600         return -EINVAL;
0601     }
0602     info->dev = &pdev->dev;
0603
0604     /* Create state holders etc for this driver */
0605     ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
0606     if (!ipctl)
0607         return -ENOMEM;
0608
0609     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0610     if (!res)
0611         return -ENOENT;
0612
0613     ipctl->base = devm_ioremap(&pdev->dev, res->start,
0614             resource_size(res));
0615     if (!ipctl->base)
0616         return -ENOMEM;
0617
0618     pctl_desc = &imx1_pinctrl_desc;
0619     pctl_desc->name = dev_name(&pdev->dev);
0620     pctl_desc->pins = info->pins;
0621     pctl_desc->npins = info->npins;
0622
0623     ret = imx1_pinctrl_parse_dt(pdev, ipctl, info);
0624     if (ret) {
0625         dev_err(&pdev->dev, "fail to probe dt properties\n");
0626         return ret;
0627     }
0628
0629     ipctl->info = info;
0630     ipctl->dev = info->dev;
0631     platform_set_drvdata(pdev, ipctl);
0632     ipctl->pctl = devm_pinctrl_register(&pdev->dev, pctl_desc, ipctl);
0633     if (IS_ERR(ipctl->pctl)) {
0634         dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
0635         return PTR_ERR(ipctl->pctl);
0636     }
0637
0638     ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
0639     if (ret) {
0640         dev_err(&pdev->dev, "Failed to populate subdevices\n");
0641         return ret;
0642     }
0643
0644     dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
0645
0646     return 0;
0647 }