pinctrl/freescale/pinctrl-imx.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * IMX pinmux core definitions
0004  *
0005  * Copyright (C) 2012 Freescale Semiconductor, Inc.
0006  * Copyright (C) 2012 Linaro Ltd.
0007  *
0008  * Author: Dong Aisheng <dong.aisheng@linaro.org>
0009  */
0010
0011 #ifndef __DRIVERS_PINCTRL_IMX_H
0012 #define __DRIVERS_PINCTRL_IMX_H
0013
0014 #include <linux/pinctrl/pinconf-generic.h>
0015 #include <linux/pinctrl/pinmux.h>
0016
0017 struct platform_device;
0018
0019 extern struct pinmux_ops imx_pmx_ops;
0020 extern const struct dev_pm_ops imx_pinctrl_pm_ops;
0021
0022 /**
0023  * struct imx_pin_mmio - MMIO pin configurations
0024  * @mux_mode: the mux mode for this pin.
0025  * @input_reg: the select input register offset for this pin if any
0026  *  0 if no select input setting needed.
0027  * @input_val: the select input value for this pin.
0028  * @configs: the config for this pin.
0029  */
0030 struct imx_pin_mmio {
0031     unsigned int mux_mode;
0032     u16 input_reg;
0033     unsigned int input_val;
0034     unsigned long config;
0035 };
0036
0037 /**
0038  * struct imx_pin_scu - SCU pin configurations
0039  * @mux: the mux mode for this pin.
0040  * @configs: the config for this pin.
0041  */
0042 struct imx_pin_scu {
0043     unsigned int mux_mode;
0044     unsigned long config;
0045 };
0046
0047 /**
0048  * struct imx_pin - describes a single i.MX pin
0049  * @pin: the pin_id of this pin
0050  * @conf: config type of this pin, either mmio or scu
0051  */
0052 struct imx_pin {
0053     unsigned int pin;
0054     union {
0055         struct imx_pin_mmio mmio;
0056         struct imx_pin_scu scu;
0057     } conf;
0058 };
0059
0060 /**
0061  * struct imx_pin_reg - describe a pin reg map
0062  * @mux_reg: mux register offset
0063  * @conf_reg: config register offset
0064  */
0065 struct imx_pin_reg {
0066     s16 mux_reg;
0067     s16 conf_reg;
0068 };
0069
0070 /* decode a generic config into raw register value */
0071 struct imx_cfg_params_decode {
0072     enum pin_config_param param;
0073     u32 mask;
0074     u8 shift;
0075     bool invert;
0076 };
0077
0078 /**
0079  * @dev: a pointer back to containing device
0080  * @base: the offset to the controller in virtual memory
0081  */
0082 struct imx_pinctrl {
0083     struct device *dev;
0084     struct pinctrl_dev *pctl;
0085     void __iomem *base;
0086     void __iomem *input_sel_base;
0087     const struct imx_pinctrl_soc_info *info;
0088     struct imx_pin_reg *pin_regs;
0089     unsigned int group_index;
0090     struct mutex mutex;
0091 };
0092
0093 struct imx_pinctrl_soc_info {
0094     const struct pinctrl_pin_desc *pins;
0095     unsigned int npins;
0096     unsigned int flags;
0097     const char *gpr_compatible;
0098
0099     /* MUX_MODE shift and mask in case SHARE_MUX_CONF_REG */
0100     unsigned int mux_mask;
0101     u8 mux_shift;
0102
0103     /* generic pinconf */
0104     bool generic_pinconf;
0105     const struct pinconf_generic_params *custom_params;
0106     unsigned int num_custom_params;
0107     const struct imx_cfg_params_decode *decodes;
0108     unsigned int num_decodes;
0109     void (*fixup)(unsigned long *configs, unsigned int num_configs,
0110               u32 *raw_config);
0111
0112     int (*gpio_set_direction)(struct pinctrl_dev *pctldev,
0113                   struct pinctrl_gpio_range *range,
0114                   unsigned offset,
0115                   bool input);
0116     int (*imx_pinconf_get)(struct pinctrl_dev *pctldev, unsigned int pin_id,
0117                    unsigned long *config);
0118     int (*imx_pinconf_set)(struct pinctrl_dev *pctldev, unsigned int pin_id,
0119                    unsigned long *configs, unsigned int num_configs);
0120     void (*imx_pinctrl_parse_pin)(struct imx_pinctrl *ipctl,
0121                       unsigned int *pin_id, struct imx_pin *pin,
0122                       const __be32 **list_p);
0123 };
0124
0125 #define IMX_CFG_PARAMS_DECODE(p, m, o) \
0126     { .param = p, .mask = m, .shift = o, .invert = false, }
0127
0128 #define IMX_CFG_PARAMS_DECODE_INVERT(p, m, o) \
0129     { .param = p, .mask = m, .shift = o, .invert = true, }
0130
0131 #define SHARE_MUX_CONF_REG  BIT(0)
0132 #define ZERO_OFFSET_VALID   BIT(1)
0133 #define IMX_USE_SCU     BIT(2)
0134
0135 #define NO_MUX      0x0
0136 #define NO_PAD      0x0
0137
0138 #define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
0139
0140 #define PAD_CTL_MASK(len)   ((1 << len) - 1)
0141 #define IMX_MUX_MASK    0x7
0142 #define IOMUXC_CONFIG_SION  (0x1 << 4)
0143
0144 int imx_pinctrl_probe(struct platform_device *pdev,
0145             const struct imx_pinctrl_soc_info *info);
0146
0147 #define BM_PAD_CTL_GP_ENABLE        BIT(30)
0148 #define BM_PAD_CTL_IFMUX_ENABLE     BIT(31)
0149 #define BP_PAD_CTL_IFMUX        27
0150
0151 int imx_pinctrl_sc_ipc_init(struct platform_device *pdev);
0152 int imx_pinconf_get_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
0153             unsigned long *config);
0154 int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
0155             unsigned long *configs, unsigned num_configs);
0156 void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl,
0157                    unsigned int *pin_id, struct imx_pin *pin,
0158                    const __be32 **list_p);
0159 #endif /* __DRIVERS_PINCTRL_IMX_H */