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0001 // SPDX-License-Identifier: GPL-2.0+
0002 //
0003 // Core driver for the imx pin controller
0004 //
0005 // Copyright (C) 2012 Freescale Semiconductor, Inc.
0006 // Copyright (C) 2012 Linaro Ltd.
0007 //
0008 // Author: Dong Aisheng <dong.aisheng@linaro.org>
0009 
0010 #include <linux/err.h>
0011 #include <linux/init.h>
0012 #include <linux/io.h>
0013 #include <linux/mfd/syscon.h>
0014 #include <linux/module.h>
0015 #include <linux/of.h>
0016 #include <linux/of_device.h>
0017 #include <linux/of_address.h>
0018 #include <linux/pinctrl/machine.h>
0019 #include <linux/pinctrl/pinconf.h>
0020 #include <linux/pinctrl/pinctrl.h>
0021 #include <linux/pinctrl/pinmux.h>
0022 #include <linux/slab.h>
0023 #include <linux/regmap.h>
0024 
0025 #include "../core.h"
0026 #include "../pinconf.h"
0027 #include "../pinmux.h"
0028 #include "pinctrl-imx.h"
0029 
0030 /* The bits in CONFIG cell defined in binding doc*/
0031 #define IMX_NO_PAD_CTL  0x80000000  /* no pin config need */
0032 #define IMX_PAD_SION 0x40000000     /* set SION */
0033 
0034 static inline const struct group_desc *imx_pinctrl_find_group_by_name(
0035                 struct pinctrl_dev *pctldev,
0036                 const char *name)
0037 {
0038     const struct group_desc *grp = NULL;
0039     int i;
0040 
0041     for (i = 0; i < pctldev->num_groups; i++) {
0042         grp = pinctrl_generic_get_group(pctldev, i);
0043         if (grp && !strcmp(grp->name, name))
0044             break;
0045     }
0046 
0047     return grp;
0048 }
0049 
0050 static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
0051            unsigned offset)
0052 {
0053     seq_printf(s, "%s", dev_name(pctldev->dev));
0054 }
0055 
0056 static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
0057             struct device_node *np,
0058             struct pinctrl_map **map, unsigned *num_maps)
0059 {
0060     struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
0061     const struct imx_pinctrl_soc_info *info = ipctl->info;
0062     const struct group_desc *grp;
0063     struct pinctrl_map *new_map;
0064     struct device_node *parent;
0065     struct imx_pin *pin;
0066     int map_num = 1;
0067     int i, j;
0068 
0069     /*
0070      * first find the group of this node and check if we need create
0071      * config maps for pins
0072      */
0073     grp = imx_pinctrl_find_group_by_name(pctldev, np->name);
0074     if (!grp) {
0075         dev_err(ipctl->dev, "unable to find group for node %pOFn\n", np);
0076         return -EINVAL;
0077     }
0078 
0079     if (info->flags & IMX_USE_SCU) {
0080         map_num += grp->num_pins;
0081     } else {
0082         for (i = 0; i < grp->num_pins; i++) {
0083             pin = &((struct imx_pin *)(grp->data))[i];
0084             if (!(pin->conf.mmio.config & IMX_NO_PAD_CTL))
0085                 map_num++;
0086         }
0087     }
0088 
0089     new_map = kmalloc_array(map_num, sizeof(struct pinctrl_map),
0090                 GFP_KERNEL);
0091     if (!new_map)
0092         return -ENOMEM;
0093 
0094     *map = new_map;
0095     *num_maps = map_num;
0096 
0097     /* create mux map */
0098     parent = of_get_parent(np);
0099     if (!parent) {
0100         kfree(new_map);
0101         return -EINVAL;
0102     }
0103     new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
0104     new_map[0].data.mux.function = parent->name;
0105     new_map[0].data.mux.group = np->name;
0106     of_node_put(parent);
0107 
0108     /* create config map */
0109     new_map++;
0110     for (i = j = 0; i < grp->num_pins; i++) {
0111         pin = &((struct imx_pin *)(grp->data))[i];
0112 
0113         /*
0114          * We only create config maps for SCU pads or MMIO pads that
0115          * are not using the default config(a.k.a IMX_NO_PAD_CTL)
0116          */
0117         if (!(info->flags & IMX_USE_SCU) &&
0118             (pin->conf.mmio.config & IMX_NO_PAD_CTL))
0119             continue;
0120 
0121         new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
0122         new_map[j].data.configs.group_or_pin =
0123                     pin_get_name(pctldev, pin->pin);
0124 
0125         if (info->flags & IMX_USE_SCU) {
0126             /*
0127              * For SCU case, we set mux and conf together
0128              * in one IPC call
0129              */
0130             new_map[j].data.configs.configs =
0131                     (unsigned long *)&pin->conf.scu;
0132             new_map[j].data.configs.num_configs = 2;
0133         } else {
0134             new_map[j].data.configs.configs =
0135                     &pin->conf.mmio.config;
0136             new_map[j].data.configs.num_configs = 1;
0137         }
0138 
0139         j++;
0140     }
0141 
0142     dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
0143         (*map)->data.mux.function, (*map)->data.mux.group, map_num);
0144 
0145     return 0;
0146 }
0147 
0148 static void imx_dt_free_map(struct pinctrl_dev *pctldev,
0149                 struct pinctrl_map *map, unsigned num_maps)
0150 {
0151     kfree(map);
0152 }
0153 
0154 static const struct pinctrl_ops imx_pctrl_ops = {
0155     .get_groups_count = pinctrl_generic_get_group_count,
0156     .get_group_name = pinctrl_generic_get_group_name,
0157     .get_group_pins = pinctrl_generic_get_group_pins,
0158     .pin_dbg_show = imx_pin_dbg_show,
0159     .dt_node_to_map = imx_dt_node_to_map,
0160     .dt_free_map = imx_dt_free_map,
0161 };
0162 
0163 static int imx_pmx_set_one_pin_mmio(struct imx_pinctrl *ipctl,
0164                     struct imx_pin *pin)
0165 {
0166     const struct imx_pinctrl_soc_info *info = ipctl->info;
0167     struct imx_pin_mmio *pin_mmio = &pin->conf.mmio;
0168     const struct imx_pin_reg *pin_reg;
0169     unsigned int pin_id;
0170 
0171     pin_id = pin->pin;
0172     pin_reg = &ipctl->pin_regs[pin_id];
0173 
0174     if (pin_reg->mux_reg == -1) {
0175         dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n",
0176             info->pins[pin_id].name);
0177         return 0;
0178     }
0179 
0180     if (info->flags & SHARE_MUX_CONF_REG) {
0181         u32 reg;
0182 
0183         reg = readl(ipctl->base + pin_reg->mux_reg);
0184         reg &= ~info->mux_mask;
0185         reg |= (pin_mmio->mux_mode << info->mux_shift);
0186         writel(reg, ipctl->base + pin_reg->mux_reg);
0187         dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
0188             pin_reg->mux_reg, reg);
0189     } else {
0190         writel(pin_mmio->mux_mode, ipctl->base + pin_reg->mux_reg);
0191         dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
0192             pin_reg->mux_reg, pin_mmio->mux_mode);
0193     }
0194 
0195     /*
0196      * If the select input value begins with 0xff, it's a quirky
0197      * select input and the value should be interpreted as below.
0198      *     31     23      15      7        0
0199      *     | 0xff | shift | width | select |
0200      * It's used to work around the problem that the select
0201      * input for some pin is not implemented in the select
0202      * input register but in some general purpose register.
0203      * We encode the select input value, width and shift of
0204      * the bit field into input_val cell of pin function ID
0205      * in device tree, and then decode them here for setting
0206      * up the select input bits in general purpose register.
0207      */
0208     if (pin_mmio->input_val >> 24 == 0xff) {
0209         u32 val = pin_mmio->input_val;
0210         u8 select = val & 0xff;
0211         u8 width = (val >> 8) & 0xff;
0212         u8 shift = (val >> 16) & 0xff;
0213         u32 mask = ((1 << width) - 1) << shift;
0214         /*
0215          * The input_reg[i] here is actually some IOMUXC general
0216          * purpose register, not regular select input register.
0217          */
0218         val = readl(ipctl->base + pin_mmio->input_reg);
0219         val &= ~mask;
0220         val |= select << shift;
0221         writel(val, ipctl->base + pin_mmio->input_reg);
0222     } else if (pin_mmio->input_reg) {
0223         /*
0224          * Regular select input register can never be at offset
0225          * 0, and we only print register value for regular case.
0226          */
0227         if (ipctl->input_sel_base)
0228             writel(pin_mmio->input_val, ipctl->input_sel_base +
0229                     pin_mmio->input_reg);
0230         else
0231             writel(pin_mmio->input_val, ipctl->base +
0232                     pin_mmio->input_reg);
0233         dev_dbg(ipctl->dev,
0234             "==>select_input: offset 0x%x val 0x%x\n",
0235             pin_mmio->input_reg, pin_mmio->input_val);
0236     }
0237 
0238     return 0;
0239 }
0240 
0241 static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
0242                unsigned group)
0243 {
0244     struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
0245     const struct imx_pinctrl_soc_info *info = ipctl->info;
0246     struct function_desc *func;
0247     struct group_desc *grp;
0248     struct imx_pin *pin;
0249     unsigned int npins;
0250     int i, err;
0251 
0252     /*
0253      * Configure the mux mode for each pin in the group for a specific
0254      * function.
0255      */
0256     grp = pinctrl_generic_get_group(pctldev, group);
0257     if (!grp)
0258         return -EINVAL;
0259 
0260     func = pinmux_generic_get_function(pctldev, selector);
0261     if (!func)
0262         return -EINVAL;
0263 
0264     npins = grp->num_pins;
0265 
0266     dev_dbg(ipctl->dev, "enable function %s group %s\n",
0267         func->name, grp->name);
0268 
0269     for (i = 0; i < npins; i++) {
0270         /*
0271          * For IMX_USE_SCU case, we postpone the mux setting
0272          * until config is set as we can set them together
0273          * in one IPC call
0274          */
0275         pin = &((struct imx_pin *)(grp->data))[i];
0276         if (!(info->flags & IMX_USE_SCU)) {
0277             err = imx_pmx_set_one_pin_mmio(ipctl, pin);
0278             if (err)
0279                 return err;
0280         }
0281     }
0282 
0283     return 0;
0284 }
0285 
0286 struct pinmux_ops imx_pmx_ops = {
0287     .get_functions_count = pinmux_generic_get_function_count,
0288     .get_function_name = pinmux_generic_get_function_name,
0289     .get_function_groups = pinmux_generic_get_function_groups,
0290     .set_mux = imx_pmx_set,
0291 };
0292 
0293 /* decode generic config into raw register values */
0294 static u32 imx_pinconf_decode_generic_config(struct imx_pinctrl *ipctl,
0295                           unsigned long *configs,
0296                           unsigned int num_configs)
0297 {
0298     const struct imx_pinctrl_soc_info *info = ipctl->info;
0299     const struct imx_cfg_params_decode *decode;
0300     enum pin_config_param param;
0301     u32 raw_config = 0;
0302     u32 param_val;
0303     int i, j;
0304 
0305     WARN_ON(num_configs > info->num_decodes);
0306 
0307     for (i = 0; i < num_configs; i++) {
0308         param = pinconf_to_config_param(configs[i]);
0309         param_val = pinconf_to_config_argument(configs[i]);
0310         decode = info->decodes;
0311         for (j = 0; j < info->num_decodes; j++) {
0312             if (param == decode->param) {
0313                 if (decode->invert)
0314                     param_val = !param_val;
0315                 raw_config |= (param_val << decode->shift)
0316                           & decode->mask;
0317                 break;
0318             }
0319             decode++;
0320         }
0321     }
0322 
0323     if (info->fixup)
0324         info->fixup(configs, num_configs, &raw_config);
0325 
0326     return raw_config;
0327 }
0328 
0329 static u32 imx_pinconf_parse_generic_config(struct device_node *np,
0330                         struct imx_pinctrl *ipctl)
0331 {
0332     const struct imx_pinctrl_soc_info *info = ipctl->info;
0333     struct pinctrl_dev *pctl = ipctl->pctl;
0334     unsigned int num_configs;
0335     unsigned long *configs;
0336     int ret;
0337 
0338     if (!info->generic_pinconf)
0339         return 0;
0340 
0341     ret = pinconf_generic_parse_dt_config(np, pctl, &configs,
0342                           &num_configs);
0343     if (ret)
0344         return 0;
0345 
0346     return imx_pinconf_decode_generic_config(ipctl, configs, num_configs);
0347 }
0348 
0349 static int imx_pinconf_get_mmio(struct pinctrl_dev *pctldev, unsigned pin_id,
0350                 unsigned long *config)
0351 {
0352     struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
0353     const struct imx_pinctrl_soc_info *info = ipctl->info;
0354     const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id];
0355 
0356     if (pin_reg->conf_reg == -1) {
0357         dev_err(ipctl->dev, "Pin(%s) does not support config function\n",
0358             info->pins[pin_id].name);
0359         return -EINVAL;
0360     }
0361 
0362     *config = readl(ipctl->base + pin_reg->conf_reg);
0363 
0364     if (info->flags & SHARE_MUX_CONF_REG)
0365         *config &= ~info->mux_mask;
0366 
0367     return 0;
0368 }
0369 
0370 static int imx_pinconf_get(struct pinctrl_dev *pctldev,
0371                unsigned pin_id, unsigned long *config)
0372 {
0373     struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
0374     const struct imx_pinctrl_soc_info *info = ipctl->info;
0375 
0376     if (info->flags & IMX_USE_SCU)
0377         return info->imx_pinconf_get(pctldev, pin_id, config);
0378     else
0379         return imx_pinconf_get_mmio(pctldev, pin_id, config);
0380 }
0381 
0382 static int imx_pinconf_set_mmio(struct pinctrl_dev *pctldev,
0383                 unsigned pin_id, unsigned long *configs,
0384                 unsigned num_configs)
0385 {
0386     struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
0387     const struct imx_pinctrl_soc_info *info = ipctl->info;
0388     const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id];
0389     int i;
0390 
0391     if (pin_reg->conf_reg == -1) {
0392         dev_err(ipctl->dev, "Pin(%s) does not support config function\n",
0393             info->pins[pin_id].name);
0394         return -EINVAL;
0395     }
0396 
0397     dev_dbg(ipctl->dev, "pinconf set pin %s\n",
0398         info->pins[pin_id].name);
0399 
0400     for (i = 0; i < num_configs; i++) {
0401         if (info->flags & SHARE_MUX_CONF_REG) {
0402             u32 reg;
0403             reg = readl(ipctl->base + pin_reg->conf_reg);
0404             reg &= info->mux_mask;
0405             reg |= configs[i];
0406             writel(reg, ipctl->base + pin_reg->conf_reg);
0407             dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
0408                 pin_reg->conf_reg, reg);
0409         } else {
0410             writel(configs[i], ipctl->base + pin_reg->conf_reg);
0411             dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
0412                 pin_reg->conf_reg, configs[i]);
0413         }
0414     } /* for each config */
0415 
0416     return 0;
0417 }
0418 
0419 static int imx_pinconf_set(struct pinctrl_dev *pctldev,
0420                unsigned pin_id, unsigned long *configs,
0421                unsigned num_configs)
0422 {
0423     struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
0424     const struct imx_pinctrl_soc_info *info = ipctl->info;
0425 
0426     if (info->flags & IMX_USE_SCU)
0427         return info->imx_pinconf_set(pctldev, pin_id,
0428                        configs, num_configs);
0429     else
0430         return imx_pinconf_set_mmio(pctldev, pin_id,
0431                         configs, num_configs);
0432 }
0433 
0434 static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
0435                    struct seq_file *s, unsigned pin_id)
0436 {
0437     struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
0438     const struct imx_pinctrl_soc_info *info = ipctl->info;
0439     const struct imx_pin_reg *pin_reg;
0440     unsigned long config;
0441     int ret;
0442 
0443     if (info->flags & IMX_USE_SCU) {
0444         ret = info->imx_pinconf_get(pctldev, pin_id, &config);
0445         if (ret) {
0446             dev_err(ipctl->dev, "failed to get %s pinconf\n",
0447                 pin_get_name(pctldev, pin_id));
0448             seq_puts(s, "N/A");
0449             return;
0450         }
0451     } else {
0452         pin_reg = &ipctl->pin_regs[pin_id];
0453         if (pin_reg->conf_reg == -1) {
0454             seq_puts(s, "N/A");
0455             return;
0456         }
0457 
0458         config = readl(ipctl->base + pin_reg->conf_reg);
0459     }
0460 
0461     seq_printf(s, "0x%lx", config);
0462 }
0463 
0464 static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
0465                      struct seq_file *s, unsigned group)
0466 {
0467     struct group_desc *grp;
0468     unsigned long config;
0469     const char *name;
0470     int i, ret;
0471 
0472     if (group >= pctldev->num_groups)
0473         return;
0474 
0475     seq_puts(s, "\n");
0476     grp = pinctrl_generic_get_group(pctldev, group);
0477     if (!grp)
0478         return;
0479 
0480     for (i = 0; i < grp->num_pins; i++) {
0481         struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
0482 
0483         name = pin_get_name(pctldev, pin->pin);
0484         ret = imx_pinconf_get(pctldev, pin->pin, &config);
0485         if (ret)
0486             return;
0487         seq_printf(s, "  %s: 0x%lx\n", name, config);
0488     }
0489 }
0490 
0491 static const struct pinconf_ops imx_pinconf_ops = {
0492     .pin_config_get = imx_pinconf_get,
0493     .pin_config_set = imx_pinconf_set,
0494     .pin_config_dbg_show = imx_pinconf_dbg_show,
0495     .pin_config_group_dbg_show = imx_pinconf_group_dbg_show,
0496 };
0497 
0498 /*
0499  * Each pin represented in fsl,pins consists of a number of u32 PIN_FUNC_ID
0500  * and 1 u32 CONFIG, the total size is PIN_FUNC_ID + CONFIG for each pin.
0501  * For generic_pinconf case, there's no extra u32 CONFIG.
0502  *
0503  * PIN_FUNC_ID format:
0504  * Default:
0505  *     <mux_reg conf_reg input_reg mux_mode input_val>
0506  * SHARE_MUX_CONF_REG:
0507  *     <mux_conf_reg input_reg mux_mode input_val>
0508  * IMX_USE_SCU:
0509  *  <pin_id mux_mode>
0510  */
0511 #define FSL_PIN_SIZE 24
0512 #define FSL_PIN_SHARE_SIZE 20
0513 #define FSL_SCU_PIN_SIZE 12
0514 
0515 static void imx_pinctrl_parse_pin_mmio(struct imx_pinctrl *ipctl,
0516                        unsigned int *pin_id, struct imx_pin *pin,
0517                        const __be32 **list_p,
0518                        struct device_node *np)
0519 {
0520     const struct imx_pinctrl_soc_info *info = ipctl->info;
0521     struct imx_pin_mmio *pin_mmio = &pin->conf.mmio;
0522     struct imx_pin_reg *pin_reg;
0523     const __be32 *list = *list_p;
0524     u32 mux_reg, conf_reg;
0525     u32 config;
0526 
0527     mux_reg = be32_to_cpu(*list++);
0528 
0529     if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
0530         mux_reg = -1;
0531 
0532     if (info->flags & SHARE_MUX_CONF_REG) {
0533         conf_reg = mux_reg;
0534     } else {
0535         conf_reg = be32_to_cpu(*list++);
0536         if (!conf_reg)
0537             conf_reg = -1;
0538     }
0539 
0540     *pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4;
0541     pin_reg = &ipctl->pin_regs[*pin_id];
0542     pin->pin = *pin_id;
0543     pin_reg->mux_reg = mux_reg;
0544     pin_reg->conf_reg = conf_reg;
0545     pin_mmio->input_reg = be32_to_cpu(*list++);
0546     pin_mmio->mux_mode = be32_to_cpu(*list++);
0547     pin_mmio->input_val = be32_to_cpu(*list++);
0548 
0549     if (info->generic_pinconf) {
0550         /* generic pin config decoded */
0551         pin_mmio->config = imx_pinconf_parse_generic_config(np, ipctl);
0552     } else {
0553         /* legacy pin config read from devicetree */
0554         config = be32_to_cpu(*list++);
0555 
0556         /* SION bit is in mux register */
0557         if (config & IMX_PAD_SION)
0558             pin_mmio->mux_mode |= IOMUXC_CONFIG_SION;
0559         pin_mmio->config = config & ~IMX_PAD_SION;
0560     }
0561 
0562     *list_p = list;
0563 
0564     dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[*pin_id].name,
0565                  pin_mmio->mux_mode, pin_mmio->config);
0566 }
0567 
0568 static int imx_pinctrl_parse_groups(struct device_node *np,
0569                     struct group_desc *grp,
0570                     struct imx_pinctrl *ipctl,
0571                     u32 index)
0572 {
0573     const struct imx_pinctrl_soc_info *info = ipctl->info;
0574     struct imx_pin *pin;
0575     int size, pin_size;
0576     const __be32 *list;
0577     int i;
0578 
0579     dev_dbg(ipctl->dev, "group(%d): %pOFn\n", index, np);
0580 
0581     if (info->flags & IMX_USE_SCU)
0582         pin_size = FSL_SCU_PIN_SIZE;
0583     else if (info->flags & SHARE_MUX_CONF_REG)
0584         pin_size = FSL_PIN_SHARE_SIZE;
0585     else
0586         pin_size = FSL_PIN_SIZE;
0587 
0588     if (info->generic_pinconf)
0589         pin_size -= 4;
0590 
0591     /* Initialise group */
0592     grp->name = np->name;
0593 
0594     /*
0595      * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
0596      * do sanity check and calculate pins number
0597      *
0598      * First try legacy 'fsl,pins' property, then fall back to the
0599      * generic 'pinmux'.
0600      *
0601      * Note: for generic 'pinmux' case, there's no CONFIG part in
0602      * the binding format.
0603      */
0604     list = of_get_property(np, "fsl,pins", &size);
0605     if (!list) {
0606         list = of_get_property(np, "pinmux", &size);
0607         if (!list) {
0608             dev_err(ipctl->dev,
0609                 "no fsl,pins and pins property in node %pOF\n", np);
0610             return -EINVAL;
0611         }
0612     }
0613 
0614     /* we do not check return since it's safe node passed down */
0615     if (!size || size % pin_size) {
0616         dev_err(ipctl->dev, "Invalid fsl,pins or pins property in node %pOF\n", np);
0617         return -EINVAL;
0618     }
0619 
0620     grp->num_pins = size / pin_size;
0621     grp->data = devm_kcalloc(ipctl->dev,
0622                  grp->num_pins, sizeof(struct imx_pin),
0623                  GFP_KERNEL);
0624     grp->pins = devm_kcalloc(ipctl->dev,
0625                  grp->num_pins, sizeof(unsigned int),
0626                  GFP_KERNEL);
0627     if (!grp->pins || !grp->data)
0628         return -ENOMEM;
0629 
0630     for (i = 0; i < grp->num_pins; i++) {
0631         pin = &((struct imx_pin *)(grp->data))[i];
0632         if (info->flags & IMX_USE_SCU)
0633             info->imx_pinctrl_parse_pin(ipctl, &grp->pins[i],
0634                           pin, &list);
0635         else
0636             imx_pinctrl_parse_pin_mmio(ipctl, &grp->pins[i],
0637                            pin, &list, np);
0638     }
0639 
0640     return 0;
0641 }
0642 
0643 static int imx_pinctrl_parse_functions(struct device_node *np,
0644                        struct imx_pinctrl *ipctl,
0645                        u32 index)
0646 {
0647     struct pinctrl_dev *pctl = ipctl->pctl;
0648     struct device_node *child;
0649     struct function_desc *func;
0650     struct group_desc *grp;
0651     const char **group_names;
0652     u32 i;
0653 
0654     dev_dbg(pctl->dev, "parse function(%d): %pOFn\n", index, np);
0655 
0656     func = pinmux_generic_get_function(pctl, index);
0657     if (!func)
0658         return -EINVAL;
0659 
0660     /* Initialise function */
0661     func->name = np->name;
0662     func->num_group_names = of_get_child_count(np);
0663     if (func->num_group_names == 0) {
0664         dev_info(ipctl->dev, "no groups defined in %pOF\n", np);
0665         return -EINVAL;
0666     }
0667 
0668     group_names = devm_kcalloc(ipctl->dev, func->num_group_names,
0669                    sizeof(char *), GFP_KERNEL);
0670     if (!group_names)
0671         return -ENOMEM;
0672     i = 0;
0673     for_each_child_of_node(np, child)
0674         group_names[i++] = child->name;
0675     func->group_names = group_names;
0676 
0677     i = 0;
0678     for_each_child_of_node(np, child) {
0679         grp = devm_kzalloc(ipctl->dev, sizeof(struct group_desc),
0680                    GFP_KERNEL);
0681         if (!grp) {
0682             of_node_put(child);
0683             return -ENOMEM;
0684         }
0685 
0686         mutex_lock(&ipctl->mutex);
0687         radix_tree_insert(&pctl->pin_group_tree,
0688                   ipctl->group_index++, grp);
0689         mutex_unlock(&ipctl->mutex);
0690 
0691         imx_pinctrl_parse_groups(child, grp, ipctl, i++);
0692     }
0693 
0694     return 0;
0695 }
0696 
0697 /*
0698  * Check if the DT contains pins in the direct child nodes. This indicates the
0699  * newer DT format to store pins. This function returns true if the first found
0700  * fsl,pins property is in a child of np. Otherwise false is returned.
0701  */
0702 static bool imx_pinctrl_dt_is_flat_functions(struct device_node *np)
0703 {
0704     struct device_node *function_np;
0705     struct device_node *pinctrl_np;
0706 
0707     for_each_child_of_node(np, function_np) {
0708         if (of_property_read_bool(function_np, "fsl,pins")) {
0709             of_node_put(function_np);
0710             return true;
0711         }
0712 
0713         for_each_child_of_node(function_np, pinctrl_np) {
0714             if (of_property_read_bool(pinctrl_np, "fsl,pins")) {
0715                 of_node_put(pinctrl_np);
0716                 of_node_put(function_np);
0717                 return false;
0718             }
0719         }
0720     }
0721 
0722     return true;
0723 }
0724 
0725 static int imx_pinctrl_probe_dt(struct platform_device *pdev,
0726                 struct imx_pinctrl *ipctl)
0727 {
0728     struct device_node *np = pdev->dev.of_node;
0729     struct device_node *child;
0730     struct pinctrl_dev *pctl = ipctl->pctl;
0731     u32 nfuncs = 0;
0732     u32 i = 0;
0733     bool flat_funcs;
0734 
0735     if (!np)
0736         return -ENODEV;
0737 
0738     flat_funcs = imx_pinctrl_dt_is_flat_functions(np);
0739     if (flat_funcs) {
0740         nfuncs = 1;
0741     } else {
0742         nfuncs = of_get_child_count(np);
0743         if (nfuncs == 0) {
0744             dev_err(&pdev->dev, "no functions defined\n");
0745             return -EINVAL;
0746         }
0747     }
0748 
0749     for (i = 0; i < nfuncs; i++) {
0750         struct function_desc *function;
0751 
0752         function = devm_kzalloc(&pdev->dev, sizeof(*function),
0753                     GFP_KERNEL);
0754         if (!function)
0755             return -ENOMEM;
0756 
0757         mutex_lock(&ipctl->mutex);
0758         radix_tree_insert(&pctl->pin_function_tree, i, function);
0759         mutex_unlock(&ipctl->mutex);
0760     }
0761     pctl->num_functions = nfuncs;
0762 
0763     ipctl->group_index = 0;
0764     if (flat_funcs) {
0765         pctl->num_groups = of_get_child_count(np);
0766     } else {
0767         pctl->num_groups = 0;
0768         for_each_child_of_node(np, child)
0769             pctl->num_groups += of_get_child_count(child);
0770     }
0771 
0772     if (flat_funcs) {
0773         imx_pinctrl_parse_functions(np, ipctl, 0);
0774     } else {
0775         i = 0;
0776         for_each_child_of_node(np, child)
0777             imx_pinctrl_parse_functions(child, ipctl, i++);
0778     }
0779 
0780     return 0;
0781 }
0782 
0783 int imx_pinctrl_probe(struct platform_device *pdev,
0784               const struct imx_pinctrl_soc_info *info)
0785 {
0786     struct regmap_config config = { .name = "gpr" };
0787     struct device_node *dev_np = pdev->dev.of_node;
0788     struct pinctrl_desc *imx_pinctrl_desc;
0789     struct device_node *np;
0790     struct imx_pinctrl *ipctl;
0791     struct regmap *gpr;
0792     int ret, i;
0793 
0794     if (!info || !info->pins || !info->npins) {
0795         dev_err(&pdev->dev, "wrong pinctrl info\n");
0796         return -EINVAL;
0797     }
0798 
0799     if (info->gpr_compatible) {
0800         gpr = syscon_regmap_lookup_by_compatible(info->gpr_compatible);
0801         if (!IS_ERR(gpr))
0802             regmap_attach_dev(&pdev->dev, gpr, &config);
0803     }
0804 
0805     /* Create state holders etc for this driver */
0806     ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
0807     if (!ipctl)
0808         return -ENOMEM;
0809 
0810     if (!(info->flags & IMX_USE_SCU)) {
0811         ipctl->pin_regs = devm_kmalloc_array(&pdev->dev, info->npins,
0812                              sizeof(*ipctl->pin_regs),
0813                              GFP_KERNEL);
0814         if (!ipctl->pin_regs)
0815             return -ENOMEM;
0816 
0817         for (i = 0; i < info->npins; i++) {
0818             ipctl->pin_regs[i].mux_reg = -1;
0819             ipctl->pin_regs[i].conf_reg = -1;
0820         }
0821 
0822         ipctl->base = devm_platform_ioremap_resource(pdev, 0);
0823         if (IS_ERR(ipctl->base))
0824             return PTR_ERR(ipctl->base);
0825 
0826         if (of_property_read_bool(dev_np, "fsl,input-sel")) {
0827             np = of_parse_phandle(dev_np, "fsl,input-sel", 0);
0828             if (!np) {
0829                 dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n");
0830                 return -EINVAL;
0831             }
0832 
0833             ipctl->input_sel_base = of_iomap(np, 0);
0834             of_node_put(np);
0835             if (!ipctl->input_sel_base) {
0836                 dev_err(&pdev->dev,
0837                     "iomuxc input select base address not found\n");
0838                 return -ENOMEM;
0839             }
0840         }
0841     }
0842 
0843     imx_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*imx_pinctrl_desc),
0844                     GFP_KERNEL);
0845     if (!imx_pinctrl_desc)
0846         return -ENOMEM;
0847 
0848     imx_pinctrl_desc->name = dev_name(&pdev->dev);
0849     imx_pinctrl_desc->pins = info->pins;
0850     imx_pinctrl_desc->npins = info->npins;
0851     imx_pinctrl_desc->pctlops = &imx_pctrl_ops;
0852     imx_pinctrl_desc->pmxops = &imx_pmx_ops;
0853     imx_pinctrl_desc->confops = &imx_pinconf_ops;
0854     imx_pinctrl_desc->owner = THIS_MODULE;
0855 
0856     /* for generic pinconf */
0857     imx_pinctrl_desc->custom_params = info->custom_params;
0858     imx_pinctrl_desc->num_custom_params = info->num_custom_params;
0859 
0860     /* platform specific callback */
0861     imx_pmx_ops.gpio_set_direction = info->gpio_set_direction;
0862 
0863     mutex_init(&ipctl->mutex);
0864 
0865     ipctl->info = info;
0866     ipctl->dev = &pdev->dev;
0867     platform_set_drvdata(pdev, ipctl);
0868     ret = devm_pinctrl_register_and_init(&pdev->dev,
0869                          imx_pinctrl_desc, ipctl,
0870                          &ipctl->pctl);
0871     if (ret) {
0872         dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
0873         return ret;
0874     }
0875 
0876     ret = imx_pinctrl_probe_dt(pdev, ipctl);
0877     if (ret) {
0878         dev_err(&pdev->dev, "fail to probe dt properties\n");
0879         return ret;
0880     }
0881 
0882     dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
0883 
0884     return pinctrl_enable(ipctl->pctl);
0885 }
0886 EXPORT_SYMBOL_GPL(imx_pinctrl_probe);
0887 
0888 static int __maybe_unused imx_pinctrl_suspend(struct device *dev)
0889 {
0890     struct imx_pinctrl *ipctl = dev_get_drvdata(dev);
0891 
0892     return pinctrl_force_sleep(ipctl->pctl);
0893 }
0894 
0895 static int __maybe_unused imx_pinctrl_resume(struct device *dev)
0896 {
0897     struct imx_pinctrl *ipctl = dev_get_drvdata(dev);
0898 
0899     return pinctrl_force_default(ipctl->pctl);
0900 }
0901 
0902 const struct dev_pm_ops imx_pinctrl_pm_ops = {
0903     SET_LATE_SYSTEM_SLEEP_PM_OPS(imx_pinctrl_suspend,
0904                     imx_pinctrl_resume)
0905 };
0906 EXPORT_SYMBOL_GPL(imx_pinctrl_pm_ops);
0907 
0908 MODULE_AUTHOR("Dong Aisheng <aisheng.dong@nxp.com>");
0909 MODULE_DESCRIPTION("NXP i.MX common pinctrl driver");
0910 MODULE_LICENSE("GPL v2");
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