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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Lochnagar pin and GPIO control
0004  *
0005  * Copyright (c) 2017-2018 Cirrus Logic, Inc. and
0006  *                         Cirrus Logic International Semiconductor Ltd.
0007  *
0008  * Author: Charles Keepax <ckeepax@opensource.cirrus.com>
0009  */
0010 
0011 #include <linux/err.h>
0012 #include <linux/errno.h>
0013 #include <linux/gpio/driver.h>
0014 #include <linux/module.h>
0015 #include <linux/of.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/regmap.h>
0018 #include <linux/pinctrl/pinctrl.h>
0019 #include <linux/pinctrl/pinmux.h>
0020 #include <linux/pinctrl/pinconf.h>
0021 #include <linux/pinctrl/pinconf-generic.h>
0022 
0023 #include <linux/mfd/lochnagar.h>
0024 #include <linux/mfd/lochnagar1_regs.h>
0025 #include <linux/mfd/lochnagar2_regs.h>
0026 
0027 #include <dt-bindings/pinctrl/lochnagar.h>
0028 
0029 #include "../pinctrl-utils.h"
0030 
0031 #define LN2_NUM_GPIO_CHANNELS   16
0032 
0033 #define LN_CDC_AIF1_STR     "codec-aif1"
0034 #define LN_CDC_AIF2_STR     "codec-aif2"
0035 #define LN_CDC_AIF3_STR     "codec-aif3"
0036 #define LN_DSP_AIF1_STR     "dsp-aif1"
0037 #define LN_DSP_AIF2_STR     "dsp-aif2"
0038 #define LN_PSIA1_STR        "psia1"
0039 #define LN_PSIA2_STR        "psia2"
0040 #define LN_GF_AIF1_STR      "gf-aif1"
0041 #define LN_GF_AIF2_STR      "gf-aif2"
0042 #define LN_GF_AIF3_STR      "gf-aif3"
0043 #define LN_GF_AIF4_STR      "gf-aif4"
0044 #define LN_SPDIF_AIF_STR    "spdif-aif"
0045 #define LN_USB_AIF1_STR     "usb-aif1"
0046 #define LN_USB_AIF2_STR     "usb-aif2"
0047 #define LN_ADAT_AIF_STR     "adat-aif"
0048 #define LN_SOUNDCARD_AIF_STR    "soundcard-aif"
0049 
0050 #define LN_PIN_GPIO(REV, ID, NAME, REG, SHIFT, INVERT) \
0051 static const struct lochnagar_pin lochnagar##REV##_##ID##_pin = { \
0052     .name = NAME, .type = LN_PTYPE_GPIO, .reg = LOCHNAGAR##REV##_##REG, \
0053     .shift = LOCHNAGAR##REV##_##SHIFT##_SHIFT, .invert = INVERT, \
0054 }
0055 
0056 #define LN_PIN_SAIF(REV, ID, NAME) \
0057 static const struct lochnagar_pin lochnagar##REV##_##ID##_pin = \
0058     { .name = NAME, .type = LN_PTYPE_AIF, }
0059 
0060 #define LN_PIN_AIF(REV, ID) \
0061     LN_PIN_SAIF(REV, ID##_BCLK,  LN_##ID##_STR"-bclk"); \
0062     LN_PIN_SAIF(REV, ID##_LRCLK, LN_##ID##_STR"-lrclk"); \
0063     LN_PIN_SAIF(REV, ID##_RXDAT, LN_##ID##_STR"-rxdat"); \
0064     LN_PIN_SAIF(REV, ID##_TXDAT, LN_##ID##_STR"-txdat")
0065 
0066 #define LN1_PIN_GPIO(ID, NAME, REG, SHIFT, INVERT) \
0067     LN_PIN_GPIO(1, ID, NAME, REG, SHIFT, INVERT)
0068 
0069 #define LN1_PIN_MUX(ID, NAME) \
0070 static const struct lochnagar_pin lochnagar1_##ID##_pin = \
0071     { .name = NAME, .type = LN_PTYPE_MUX, .reg = LOCHNAGAR1_##ID, }
0072 
0073 #define LN1_PIN_AIF(ID) LN_PIN_AIF(1, ID)
0074 
0075 #define LN2_PIN_GPIO(ID, NAME, REG, SHIFT, INVERT) \
0076     LN_PIN_GPIO(2, ID, NAME, REG, SHIFT, INVERT)
0077 
0078 #define LN2_PIN_MUX(ID, NAME) \
0079 static const struct lochnagar_pin lochnagar2_##ID##_pin = \
0080     { .name = NAME, .type = LN_PTYPE_MUX, .reg = LOCHNAGAR2_GPIO_##ID, }
0081 
0082 #define LN2_PIN_AIF(ID) LN_PIN_AIF(2, ID)
0083 
0084 #define LN2_PIN_GAI(ID) \
0085     LN2_PIN_MUX(ID##_BCLK,  LN_##ID##_STR"-bclk"); \
0086     LN2_PIN_MUX(ID##_LRCLK, LN_##ID##_STR"-lrclk"); \
0087     LN2_PIN_MUX(ID##_RXDAT, LN_##ID##_STR"-rxdat"); \
0088     LN2_PIN_MUX(ID##_TXDAT, LN_##ID##_STR"-txdat")
0089 
0090 #define LN_PIN(REV, ID) [LOCHNAGAR##REV##_PIN_##ID] = { \
0091     .number = LOCHNAGAR##REV##_PIN_##ID, \
0092     .name = lochnagar##REV##_##ID##_pin.name, \
0093     .drv_data = (void *)&lochnagar##REV##_##ID##_pin, \
0094 }
0095 
0096 #define LN1_PIN(ID) LN_PIN(1, ID)
0097 #define LN2_PIN(ID) LN_PIN(2, ID)
0098 
0099 #define LN_PINS(REV, ID) \
0100     LN_PIN(REV, ID##_BCLK), LN_PIN(REV, ID##_LRCLK), \
0101     LN_PIN(REV, ID##_RXDAT), LN_PIN(REV, ID##_TXDAT)
0102 
0103 #define LN1_PINS(ID) LN_PINS(1, ID)
0104 #define LN2_PINS(ID) LN_PINS(2, ID)
0105 
0106 enum {
0107     LOCHNAGAR1_PIN_GF_GPIO2 = LOCHNAGAR1_PIN_NUM_GPIOS,
0108     LOCHNAGAR1_PIN_GF_GPIO3,
0109     LOCHNAGAR1_PIN_GF_GPIO7,
0110     LOCHNAGAR1_PIN_LED1,
0111     LOCHNAGAR1_PIN_LED2,
0112     LOCHNAGAR1_PIN_CDC_AIF1_BCLK,
0113     LOCHNAGAR1_PIN_CDC_AIF1_LRCLK,
0114     LOCHNAGAR1_PIN_CDC_AIF1_RXDAT,
0115     LOCHNAGAR1_PIN_CDC_AIF1_TXDAT,
0116     LOCHNAGAR1_PIN_CDC_AIF2_BCLK,
0117     LOCHNAGAR1_PIN_CDC_AIF2_LRCLK,
0118     LOCHNAGAR1_PIN_CDC_AIF2_RXDAT,
0119     LOCHNAGAR1_PIN_CDC_AIF2_TXDAT,
0120     LOCHNAGAR1_PIN_CDC_AIF3_BCLK,
0121     LOCHNAGAR1_PIN_CDC_AIF3_LRCLK,
0122     LOCHNAGAR1_PIN_CDC_AIF3_RXDAT,
0123     LOCHNAGAR1_PIN_CDC_AIF3_TXDAT,
0124     LOCHNAGAR1_PIN_DSP_AIF1_BCLK,
0125     LOCHNAGAR1_PIN_DSP_AIF1_LRCLK,
0126     LOCHNAGAR1_PIN_DSP_AIF1_RXDAT,
0127     LOCHNAGAR1_PIN_DSP_AIF1_TXDAT,
0128     LOCHNAGAR1_PIN_DSP_AIF2_BCLK,
0129     LOCHNAGAR1_PIN_DSP_AIF2_LRCLK,
0130     LOCHNAGAR1_PIN_DSP_AIF2_RXDAT,
0131     LOCHNAGAR1_PIN_DSP_AIF2_TXDAT,
0132     LOCHNAGAR1_PIN_PSIA1_BCLK,
0133     LOCHNAGAR1_PIN_PSIA1_LRCLK,
0134     LOCHNAGAR1_PIN_PSIA1_RXDAT,
0135     LOCHNAGAR1_PIN_PSIA1_TXDAT,
0136     LOCHNAGAR1_PIN_PSIA2_BCLK,
0137     LOCHNAGAR1_PIN_PSIA2_LRCLK,
0138     LOCHNAGAR1_PIN_PSIA2_RXDAT,
0139     LOCHNAGAR1_PIN_PSIA2_TXDAT,
0140     LOCHNAGAR1_PIN_SPDIF_AIF_BCLK,
0141     LOCHNAGAR1_PIN_SPDIF_AIF_LRCLK,
0142     LOCHNAGAR1_PIN_SPDIF_AIF_RXDAT,
0143     LOCHNAGAR1_PIN_SPDIF_AIF_TXDAT,
0144     LOCHNAGAR1_PIN_GF_AIF3_BCLK,
0145     LOCHNAGAR1_PIN_GF_AIF3_RXDAT,
0146     LOCHNAGAR1_PIN_GF_AIF3_LRCLK,
0147     LOCHNAGAR1_PIN_GF_AIF3_TXDAT,
0148     LOCHNAGAR1_PIN_GF_AIF4_BCLK,
0149     LOCHNAGAR1_PIN_GF_AIF4_RXDAT,
0150     LOCHNAGAR1_PIN_GF_AIF4_LRCLK,
0151     LOCHNAGAR1_PIN_GF_AIF4_TXDAT,
0152     LOCHNAGAR1_PIN_GF_AIF1_BCLK,
0153     LOCHNAGAR1_PIN_GF_AIF1_RXDAT,
0154     LOCHNAGAR1_PIN_GF_AIF1_LRCLK,
0155     LOCHNAGAR1_PIN_GF_AIF1_TXDAT,
0156     LOCHNAGAR1_PIN_GF_AIF2_BCLK,
0157     LOCHNAGAR1_PIN_GF_AIF2_RXDAT,
0158     LOCHNAGAR1_PIN_GF_AIF2_LRCLK,
0159     LOCHNAGAR1_PIN_GF_AIF2_TXDAT,
0160 
0161     LOCHNAGAR2_PIN_SPDIF_AIF_BCLK = LOCHNAGAR2_PIN_NUM_GPIOS,
0162     LOCHNAGAR2_PIN_SPDIF_AIF_LRCLK,
0163     LOCHNAGAR2_PIN_SPDIF_AIF_RXDAT,
0164     LOCHNAGAR2_PIN_SPDIF_AIF_TXDAT,
0165     LOCHNAGAR2_PIN_USB_AIF1_BCLK,
0166     LOCHNAGAR2_PIN_USB_AIF1_LRCLK,
0167     LOCHNAGAR2_PIN_USB_AIF1_RXDAT,
0168     LOCHNAGAR2_PIN_USB_AIF1_TXDAT,
0169     LOCHNAGAR2_PIN_USB_AIF2_BCLK,
0170     LOCHNAGAR2_PIN_USB_AIF2_LRCLK,
0171     LOCHNAGAR2_PIN_USB_AIF2_RXDAT,
0172     LOCHNAGAR2_PIN_USB_AIF2_TXDAT,
0173     LOCHNAGAR2_PIN_ADAT_AIF_BCLK,
0174     LOCHNAGAR2_PIN_ADAT_AIF_LRCLK,
0175     LOCHNAGAR2_PIN_ADAT_AIF_RXDAT,
0176     LOCHNAGAR2_PIN_ADAT_AIF_TXDAT,
0177     LOCHNAGAR2_PIN_SOUNDCARD_AIF_BCLK,
0178     LOCHNAGAR2_PIN_SOUNDCARD_AIF_LRCLK,
0179     LOCHNAGAR2_PIN_SOUNDCARD_AIF_RXDAT,
0180     LOCHNAGAR2_PIN_SOUNDCARD_AIF_TXDAT,
0181 };
0182 
0183 enum lochnagar_pin_type {
0184     LN_PTYPE_GPIO,
0185     LN_PTYPE_MUX,
0186     LN_PTYPE_AIF,
0187     LN_PTYPE_COUNT,
0188 };
0189 
0190 struct lochnagar_pin {
0191     const char name[20];
0192 
0193     enum lochnagar_pin_type type;
0194 
0195     unsigned int reg;
0196     int shift;
0197     bool invert;
0198 };
0199 
0200 LN1_PIN_GPIO(CDC_RESET,    "codec-reset",    RST,      CDC_RESET,    1);
0201 LN1_PIN_GPIO(DSP_RESET,    "dsp-reset",      RST,      DSP_RESET,    1);
0202 LN1_PIN_GPIO(CDC_CIF1MODE, "codec-cif1mode", I2C_CTRL, CDC_CIF_MODE, 0);
0203 LN1_PIN_MUX(GF_GPIO2,      "gf-gpio2");
0204 LN1_PIN_MUX(GF_GPIO3,      "gf-gpio3");
0205 LN1_PIN_MUX(GF_GPIO7,      "gf-gpio7");
0206 LN1_PIN_MUX(LED1,          "led1");
0207 LN1_PIN_MUX(LED2,          "led2");
0208 LN1_PIN_AIF(CDC_AIF1);
0209 LN1_PIN_AIF(CDC_AIF2);
0210 LN1_PIN_AIF(CDC_AIF3);
0211 LN1_PIN_AIF(DSP_AIF1);
0212 LN1_PIN_AIF(DSP_AIF2);
0213 LN1_PIN_AIF(PSIA1);
0214 LN1_PIN_AIF(PSIA2);
0215 LN1_PIN_AIF(SPDIF_AIF);
0216 LN1_PIN_AIF(GF_AIF1);
0217 LN1_PIN_AIF(GF_AIF2);
0218 LN1_PIN_AIF(GF_AIF3);
0219 LN1_PIN_AIF(GF_AIF4);
0220 
0221 LN2_PIN_GPIO(CDC_RESET,    "codec-reset",    MINICARD_RESETS, CDC_RESET,     1);
0222 LN2_PIN_GPIO(DSP_RESET,    "dsp-reset",      MINICARD_RESETS, DSP_RESET,     1);
0223 LN2_PIN_GPIO(CDC_CIF1MODE, "codec-cif1mode", COMMS_CTRL4,     CDC_CIF1MODE,  0);
0224 LN2_PIN_GPIO(CDC_LDOENA,   "codec-ldoena",   POWER_CTRL,      PWR_ENA,       0);
0225 LN2_PIN_GPIO(SPDIF_HWMODE, "spdif-hwmode",   SPDIF_CTRL,      SPDIF_HWMODE,  0);
0226 LN2_PIN_GPIO(SPDIF_RESET,  "spdif-reset",    SPDIF_CTRL,      SPDIF_RESET,   1);
0227 LN2_PIN_MUX(FPGA_GPIO1,    "fpga-gpio1");
0228 LN2_PIN_MUX(FPGA_GPIO2,    "fpga-gpio2");
0229 LN2_PIN_MUX(FPGA_GPIO3,    "fpga-gpio3");
0230 LN2_PIN_MUX(FPGA_GPIO4,    "fpga-gpio4");
0231 LN2_PIN_MUX(FPGA_GPIO5,    "fpga-gpio5");
0232 LN2_PIN_MUX(FPGA_GPIO6,    "fpga-gpio6");
0233 LN2_PIN_MUX(CDC_GPIO1,     "codec-gpio1");
0234 LN2_PIN_MUX(CDC_GPIO2,     "codec-gpio2");
0235 LN2_PIN_MUX(CDC_GPIO3,     "codec-gpio3");
0236 LN2_PIN_MUX(CDC_GPIO4,     "codec-gpio4");
0237 LN2_PIN_MUX(CDC_GPIO5,     "codec-gpio5");
0238 LN2_PIN_MUX(CDC_GPIO6,     "codec-gpio6");
0239 LN2_PIN_MUX(CDC_GPIO7,     "codec-gpio7");
0240 LN2_PIN_MUX(CDC_GPIO8,     "codec-gpio8");
0241 LN2_PIN_MUX(DSP_GPIO1,     "dsp-gpio1");
0242 LN2_PIN_MUX(DSP_GPIO2,     "dsp-gpio2");
0243 LN2_PIN_MUX(DSP_GPIO3,     "dsp-gpio3");
0244 LN2_PIN_MUX(DSP_GPIO4,     "dsp-gpio4");
0245 LN2_PIN_MUX(DSP_GPIO5,     "dsp-gpio5");
0246 LN2_PIN_MUX(DSP_GPIO6,     "dsp-gpio6");
0247 LN2_PIN_MUX(GF_GPIO2,      "gf-gpio2");
0248 LN2_PIN_MUX(GF_GPIO3,      "gf-gpio3");
0249 LN2_PIN_MUX(GF_GPIO7,      "gf-gpio7");
0250 LN2_PIN_MUX(DSP_UART1_RX,  "dsp-uart1-rx");
0251 LN2_PIN_MUX(DSP_UART1_TX,  "dsp-uart1-tx");
0252 LN2_PIN_MUX(DSP_UART2_RX,  "dsp-uart2-rx");
0253 LN2_PIN_MUX(DSP_UART2_TX,  "dsp-uart2-tx");
0254 LN2_PIN_MUX(GF_UART2_RX,   "gf-uart2-rx");
0255 LN2_PIN_MUX(GF_UART2_TX,   "gf-uart2-tx");
0256 LN2_PIN_MUX(USB_UART_RX,   "usb-uart-rx");
0257 LN2_PIN_MUX(CDC_PDMCLK1,   "codec-pdmclk1");
0258 LN2_PIN_MUX(CDC_PDMDAT1,   "codec-pdmdat1");
0259 LN2_PIN_MUX(CDC_PDMCLK2,   "codec-pdmclk2");
0260 LN2_PIN_MUX(CDC_PDMDAT2,   "codec-pdmdat2");
0261 LN2_PIN_MUX(CDC_DMICCLK1,  "codec-dmicclk1");
0262 LN2_PIN_MUX(CDC_DMICDAT1,  "codec-dmicdat1");
0263 LN2_PIN_MUX(CDC_DMICCLK2,  "codec-dmicclk2");
0264 LN2_PIN_MUX(CDC_DMICDAT2,  "codec-dmicdat2");
0265 LN2_PIN_MUX(CDC_DMICCLK3,  "codec-dmicclk3");
0266 LN2_PIN_MUX(CDC_DMICDAT3,  "codec-dmicdat3");
0267 LN2_PIN_MUX(CDC_DMICCLK4,  "codec-dmicclk4");
0268 LN2_PIN_MUX(CDC_DMICDAT4,  "codec-dmicdat4");
0269 LN2_PIN_MUX(DSP_DMICCLK1,  "dsp-dmicclk1");
0270 LN2_PIN_MUX(DSP_DMICDAT1,  "dsp-dmicdat1");
0271 LN2_PIN_MUX(DSP_DMICCLK2,  "dsp-dmicclk2");
0272 LN2_PIN_MUX(DSP_DMICDAT2,  "dsp-dmicdat2");
0273 LN2_PIN_MUX(I2C2_SCL,      "i2c2-scl");
0274 LN2_PIN_MUX(I2C2_SDA,      "i2c2-sda");
0275 LN2_PIN_MUX(I2C3_SCL,      "i2c3-scl");
0276 LN2_PIN_MUX(I2C3_SDA,      "i2c3-sda");
0277 LN2_PIN_MUX(I2C4_SCL,      "i2c4-scl");
0278 LN2_PIN_MUX(I2C4_SDA,      "i2c4-sda");
0279 LN2_PIN_MUX(DSP_STANDBY,   "dsp-standby");
0280 LN2_PIN_MUX(CDC_MCLK1,     "codec-mclk1");
0281 LN2_PIN_MUX(CDC_MCLK2,     "codec-mclk2");
0282 LN2_PIN_MUX(DSP_CLKIN,     "dsp-clkin");
0283 LN2_PIN_MUX(PSIA1_MCLK,    "psia1-mclk");
0284 LN2_PIN_MUX(PSIA2_MCLK,    "psia2-mclk");
0285 LN2_PIN_MUX(GF_GPIO1,      "gf-gpio1");
0286 LN2_PIN_MUX(GF_GPIO5,      "gf-gpio5");
0287 LN2_PIN_MUX(DSP_GPIO20,    "dsp-gpio20");
0288 LN2_PIN_GAI(CDC_AIF1);
0289 LN2_PIN_GAI(CDC_AIF2);
0290 LN2_PIN_GAI(CDC_AIF3);
0291 LN2_PIN_GAI(DSP_AIF1);
0292 LN2_PIN_GAI(DSP_AIF2);
0293 LN2_PIN_GAI(PSIA1);
0294 LN2_PIN_GAI(PSIA2);
0295 LN2_PIN_GAI(GF_AIF1);
0296 LN2_PIN_GAI(GF_AIF2);
0297 LN2_PIN_GAI(GF_AIF3);
0298 LN2_PIN_GAI(GF_AIF4);
0299 LN2_PIN_AIF(SPDIF_AIF);
0300 LN2_PIN_AIF(USB_AIF1);
0301 LN2_PIN_AIF(USB_AIF2);
0302 LN2_PIN_AIF(ADAT_AIF);
0303 LN2_PIN_AIF(SOUNDCARD_AIF);
0304 
0305 static const struct pinctrl_pin_desc lochnagar1_pins[] = {
0306     LN1_PIN(CDC_RESET),      LN1_PIN(DSP_RESET),    LN1_PIN(CDC_CIF1MODE),
0307     LN1_PIN(GF_GPIO2),       LN1_PIN(GF_GPIO3),     LN1_PIN(GF_GPIO7),
0308     LN1_PIN(LED1),           LN1_PIN(LED2),
0309     LN1_PINS(CDC_AIF1),      LN1_PINS(CDC_AIF2),    LN1_PINS(CDC_AIF3),
0310     LN1_PINS(DSP_AIF1),      LN1_PINS(DSP_AIF2),
0311     LN1_PINS(PSIA1),         LN1_PINS(PSIA2),
0312     LN1_PINS(SPDIF_AIF),
0313     LN1_PINS(GF_AIF1),       LN1_PINS(GF_AIF2),
0314     LN1_PINS(GF_AIF3),       LN1_PINS(GF_AIF4),
0315 };
0316 
0317 static const struct pinctrl_pin_desc lochnagar2_pins[] = {
0318     LN2_PIN(CDC_RESET),      LN2_PIN(DSP_RESET),    LN2_PIN(CDC_CIF1MODE),
0319     LN2_PIN(CDC_LDOENA),
0320     LN2_PIN(SPDIF_HWMODE),   LN2_PIN(SPDIF_RESET),
0321     LN2_PIN(FPGA_GPIO1),     LN2_PIN(FPGA_GPIO2),   LN2_PIN(FPGA_GPIO3),
0322     LN2_PIN(FPGA_GPIO4),     LN2_PIN(FPGA_GPIO5),   LN2_PIN(FPGA_GPIO6),
0323     LN2_PIN(CDC_GPIO1),      LN2_PIN(CDC_GPIO2),    LN2_PIN(CDC_GPIO3),
0324     LN2_PIN(CDC_GPIO4),      LN2_PIN(CDC_GPIO5),    LN2_PIN(CDC_GPIO6),
0325     LN2_PIN(CDC_GPIO7),      LN2_PIN(CDC_GPIO8),
0326     LN2_PIN(DSP_GPIO1),      LN2_PIN(DSP_GPIO2),    LN2_PIN(DSP_GPIO3),
0327     LN2_PIN(DSP_GPIO4),      LN2_PIN(DSP_GPIO5),    LN2_PIN(DSP_GPIO6),
0328     LN2_PIN(DSP_GPIO20),
0329     LN2_PIN(GF_GPIO1),       LN2_PIN(GF_GPIO2),     LN2_PIN(GF_GPIO3),
0330     LN2_PIN(GF_GPIO5),       LN2_PIN(GF_GPIO7),
0331     LN2_PINS(CDC_AIF1),      LN2_PINS(CDC_AIF2),    LN2_PINS(CDC_AIF3),
0332     LN2_PINS(DSP_AIF1),      LN2_PINS(DSP_AIF2),
0333     LN2_PINS(PSIA1),         LN2_PINS(PSIA2),
0334     LN2_PINS(GF_AIF1),       LN2_PINS(GF_AIF2),
0335     LN2_PINS(GF_AIF3),       LN2_PINS(GF_AIF4),
0336     LN2_PIN(DSP_UART1_RX),   LN2_PIN(DSP_UART1_TX),
0337     LN2_PIN(DSP_UART2_RX),   LN2_PIN(DSP_UART2_TX),
0338     LN2_PIN(GF_UART2_RX),    LN2_PIN(GF_UART2_TX),
0339     LN2_PIN(USB_UART_RX),
0340     LN2_PIN(CDC_PDMCLK1),    LN2_PIN(CDC_PDMDAT1),
0341     LN2_PIN(CDC_PDMCLK2),    LN2_PIN(CDC_PDMDAT2),
0342     LN2_PIN(CDC_DMICCLK1),   LN2_PIN(CDC_DMICDAT1),
0343     LN2_PIN(CDC_DMICCLK2),   LN2_PIN(CDC_DMICDAT2),
0344     LN2_PIN(CDC_DMICCLK3),   LN2_PIN(CDC_DMICDAT3),
0345     LN2_PIN(CDC_DMICCLK4),   LN2_PIN(CDC_DMICDAT4),
0346     LN2_PIN(DSP_DMICCLK1),   LN2_PIN(DSP_DMICDAT1),
0347     LN2_PIN(DSP_DMICCLK2),   LN2_PIN(DSP_DMICDAT2),
0348     LN2_PIN(I2C2_SCL),       LN2_PIN(I2C2_SDA),
0349     LN2_PIN(I2C3_SCL),       LN2_PIN(I2C3_SDA),
0350     LN2_PIN(I2C4_SCL),       LN2_PIN(I2C4_SDA),
0351     LN2_PIN(DSP_STANDBY),
0352     LN2_PIN(CDC_MCLK1),      LN2_PIN(CDC_MCLK2),
0353     LN2_PIN(DSP_CLKIN),
0354     LN2_PIN(PSIA1_MCLK),     LN2_PIN(PSIA2_MCLK),
0355     LN2_PINS(SPDIF_AIF),
0356     LN2_PINS(USB_AIF1),      LN2_PINS(USB_AIF2),
0357     LN2_PINS(ADAT_AIF),
0358     LN2_PINS(SOUNDCARD_AIF),
0359 };
0360 
0361 #define LN_AIF_PINS(REV, ID) \
0362     LOCHNAGAR##REV##_PIN_##ID##_BCLK, \
0363     LOCHNAGAR##REV##_PIN_##ID##_LRCLK, \
0364     LOCHNAGAR##REV##_PIN_##ID##_TXDAT, \
0365     LOCHNAGAR##REV##_PIN_##ID##_RXDAT,
0366 
0367 #define LN1_AIF(ID, CTRL) \
0368 static const struct lochnagar_aif lochnagar1_##ID##_aif = { \
0369     .name = LN_##ID##_STR, \
0370     .pins = { LN_AIF_PINS(1, ID) }, \
0371     .src_reg = LOCHNAGAR1_##ID##_SEL, \
0372     .src_mask = LOCHNAGAR1_SRC_MASK, \
0373     .ctrl_reg = LOCHNAGAR1_##CTRL, \
0374     .ena_mask = LOCHNAGAR1_##ID##_ENA_MASK, \
0375     .master_mask = LOCHNAGAR1_##ID##_LRCLK_DIR_MASK | \
0376                LOCHNAGAR1_##ID##_BCLK_DIR_MASK, \
0377 }
0378 
0379 #define LN2_AIF(ID) \
0380 static const struct lochnagar_aif lochnagar2_##ID##_aif = { \
0381     .name = LN_##ID##_STR, \
0382     .pins = { LN_AIF_PINS(2, ID) }, \
0383     .src_reg = LOCHNAGAR2_##ID##_CTRL,  \
0384     .src_mask = LOCHNAGAR2_AIF_SRC_MASK, \
0385     .ctrl_reg = LOCHNAGAR2_##ID##_CTRL, \
0386     .ena_mask = LOCHNAGAR2_AIF_ENA_MASK, \
0387     .master_mask = LOCHNAGAR2_AIF_LRCLK_DIR_MASK | \
0388                LOCHNAGAR2_AIF_BCLK_DIR_MASK, \
0389 }
0390 
0391 struct lochnagar_aif {
0392     const char name[16];
0393 
0394     unsigned int pins[4];
0395 
0396     u16 src_reg;
0397     u16 src_mask;
0398 
0399     u16 ctrl_reg;
0400     u16 ena_mask;
0401     u16 master_mask;
0402 };
0403 
0404 LN1_AIF(CDC_AIF1,      CDC_AIF_CTRL1);
0405 LN1_AIF(CDC_AIF2,      CDC_AIF_CTRL1);
0406 LN1_AIF(CDC_AIF3,      CDC_AIF_CTRL2);
0407 LN1_AIF(DSP_AIF1,      DSP_AIF);
0408 LN1_AIF(DSP_AIF2,      DSP_AIF);
0409 LN1_AIF(PSIA1,         PSIA_AIF);
0410 LN1_AIF(PSIA2,         PSIA_AIF);
0411 LN1_AIF(GF_AIF1,       GF_AIF1);
0412 LN1_AIF(GF_AIF2,       GF_AIF2);
0413 LN1_AIF(GF_AIF3,       GF_AIF1);
0414 LN1_AIF(GF_AIF4,       GF_AIF2);
0415 LN1_AIF(SPDIF_AIF,     EXT_AIF_CTRL);
0416 
0417 LN2_AIF(CDC_AIF1);
0418 LN2_AIF(CDC_AIF2);
0419 LN2_AIF(CDC_AIF3);
0420 LN2_AIF(DSP_AIF1);
0421 LN2_AIF(DSP_AIF2);
0422 LN2_AIF(PSIA1);
0423 LN2_AIF(PSIA2);
0424 LN2_AIF(GF_AIF1);
0425 LN2_AIF(GF_AIF2);
0426 LN2_AIF(GF_AIF3);
0427 LN2_AIF(GF_AIF4);
0428 LN2_AIF(SPDIF_AIF);
0429 LN2_AIF(USB_AIF1);
0430 LN2_AIF(USB_AIF2);
0431 LN2_AIF(ADAT_AIF);
0432 LN2_AIF(SOUNDCARD_AIF);
0433 
0434 #define LN2_OP_AIF  0x00
0435 #define LN2_OP_GPIO 0xFE
0436 
0437 #define LN_FUNC(NAME, TYPE, OP) \
0438     { .name = NAME, .type = LN_FTYPE_##TYPE, .op = OP }
0439 
0440 #define LN_FUNC_PIN(REV, ID, OP) \
0441     LN_FUNC(lochnagar##REV##_##ID##_pin.name, PIN, OP)
0442 
0443 #define LN1_FUNC_PIN(ID, OP) LN_FUNC_PIN(1, ID, OP)
0444 #define LN2_FUNC_PIN(ID, OP) LN_FUNC_PIN(2, ID, OP)
0445 
0446 #define LN_FUNC_AIF(REV, ID, OP) \
0447     LN_FUNC(lochnagar##REV##_##ID##_aif.name, AIF, OP)
0448 
0449 #define LN1_FUNC_AIF(ID, OP) LN_FUNC_AIF(1, ID, OP)
0450 #define LN2_FUNC_AIF(ID, OP) LN_FUNC_AIF(2, ID, OP)
0451 
0452 #define LN2_FUNC_GAI(ID, OP, BOP, LROP, RXOP, TXOP) \
0453     LN2_FUNC_AIF(ID, OP), \
0454     LN_FUNC(lochnagar2_##ID##_BCLK_pin.name, PIN, BOP), \
0455     LN_FUNC(lochnagar2_##ID##_LRCLK_pin.name, PIN, LROP), \
0456     LN_FUNC(lochnagar2_##ID##_RXDAT_pin.name, PIN, RXOP), \
0457     LN_FUNC(lochnagar2_##ID##_TXDAT_pin.name, PIN, TXOP)
0458 
0459 enum lochnagar_func_type {
0460     LN_FTYPE_PIN,
0461     LN_FTYPE_AIF,
0462     LN_FTYPE_COUNT,
0463 };
0464 
0465 struct lochnagar_func {
0466     const char * const name;
0467 
0468     enum lochnagar_func_type type;
0469 
0470     u8 op;
0471 };
0472 
0473 static const struct lochnagar_func lochnagar1_funcs[] = {
0474     LN_FUNC("dsp-gpio1",       PIN, 0x01),
0475     LN_FUNC("dsp-gpio2",       PIN, 0x02),
0476     LN_FUNC("dsp-gpio3",       PIN, 0x03),
0477     LN_FUNC("codec-gpio1",     PIN, 0x04),
0478     LN_FUNC("codec-gpio2",     PIN, 0x05),
0479     LN_FUNC("codec-gpio3",     PIN, 0x06),
0480     LN_FUNC("codec-gpio4",     PIN, 0x07),
0481     LN_FUNC("codec-gpio5",     PIN, 0x08),
0482     LN_FUNC("codec-gpio6",     PIN, 0x09),
0483     LN_FUNC("codec-gpio7",     PIN, 0x0A),
0484     LN_FUNC("codec-gpio8",     PIN, 0x0B),
0485     LN1_FUNC_PIN(GF_GPIO2,          0x0C),
0486     LN1_FUNC_PIN(GF_GPIO3,          0x0D),
0487     LN1_FUNC_PIN(GF_GPIO7,          0x0E),
0488 
0489     LN1_FUNC_AIF(SPDIF_AIF,         0x01),
0490     LN1_FUNC_AIF(PSIA1,             0x02),
0491     LN1_FUNC_AIF(PSIA2,             0x03),
0492     LN1_FUNC_AIF(CDC_AIF1,          0x04),
0493     LN1_FUNC_AIF(CDC_AIF2,          0x05),
0494     LN1_FUNC_AIF(CDC_AIF3,          0x06),
0495     LN1_FUNC_AIF(DSP_AIF1,          0x07),
0496     LN1_FUNC_AIF(DSP_AIF2,          0x08),
0497     LN1_FUNC_AIF(GF_AIF3,           0x09),
0498     LN1_FUNC_AIF(GF_AIF4,           0x0A),
0499     LN1_FUNC_AIF(GF_AIF1,           0x0B),
0500     LN1_FUNC_AIF(GF_AIF2,           0x0C),
0501 };
0502 
0503 static const struct lochnagar_func lochnagar2_funcs[] = {
0504     LN_FUNC("aif",             PIN, LN2_OP_AIF),
0505     LN2_FUNC_PIN(FPGA_GPIO1,        0x01),
0506     LN2_FUNC_PIN(FPGA_GPIO2,        0x02),
0507     LN2_FUNC_PIN(FPGA_GPIO3,        0x03),
0508     LN2_FUNC_PIN(FPGA_GPIO4,        0x04),
0509     LN2_FUNC_PIN(FPGA_GPIO5,        0x05),
0510     LN2_FUNC_PIN(FPGA_GPIO6,        0x06),
0511     LN2_FUNC_PIN(CDC_GPIO1,         0x07),
0512     LN2_FUNC_PIN(CDC_GPIO2,         0x08),
0513     LN2_FUNC_PIN(CDC_GPIO3,         0x09),
0514     LN2_FUNC_PIN(CDC_GPIO4,         0x0A),
0515     LN2_FUNC_PIN(CDC_GPIO5,         0x0B),
0516     LN2_FUNC_PIN(CDC_GPIO6,         0x0C),
0517     LN2_FUNC_PIN(CDC_GPIO7,         0x0D),
0518     LN2_FUNC_PIN(CDC_GPIO8,         0x0E),
0519     LN2_FUNC_PIN(DSP_GPIO1,         0x0F),
0520     LN2_FUNC_PIN(DSP_GPIO2,         0x10),
0521     LN2_FUNC_PIN(DSP_GPIO3,         0x11),
0522     LN2_FUNC_PIN(DSP_GPIO4,         0x12),
0523     LN2_FUNC_PIN(DSP_GPIO5,         0x13),
0524     LN2_FUNC_PIN(DSP_GPIO6,         0x14),
0525     LN2_FUNC_PIN(GF_GPIO2,          0x15),
0526     LN2_FUNC_PIN(GF_GPIO3,          0x16),
0527     LN2_FUNC_PIN(GF_GPIO7,          0x17),
0528     LN2_FUNC_PIN(GF_GPIO1,          0x18),
0529     LN2_FUNC_PIN(GF_GPIO5,          0x19),
0530     LN2_FUNC_PIN(DSP_GPIO20,        0x1A),
0531     LN_FUNC("codec-clkout",    PIN, 0x20),
0532     LN_FUNC("dsp-clkout",      PIN, 0x21),
0533     LN_FUNC("pmic-32k",        PIN, 0x22),
0534     LN_FUNC("spdif-clkout",    PIN, 0x23),
0535     LN_FUNC("clk-12m288",      PIN, 0x24),
0536     LN_FUNC("clk-11m2986",     PIN, 0x25),
0537     LN_FUNC("clk-24m576",      PIN, 0x26),
0538     LN_FUNC("clk-22m5792",     PIN, 0x27),
0539     LN_FUNC("xmos-mclk",       PIN, 0x29),
0540     LN_FUNC("gf-clkout1",      PIN, 0x2A),
0541     LN_FUNC("gf-mclk1",        PIN, 0x2B),
0542     LN_FUNC("gf-mclk3",        PIN, 0x2C),
0543     LN_FUNC("gf-mclk2",        PIN, 0x2D),
0544     LN_FUNC("gf-clkout2",      PIN, 0x2E),
0545     LN2_FUNC_PIN(CDC_MCLK1,         0x2F),
0546     LN2_FUNC_PIN(CDC_MCLK2,         0x30),
0547     LN2_FUNC_PIN(DSP_CLKIN,         0x31),
0548     LN2_FUNC_PIN(PSIA1_MCLK,        0x32),
0549     LN2_FUNC_PIN(PSIA2_MCLK,        0x33),
0550     LN_FUNC("spdif-mclk",      PIN, 0x34),
0551     LN_FUNC("codec-irq",       PIN, 0x42),
0552     LN2_FUNC_PIN(CDC_RESET,         0x43),
0553     LN2_FUNC_PIN(DSP_RESET,         0x44),
0554     LN_FUNC("dsp-irq",         PIN, 0x45),
0555     LN2_FUNC_PIN(DSP_STANDBY,       0x46),
0556     LN2_FUNC_PIN(CDC_PDMCLK1,       0x90),
0557     LN2_FUNC_PIN(CDC_PDMDAT1,       0x91),
0558     LN2_FUNC_PIN(CDC_PDMCLK2,       0x92),
0559     LN2_FUNC_PIN(CDC_PDMDAT2,       0x93),
0560     LN2_FUNC_PIN(CDC_DMICCLK1,      0xA0),
0561     LN2_FUNC_PIN(CDC_DMICDAT1,      0xA1),
0562     LN2_FUNC_PIN(CDC_DMICCLK2,      0xA2),
0563     LN2_FUNC_PIN(CDC_DMICDAT2,      0xA3),
0564     LN2_FUNC_PIN(CDC_DMICCLK3,      0xA4),
0565     LN2_FUNC_PIN(CDC_DMICDAT3,      0xA5),
0566     LN2_FUNC_PIN(CDC_DMICCLK4,      0xA6),
0567     LN2_FUNC_PIN(CDC_DMICDAT4,      0xA7),
0568     LN2_FUNC_PIN(DSP_DMICCLK1,      0xA8),
0569     LN2_FUNC_PIN(DSP_DMICDAT1,      0xA9),
0570     LN2_FUNC_PIN(DSP_DMICCLK2,      0xAA),
0571     LN2_FUNC_PIN(DSP_DMICDAT2,      0xAB),
0572     LN2_FUNC_PIN(DSP_UART1_RX,      0xC0),
0573     LN2_FUNC_PIN(DSP_UART1_TX,      0xC1),
0574     LN2_FUNC_PIN(DSP_UART2_RX,      0xC2),
0575     LN2_FUNC_PIN(DSP_UART2_TX,      0xC3),
0576     LN2_FUNC_PIN(GF_UART2_RX,       0xC4),
0577     LN2_FUNC_PIN(GF_UART2_TX,       0xC5),
0578     LN2_FUNC_PIN(USB_UART_RX,       0xC6),
0579     LN_FUNC("usb-uart-tx",     PIN, 0xC7),
0580     LN2_FUNC_PIN(I2C2_SCL,          0xE0),
0581     LN2_FUNC_PIN(I2C2_SDA,          0xE1),
0582     LN2_FUNC_PIN(I2C3_SCL,          0xE2),
0583     LN2_FUNC_PIN(I2C3_SDA,          0xE3),
0584     LN2_FUNC_PIN(I2C4_SCL,          0xE4),
0585     LN2_FUNC_PIN(I2C4_SDA,          0xE5),
0586 
0587     LN2_FUNC_AIF(SPDIF_AIF,         0x01),
0588     LN2_FUNC_GAI(PSIA1,             0x02, 0x50, 0x51, 0x52, 0x53),
0589     LN2_FUNC_GAI(PSIA2,             0x03, 0x54, 0x55, 0x56, 0x57),
0590     LN2_FUNC_GAI(CDC_AIF1,          0x04, 0x59, 0x5B, 0x5A, 0x58),
0591     LN2_FUNC_GAI(CDC_AIF2,          0x05, 0x5D, 0x5F, 0x5E, 0x5C),
0592     LN2_FUNC_GAI(CDC_AIF3,          0x06, 0x61, 0x62, 0x63, 0x60),
0593     LN2_FUNC_GAI(DSP_AIF1,          0x07, 0x65, 0x67, 0x66, 0x64),
0594     LN2_FUNC_GAI(DSP_AIF2,          0x08, 0x69, 0x6B, 0x6A, 0x68),
0595     LN2_FUNC_GAI(GF_AIF3,           0x09, 0x6D, 0x6F, 0x6C, 0x6E),
0596     LN2_FUNC_GAI(GF_AIF4,           0x0A, 0x71, 0x73, 0x70, 0x72),
0597     LN2_FUNC_GAI(GF_AIF1,           0x0B, 0x75, 0x77, 0x74, 0x76),
0598     LN2_FUNC_GAI(GF_AIF2,           0x0C, 0x79, 0x7B, 0x78, 0x7A),
0599     LN2_FUNC_AIF(USB_AIF1,          0x0D),
0600     LN2_FUNC_AIF(USB_AIF2,          0x0E),
0601     LN2_FUNC_AIF(ADAT_AIF,          0x0F),
0602     LN2_FUNC_AIF(SOUNDCARD_AIF,     0x10),
0603 };
0604 
0605 #define LN_GROUP_PIN(REV, ID) { \
0606     .name = lochnagar##REV##_##ID##_pin.name, \
0607     .type = LN_FTYPE_PIN, \
0608     .pins = &lochnagar##REV##_pins[LOCHNAGAR##REV##_PIN_##ID].number, \
0609     .npins = 1, \
0610     .priv = &lochnagar##REV##_pins[LOCHNAGAR##REV##_PIN_##ID], \
0611 }
0612 
0613 #define LN_GROUP_AIF(REV, ID) { \
0614     .name = lochnagar##REV##_##ID##_aif.name, \
0615     .type = LN_FTYPE_AIF, \
0616     .pins = lochnagar##REV##_##ID##_aif.pins, \
0617     .npins = ARRAY_SIZE(lochnagar##REV##_##ID##_aif.pins), \
0618     .priv = &lochnagar##REV##_##ID##_aif, \
0619 }
0620 
0621 #define LN1_GROUP_PIN(ID) LN_GROUP_PIN(1, ID)
0622 #define LN2_GROUP_PIN(ID) LN_GROUP_PIN(2, ID)
0623 
0624 #define LN1_GROUP_AIF(ID) LN_GROUP_AIF(1, ID)
0625 #define LN2_GROUP_AIF(ID) LN_GROUP_AIF(2, ID)
0626 
0627 #define LN2_GROUP_GAI(ID) \
0628     LN2_GROUP_AIF(ID), \
0629     LN2_GROUP_PIN(ID##_BCLK), LN2_GROUP_PIN(ID##_LRCLK), \
0630     LN2_GROUP_PIN(ID##_RXDAT), LN2_GROUP_PIN(ID##_TXDAT)
0631 
0632 struct lochnagar_group {
0633     const char * const name;
0634 
0635     enum lochnagar_func_type type;
0636 
0637     const unsigned int *pins;
0638     unsigned int npins;
0639 
0640     const void *priv;
0641 };
0642 
0643 static const struct lochnagar_group lochnagar1_groups[] = {
0644     LN1_GROUP_PIN(GF_GPIO2),       LN1_GROUP_PIN(GF_GPIO3),
0645     LN1_GROUP_PIN(GF_GPIO7),
0646     LN1_GROUP_PIN(LED1),           LN1_GROUP_PIN(LED2),
0647     LN1_GROUP_AIF(CDC_AIF1),       LN1_GROUP_AIF(CDC_AIF2),
0648     LN1_GROUP_AIF(CDC_AIF3),
0649     LN1_GROUP_AIF(DSP_AIF1),       LN1_GROUP_AIF(DSP_AIF2),
0650     LN1_GROUP_AIF(PSIA1),          LN1_GROUP_AIF(PSIA2),
0651     LN1_GROUP_AIF(GF_AIF1),        LN1_GROUP_AIF(GF_AIF2),
0652     LN1_GROUP_AIF(GF_AIF3),        LN1_GROUP_AIF(GF_AIF4),
0653     LN1_GROUP_AIF(SPDIF_AIF),
0654 };
0655 
0656 static const struct lochnagar_group lochnagar2_groups[] = {
0657     LN2_GROUP_PIN(FPGA_GPIO1),     LN2_GROUP_PIN(FPGA_GPIO2),
0658     LN2_GROUP_PIN(FPGA_GPIO3),     LN2_GROUP_PIN(FPGA_GPIO4),
0659     LN2_GROUP_PIN(FPGA_GPIO5),     LN2_GROUP_PIN(FPGA_GPIO6),
0660     LN2_GROUP_PIN(CDC_GPIO1),      LN2_GROUP_PIN(CDC_GPIO2),
0661     LN2_GROUP_PIN(CDC_GPIO3),      LN2_GROUP_PIN(CDC_GPIO4),
0662     LN2_GROUP_PIN(CDC_GPIO5),      LN2_GROUP_PIN(CDC_GPIO6),
0663     LN2_GROUP_PIN(CDC_GPIO7),      LN2_GROUP_PIN(CDC_GPIO8),
0664     LN2_GROUP_PIN(DSP_GPIO1),      LN2_GROUP_PIN(DSP_GPIO2),
0665     LN2_GROUP_PIN(DSP_GPIO3),      LN2_GROUP_PIN(DSP_GPIO4),
0666     LN2_GROUP_PIN(DSP_GPIO5),      LN2_GROUP_PIN(DSP_GPIO6),
0667     LN2_GROUP_PIN(DSP_GPIO20),
0668     LN2_GROUP_PIN(GF_GPIO1),
0669     LN2_GROUP_PIN(GF_GPIO2),       LN2_GROUP_PIN(GF_GPIO5),
0670     LN2_GROUP_PIN(GF_GPIO3),       LN2_GROUP_PIN(GF_GPIO7),
0671     LN2_GROUP_PIN(DSP_UART1_RX),   LN2_GROUP_PIN(DSP_UART1_TX),
0672     LN2_GROUP_PIN(DSP_UART2_RX),   LN2_GROUP_PIN(DSP_UART2_TX),
0673     LN2_GROUP_PIN(GF_UART2_RX),    LN2_GROUP_PIN(GF_UART2_TX),
0674     LN2_GROUP_PIN(USB_UART_RX),
0675     LN2_GROUP_PIN(CDC_PDMCLK1),    LN2_GROUP_PIN(CDC_PDMDAT1),
0676     LN2_GROUP_PIN(CDC_PDMCLK2),    LN2_GROUP_PIN(CDC_PDMDAT2),
0677     LN2_GROUP_PIN(CDC_DMICCLK1),   LN2_GROUP_PIN(CDC_DMICDAT1),
0678     LN2_GROUP_PIN(CDC_DMICCLK2),   LN2_GROUP_PIN(CDC_DMICDAT2),
0679     LN2_GROUP_PIN(CDC_DMICCLK3),   LN2_GROUP_PIN(CDC_DMICDAT3),
0680     LN2_GROUP_PIN(CDC_DMICCLK4),   LN2_GROUP_PIN(CDC_DMICDAT4),
0681     LN2_GROUP_PIN(DSP_DMICCLK1),   LN2_GROUP_PIN(DSP_DMICDAT1),
0682     LN2_GROUP_PIN(DSP_DMICCLK2),   LN2_GROUP_PIN(DSP_DMICDAT2),
0683     LN2_GROUP_PIN(I2C2_SCL),       LN2_GROUP_PIN(I2C2_SDA),
0684     LN2_GROUP_PIN(I2C3_SCL),       LN2_GROUP_PIN(I2C3_SDA),
0685     LN2_GROUP_PIN(I2C4_SCL),       LN2_GROUP_PIN(I2C4_SDA),
0686     LN2_GROUP_PIN(DSP_STANDBY),
0687     LN2_GROUP_PIN(CDC_MCLK1),      LN2_GROUP_PIN(CDC_MCLK2),
0688     LN2_GROUP_PIN(DSP_CLKIN),
0689     LN2_GROUP_PIN(PSIA1_MCLK),     LN2_GROUP_PIN(PSIA2_MCLK),
0690     LN2_GROUP_GAI(CDC_AIF1),       LN2_GROUP_GAI(CDC_AIF2),
0691     LN2_GROUP_GAI(CDC_AIF3),
0692     LN2_GROUP_GAI(DSP_AIF1),       LN2_GROUP_GAI(DSP_AIF2),
0693     LN2_GROUP_GAI(PSIA1),          LN2_GROUP_GAI(PSIA2),
0694     LN2_GROUP_GAI(GF_AIF1),        LN2_GROUP_GAI(GF_AIF2),
0695     LN2_GROUP_GAI(GF_AIF3),        LN2_GROUP_GAI(GF_AIF4),
0696     LN2_GROUP_AIF(SPDIF_AIF),
0697     LN2_GROUP_AIF(USB_AIF1),       LN2_GROUP_AIF(USB_AIF2),
0698     LN2_GROUP_AIF(ADAT_AIF),
0699     LN2_GROUP_AIF(SOUNDCARD_AIF),
0700 };
0701 
0702 struct lochnagar_func_groups {
0703     const char **groups;
0704     unsigned int ngroups;
0705 };
0706 
0707 struct lochnagar_pin_priv {
0708     struct lochnagar *lochnagar;
0709     struct device *dev;
0710 
0711     const struct lochnagar_func *funcs;
0712     unsigned int nfuncs;
0713 
0714     const struct pinctrl_pin_desc *pins;
0715     unsigned int npins;
0716 
0717     const struct lochnagar_group *groups;
0718     unsigned int ngroups;
0719 
0720     struct lochnagar_func_groups func_groups[LN_FTYPE_COUNT];
0721 
0722     struct gpio_chip gpio_chip;
0723 };
0724 
0725 static int lochnagar_get_groups_count(struct pinctrl_dev *pctldev)
0726 {
0727     struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
0728 
0729     return priv->ngroups;
0730 }
0731 
0732 static const char *lochnagar_get_group_name(struct pinctrl_dev *pctldev,
0733                         unsigned int group_idx)
0734 {
0735     struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
0736 
0737     return priv->groups[group_idx].name;
0738 }
0739 
0740 static int lochnagar_get_group_pins(struct pinctrl_dev *pctldev,
0741                     unsigned int group_idx,
0742                     const unsigned int **pins,
0743                     unsigned int *num_pins)
0744 {
0745     struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
0746 
0747     *pins = priv->groups[group_idx].pins;
0748     *num_pins = priv->groups[group_idx].npins;
0749 
0750     return 0;
0751 }
0752 
0753 static const struct pinctrl_ops lochnagar_pin_group_ops = {
0754     .get_groups_count = lochnagar_get_groups_count,
0755     .get_group_name = lochnagar_get_group_name,
0756     .get_group_pins = lochnagar_get_group_pins,
0757     .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
0758     .dt_free_map = pinctrl_utils_free_map,
0759 };
0760 
0761 static int lochnagar_get_funcs_count(struct pinctrl_dev *pctldev)
0762 {
0763     struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
0764 
0765     return priv->nfuncs;
0766 }
0767 
0768 static const char *lochnagar_get_func_name(struct pinctrl_dev *pctldev,
0769                        unsigned int func_idx)
0770 {
0771     struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
0772 
0773     return priv->funcs[func_idx].name;
0774 }
0775 
0776 static int lochnagar_get_func_groups(struct pinctrl_dev *pctldev,
0777                      unsigned int func_idx,
0778                      const char * const **groups,
0779                      unsigned int * const num_groups)
0780 {
0781     struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
0782     int func_type;
0783 
0784     func_type = priv->funcs[func_idx].type;
0785 
0786     *groups = priv->func_groups[func_type].groups;
0787     *num_groups = priv->func_groups[func_type].ngroups;
0788 
0789     return 0;
0790 }
0791 
0792 static int lochnagar2_get_gpio_chan(struct lochnagar_pin_priv *priv,
0793                     unsigned int op)
0794 {
0795     struct regmap *regmap = priv->lochnagar->regmap;
0796     unsigned int val;
0797     int free = -1;
0798     int i, ret;
0799 
0800     for (i = 0; i < LN2_NUM_GPIO_CHANNELS; i++) {
0801         ret = regmap_read(regmap, LOCHNAGAR2_GPIO_CHANNEL1 + i, &val);
0802         if (ret)
0803             return ret;
0804 
0805         val &= LOCHNAGAR2_GPIO_CHANNEL_SRC_MASK;
0806 
0807         if (val == op)
0808             return i + 1;
0809 
0810         if (free < 0 && !val)
0811             free = i;
0812     }
0813 
0814     if (free >= 0) {
0815         ret = regmap_update_bits(regmap,
0816                      LOCHNAGAR2_GPIO_CHANNEL1 + free,
0817                      LOCHNAGAR2_GPIO_CHANNEL_SRC_MASK, op);
0818         if (ret)
0819             return ret;
0820 
0821         free++;
0822 
0823         dev_dbg(priv->dev, "Set channel %d to 0x%x\n", free, op);
0824 
0825         return free;
0826     }
0827 
0828     return -ENOSPC;
0829 }
0830 
0831 static int lochnagar_pin_set_mux(struct lochnagar_pin_priv *priv,
0832                  const struct lochnagar_pin *pin,
0833                  unsigned int op)
0834 {
0835     int ret;
0836 
0837     switch (priv->lochnagar->type) {
0838     case LOCHNAGAR1:
0839         break;
0840     default:
0841         ret = lochnagar2_get_gpio_chan(priv, op);
0842         if (ret < 0) {
0843             dev_err(priv->dev, "Failed to get channel for %s: %d\n",
0844                 pin->name, ret);
0845             return ret;
0846         }
0847 
0848         op = ret;
0849         break;
0850     }
0851 
0852     dev_dbg(priv->dev, "Set pin %s to 0x%x\n", pin->name, op);
0853 
0854     ret = regmap_write(priv->lochnagar->regmap, pin->reg, op);
0855     if (ret)
0856         dev_err(priv->dev, "Failed to set %s mux: %d\n",
0857             pin->name, ret);
0858 
0859     return 0;
0860 }
0861 
0862 static int lochnagar_aif_set_mux(struct lochnagar_pin_priv *priv,
0863                  const struct lochnagar_group *group,
0864                  unsigned int op)
0865 {
0866     struct regmap *regmap = priv->lochnagar->regmap;
0867     const struct lochnagar_aif *aif = group->priv;
0868     const struct lochnagar_pin *pin;
0869     int i, ret;
0870 
0871     ret = regmap_update_bits(regmap, aif->src_reg, aif->src_mask, op);
0872     if (ret) {
0873         dev_err(priv->dev, "Failed to set %s source: %d\n",
0874             group->name, ret);
0875         return ret;
0876     }
0877 
0878     ret = regmap_update_bits(regmap, aif->ctrl_reg,
0879                  aif->ena_mask, aif->ena_mask);
0880     if (ret) {
0881         dev_err(priv->dev, "Failed to set %s enable: %d\n",
0882             group->name, ret);
0883         return ret;
0884     }
0885 
0886     for (i = 0; i < group->npins; i++) {
0887         pin = priv->pins[group->pins[i]].drv_data;
0888 
0889         if (pin->type != LN_PTYPE_MUX)
0890             continue;
0891 
0892         dev_dbg(priv->dev, "Set pin %s to AIF\n", pin->name);
0893 
0894         ret = regmap_update_bits(regmap, pin->reg,
0895                      LOCHNAGAR2_GPIO_SRC_MASK,
0896                      LN2_OP_AIF);
0897         if (ret) {
0898             dev_err(priv->dev, "Failed to set %s to AIF: %d\n",
0899                 pin->name, ret);
0900             return ret;
0901         }
0902     }
0903 
0904     return 0;
0905 }
0906 
0907 static int lochnagar_set_mux(struct pinctrl_dev *pctldev,
0908                  unsigned int func_idx, unsigned int group_idx)
0909 {
0910     struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
0911     const struct lochnagar_func *func = &priv->funcs[func_idx];
0912     const struct lochnagar_group *group = &priv->groups[group_idx];
0913     const struct lochnagar_pin *pin;
0914 
0915     switch (func->type) {
0916     case LN_FTYPE_AIF:
0917         dev_dbg(priv->dev, "Set group %s to %s\n",
0918             group->name, func->name);
0919 
0920         return lochnagar_aif_set_mux(priv, group, func->op);
0921     case LN_FTYPE_PIN:
0922         pin = priv->pins[*group->pins].drv_data;
0923 
0924         dev_dbg(priv->dev, "Set pin %s to %s\n", pin->name, func->name);
0925 
0926         return lochnagar_pin_set_mux(priv, pin, func->op);
0927     default:
0928         return -EINVAL;
0929     }
0930 }
0931 
0932 static int lochnagar_gpio_request(struct pinctrl_dev *pctldev,
0933                   struct pinctrl_gpio_range *range,
0934                   unsigned int offset)
0935 {
0936     struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
0937     struct lochnagar *lochnagar = priv->lochnagar;
0938     const struct lochnagar_pin *pin = priv->pins[offset].drv_data;
0939     int ret;
0940 
0941     dev_dbg(priv->dev, "Requesting GPIO %s\n", pin->name);
0942 
0943     if (lochnagar->type == LOCHNAGAR1 || pin->type != LN_PTYPE_MUX)
0944         return 0;
0945 
0946     ret = lochnagar2_get_gpio_chan(priv, LN2_OP_GPIO);
0947     if (ret < 0) {
0948         dev_err(priv->dev, "Failed to get low channel: %d\n", ret);
0949         return ret;
0950     }
0951 
0952     ret = lochnagar2_get_gpio_chan(priv, LN2_OP_GPIO | 0x1);
0953     if (ret < 0) {
0954         dev_err(priv->dev, "Failed to get high channel: %d\n", ret);
0955         return ret;
0956     }
0957 
0958     return 0;
0959 }
0960 
0961 static int lochnagar_gpio_set_direction(struct pinctrl_dev *pctldev,
0962                     struct pinctrl_gpio_range *range,
0963                     unsigned int offset,
0964                     bool input)
0965 {
0966     /* The GPIOs only support output */
0967     if (input)
0968         return -EINVAL;
0969 
0970     return 0;
0971 }
0972 
0973 static const struct pinmux_ops lochnagar_pin_mux_ops = {
0974     .get_functions_count = lochnagar_get_funcs_count,
0975     .get_function_name = lochnagar_get_func_name,
0976     .get_function_groups = lochnagar_get_func_groups,
0977     .set_mux = lochnagar_set_mux,
0978 
0979     .gpio_request_enable = lochnagar_gpio_request,
0980     .gpio_set_direction = lochnagar_gpio_set_direction,
0981 
0982     .strict = true,
0983 };
0984 
0985 static int lochnagar_aif_set_master(struct lochnagar_pin_priv *priv,
0986                     unsigned int group_idx, bool master)
0987 {
0988     struct regmap *regmap = priv->lochnagar->regmap;
0989     const struct lochnagar_group *group = &priv->groups[group_idx];
0990     const struct lochnagar_aif *aif = group->priv;
0991     unsigned int val = 0;
0992     int ret;
0993 
0994     if (group->type != LN_FTYPE_AIF)
0995         return -EINVAL;
0996 
0997     if (!master)
0998         val = aif->master_mask;
0999 
1000     dev_dbg(priv->dev, "Set AIF %s to %s\n",
1001         group->name, master ? "master" : "slave");
1002 
1003     ret = regmap_update_bits(regmap, aif->ctrl_reg, aif->master_mask, val);
1004     if (ret) {
1005         dev_err(priv->dev, "Failed to set %s mode: %d\n",
1006             group->name, ret);
1007         return ret;
1008     }
1009 
1010     return 0;
1011 }
1012 
1013 static int lochnagar_conf_group_set(struct pinctrl_dev *pctldev,
1014                     unsigned int group_idx,
1015                     unsigned long *configs,
1016                     unsigned int num_configs)
1017 {
1018     struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
1019     int i, ret;
1020 
1021     for (i = 0; i < num_configs; i++) {
1022         unsigned int param = pinconf_to_config_param(*configs);
1023 
1024         switch (param) {
1025         case PIN_CONFIG_OUTPUT_ENABLE:
1026             ret = lochnagar_aif_set_master(priv, group_idx, true);
1027             if (ret)
1028                 return ret;
1029             break;
1030         case PIN_CONFIG_INPUT_ENABLE:
1031             ret = lochnagar_aif_set_master(priv, group_idx, false);
1032             if (ret)
1033                 return ret;
1034             break;
1035         default:
1036             return -ENOTSUPP;
1037         }
1038 
1039         configs++;
1040     }
1041 
1042     return 0;
1043 }
1044 
1045 static const struct pinconf_ops lochnagar_pin_conf_ops = {
1046     .pin_config_group_set = lochnagar_conf_group_set,
1047 };
1048 
1049 static const struct pinctrl_desc lochnagar_pin_desc = {
1050     .name = "lochnagar-pinctrl",
1051     .owner = THIS_MODULE,
1052 
1053     .pctlops = &lochnagar_pin_group_ops,
1054     .pmxops = &lochnagar_pin_mux_ops,
1055     .confops = &lochnagar_pin_conf_ops,
1056 };
1057 
1058 static void lochnagar_gpio_set(struct gpio_chip *chip,
1059                    unsigned int offset, int value)
1060 {
1061     struct lochnagar_pin_priv *priv = gpiochip_get_data(chip);
1062     struct lochnagar *lochnagar = priv->lochnagar;
1063     const struct lochnagar_pin *pin = priv->pins[offset].drv_data;
1064     int ret;
1065 
1066     value = !!value;
1067 
1068     dev_dbg(priv->dev, "Set GPIO %s to %s\n",
1069         pin->name, value ? "high" : "low");
1070 
1071     switch (pin->type) {
1072     case LN_PTYPE_MUX:
1073         value |= LN2_OP_GPIO;
1074 
1075         ret = lochnagar_pin_set_mux(priv, pin, value);
1076         break;
1077     case LN_PTYPE_GPIO:
1078         if (pin->invert)
1079             value = !value;
1080 
1081         ret = regmap_update_bits(lochnagar->regmap, pin->reg,
1082                      BIT(pin->shift), value << pin->shift);
1083         break;
1084     default:
1085         ret = -EINVAL;
1086         break;
1087     }
1088 
1089     if (ret < 0)
1090         dev_err(chip->parent, "Failed to set %s value: %d\n",
1091             pin->name, ret);
1092 }
1093 
1094 static int lochnagar_gpio_direction_out(struct gpio_chip *chip,
1095                     unsigned int offset, int value)
1096 {
1097     lochnagar_gpio_set(chip, offset, value);
1098 
1099     return pinctrl_gpio_direction_output(chip->base + offset);
1100 }
1101 
1102 static int lochnagar_fill_func_groups(struct lochnagar_pin_priv *priv)
1103 {
1104     struct lochnagar_func_groups *funcs;
1105     int i;
1106 
1107     for (i = 0; i < priv->ngroups; i++)
1108         priv->func_groups[priv->groups[i].type].ngroups++;
1109 
1110     for (i = 0; i < LN_FTYPE_COUNT; i++) {
1111         funcs = &priv->func_groups[i];
1112 
1113         if (!funcs->ngroups)
1114             continue;
1115 
1116         funcs->groups = devm_kcalloc(priv->dev, funcs->ngroups,
1117                          sizeof(*funcs->groups),
1118                          GFP_KERNEL);
1119         if (!funcs->groups)
1120             return -ENOMEM;
1121 
1122         funcs->ngroups = 0;
1123     }
1124 
1125     for (i = 0; i < priv->ngroups; i++) {
1126         funcs = &priv->func_groups[priv->groups[i].type];
1127 
1128         funcs->groups[funcs->ngroups++] = priv->groups[i].name;
1129     }
1130 
1131     return 0;
1132 }
1133 
1134 static int lochnagar_pin_probe(struct platform_device *pdev)
1135 {
1136     struct lochnagar *lochnagar = dev_get_drvdata(pdev->dev.parent);
1137     struct lochnagar_pin_priv *priv;
1138     struct pinctrl_desc *desc;
1139     struct pinctrl_dev *pctl;
1140     struct device *dev = &pdev->dev;
1141     int ret;
1142 
1143     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1144     if (!priv)
1145         return -ENOMEM;
1146 
1147     priv->dev = dev;
1148     priv->lochnagar = lochnagar;
1149 
1150     desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
1151     if (!desc)
1152         return -ENOMEM;
1153 
1154     *desc = lochnagar_pin_desc;
1155 
1156     priv->gpio_chip.label = dev_name(dev);
1157     priv->gpio_chip.request = gpiochip_generic_request;
1158     priv->gpio_chip.free = gpiochip_generic_free;
1159     priv->gpio_chip.direction_output = lochnagar_gpio_direction_out;
1160     priv->gpio_chip.set = lochnagar_gpio_set;
1161     priv->gpio_chip.can_sleep = true;
1162     priv->gpio_chip.parent = dev;
1163     priv->gpio_chip.base = -1;
1164 
1165     switch (lochnagar->type) {
1166     case LOCHNAGAR1:
1167         priv->funcs = lochnagar1_funcs;
1168         priv->nfuncs = ARRAY_SIZE(lochnagar1_funcs);
1169         priv->pins = lochnagar1_pins;
1170         priv->npins = ARRAY_SIZE(lochnagar1_pins);
1171         priv->groups = lochnagar1_groups;
1172         priv->ngroups = ARRAY_SIZE(lochnagar1_groups);
1173 
1174         priv->gpio_chip.ngpio = LOCHNAGAR1_PIN_NUM_GPIOS;
1175         break;
1176     case LOCHNAGAR2:
1177         priv->funcs = lochnagar2_funcs;
1178         priv->nfuncs = ARRAY_SIZE(lochnagar2_funcs);
1179         priv->pins = lochnagar2_pins;
1180         priv->npins = ARRAY_SIZE(lochnagar2_pins);
1181         priv->groups = lochnagar2_groups;
1182         priv->ngroups = ARRAY_SIZE(lochnagar2_groups);
1183 
1184         priv->gpio_chip.ngpio = LOCHNAGAR2_PIN_NUM_GPIOS;
1185         break;
1186     default:
1187         dev_err(dev, "Unknown Lochnagar type: %d\n", lochnagar->type);
1188         return -EINVAL;
1189     }
1190 
1191     ret = lochnagar_fill_func_groups(priv);
1192     if (ret < 0)
1193         return ret;
1194 
1195     desc->pins = priv->pins;
1196     desc->npins = priv->npins;
1197 
1198     pctl = devm_pinctrl_register(dev, desc, priv);
1199     if (IS_ERR(pctl)) {
1200         ret = PTR_ERR(pctl);
1201         dev_err(priv->dev, "Failed to register pinctrl: %d\n", ret);
1202         return ret;
1203     }
1204 
1205     ret = devm_gpiochip_add_data(dev, &priv->gpio_chip, priv);
1206     if (ret < 0) {
1207         dev_err(&pdev->dev, "Failed to register gpiochip: %d\n", ret);
1208         return ret;
1209     }
1210 
1211     return 0;
1212 }
1213 
1214 static const struct of_device_id lochnagar_of_match[] = {
1215     { .compatible = "cirrus,lochnagar-pinctrl" },
1216     {}
1217 };
1218 MODULE_DEVICE_TABLE(of, lochnagar_of_match);
1219 
1220 static struct platform_driver lochnagar_pin_driver = {
1221     .driver = {
1222         .name = "lochnagar-pinctrl",
1223         .of_match_table = of_match_ptr(lochnagar_of_match),
1224     },
1225 
1226     .probe = lochnagar_pin_probe,
1227 };
1228 module_platform_driver(lochnagar_pin_driver);
1229 
1230 MODULE_AUTHOR("Charles Keepax <ckeepax@opensource.cirrus.com>");
1231 MODULE_DESCRIPTION("Pinctrl driver for Cirrus Logic Lochnagar Board");
1232 MODULE_LICENSE("GPL v2");
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