pinctrl/bcm/pinctrl-nsp-mux.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /* Copyright (C) 2015 Broadcom Corporation
0003  *
0004  * This file contains the Northstar plus (NSP) IOMUX driver that supports
0005  * group based PINMUX configuration. The Northstar plus IOMUX controller
0006  * allows pins to be individually muxed to GPIO function. The NAND and MMC is
0007  * a group based selection. The gpio_a 8 - 11 are muxed with gpio_b and pwm.
0008  * To select PWM, one need to enable the corresponding gpio_b as well.
0009  *
0010  *              gpio_a (8 - 11)
0011  *              +----------
0012  *              |
0013  *      gpio_a (8-11)   |   gpio_b (0 - 3)
0014  *  ------------------------+-------+----------
0015  *                  |
0016  *                  |   pwm (0 - 3)
0017  *                  +----------
0018  */
0019
0020 #include <linux/err.h>
0021 #include <linux/io.h>
0022 #include <linux/of.h>
0023 #include <linux/pinctrl/pinconf.h>
0024 #include <linux/pinctrl/pinconf-generic.h>
0025 #include <linux/pinctrl/pinctrl.h>
0026 #include <linux/pinctrl/pinmux.h>
0027 #include <linux/platform_device.h>
0028 #include <linux/slab.h>
0029
0030 #include "../core.h"
0031 #include "../pinctrl-utils.h"
0032
0033 #define NSP_MUX_BASE0   0x00
0034 #define NSP_MUX_BASE1   0x01
0035 #define NSP_MUX_BASE2   0x02
0036 /*
0037  * nsp IOMUX register description
0038  *
0039  * @base: base 0 or base 1
0040  * @shift: bit shift for mux configuration of a group
0041  * @mask: bit mask of the function
0042  * @alt: alternate function to set to
0043  */
0044 struct nsp_mux {
0045     unsigned int base;
0046     unsigned int shift;
0047     unsigned int mask;
0048     unsigned int alt;
0049 };
0050
0051 /*
0052  * Keep track of nsp IOMUX configuration and prevent double configuration
0053  *
0054  * @nsp_mux: nsp IOMUX register description
0055  * @is_configured: flag to indicate whether a mux setting has already been
0056  * configured
0057  */
0058 struct nsp_mux_log {
0059     struct nsp_mux mux;
0060     bool is_configured;
0061 };
0062
0063 /*
0064  * Group based IOMUX configuration
0065  *
0066  * @name: name of the group
0067  * @pins: array of pins used by this group
0068  * @num_pins: total number of pins used by this group
0069  * @mux: nsp group based IOMUX configuration
0070  */
0071 struct nsp_pin_group {
0072     const char *name;
0073     const unsigned int *pins;
0074     const unsigned int num_pins;
0075     const struct nsp_mux mux;
0076 };
0077
0078 /*
0079  * nsp mux function and supported pin groups
0080  *
0081  * @name: name of the function
0082  * @groups: array of groups that can be supported by this function
0083  * @num_groups: total number of groups that can be supported by this function
0084  */
0085 struct nsp_pin_function {
0086     const char *name;
0087     const char * const *groups;
0088     const unsigned int num_groups;
0089 };
0090
0091 /*
0092  * nsp IOMUX pinctrl core
0093  *
0094  * @pctl: pointer to pinctrl_dev
0095  * @dev: pointer to device
0096  * @base0: first mux register
0097  * @base1: second mux register
0098  * @base2: third mux register
0099  * @groups: pointer to array of groups
0100  * @num_groups: total number of groups
0101  * @functions: pointer to array of functions
0102  * @num_functions: total number of functions
0103  * @mux_log: pointer to the array of mux logs
0104  * @lock: lock to protect register access
0105  */
0106 struct nsp_pinctrl {
0107     struct pinctrl_dev *pctl;
0108     struct device *dev;
0109     void __iomem *base0;
0110     void __iomem *base1;
0111     void __iomem *base2;
0112     const struct nsp_pin_group *groups;
0113     unsigned int num_groups;
0114     const struct nsp_pin_function *functions;
0115     unsigned int num_functions;
0116     struct nsp_mux_log *mux_log;
0117     spinlock_t lock;
0118 };
0119
0120 /*
0121  * Description of a pin in nsp
0122  *
0123  * @pin: pin number
0124  * @name: pin name
0125  * @gpio_select: reg data to select GPIO
0126  */
0127 struct nsp_pin {
0128     unsigned int pin;
0129     char *name;
0130     unsigned int gpio_select;
0131 };
0132
0133 #define NSP_PIN_DESC(p, n, g)       \
0134 {                   \
0135     .pin = p,           \
0136     .name = n,          \
0137     .gpio_select = g,       \
0138 }
0139
0140 /*
0141  * List of muxable pins in nsp
0142  */
0143 static struct nsp_pin nsp_pins[] = {
0144     NSP_PIN_DESC(0, "spi_clk", 1),
0145     NSP_PIN_DESC(1, "spi_ss", 1),
0146     NSP_PIN_DESC(2, "spi_mosi", 1),
0147     NSP_PIN_DESC(3, "spi_miso", 1),
0148     NSP_PIN_DESC(4, "scl", 1),
0149     NSP_PIN_DESC(5, "sda", 1),
0150     NSP_PIN_DESC(6, "mdc", 1),
0151     NSP_PIN_DESC(7, "mdio", 1),
0152     NSP_PIN_DESC(8, "pwm0", 1),
0153     NSP_PIN_DESC(9, "pwm1", 1),
0154     NSP_PIN_DESC(10, "pwm2", 1),
0155     NSP_PIN_DESC(11, "pwm3", 1),
0156     NSP_PIN_DESC(12, "uart1_rx", 1),
0157     NSP_PIN_DESC(13, "uart1_tx", 1),
0158     NSP_PIN_DESC(14, "uart1_cts", 1),
0159     NSP_PIN_DESC(15, "uart1_rts", 1),
0160     NSP_PIN_DESC(16, "uart2_rx", 1),
0161     NSP_PIN_DESC(17, "uart2_tx", 1),
0162     NSP_PIN_DESC(18, "synce", 0),
0163     NSP_PIN_DESC(19, "sata0_led", 0),
0164     NSP_PIN_DESC(20, "sata1_led", 0),
0165     NSP_PIN_DESC(21, "xtal_out", 1),
0166     NSP_PIN_DESC(22, "sdio_pwr", 1),
0167     NSP_PIN_DESC(23, "sdio_en_1p8v", 1),
0168     NSP_PIN_DESC(24, "gpio_24", 1),
0169     NSP_PIN_DESC(25, "gpio_25", 1),
0170     NSP_PIN_DESC(26, "p5_led0", 0),
0171     NSP_PIN_DESC(27, "p5_led1", 0),
0172     NSP_PIN_DESC(28, "gpio_28", 1),
0173     NSP_PIN_DESC(29, "gpio_29", 1),
0174     NSP_PIN_DESC(30, "gpio_30", 1),
0175     NSP_PIN_DESC(31, "gpio_31", 1),
0176     NSP_PIN_DESC(32, "nand_ale", 0),
0177     NSP_PIN_DESC(33, "nand_ce0", 0),
0178     NSP_PIN_DESC(34, "nand_r/b", 0),
0179     NSP_PIN_DESC(35, "nand_dq0", 0),
0180     NSP_PIN_DESC(36, "nand_dq1", 0),
0181     NSP_PIN_DESC(37, "nand_dq2", 0),
0182     NSP_PIN_DESC(38, "nand_dq3", 0),
0183     NSP_PIN_DESC(39, "nand_dq4", 0),
0184     NSP_PIN_DESC(40, "nand_dq5", 0),
0185     NSP_PIN_DESC(41, "nand_dq6", 0),
0186     NSP_PIN_DESC(42, "nand_dq7", 0),
0187 };
0188
0189 /*
0190  * List of groups of pins
0191  */
0192
0193 static const unsigned int spi_pins[] = {0, 1, 2, 3};
0194 static const unsigned int i2c_pins[] = {4, 5};
0195 static const unsigned int mdio_pins[] = {6, 7};
0196 static const unsigned int pwm0_pins[] = {8};
0197 static const unsigned int gpio_b_0_pins[] = {8};
0198 static const unsigned int pwm1_pins[] = {9};
0199 static const unsigned int gpio_b_1_pins[] = {9};
0200 static const unsigned int pwm2_pins[] = {10};
0201 static const unsigned int gpio_b_2_pins[] = {10};
0202 static const unsigned int pwm3_pins[] = {11};
0203 static const unsigned int gpio_b_3_pins[] = {11};
0204 static const unsigned int uart1_pins[] = {12, 13, 14, 15};
0205 static const unsigned int uart2_pins[] = {16, 17};
0206 static const unsigned int synce_pins[] = {18};
0207 static const unsigned int sata0_led_pins[] = {19};
0208 static const unsigned int sata1_led_pins[] = {20};
0209 static const unsigned int xtal_out_pins[] = {21};
0210 static const unsigned int sdio_pwr_pins[] = {22};
0211 static const unsigned int sdio_1p8v_pins[] = {23};
0212 static const unsigned int switch_p05_led0_pins[] = {26};
0213 static const unsigned int switch_p05_led1_pins[] = {27};
0214 static const unsigned int nand_pins[] = {32, 33, 34, 35, 36, 37, 38, 39,
0215                             40, 41, 42};
0216 static const unsigned int emmc_pins[] = {32, 33, 34, 35, 36, 37, 38, 39,
0217                             40, 41, 42};
0218
0219 #define NSP_PIN_GROUP(group_name, ba, sh, ma, al)   \
0220 {                           \
0221     .name = __stringify(group_name) "_grp",     \
0222     .pins = group_name ## _pins,            \
0223     .num_pins = ARRAY_SIZE(group_name ## _pins),    \
0224     .mux = {                    \
0225         .base = ba,             \
0226         .shift = sh,                \
0227         .mask = ma,             \
0228         .alt = al,              \
0229     }                       \
0230 }
0231
0232 /*
0233  * List of nsp pin groups
0234  */
0235 static const struct nsp_pin_group nsp_pin_groups[] = {
0236     NSP_PIN_GROUP(spi, NSP_MUX_BASE0, 0, 0x0f, 0x00),
0237     NSP_PIN_GROUP(i2c, NSP_MUX_BASE0, 3, 0x03, 0x00),
0238     NSP_PIN_GROUP(mdio, NSP_MUX_BASE0, 5, 0x03, 0x00),
0239     NSP_PIN_GROUP(gpio_b_0, NSP_MUX_BASE0, 7, 0x01, 0x00),
0240     NSP_PIN_GROUP(pwm0, NSP_MUX_BASE1, 0, 0x01, 0x01),
0241     NSP_PIN_GROUP(gpio_b_1, NSP_MUX_BASE0, 8, 0x01, 0x00),
0242     NSP_PIN_GROUP(pwm1, NSP_MUX_BASE1, 1, 0x01, 0x01),
0243     NSP_PIN_GROUP(gpio_b_2, NSP_MUX_BASE0, 9, 0x01, 0x00),
0244     NSP_PIN_GROUP(pwm2, NSP_MUX_BASE1, 2, 0x01, 0x01),
0245     NSP_PIN_GROUP(gpio_b_3, NSP_MUX_BASE0, 10, 0x01, 0x00),
0246     NSP_PIN_GROUP(pwm3, NSP_MUX_BASE1, 3, 0x01, 0x01),
0247     NSP_PIN_GROUP(uart1, NSP_MUX_BASE0, 11, 0x0f, 0x00),
0248     NSP_PIN_GROUP(uart2, NSP_MUX_BASE0, 15, 0x03, 0x00),
0249     NSP_PIN_GROUP(synce, NSP_MUX_BASE0, 17, 0x01, 0x01),
0250     NSP_PIN_GROUP(sata0_led, NSP_MUX_BASE0, 18, 0x01, 0x01),
0251     NSP_PIN_GROUP(sata1_led, NSP_MUX_BASE0, 19, 0x01, 0x01),
0252     NSP_PIN_GROUP(xtal_out, NSP_MUX_BASE0, 20, 0x01, 0x00),
0253     NSP_PIN_GROUP(sdio_pwr, NSP_MUX_BASE0, 21, 0x01, 0x00),
0254     NSP_PIN_GROUP(sdio_1p8v, NSP_MUX_BASE0, 22, 0x01, 0x00),
0255     NSP_PIN_GROUP(switch_p05_led0, NSP_MUX_BASE0, 26, 0x01, 0x01),
0256     NSP_PIN_GROUP(switch_p05_led1, NSP_MUX_BASE0, 27, 0x01, 0x01),
0257     NSP_PIN_GROUP(nand, NSP_MUX_BASE2, 0, 0x01, 0x00),
0258     NSP_PIN_GROUP(emmc, NSP_MUX_BASE2, 0, 0x01, 0x01)
0259 };
0260
0261 /*
0262  * List of groups supported by functions
0263  */
0264
0265 static const char * const spi_grps[] = {"spi_grp"};
0266 static const char * const i2c_grps[] = {"i2c_grp"};
0267 static const char * const mdio_grps[] = {"mdio_grp"};
0268 static const char * const pwm_grps[] = {"pwm0_grp", "pwm1_grp", "pwm2_grp"
0269                         , "pwm3_grp"};
0270 static const char * const gpio_b_grps[] = {"gpio_b_0_grp", "gpio_b_1_grp",
0271                     "gpio_b_2_grp", "gpio_b_3_grp"};
0272 static const char * const uart1_grps[] = {"uart1_grp"};
0273 static const char * const uart2_grps[] = {"uart2_grp"};
0274 static const char * const synce_grps[] = {"synce_grp"};
0275 static const char * const sata_led_grps[] = {"sata0_led_grp", "sata1_led_grp"};
0276 static const char * const xtal_out_grps[] = {"xtal_out_grp"};
0277 static const char * const sdio_grps[] = {"sdio_pwr_grp", "sdio_1p8v_grp"};
0278 static const char * const switch_led_grps[] = {"switch_p05_led0_grp",
0279                         "switch_p05_led1_grp"};
0280 static const char * const nand_grps[] = {"nand_grp"};
0281 static const char * const emmc_grps[] = {"emmc_grp"};
0282
0283 #define NSP_PIN_FUNCTION(func)              \
0284 {                           \
0285     .name = #func,                  \
0286     .groups = func ## _grps,            \
0287     .num_groups = ARRAY_SIZE(func ## _grps),    \
0288 }
0289
0290 /*
0291  * List of supported functions in nsp
0292  */
0293 static const struct nsp_pin_function nsp_pin_functions[] = {
0294     NSP_PIN_FUNCTION(spi),
0295     NSP_PIN_FUNCTION(i2c),
0296     NSP_PIN_FUNCTION(mdio),
0297     NSP_PIN_FUNCTION(pwm),
0298     NSP_PIN_FUNCTION(gpio_b),
0299     NSP_PIN_FUNCTION(uart1),
0300     NSP_PIN_FUNCTION(uart2),
0301     NSP_PIN_FUNCTION(synce),
0302     NSP_PIN_FUNCTION(sata_led),
0303     NSP_PIN_FUNCTION(xtal_out),
0304     NSP_PIN_FUNCTION(sdio),
0305     NSP_PIN_FUNCTION(switch_led),
0306     NSP_PIN_FUNCTION(nand),
0307     NSP_PIN_FUNCTION(emmc)
0308 };
0309
0310 static int nsp_get_groups_count(struct pinctrl_dev *pctrl_dev)
0311 {
0312     struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
0313
0314     return pinctrl->num_groups;
0315 }
0316
0317 static const char *nsp_get_group_name(struct pinctrl_dev *pctrl_dev,
0318                       unsigned int selector)
0319 {
0320     struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
0321
0322     return pinctrl->groups[selector].name;
0323 }
0324
0325 static int nsp_get_group_pins(struct pinctrl_dev *pctrl_dev,
0326                   unsigned int selector, const unsigned int **pins,
0327                   unsigned int *num_pins)
0328 {
0329     struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
0330
0331     *pins = pinctrl->groups[selector].pins;
0332     *num_pins = pinctrl->groups[selector].num_pins;
0333
0334     return 0;
0335 }
0336
0337 static void nsp_pin_dbg_show(struct pinctrl_dev *pctrl_dev,
0338                  struct seq_file *s, unsigned int offset)
0339 {
0340     seq_printf(s, " %s", dev_name(pctrl_dev->dev));
0341 }
0342
0343 static const struct pinctrl_ops nsp_pinctrl_ops = {
0344     .get_groups_count = nsp_get_groups_count,
0345     .get_group_name = nsp_get_group_name,
0346     .get_group_pins = nsp_get_group_pins,
0347     .pin_dbg_show = nsp_pin_dbg_show,
0348     .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
0349     .dt_free_map = pinctrl_utils_free_map,
0350 };
0351
0352 static int nsp_get_functions_count(struct pinctrl_dev *pctrl_dev)
0353 {
0354     struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
0355
0356     return pinctrl->num_functions;
0357 }
0358
0359 static const char *nsp_get_function_name(struct pinctrl_dev *pctrl_dev,
0360                      unsigned int selector)
0361 {
0362     struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
0363
0364     return pinctrl->functions[selector].name;
0365 }
0366
0367 static int nsp_get_function_groups(struct pinctrl_dev *pctrl_dev,
0368                    unsigned int selector,
0369                    const char * const **groups,
0370                    unsigned * const num_groups)
0371 {
0372     struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
0373
0374     *groups = pinctrl->functions[selector].groups;
0375     *num_groups = pinctrl->functions[selector].num_groups;
0376
0377     return 0;
0378 }
0379
0380 static int nsp_pinmux_set(struct nsp_pinctrl *pinctrl,
0381               const struct nsp_pin_function *func,
0382               const struct nsp_pin_group *grp,
0383               struct nsp_mux_log *mux_log)
0384 {
0385     const struct nsp_mux *mux = &grp->mux;
0386     int i;
0387     u32 val, mask;
0388     unsigned long flags;
0389     void __iomem *base_address;
0390
0391     for (i = 0; i < pinctrl->num_groups; i++) {
0392         if ((mux->shift != mux_log[i].mux.shift) ||
0393             (mux->base != mux_log[i].mux.base))
0394             continue;
0395
0396         /* if this is a new configuration, just do it! */
0397         if (!mux_log[i].is_configured)
0398             break;
0399
0400         /*
0401          * IOMUX has been configured previously and one is trying to
0402          * configure it to a different function
0403          */
0404         if (mux_log[i].mux.alt != mux->alt) {
0405             dev_err(pinctrl->dev,
0406                 "double configuration error detected!\n");
0407             dev_err(pinctrl->dev, "func:%s grp:%s\n",
0408                 func->name, grp->name);
0409             return -EINVAL;
0410         }
0411
0412         return 0;
0413     }
0414     if (i == pinctrl->num_groups)
0415         return -EINVAL;
0416
0417     mask = mux->mask;
0418     mux_log[i].mux.alt = mux->alt;
0419     mux_log[i].is_configured = true;
0420
0421     switch (mux->base) {
0422     case NSP_MUX_BASE0:
0423         base_address = pinctrl->base0;
0424         break;
0425
0426     case NSP_MUX_BASE1:
0427         base_address = pinctrl->base1;
0428         break;
0429
0430     case NSP_MUX_BASE2:
0431         base_address = pinctrl->base2;
0432         break;
0433
0434     default:
0435         return -EINVAL;
0436     }
0437
0438     spin_lock_irqsave(&pinctrl->lock, flags);
0439     val = readl(base_address);
0440     val &= ~(mask << grp->mux.shift);
0441     val |= grp->mux.alt << grp->mux.shift;
0442     writel(val, base_address);
0443     spin_unlock_irqrestore(&pinctrl->lock, flags);
0444
0445     return 0;
0446 }
0447
0448 static int nsp_pinmux_enable(struct pinctrl_dev *pctrl_dev,
0449                  unsigned int func_select, unsigned int grp_select)
0450 {
0451     struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
0452     const struct nsp_pin_function *func;
0453     const struct nsp_pin_group *grp;
0454
0455     if (grp_select >= pinctrl->num_groups ||
0456         func_select >= pinctrl->num_functions)
0457         return -EINVAL;
0458
0459     func = &pinctrl->functions[func_select];
0460     grp = &pinctrl->groups[grp_select];
0461
0462     dev_dbg(pctrl_dev->dev, "func:%u name:%s grp:%u name:%s\n",
0463         func_select, func->name, grp_select, grp->name);
0464
0465     dev_dbg(pctrl_dev->dev, "shift:%u alt:%u\n", grp->mux.shift,
0466         grp->mux.alt);
0467
0468     return nsp_pinmux_set(pinctrl, func, grp, pinctrl->mux_log);
0469 }
0470
0471
0472 static int nsp_gpio_request_enable(struct pinctrl_dev *pctrl_dev,
0473                    struct pinctrl_gpio_range *range,
0474                    unsigned int pin)
0475 {
0476     struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
0477     u32 *gpio_select = pctrl_dev->desc->pins[pin].drv_data;
0478     u32 val;
0479     unsigned long flags;
0480
0481     spin_lock_irqsave(&pinctrl->lock, flags);
0482     val = readl(pinctrl->base0);
0483     if ((val & BIT(pin)) != (*gpio_select << pin)) {
0484         val &= ~BIT(pin);
0485         val |= *gpio_select << pin;
0486         writel(val, pinctrl->base0);
0487     }
0488     spin_unlock_irqrestore(&pinctrl->lock, flags);
0489
0490     return 0;
0491 }
0492
0493 static void nsp_gpio_disable_free(struct pinctrl_dev *pctrl_dev,
0494                   struct pinctrl_gpio_range *range,
0495                   unsigned int pin)
0496 {
0497     struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
0498     u32 *gpio_select = pctrl_dev->desc->pins[pin].drv_data;
0499     u32 val;
0500     unsigned long flags;
0501
0502     spin_lock_irqsave(&pinctrl->lock, flags);
0503     val = readl(pinctrl->base0);
0504     if ((val & (1 << pin)) == (*gpio_select << pin)) {
0505         val &= ~(1 << pin);
0506         if (!(*gpio_select))
0507             val |= (1 << pin);
0508         writel(val, pinctrl->base0);
0509     }
0510     spin_unlock_irqrestore(&pinctrl->lock, flags);
0511 }
0512
0513 static const struct pinmux_ops nsp_pinmux_ops = {
0514     .get_functions_count = nsp_get_functions_count,
0515     .get_function_name = nsp_get_function_name,
0516     .get_function_groups = nsp_get_function_groups,
0517     .set_mux = nsp_pinmux_enable,
0518     .gpio_request_enable = nsp_gpio_request_enable,
0519     .gpio_disable_free = nsp_gpio_disable_free,
0520 };
0521
0522 static struct pinctrl_desc nsp_pinctrl_desc = {
0523     .name = "nsp-pinmux",
0524     .pctlops = &nsp_pinctrl_ops,
0525     .pmxops = &nsp_pinmux_ops,
0526 };
0527
0528 static int nsp_mux_log_init(struct nsp_pinctrl *pinctrl)
0529 {
0530     struct nsp_mux_log *log;
0531     unsigned int i;
0532     u32 no_of_groups = ARRAY_SIZE(nsp_pin_groups);
0533
0534     pinctrl->mux_log = devm_kcalloc(pinctrl->dev, no_of_groups,
0535                     sizeof(struct nsp_mux_log),
0536                     GFP_KERNEL);
0537     if (!pinctrl->mux_log)
0538         return -ENOMEM;
0539
0540     for (i = 0; i < no_of_groups; i++) {
0541         log = &pinctrl->mux_log[i];
0542         log->mux.base = nsp_pin_groups[i].mux.base;
0543         log->mux.shift = nsp_pin_groups[i].mux.shift;
0544         log->mux.alt = 0;
0545         log->is_configured = false;
0546     }
0547
0548     return 0;
0549 }
0550
0551 static int nsp_pinmux_probe(struct platform_device *pdev)
0552 {
0553     struct nsp_pinctrl *pinctrl;
0554     struct resource *res;
0555     int i, ret;
0556     struct pinctrl_pin_desc *pins;
0557     unsigned int num_pins = ARRAY_SIZE(nsp_pins);
0558
0559     pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);
0560     if (!pinctrl)
0561         return -ENOMEM;
0562     pinctrl->dev = &pdev->dev;
0563     platform_set_drvdata(pdev, pinctrl);
0564     spin_lock_init(&pinctrl->lock);
0565
0566     pinctrl->base0 = devm_platform_ioremap_resource(pdev, 0);
0567     if (IS_ERR(pinctrl->base0))
0568         return PTR_ERR(pinctrl->base0);
0569
0570     res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
0571     if (!res)
0572         return -EINVAL;
0573     pinctrl->base1 = devm_ioremap(&pdev->dev, res->start,
0574                           resource_size(res));
0575     if (!pinctrl->base1) {
0576         dev_err(&pdev->dev, "unable to map I/O space\n");
0577         return -ENOMEM;
0578     }
0579
0580     pinctrl->base2 = devm_platform_ioremap_resource(pdev, 2);
0581     if (IS_ERR(pinctrl->base2))
0582         return PTR_ERR(pinctrl->base2);
0583
0584     ret = nsp_mux_log_init(pinctrl);
0585     if (ret) {
0586         dev_err(&pdev->dev, "unable to initialize IOMUX log\n");
0587         return ret;
0588     }
0589
0590     pins = devm_kcalloc(&pdev->dev, num_pins, sizeof(*pins), GFP_KERNEL);
0591     if (!pins)
0592         return -ENOMEM;
0593
0594     for (i = 0; i < num_pins; i++) {
0595         pins[i].number = nsp_pins[i].pin;
0596         pins[i].name = nsp_pins[i].name;
0597         pins[i].drv_data = &nsp_pins[i].gpio_select;
0598     }
0599
0600     pinctrl->groups = nsp_pin_groups;
0601     pinctrl->num_groups = ARRAY_SIZE(nsp_pin_groups);
0602     pinctrl->functions = nsp_pin_functions;
0603     pinctrl->num_functions = ARRAY_SIZE(nsp_pin_functions);
0604     nsp_pinctrl_desc.pins = pins;
0605     nsp_pinctrl_desc.npins = num_pins;
0606
0607     pinctrl->pctl = devm_pinctrl_register(&pdev->dev, &nsp_pinctrl_desc,
0608                      pinctrl);
0609     if (IS_ERR(pinctrl->pctl)) {
0610         dev_err(&pdev->dev, "unable to register nsp IOMUX pinctrl\n");
0611         return PTR_ERR(pinctrl->pctl);
0612     }
0613
0614     return 0;
0615 }
0616
0617 static const struct of_device_id nsp_pinmux_of_match[] = {
0618     { .compatible = "brcm,nsp-pinmux" },
0619     { }
0620 };
0621
0622 static struct platform_driver nsp_pinmux_driver = {
0623     .driver = {
0624         .name = "nsp-pinmux",
0625         .of_match_table = nsp_pinmux_of_match,
0626     },
0627     .probe = nsp_pinmux_probe,
0628 };
0629
0630 static int __init nsp_pinmux_init(void)
0631 {
0632     return platform_driver_register(&nsp_pinmux_driver);
0633 }
0634 arch_initcall(nsp_pinmux_init);