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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 // Copyright (C) 2014-2017 Broadcom
0003 
0004 /*
0005  * This file contains the Broadcom Northstar Plus (NSP) GPIO driver that
0006  * supports the chipCommonA GPIO controller. Basic PINCONF such as bias,
0007  * pull up/down, slew and drive strength are also supported in this driver.
0008  *
0009  * Pins from the chipCommonA  GPIO can be individually muxed to GPIO function,
0010  * through the interaction with the NSP IOMUX controller.
0011  */
0012 
0013 #include <linux/gpio/driver.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/io.h>
0016 #include <linux/ioport.h>
0017 #include <linux/kernel.h>
0018 #include <linux/of_address.h>
0019 #include <linux/of_device.h>
0020 #include <linux/of_irq.h>
0021 #include <linux/pinctrl/pinconf.h>
0022 #include <linux/pinctrl/pinconf-generic.h>
0023 #include <linux/pinctrl/pinctrl.h>
0024 #include <linux/slab.h>
0025 
0026 #include "../pinctrl-utils.h"
0027 
0028 #define NSP_CHIP_A_INT_STATUS       0x00
0029 #define NSP_CHIP_A_INT_MASK     0x04
0030 #define NSP_GPIO_DATA_IN        0x40
0031 #define NSP_GPIO_DATA_OUT       0x44
0032 #define NSP_GPIO_OUT_EN         0x48
0033 #define NSP_GPIO_INT_POLARITY       0x50
0034 #define NSP_GPIO_INT_MASK       0x54
0035 #define NSP_GPIO_EVENT          0x58
0036 #define NSP_GPIO_EVENT_INT_MASK     0x5c
0037 #define NSP_GPIO_EVENT_INT_POLARITY 0x64
0038 #define NSP_CHIP_A_GPIO_INT_BIT     0x01
0039 
0040 /* I/O parameters offset for chipcommon A GPIO */
0041 #define NSP_GPIO_DRV_CTRL       0x00
0042 #define NSP_GPIO_HYSTERESIS_EN      0x10
0043 #define NSP_GPIO_SLEW_RATE_EN       0x14
0044 #define NSP_PULL_UP_EN          0x18
0045 #define NSP_PULL_DOWN_EN        0x1c
0046 #define GPIO_DRV_STRENGTH_BITS      0x03
0047 
0048 /*
0049  * nsp GPIO core
0050  *
0051  * @dev: pointer to device
0052  * @base: I/O register base for nsp GPIO controller
0053  * @io_ctrl: I/O register base for PINCONF support outside the GPIO block
0054  * @gc: GPIO chip
0055  * @pctl: pointer to pinctrl_dev
0056  * @pctldesc: pinctrl descriptor
0057  * @lock: lock to protect access to I/O registers
0058  */
0059 struct nsp_gpio {
0060     struct device *dev;
0061     void __iomem *base;
0062     void __iomem *io_ctrl;
0063     struct irq_chip irqchip;
0064     struct gpio_chip gc;
0065     struct pinctrl_dev *pctl;
0066     struct pinctrl_desc pctldesc;
0067     raw_spinlock_t lock;
0068 };
0069 
0070 enum base_type {
0071     REG,
0072     IO_CTRL
0073 };
0074 
0075 /*
0076  * Mapping from PINCONF pins to GPIO pins is 1-to-1
0077  */
0078 static inline unsigned nsp_pin_to_gpio(unsigned pin)
0079 {
0080     return pin;
0081 }
0082 
0083 /*
0084  *  nsp_set_bit - set or clear one bit (corresponding to the GPIO pin) in a
0085  *  nsp GPIO register
0086  *
0087  *  @nsp_gpio: nsp GPIO device
0088  *  @base_type: reg base to modify
0089  *  @reg: register offset
0090  *  @gpio: GPIO pin
0091  *  @set: set or clear
0092  */
0093 static inline void nsp_set_bit(struct nsp_gpio *chip, enum base_type address,
0094                    unsigned int reg, unsigned gpio, bool set)
0095 {
0096     u32 val;
0097     void __iomem *base_address;
0098 
0099     if (address == IO_CTRL)
0100         base_address = chip->io_ctrl;
0101     else
0102         base_address = chip->base;
0103 
0104     val = readl(base_address + reg);
0105     if (set)
0106         val |= BIT(gpio);
0107     else
0108         val &= ~BIT(gpio);
0109 
0110     writel(val, base_address + reg);
0111 }
0112 
0113 /*
0114  *  nsp_get_bit - get one bit (corresponding to the GPIO pin) in a
0115  *  nsp GPIO register
0116  */
0117 static inline bool nsp_get_bit(struct nsp_gpio *chip, enum base_type address,
0118                    unsigned int reg, unsigned gpio)
0119 {
0120     if (address == IO_CTRL)
0121         return !!(readl(chip->io_ctrl + reg) & BIT(gpio));
0122     else
0123         return !!(readl(chip->base + reg) & BIT(gpio));
0124 }
0125 
0126 static irqreturn_t nsp_gpio_irq_handler(int irq, void *data)
0127 {
0128     struct gpio_chip *gc = (struct gpio_chip *)data;
0129     struct nsp_gpio *chip = gpiochip_get_data(gc);
0130     int bit;
0131     unsigned long int_bits = 0;
0132     u32 int_status;
0133 
0134     /* go through the entire GPIOs and handle all interrupts */
0135     int_status = readl(chip->base + NSP_CHIP_A_INT_STATUS);
0136     if (int_status & NSP_CHIP_A_GPIO_INT_BIT) {
0137         unsigned int event, level;
0138 
0139         /* Get level and edge interrupts */
0140         event = readl(chip->base + NSP_GPIO_EVENT_INT_MASK) &
0141                   readl(chip->base + NSP_GPIO_EVENT);
0142         level = readl(chip->base + NSP_GPIO_DATA_IN) ^
0143                   readl(chip->base + NSP_GPIO_INT_POLARITY);
0144         level &= readl(chip->base + NSP_GPIO_INT_MASK);
0145         int_bits = level | event;
0146 
0147         for_each_set_bit(bit, &int_bits, gc->ngpio)
0148             generic_handle_domain_irq(gc->irq.domain, bit);
0149     }
0150 
0151     return  int_bits ? IRQ_HANDLED : IRQ_NONE;
0152 }
0153 
0154 static void nsp_gpio_irq_ack(struct irq_data *d)
0155 {
0156     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0157     struct nsp_gpio *chip = gpiochip_get_data(gc);
0158     unsigned gpio = d->hwirq;
0159     u32 val = BIT(gpio);
0160     u32 trigger_type;
0161 
0162     trigger_type = irq_get_trigger_type(d->irq);
0163     if (trigger_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
0164         writel(val, chip->base + NSP_GPIO_EVENT);
0165 }
0166 
0167 /*
0168  *  nsp_gpio_irq_set_mask - mask/unmask a GPIO interrupt
0169  *
0170  *  @d: IRQ chip data
0171  *  @unmask: mask/unmask GPIO interrupt
0172  */
0173 static void nsp_gpio_irq_set_mask(struct irq_data *d, bool unmask)
0174 {
0175     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0176     struct nsp_gpio *chip = gpiochip_get_data(gc);
0177     unsigned gpio = d->hwirq;
0178     u32 trigger_type;
0179 
0180     trigger_type = irq_get_trigger_type(d->irq);
0181     if (trigger_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
0182         nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_MASK, gpio, unmask);
0183     else
0184         nsp_set_bit(chip, REG, NSP_GPIO_INT_MASK, gpio, unmask);
0185 }
0186 
0187 static void nsp_gpio_irq_mask(struct irq_data *d)
0188 {
0189     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0190     struct nsp_gpio *chip = gpiochip_get_data(gc);
0191     unsigned long flags;
0192 
0193     raw_spin_lock_irqsave(&chip->lock, flags);
0194     nsp_gpio_irq_set_mask(d, false);
0195     raw_spin_unlock_irqrestore(&chip->lock, flags);
0196 }
0197 
0198 static void nsp_gpio_irq_unmask(struct irq_data *d)
0199 {
0200     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0201     struct nsp_gpio *chip = gpiochip_get_data(gc);
0202     unsigned long flags;
0203 
0204     raw_spin_lock_irqsave(&chip->lock, flags);
0205     nsp_gpio_irq_set_mask(d, true);
0206     raw_spin_unlock_irqrestore(&chip->lock, flags);
0207 }
0208 
0209 static int nsp_gpio_irq_set_type(struct irq_data *d, unsigned int type)
0210 {
0211     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0212     struct nsp_gpio *chip = gpiochip_get_data(gc);
0213     unsigned gpio = d->hwirq;
0214     bool level_low;
0215     bool falling;
0216     unsigned long flags;
0217 
0218     raw_spin_lock_irqsave(&chip->lock, flags);
0219     falling = nsp_get_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio);
0220     level_low = nsp_get_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio);
0221 
0222     switch (type & IRQ_TYPE_SENSE_MASK) {
0223     case IRQ_TYPE_EDGE_RISING:
0224         falling = false;
0225         break;
0226 
0227     case IRQ_TYPE_EDGE_FALLING:
0228         falling = true;
0229         break;
0230 
0231     case IRQ_TYPE_LEVEL_HIGH:
0232         level_low = false;
0233         break;
0234 
0235     case IRQ_TYPE_LEVEL_LOW:
0236         level_low = true;
0237         break;
0238 
0239     default:
0240         dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n",
0241             type);
0242         raw_spin_unlock_irqrestore(&chip->lock, flags);
0243         return -EINVAL;
0244     }
0245 
0246     nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio, falling);
0247     nsp_set_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio, level_low);
0248 
0249     if (type & IRQ_TYPE_EDGE_BOTH)
0250         irq_set_handler_locked(d, handle_edge_irq);
0251     else
0252         irq_set_handler_locked(d, handle_level_irq);
0253 
0254     raw_spin_unlock_irqrestore(&chip->lock, flags);
0255 
0256     dev_dbg(chip->dev, "gpio:%u level_low:%s falling:%s\n", gpio,
0257         level_low ? "true" : "false", falling ? "true" : "false");
0258     return 0;
0259 }
0260 
0261 static int nsp_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
0262 {
0263     struct nsp_gpio *chip = gpiochip_get_data(gc);
0264     unsigned long flags;
0265 
0266     raw_spin_lock_irqsave(&chip->lock, flags);
0267     nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, false);
0268     raw_spin_unlock_irqrestore(&chip->lock, flags);
0269 
0270     dev_dbg(chip->dev, "gpio:%u set input\n", gpio);
0271     return 0;
0272 }
0273 
0274 static int nsp_gpio_direction_output(struct gpio_chip *gc, unsigned gpio,
0275                      int val)
0276 {
0277     struct nsp_gpio *chip = gpiochip_get_data(gc);
0278     unsigned long flags;
0279 
0280     raw_spin_lock_irqsave(&chip->lock, flags);
0281     nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, true);
0282     nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val));
0283     raw_spin_unlock_irqrestore(&chip->lock, flags);
0284 
0285     dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val);
0286     return 0;
0287 }
0288 
0289 static int nsp_gpio_get_direction(struct gpio_chip *gc, unsigned gpio)
0290 {
0291     struct nsp_gpio *chip = gpiochip_get_data(gc);
0292     unsigned long flags;
0293     int val;
0294 
0295     raw_spin_lock_irqsave(&chip->lock, flags);
0296     val = nsp_get_bit(chip, REG, NSP_GPIO_OUT_EN, gpio);
0297     raw_spin_unlock_irqrestore(&chip->lock, flags);
0298 
0299     return !val;
0300 }
0301 
0302 static void nsp_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
0303 {
0304     struct nsp_gpio *chip = gpiochip_get_data(gc);
0305     unsigned long flags;
0306 
0307     raw_spin_lock_irqsave(&chip->lock, flags);
0308     nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val));
0309     raw_spin_unlock_irqrestore(&chip->lock, flags);
0310 
0311     dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val);
0312 }
0313 
0314 static int nsp_gpio_get(struct gpio_chip *gc, unsigned gpio)
0315 {
0316     struct nsp_gpio *chip = gpiochip_get_data(gc);
0317 
0318     return !!(readl(chip->base + NSP_GPIO_DATA_IN) & BIT(gpio));
0319 }
0320 
0321 static int nsp_get_groups_count(struct pinctrl_dev *pctldev)
0322 {
0323     return 1;
0324 }
0325 
0326 /*
0327  * Only one group: "gpio_grp", since this local pinctrl device only performs
0328  * GPIO specific PINCONF configurations
0329  */
0330 static const char *nsp_get_group_name(struct pinctrl_dev *pctldev,
0331                       unsigned selector)
0332 {
0333     return "gpio_grp";
0334 }
0335 
0336 static const struct pinctrl_ops nsp_pctrl_ops = {
0337     .get_groups_count = nsp_get_groups_count,
0338     .get_group_name = nsp_get_group_name,
0339     .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
0340     .dt_free_map = pinctrl_utils_free_map,
0341 };
0342 
0343 static int nsp_gpio_set_slew(struct nsp_gpio *chip, unsigned gpio, u32 slew)
0344 {
0345     if (slew)
0346         nsp_set_bit(chip, IO_CTRL, NSP_GPIO_SLEW_RATE_EN, gpio, true);
0347     else
0348         nsp_set_bit(chip, IO_CTRL, NSP_GPIO_SLEW_RATE_EN, gpio, false);
0349 
0350     return 0;
0351 }
0352 
0353 static int nsp_gpio_set_pull(struct nsp_gpio *chip, unsigned gpio,
0354                  bool pull_up, bool pull_down)
0355 {
0356     unsigned long flags;
0357 
0358     raw_spin_lock_irqsave(&chip->lock, flags);
0359     nsp_set_bit(chip, IO_CTRL, NSP_PULL_DOWN_EN, gpio, pull_down);
0360     nsp_set_bit(chip, IO_CTRL, NSP_PULL_UP_EN, gpio, pull_up);
0361     raw_spin_unlock_irqrestore(&chip->lock, flags);
0362 
0363     dev_dbg(chip->dev, "gpio:%u set pullup:%d pulldown: %d\n",
0364         gpio, pull_up, pull_down);
0365     return 0;
0366 }
0367 
0368 static void nsp_gpio_get_pull(struct nsp_gpio *chip, unsigned gpio,
0369                   bool *pull_up, bool *pull_down)
0370 {
0371     unsigned long flags;
0372 
0373     raw_spin_lock_irqsave(&chip->lock, flags);
0374     *pull_up = nsp_get_bit(chip, IO_CTRL, NSP_PULL_UP_EN, gpio);
0375     *pull_down = nsp_get_bit(chip, IO_CTRL, NSP_PULL_DOWN_EN, gpio);
0376     raw_spin_unlock_irqrestore(&chip->lock, flags);
0377 }
0378 
0379 static int nsp_gpio_set_strength(struct nsp_gpio *chip, unsigned gpio,
0380                  u32 strength)
0381 {
0382     u32 offset, shift, i;
0383     u32 val;
0384     unsigned long flags;
0385 
0386     /* make sure drive strength is supported */
0387     if (strength < 2 || strength > 16 || (strength % 2))
0388         return -ENOTSUPP;
0389 
0390     shift = gpio;
0391     offset = NSP_GPIO_DRV_CTRL;
0392     dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio,
0393         strength);
0394     raw_spin_lock_irqsave(&chip->lock, flags);
0395     strength = (strength / 2) - 1;
0396     for (i = GPIO_DRV_STRENGTH_BITS; i > 0; i--) {
0397         val = readl(chip->io_ctrl + offset);
0398         val &= ~BIT(shift);
0399         val |= ((strength >> (i-1)) & 0x1) << shift;
0400         writel(val, chip->io_ctrl + offset);
0401         offset += 4;
0402     }
0403     raw_spin_unlock_irqrestore(&chip->lock, flags);
0404 
0405     return 0;
0406 }
0407 
0408 static int nsp_gpio_get_strength(struct nsp_gpio *chip, unsigned gpio,
0409                  u16 *strength)
0410 {
0411     unsigned int offset, shift;
0412     u32 val;
0413     unsigned long flags;
0414     int i;
0415 
0416     offset = NSP_GPIO_DRV_CTRL;
0417     shift = gpio;
0418 
0419     raw_spin_lock_irqsave(&chip->lock, flags);
0420     *strength = 0;
0421     for (i = (GPIO_DRV_STRENGTH_BITS - 1); i >= 0; i--) {
0422         val = readl(chip->io_ctrl + offset) & BIT(shift);
0423         val >>= shift;
0424         *strength += (val << i);
0425         offset += 4;
0426     }
0427 
0428     /* convert to mA */
0429     *strength = (*strength + 1) * 2;
0430     raw_spin_unlock_irqrestore(&chip->lock, flags);
0431 
0432     return 0;
0433 }
0434 
0435 static int nsp_pin_config_group_get(struct pinctrl_dev *pctldev,
0436                     unsigned selector,
0437                  unsigned long *config)
0438 {
0439     return 0;
0440 }
0441 
0442 static int nsp_pin_config_group_set(struct pinctrl_dev *pctldev,
0443                     unsigned selector,
0444                  unsigned long *configs, unsigned num_configs)
0445 {
0446     return 0;
0447 }
0448 
0449 static int nsp_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
0450                   unsigned long *config)
0451 {
0452     struct nsp_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
0453     enum pin_config_param param = pinconf_to_config_param(*config);
0454     unsigned int gpio;
0455     u16 arg = 0;
0456     bool pull_up, pull_down;
0457     int ret;
0458 
0459     gpio = nsp_pin_to_gpio(pin);
0460     switch (param) {
0461     case PIN_CONFIG_BIAS_DISABLE:
0462         nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down);
0463         if ((pull_up == false) && (pull_down == false))
0464             return 0;
0465         else
0466             return -EINVAL;
0467 
0468     case PIN_CONFIG_BIAS_PULL_UP:
0469         nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down);
0470         if (pull_up)
0471             return 0;
0472         else
0473             return -EINVAL;
0474 
0475     case PIN_CONFIG_BIAS_PULL_DOWN:
0476         nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down);
0477         if (pull_down)
0478             return 0;
0479         else
0480             return -EINVAL;
0481 
0482     case PIN_CONFIG_DRIVE_STRENGTH:
0483         ret = nsp_gpio_get_strength(chip, gpio, &arg);
0484         if (ret)
0485             return ret;
0486         *config = pinconf_to_config_packed(param, arg);
0487         return 0;
0488 
0489     default:
0490         return -ENOTSUPP;
0491     }
0492 }
0493 
0494 static int nsp_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
0495                   unsigned long *configs, unsigned num_configs)
0496 {
0497     struct nsp_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
0498     enum pin_config_param param;
0499     u32 arg;
0500     unsigned int i, gpio;
0501     int ret = -ENOTSUPP;
0502 
0503     gpio = nsp_pin_to_gpio(pin);
0504     for (i = 0; i < num_configs; i++) {
0505         param = pinconf_to_config_param(configs[i]);
0506         arg = pinconf_to_config_argument(configs[i]);
0507 
0508         switch (param) {
0509         case PIN_CONFIG_BIAS_DISABLE:
0510             ret = nsp_gpio_set_pull(chip, gpio, false, false);
0511             if (ret < 0)
0512                 goto out;
0513             break;
0514 
0515         case PIN_CONFIG_BIAS_PULL_UP:
0516             ret = nsp_gpio_set_pull(chip, gpio, true, false);
0517             if (ret < 0)
0518                 goto out;
0519             break;
0520 
0521         case PIN_CONFIG_BIAS_PULL_DOWN:
0522             ret = nsp_gpio_set_pull(chip, gpio, false, true);
0523             if (ret < 0)
0524                 goto out;
0525             break;
0526 
0527         case PIN_CONFIG_DRIVE_STRENGTH:
0528             ret = nsp_gpio_set_strength(chip, gpio, arg);
0529             if (ret < 0)
0530                 goto out;
0531             break;
0532 
0533         case PIN_CONFIG_SLEW_RATE:
0534             ret = nsp_gpio_set_slew(chip, gpio, arg);
0535             if (ret < 0)
0536                 goto out;
0537             break;
0538 
0539         default:
0540             dev_err(chip->dev, "invalid configuration\n");
0541             return -ENOTSUPP;
0542         }
0543     }
0544 
0545 out:
0546     return ret;
0547 }
0548 
0549 static const struct pinconf_ops nsp_pconf_ops = {
0550     .is_generic = true,
0551     .pin_config_get = nsp_pin_config_get,
0552     .pin_config_set = nsp_pin_config_set,
0553     .pin_config_group_get = nsp_pin_config_group_get,
0554     .pin_config_group_set = nsp_pin_config_group_set,
0555 };
0556 
0557 /*
0558  * NSP GPIO controller supports some PINCONF related configurations such as
0559  * pull up, pull down, slew and drive strength, when the pin is configured
0560  * to GPIO.
0561  *
0562  * Here a local pinctrl device is created with simple 1-to-1 pin mapping to the
0563  * local GPIO pins
0564  */
0565 static int nsp_gpio_register_pinconf(struct nsp_gpio *chip)
0566 {
0567     struct pinctrl_desc *pctldesc = &chip->pctldesc;
0568     struct pinctrl_pin_desc *pins;
0569     struct gpio_chip *gc = &chip->gc;
0570     int i;
0571 
0572     pins = devm_kcalloc(chip->dev, gc->ngpio, sizeof(*pins), GFP_KERNEL);
0573     if (!pins)
0574         return -ENOMEM;
0575     for (i = 0; i < gc->ngpio; i++) {
0576         pins[i].number = i;
0577         pins[i].name = devm_kasprintf(chip->dev, GFP_KERNEL,
0578                           "gpio-%d", i);
0579         if (!pins[i].name)
0580             return -ENOMEM;
0581     }
0582     pctldesc->name = dev_name(chip->dev);
0583     pctldesc->pctlops = &nsp_pctrl_ops;
0584     pctldesc->pins = pins;
0585     pctldesc->npins = gc->ngpio;
0586     pctldesc->confops = &nsp_pconf_ops;
0587 
0588     chip->pctl = devm_pinctrl_register(chip->dev, pctldesc, chip);
0589     if (IS_ERR(chip->pctl)) {
0590         dev_err(chip->dev, "unable to register pinctrl device\n");
0591         return PTR_ERR(chip->pctl);
0592     }
0593 
0594     return 0;
0595 }
0596 
0597 static const struct of_device_id nsp_gpio_of_match[] = {
0598     {.compatible = "brcm,nsp-gpio-a",},
0599     {}
0600 };
0601 
0602 static int nsp_gpio_probe(struct platform_device *pdev)
0603 {
0604     struct device *dev = &pdev->dev;
0605     struct nsp_gpio *chip;
0606     struct gpio_chip *gc;
0607     u32 val;
0608     int irq, ret;
0609 
0610     if (of_property_read_u32(pdev->dev.of_node, "ngpios", &val)) {
0611         dev_err(&pdev->dev, "Missing ngpios OF property\n");
0612         return -ENODEV;
0613     }
0614 
0615     chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
0616     if (!chip)
0617         return -ENOMEM;
0618 
0619     chip->dev = dev;
0620     platform_set_drvdata(pdev, chip);
0621 
0622     chip->base = devm_platform_ioremap_resource(pdev, 0);
0623     if (IS_ERR(chip->base)) {
0624         dev_err(dev, "unable to map I/O memory\n");
0625         return PTR_ERR(chip->base);
0626     }
0627 
0628     chip->io_ctrl = devm_platform_ioremap_resource(pdev, 1);
0629     if (IS_ERR(chip->io_ctrl)) {
0630         dev_err(dev, "unable to map I/O memory\n");
0631         return PTR_ERR(chip->io_ctrl);
0632     }
0633 
0634     raw_spin_lock_init(&chip->lock);
0635     gc = &chip->gc;
0636     gc->base = -1;
0637     gc->can_sleep = false;
0638     gc->ngpio = val;
0639     gc->label = dev_name(dev);
0640     gc->parent = dev;
0641     gc->request = gpiochip_generic_request;
0642     gc->free = gpiochip_generic_free;
0643     gc->direction_input = nsp_gpio_direction_input;
0644     gc->direction_output = nsp_gpio_direction_output;
0645     gc->get_direction = nsp_gpio_get_direction;
0646     gc->set = nsp_gpio_set;
0647     gc->get = nsp_gpio_get;
0648 
0649     /* optional GPIO interrupt support */
0650     irq = platform_get_irq(pdev, 0);
0651     if (irq > 0) {
0652         struct gpio_irq_chip *girq;
0653         struct irq_chip *irqc;
0654 
0655         irqc = &chip->irqchip;
0656         irqc->name = "gpio-a";
0657         irqc->irq_ack = nsp_gpio_irq_ack;
0658         irqc->irq_mask = nsp_gpio_irq_mask;
0659         irqc->irq_unmask = nsp_gpio_irq_unmask;
0660         irqc->irq_set_type = nsp_gpio_irq_set_type;
0661 
0662         val = readl(chip->base + NSP_CHIP_A_INT_MASK);
0663         val = val | NSP_CHIP_A_GPIO_INT_BIT;
0664         writel(val, (chip->base + NSP_CHIP_A_INT_MASK));
0665 
0666         /* Install ISR for this GPIO controller. */
0667         ret = devm_request_irq(dev, irq, nsp_gpio_irq_handler,
0668                        IRQF_SHARED, "gpio-a", &chip->gc);
0669         if (ret) {
0670             dev_err(&pdev->dev, "Unable to request IRQ%d: %d\n",
0671                 irq, ret);
0672             return ret;
0673         }
0674 
0675         girq = &chip->gc.irq;
0676         girq->chip = irqc;
0677         /* This will let us handle the parent IRQ in the driver */
0678         girq->parent_handler = NULL;
0679         girq->num_parents = 0;
0680         girq->parents = NULL;
0681         girq->default_type = IRQ_TYPE_NONE;
0682         girq->handler = handle_bad_irq;
0683     }
0684 
0685     ret = devm_gpiochip_add_data(dev, gc, chip);
0686     if (ret < 0) {
0687         dev_err(dev, "unable to add GPIO chip\n");
0688         return ret;
0689     }
0690 
0691     ret = nsp_gpio_register_pinconf(chip);
0692     if (ret) {
0693         dev_err(dev, "unable to register pinconf\n");
0694         return ret;
0695     }
0696 
0697     return 0;
0698 }
0699 
0700 static struct platform_driver nsp_gpio_driver = {
0701     .driver = {
0702         .name = "nsp-gpio-a",
0703         .of_match_table = nsp_gpio_of_match,
0704     },
0705     .probe = nsp_gpio_probe,
0706 };
0707 
0708 static int __init nsp_gpio_init(void)
0709 {
0710     return platform_driver_register(&nsp_gpio_driver);
0711 }
0712 arch_initcall_sync(nsp_gpio_init);
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